From 39943a5b0c3c210babfd6e62711ea4bf3133866b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 24 May 2010 16:31:23 -0700 Subject: Added support to set GPIO pins from dboard interface: write gpio and set pin control (atr or gpio) Added property to get dboard interface from the dboard obj. --- host/lib/usrp/usrp2/dboard_iface.cpp | 34 ++++++++++++++++++++++++++-------- host/lib/usrp/usrp2/dboard_impl.cpp | 12 +++++++++--- host/lib/usrp/usrp2/usrp2_impl.hpp | 1 + host/lib/usrp/usrp2/usrp2_regs.hpp | 2 +- 4 files changed, 37 insertions(+), 12 deletions(-) (limited to 'host/lib/usrp/usrp2') diff --git a/host/lib/usrp/usrp2/dboard_iface.cpp b/host/lib/usrp/usrp2/dboard_iface.cpp index d33a11fd6..0a2e4b550 100644 --- a/host/lib/usrp/usrp2/dboard_iface.cpp +++ b/host/lib/usrp/usrp2/dboard_iface.cpp @@ -39,8 +39,10 @@ public: void write_aux_dac(unit_t, int, float); float read_aux_adc(unit_t, int); + void set_pin_ctrl(unit_t, boost::uint16_t); void set_atr_reg(unit_t, atr_reg_t, boost::uint16_t); void set_gpio_ddr(unit_t, boost::uint16_t); + void write_gpio(unit_t, boost::uint16_t); boost::uint16_t read_gpio(unit_t); void write_i2c(boost::uint8_t, const byte_vector_t &); @@ -68,6 +70,7 @@ private: usrp2_iface::sptr _iface; clock_ctrl::sptr _clock_ctrl; boost::uint32_t _ddr_shadow; + boost::uint32_t _gpio_shadow; uhd::dict _dac_regs; void _write_aux_dac(unit_t); @@ -90,14 +93,7 @@ usrp2_dboard_iface::usrp2_dboard_iface(usrp2_iface::sptr iface, clock_ctrl::sptr _iface = iface; _clock_ctrl = clock_ctrl; _ddr_shadow = 0; - - //set the selection mux to use atr - boost::uint32_t new_sels = 0x0; - for(size_t i = 0; i < 16; i++){ - new_sels |= FRF_GPIO_SEL_ATR << (i*2); - } - _iface->poke32(FR_GPIO_TX_SEL, new_sels); - _iface->poke32(FR_GPIO_RX_SEL, new_sels); + _gpio_shadow = 0; //reset the aux dacs _dac_regs[UNIT_RX] = ad5624_regs_t(); @@ -136,6 +132,21 @@ static const uhd::dict unit_to_shift = map_list_of (dboard_iface::UNIT_TX, 16) ; +void usrp2_dboard_iface::set_pin_ctrl(unit_t unit, boost::uint16_t value){ + //calculate the new selection mux setting + boost::uint32_t new_sels = 0x0; + for(size_t i = 0; i < 16; i++){ + bool is_bit_set = bool(value & (0x1 << i)); + new_sels |= ((is_bit_set)? FRF_GPIO_SEL_ATR : FRF_GPIO_SEL_GPIO) << (i*2); + } + + //write the selection mux value to register + switch(unit){ + case UNIT_RX: _iface->poke32(FR_GPIO_RX_SEL, new_sels); return; + case UNIT_TX: _iface->poke32(FR_GPIO_TX_SEL, new_sels); return; + } +} + void usrp2_dboard_iface::set_gpio_ddr(unit_t unit, boost::uint16_t value){ _ddr_shadow = \ (_ddr_shadow & ~(0xffff << unit_to_shift[unit])) | @@ -143,6 +154,13 @@ void usrp2_dboard_iface::set_gpio_ddr(unit_t unit, boost::uint16_t value){ _iface->poke32(FR_GPIO_DDR, _ddr_shadow); } +void usrp2_dboard_iface::write_gpio(unit_t unit, boost::uint16_t value){ + _gpio_shadow = \ + (_gpio_shadow & ~(0xffff << unit_to_shift[unit])) | + (boost::uint32_t(value) << unit_to_shift[unit]); + _iface->poke32(FR_GPIO_IO, _gpio_shadow); +} + boost::uint16_t usrp2_dboard_iface::read_gpio(unit_t unit){ return boost::uint16_t(_iface->peek32(FR_GPIO_IO) >> unit_to_shift[unit]); } diff --git a/host/lib/usrp/usrp2/dboard_impl.cpp b/host/lib/usrp/usrp2/dboard_impl.cpp index 0f8a739f2..0ac39d2a3 100644 --- a/host/lib/usrp/usrp2/dboard_impl.cpp +++ b/host/lib/usrp/usrp2/dboard_impl.cpp @@ -38,9 +38,7 @@ void usrp2_impl::dboard_init(void){ _tx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_TX_DB, 0, dboard_eeprom_t::num_bytes())); //create a new dboard interface and manager - dboard_iface::sptr _dboard_iface( - make_usrp2_dboard_iface(_iface, _clock_ctrl) - ); + _dboard_iface = make_usrp2_dboard_iface(_iface, _clock_ctrl); _dboard_manager = dboard_manager::make( _rx_db_eeprom.id, _tx_db_eeprom.id, _dboard_iface ); @@ -123,6 +121,10 @@ void usrp2_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ val = _rx_db_eeprom.id; return; + case DBOARD_PROP_DBOARD_IFACE: + val = _dboard_iface; + return; + default: UHD_THROW_PROP_GET_ERROR(); } } @@ -172,6 +174,10 @@ void usrp2_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ val = _tx_db_eeprom.id; return; + case DBOARD_PROP_DBOARD_IFACE: + val = _dboard_iface; + return; + default: UHD_THROW_PROP_GET_ERROR(); } } diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp index afea9683c..7948a2069 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.hpp +++ b/host/lib/usrp/usrp2/usrp2_impl.hpp @@ -169,6 +169,7 @@ private: //rx and tx dboard methods and objects uhd::usrp::dboard_manager::sptr _dboard_manager; + uhd::usrp::dboard_iface::sptr _dboard_iface; void dboard_init(void); //properties for the mboard diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index feeccaa34..0f675357b 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -204,7 +204,7 @@ #define FR_GPIO_RX_SEL FR_GPIO_BASE + 12 // 16 2-bit fields select which source goes to RX DB // each 2-bit sel field is layed out this way -#define FRF_GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define FRF_GPIO_SEL_GPIO 0 // if pin is an output, set by GPIO register #define FRF_GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic #define FRF_GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric #define FRF_GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric -- cgit v1.2.3