From 9cb9e7d52255d3e14e57867eee76b555f705954c Mon Sep 17 00:00:00 2001 From: Thomas Tsou Date: Fri, 13 Aug 2010 16:20:41 -0700 Subject: usrp1: Add usrp1 implementation --- host/lib/usrp/usrp1/clock_ctrl.cpp | 124 +++++++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 host/lib/usrp/usrp1/clock_ctrl.cpp (limited to 'host/lib/usrp/usrp1/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp1/clock_ctrl.cpp b/host/lib/usrp/usrp1/clock_ctrl.cpp new file mode 100644 index 000000000..c83ad4c68 --- /dev/null +++ b/host/lib/usrp/usrp1/clock_ctrl.cpp @@ -0,0 +1,124 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "clock_ctrl.hpp" +#include "fpga_regs_standard.h" +#include +#include +#include +#include +#include +#include + +using namespace uhd; + +/*********************************************************************** + * Constants + **********************************************************************/ +static const double master_clock_rate = 64e6; + +/*********************************************************************** + * Clock Control Implementation + **********************************************************************/ +class usrp1_clock_ctrl_impl : public usrp1_clock_ctrl { +public: + usrp1_clock_ctrl_impl(usrp1_iface::sptr iface) + { + _iface = iface; + } + + double get_master_clock_freq(void) + { + return master_clock_rate; + } + + /*********************************************************************** + * RX Dboard Clock Control (output 9, divider 3) + **********************************************************************/ + void enable_rx_dboard_clock(bool) + { + std::cerr << "USRP: enable_rx_dboard_clock() disabled" << std::endl; + _iface->poke32(FR_RX_A_REFCLK, 0); + _iface->poke32(FR_RX_B_REFCLK, 0); + } + + std::vector get_rx_dboard_clock_rates(void) + { +#if 0 + std::vector rates; + for (size_t div = 1; div <= 127; div++) + rates.push_back(master_clock_rate / div); + return rates; +#else + return std::vector(1, 64e6); +#endif + } + + /* + * Daughterboard reference clock register + * + * Bit 7 - 1 turns on refclk, 0 allows IO use + * Bits 6:0 - Divider value + */ + void set_rx_dboard_clock_rate(double) + { +#if 0 + assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate"); + size_t divider = size_t(rate/master_clock_rate); + _iface->poke32(FR_RX_A_REFCLK, (divider & 0x7f) | 0x80); +#else + std::cerr << "USRP: set_rx_dboard_clock_rate() disabled" << std::endl; + _iface->poke32(FR_RX_A_REFCLK, 0); + _iface->poke32(FR_RX_B_REFCLK, 0); +#endif + } + + /*********************************************************************** + * TX Dboard Clock Control + **********************************************************************/ + void enable_tx_dboard_clock(bool) + { + std::cerr << "USRP: set_tx_dboard_clock() disabled" << std::endl; + _iface->poke32(FR_TX_A_REFCLK, 0); + _iface->poke32(FR_TX_B_REFCLK, 0); + + } + + std::vector get_tx_dboard_clock_rates(void) + { + return get_rx_dboard_clock_rates(); //same master clock, same dividers... + } + + void set_tx_dboard_clock_rate(double) + { + std::cerr << "USRP: set_tx_dboard_clock_rate() disabled" << std::endl; + _iface->poke32(FR_TX_A_REFCLK, 0); + _iface->poke32(FR_TX_B_REFCLK, 0); + } + +private: + usrp1_iface::sptr _iface; + +}; + +/*********************************************************************** + * Clock Control Make + **********************************************************************/ +usrp1_clock_ctrl::sptr usrp1_clock_ctrl::make(usrp1_iface::sptr iface) +{ + return sptr(new usrp1_clock_ctrl_impl(iface)); +} -- cgit v1.2.3 From 3f4e998bbf59dcc1c5df88ed37ca74f80a1b2e70 Mon Sep 17 00:00:00 2001 From: Thomas Tsou Date: Mon, 23 Aug 2010 15:21:14 -0700 Subject: usrp1: Remove hard coded value in clock rate property --- host/lib/usrp/usrp1/clock_ctrl.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'host/lib/usrp/usrp1/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp1/clock_ctrl.cpp b/host/lib/usrp/usrp1/clock_ctrl.cpp index c83ad4c68..54f7b0b98 100644 --- a/host/lib/usrp/usrp1/clock_ctrl.cpp +++ b/host/lib/usrp/usrp1/clock_ctrl.cpp @@ -64,7 +64,7 @@ public: rates.push_back(master_clock_rate / div); return rates; #else - return std::vector(1, 64e6); + return std::vector(1, master_clock_rate); #endif } -- cgit v1.2.3 From c9569736930cf436f340d70c7537a5f46f3ab3aa Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 26 Aug 2010 22:15:12 -0700 Subject: usrp1: handle special dbsrx clocking case --- host/lib/usrp/usrp1/clock_ctrl.cpp | 64 -------------------------------- host/lib/usrp/usrp1/clock_ctrl.hpp | 38 ------------------- host/lib/usrp/usrp1/dboard_iface.cpp | 72 ++++++++++++++++++++++++------------ host/lib/usrp/usrp1/dboard_impl.cpp | 3 +- host/lib/usrp/usrp1/usrp1_impl.hpp | 8 ++-- 5 files changed, 55 insertions(+), 130 deletions(-) (limited to 'host/lib/usrp/usrp1/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp1/clock_ctrl.cpp b/host/lib/usrp/usrp1/clock_ctrl.cpp index 54f7b0b98..68c5f5320 100644 --- a/host/lib/usrp/usrp1/clock_ctrl.cpp +++ b/host/lib/usrp/usrp1/clock_ctrl.cpp @@ -46,70 +46,6 @@ public: return master_clock_rate; } - /*********************************************************************** - * RX Dboard Clock Control (output 9, divider 3) - **********************************************************************/ - void enable_rx_dboard_clock(bool) - { - std::cerr << "USRP: enable_rx_dboard_clock() disabled" << std::endl; - _iface->poke32(FR_RX_A_REFCLK, 0); - _iface->poke32(FR_RX_B_REFCLK, 0); - } - - std::vector get_rx_dboard_clock_rates(void) - { -#if 0 - std::vector rates; - for (size_t div = 1; div <= 127; div++) - rates.push_back(master_clock_rate / div); - return rates; -#else - return std::vector(1, master_clock_rate); -#endif - } - - /* - * Daughterboard reference clock register - * - * Bit 7 - 1 turns on refclk, 0 allows IO use - * Bits 6:0 - Divider value - */ - void set_rx_dboard_clock_rate(double) - { -#if 0 - assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate"); - size_t divider = size_t(rate/master_clock_rate); - _iface->poke32(FR_RX_A_REFCLK, (divider & 0x7f) | 0x80); -#else - std::cerr << "USRP: set_rx_dboard_clock_rate() disabled" << std::endl; - _iface->poke32(FR_RX_A_REFCLK, 0); - _iface->poke32(FR_RX_B_REFCLK, 0); -#endif - } - - /*********************************************************************** - * TX Dboard Clock Control - **********************************************************************/ - void enable_tx_dboard_clock(bool) - { - std::cerr << "USRP: set_tx_dboard_clock() disabled" << std::endl; - _iface->poke32(FR_TX_A_REFCLK, 0); - _iface->poke32(FR_TX_B_REFCLK, 0); - - } - - std::vector get_tx_dboard_clock_rates(void) - { - return get_rx_dboard_clock_rates(); //same master clock, same dividers... - } - - void set_tx_dboard_clock_rate(double) - { - std::cerr << "USRP: set_tx_dboard_clock_rate() disabled" << std::endl; - _iface->poke32(FR_TX_A_REFCLK, 0); - _iface->poke32(FR_TX_B_REFCLK, 0); - } - private: usrp1_iface::sptr _iface; diff --git a/host/lib/usrp/usrp1/clock_ctrl.hpp b/host/lib/usrp/usrp1/clock_ctrl.hpp index 9ba4d56e3..366869dab 100644 --- a/host/lib/usrp/usrp1/clock_ctrl.hpp +++ b/host/lib/usrp/usrp1/clock_ctrl.hpp @@ -45,44 +45,6 @@ public: */ virtual double get_master_clock_freq(void) = 0; - /*! - * Get the possible rates of the rx dboard clock. - * \return a vector of clock rates in Hz - */ - virtual std::vector get_rx_dboard_clock_rates(void) = 0; - - /*! - * Get the possible rates of the tx dboard clock. - * \return a vector of clock rates in Hz - */ - virtual std::vector get_tx_dboard_clock_rates(void) = 0; - - /*! - * Set the rx dboard clock rate to a possible rate. - * \param rate the new clock rate in Hz - * \throw exception when rate cannot be achieved - */ - virtual void set_rx_dboard_clock_rate(double rate) = 0; - - /*! - * Set the tx dboard clock rate to a possible rate. - * \param rate the new clock rate in Hz - * \throw exception when rate cannot be achieved - */ - virtual void set_tx_dboard_clock_rate(double rate) = 0; - - /*! - * Enable/disable the rx dboard clock. - * \param enb true to enable - */ - virtual void enable_rx_dboard_clock(bool enb) = 0; - - /*! - * Enable/disable the tx dboard clock. - * \param enb true to enable - */ - virtual void enable_tx_dboard_clock(bool enb) = 0; - }; #endif /* INCLUDED_USRP1_CLOCK_CTRL_HPP */ diff --git a/host/lib/usrp/usrp1/dboard_iface.cpp b/host/lib/usrp/usrp1/dboard_iface.cpp index 3078b884d..b2221e221 100644 --- a/host/lib/usrp/usrp1/dboard_iface.cpp +++ b/host/lib/usrp/usrp1/dboard_iface.cpp @@ -19,6 +19,7 @@ #include "usrp1_impl.hpp" #include "fpga_regs_common.h" #include "usrp_spi_defs.h" +#include "fpga_regs_standard.h" #include "clock_ctrl.hpp" #include "codec_ctrl.hpp" #include @@ -37,12 +38,15 @@ public: usrp1_dboard_iface(usrp1_iface::sptr iface, usrp1_clock_ctrl::sptr clock, usrp1_codec_ctrl::sptr codec, - usrp1_impl::dboard_slot_t dboard_slot - ){ + usrp1_impl::dboard_slot_t dboard_slot, + const dboard_id_t &rx_dboard_id + ): + _dboard_slot(dboard_slot), + _rx_dboard_id(rx_dboard_id) + { _iface = iface; _clock = clock; _codec = codec; - _dboard_slot = dboard_slot; //init the clock rate shadows this->set_clock_rate(UNIT_RX, _clock->get_master_clock_freq()); @@ -95,7 +99,8 @@ private: usrp1_clock_ctrl::sptr _clock; usrp1_codec_ctrl::sptr _codec; uhd::dict _clock_rates; - usrp1_impl::dboard_slot_t _dboard_slot; + const usrp1_impl::dboard_slot_t _dboard_slot; + const dboard_id_t &_rx_dboard_id; }; /*********************************************************************** @@ -104,33 +109,55 @@ private: dboard_iface::sptr usrp1_impl::make_dboard_iface(usrp1_iface::sptr iface, usrp1_clock_ctrl::sptr clock, usrp1_codec_ctrl::sptr codec, - dboard_slot_t dboard_slot + dboard_slot_t dboard_slot, + const dboard_id_t &rx_dboard_id ){ - return dboard_iface::sptr(new usrp1_dboard_iface(iface, clock, codec, dboard_slot)); + return dboard_iface::sptr(new usrp1_dboard_iface( + iface, clock, codec, dboard_slot, rx_dboard_id + )); } /*********************************************************************** * Clock Rates **********************************************************************/ +static const dboard_id_t dbsrx_classic_id(0x0002); + +/* + * Daughterboard reference clock register + * + * Bit 7 - 1 turns on refclk, 0 allows IO use + * Bits 6:0 - Divider value + */ void usrp1_dboard_iface::set_clock_rate(unit_t unit, double rate) { + assert_has(this->get_clock_rates(unit), rate, "dboard clock rate"); _clock_rates[unit] = rate; - switch(unit) { - case UNIT_RX: return _clock->set_rx_dboard_clock_rate(rate); - case UNIT_TX: return _clock->set_tx_dboard_clock_rate(rate); + + if (unit == UNIT_RX && _rx_dboard_id == dbsrx_classic_id){ + size_t divider = size_t(rate/_clock->get_master_clock_freq()); + switch(_dboard_slot){ + case usrp1_impl::DBOARD_SLOT_A: + _iface->poke32(FR_RX_A_REFCLK, (divider & 0x7f) | 0x80); + break; + + case usrp1_impl::DBOARD_SLOT_B: + _iface->poke32(FR_RX_B_REFCLK, (divider & 0x7f) | 0x80); + break; + } } } -/* - * TODO: if this is a dbsrx return the rate of 4MHZ and set FPGA magic - */ std::vector usrp1_dboard_iface::get_clock_rates(unit_t unit) { - switch(unit) { - case UNIT_RX: return _clock->get_rx_dboard_clock_rates(); - case UNIT_TX: return _clock->get_tx_dboard_clock_rates(); - default: UHD_THROW_INVALID_CODE_PATH(); + std::vector rates; + if (unit == UNIT_RX && _rx_dboard_id == dbsrx_classic_id){ + for (size_t div = 1; div <= 127; div++) + rates.push_back(_clock->get_master_clock_freq() / div); } + else{ + rates.push_back(_clock->get_master_clock_freq()); + } + return rates; } double usrp1_dboard_iface::get_clock_rate(unit_t unit) @@ -138,12 +165,9 @@ double usrp1_dboard_iface::get_clock_rate(unit_t unit) return _clock_rates[unit]; } -void usrp1_dboard_iface::set_clock_enabled(unit_t unit, bool enb) +void usrp1_dboard_iface::set_clock_enabled(unit_t, bool) { - switch(unit) { - case UNIT_RX: return _clock->enable_rx_dboard_clock(enb); - case UNIT_TX: return _clock->enable_tx_dboard_clock(enb); - } + //TODO we can only enable for special case anyway... } /*********************************************************************** @@ -241,7 +265,7 @@ void usrp1_dboard_iface::set_atr_reg(unit_t unit, _iface->poke32(FR_ATR_RXVAL_1, value); else if (_dboard_slot == usrp1_impl::DBOARD_SLOT_B) _iface->poke32(FR_ATR_RXVAL_3, value); - break; + break; case UNIT_TX: if (_dboard_slot == usrp1_impl::DBOARD_SLOT_A) _iface->poke32(FR_ATR_TXVAL_0, value); @@ -265,14 +289,14 @@ static boost::uint32_t unit_to_otw_spi_dev(dboard_iface::unit_t unit, switch(unit) { case dboard_iface::UNIT_TX: if (slot == usrp1_impl::DBOARD_SLOT_A) - return SPI_ENABLE_TX_A; + return SPI_ENABLE_TX_A; else if (slot == usrp1_impl::DBOARD_SLOT_B) return SPI_ENABLE_TX_B; else break; case dboard_iface::UNIT_RX: if (slot == usrp1_impl::DBOARD_SLOT_A) - return SPI_ENABLE_RX_A; + return SPI_ENABLE_RX_A; else if (slot == usrp1_impl::DBOARD_SLOT_B) return SPI_ENABLE_RX_B; else diff --git a/host/lib/usrp/usrp1/dboard_impl.cpp b/host/lib/usrp/usrp1/dboard_impl.cpp index f52117c34..3a8480e1b 100644 --- a/host/lib/usrp/usrp1/dboard_impl.cpp +++ b/host/lib/usrp/usrp1/dboard_impl.cpp @@ -67,7 +67,8 @@ void usrp1_impl::dboard_init(void) //create a new dboard interface and manager _dboard_ifaces[dboard_slot] = make_dboard_iface( - _iface, _clock_ctrl, _codec_ctrls[dboard_slot], dboard_slot + _iface, _clock_ctrl, _codec_ctrls[dboard_slot], + dboard_slot, _rx_db_eeproms[dboard_slot].id ); _dboard_managers[dboard_slot] = dboard_manager::make( diff --git a/host/lib/usrp/usrp1/usrp1_impl.hpp b/host/lib/usrp/usrp1/usrp1_impl.hpp index 4b4ac51dd..c2f693eeb 100644 --- a/host/lib/usrp/usrp1/usrp1_impl.hpp +++ b/host/lib/usrp/usrp1/usrp1_impl.hpp @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -45,8 +46,7 @@ public: typedef boost::function set_t; typedef boost::shared_ptr sptr; - static sptr make(const get_t &get, const set_t &set) - { + static sptr make(const get_t &get, const set_t &set){ return sptr(new wax_obj_proxy(get, set)); } @@ -102,13 +102,15 @@ private: * \param clock the clock control interface * \param codec the codec control interface * \param dboard_slot the slot identifier + * \param rx_dboard_id the db id for the rx board (used for evil dbsrx purposes) * \return a sptr to a new dboard interface */ static uhd::usrp::dboard_iface::sptr make_dboard_iface( usrp1_iface::sptr iface, usrp1_clock_ctrl::sptr clock, usrp1_codec_ctrl::sptr codec, - dboard_slot_t dboard_slot + dboard_slot_t dboard_slot, + const uhd::usrp::dboard_id_t &rx_dboard_id ); //interface to ioctls and file descriptor -- cgit v1.2.3