From 5bbc3c6282bb73db72d3dd1738aa906a89a6f772 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 15 Jun 2011 07:35:49 +0100 Subject: e100: clean up gpio wrapper stuff, fix order of setup in make() --- host/lib/usrp/e100/e100_impl.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'host/lib/usrp/e100/e100_impl.cpp') diff --git a/host/lib/usrp/e100/e100_impl.cpp b/host/lib/usrp/e100/e100_impl.cpp index 5485388f9..40ae20eaa 100644 --- a/host/lib/usrp/e100/e100_impl.cpp +++ b/host/lib/usrp/e100/e100_impl.cpp @@ -90,11 +90,6 @@ static device::sptr e100_make(const device_addr_t &device_addr){ //setup the main interface into fpga const std::string node = device_addr["node"]; e100_iface::sptr iface = e100_iface::make(); - iface->open(node); - - //setup clock control here to ensure that the FPGA has a good clock before we continue - const double master_clock_rate = device_addr.cast("master_clock_rate", E100_DEFAULT_CLOCK_RATE); - e100_clock_ctrl::sptr clock_ctrl = e100_clock_ctrl::make(iface, master_clock_rate); //extract the fpga path for usrp-e and compute hash const std::string e100_fpga_image = find_image_path(device_addr.get("fpga", E100_FPGA_FILE_NAME)); @@ -104,12 +99,17 @@ static device::sptr e100_make(const device_addr_t &device_addr){ // - close the device node // - load the fpga bin file // - re-open the device node + iface->open(node); //open here so we can do FPGA hash check if (iface->peek32(E100_REG_RB_MISC_TEST32) != file_hash){ iface->close(); e100_load_fpga(e100_fpga_image); iface->open(node); } + //setup clock control here to ensure that the FPGA has a good clock before we continue + const double master_clock_rate = device_addr.cast("master_clock_rate", E100_DEFAULT_CLOCK_RATE); + e100_clock_ctrl::sptr clock_ctrl = e100_clock_ctrl::make(iface, master_clock_rate); + //Perform wishbone readback tests, these tests also write the hash bool test_fail = false; UHD_MSG(status) << "Performing wishbone readback test... " << std::flush; -- cgit v1.2.3