From 38ece31201d7c940a82b633cc0e1facee718543c Mon Sep 17 00:00:00 2001 From: michael-west Date: Thu, 15 Apr 2021 23:18:19 -0700 Subject: N320: Fix IQ mapping and frontend corrections Changed register offset from 4 bytes to 8 bytes. The registers in the frontend were not being properly addressed, so calibration, IQ mapping, and frontend corrections were not working properly. Signed-off-by: michael-west --- host/lib/usrp/dboard/rhodium/rhodium_radio_control_init.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'host/lib/usrp/dboard/rhodium') diff --git a/host/lib/usrp/dboard/rhodium/rhodium_radio_control_init.cpp b/host/lib/usrp/dboard/rhodium/rhodium_radio_control_init.cpp index f19298697..844b0752b 100644 --- a/host/lib/usrp/dboard/rhodium/rhodium_radio_control_init.cpp +++ b/host/lib/usrp/dboard/rhodium/rhodium_radio_control_init.cpp @@ -154,13 +154,15 @@ void rhodium_radio_control_impl::_init_peripherals() _generate_read_spi(this->_spi, SEN_CPLD, _get_cpld_spi_config())); RFNOC_LOG_TRACE("Initializing TX frontend DSP core...") - _tx_fe_core = tx_frontend_core_200::make(_wb_iface, n320_regs::SR_TX_FE_BASE); + _tx_fe_core = tx_frontend_core_200::make( + _wb_iface, n320_regs::SR_TX_FE_BASE, n320_regs::PERIPH_REG_OFFSET); _tx_fe_core->set_dc_offset(tx_frontend_core_200::DEFAULT_DC_OFFSET_VALUE); _tx_fe_core->set_iq_balance(tx_frontend_core_200::DEFAULT_IQ_BALANCE_VALUE); _tx_fe_core->populate_subtree(get_tree()->subtree(FE_PATH / "tx_fe_corrections" / 0)); RFNOC_LOG_TRACE("Initializing RX frontend DSP core...") - _rx_fe_core = rx_frontend_core_3000::make(_wb_iface, n320_regs::SR_RX_FE_BASE); + _rx_fe_core = rx_frontend_core_3000::make( + _wb_iface, n320_regs::SR_RX_FE_BASE, n320_regs::PERIPH_REG_OFFSET); _rx_fe_core->set_adc_rate(_master_clock_rate); _rx_fe_core->set_dc_offset(rx_frontend_core_3000::DEFAULT_DC_OFFSET_VALUE); _rx_fe_core->set_dc_offset_auto(rx_frontend_core_3000::DEFAULT_DC_OFFSET_ENABLE); -- cgit v1.2.3