From 69bcfba936e49c2825a6d9be677c3150a5c6b70c Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Tue, 26 May 2015 15:35:04 -0700 Subject: B200: New AD9361 I/O timing programming to work with new b200_io.v logic design. --- host/lib/usrp/common/ad9361_driver/ad9361_device.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'host/lib/usrp/common') diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp index e63460730..db5de52d0 100644 --- a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp +++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp @@ -1455,13 +1455,13 @@ void ad9361_device_t::initialize() * Force TX on one port, RX on the other. */ switch (_client_params->get_digital_interface_mode()) { case AD9361_DDR_FDD_LVCMOS: { - _io_iface->poke8(0x010, 0xc8); + _io_iface->poke8(0x010, 0xc8); // Swap I&Q on Tx, Swap I&Q on Rx, Toggle frame sync mode _io_iface->poke8(0x011, 0x00); _io_iface->poke8(0x012, 0x02); } break; case AD9361_DDR_FDD_LVDS: { - _io_iface->poke8(0x010, 0xcc); + _io_iface->poke8(0x010, 0xcc); // Swap I&Q on Tx, Swap I&Q on Rx, Toggle frame sync mode, 2R2T timing. _io_iface->poke8(0x011, 0x00); _io_iface->poke8(0x012, 0x10); -- cgit v1.2.3