From 965b9a17cce1dc69cf907d2d551eae754aafcd49 Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Wed, 30 Sep 2015 18:23:20 -0700 Subject: b200: Updated minimum clock rate to match DCM changes Lowest master clock rate is now 220 kHz. At low clock rates, the convergence time for the DC offset and quadrature calibration times is much larger, though. --- host/lib/usrp/common/ad9361_driver/ad9361_device.h | 1 + 1 file changed, 1 insertion(+) (limited to 'host/lib/usrp/common/ad9361_driver/ad9361_device.h') diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.h b/host/lib/usrp/common/ad9361_driver/ad9361_device.h index 66bc2e8b9..73b1d9a35 100644 --- a/host/lib/usrp/common/ad9361_driver/ad9361_device.h +++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.h @@ -157,6 +157,7 @@ public: //Constants static const double AD9361_MAX_GAIN; static const double AD9361_MAX_CLOCK_RATE; + static const double AD9361_MIN_CLOCK_RATE; static const double AD9361_CAL_VALID_WINDOW; static const double AD9361_RECOMMENDED_MAX_BANDWIDTH; static const double DEFAULT_RX_FREQ; -- cgit v1.2.3