From 965b9a17cce1dc69cf907d2d551eae754aafcd49 Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Wed, 30 Sep 2015 18:23:20 -0700 Subject: b200: Updated minimum clock rate to match DCM changes Lowest master clock rate is now 220 kHz. At low clock rates, the convergence time for the DC offset and quadrature calibration times is much larger, though. --- host/lib/usrp/common/ad9361_ctrl.hpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'host/lib/usrp/common/ad9361_ctrl.hpp') diff --git a/host/lib/usrp/common/ad9361_ctrl.hpp b/host/lib/usrp/common/ad9361_ctrl.hpp index 5c438ee9c..8cd75d539 100644 --- a/host/lib/usrp/common/ad9361_ctrl.hpp +++ b/host/lib/usrp/common/ad9361_ctrl.hpp @@ -89,8 +89,10 @@ public: //! get the clock rate range for the frontend static uhd::meta_range_t get_clock_rate_range(void) { - //return uhd::meta_range_t(220e3, 61.44e6); - return uhd::meta_range_t(5e6, ad9361_device_t::AD9361_MAX_CLOCK_RATE); //5 MHz DCM low end + return uhd::meta_range_t( + ad9361_device_t::AD9361_MIN_CLOCK_RATE, + ad9361_device_t::AD9361_MAX_CLOCK_RATE + ); } //! set the filter bandwidth for the frontend's analog low pass -- cgit v1.2.3