From 949eebc0e456db83bb44da24197a038ea695b65b Mon Sep 17 00:00:00 2001 From: Ashish Chaudhari Date: Thu, 2 Apr 2015 16:57:29 -0700 Subject: b200: Bumped FPGA compat number to 5 --- host/lib/usrp/b200/b200_impl.hpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'host/lib/usrp/b200') diff --git a/host/lib/usrp/b200/b200_impl.hpp b/host/lib/usrp/b200/b200_impl.hpp index cff767b4b..b68293109 100644 --- a/host/lib/usrp/b200/b200_impl.hpp +++ b/host/lib/usrp/b200/b200_impl.hpp @@ -47,7 +47,7 @@ #include "recv_packet_demuxer_3000.hpp" static const boost::uint8_t B200_FW_COMPAT_NUM_MAJOR = 7; static const boost::uint8_t B200_FW_COMPAT_NUM_MINOR = 0; -static const boost::uint16_t B200_FPGA_COMPAT_NUM = 4; +static const boost::uint16_t B200_FPGA_COMPAT_NUM = 5; static const double B200_BUS_CLOCK_RATE = 100e6; static const double B200_DEFAULT_TICK_RATE = 32e6; static const double B200_DEFAULT_FREQ = 100e6; // Hz -- cgit v1.2.3 From 93d909e7c8c4053a05cdc9cb69c886183b4a7f09 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Mon, 6 Apr 2015 14:01:03 -0700 Subject: B200: Change Catalina Reg 0x06 for RX data setup/hold timing issue @ 30.72MHz. Issue #726 --- host/lib/usrp/b200/b200_impl.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'host/lib/usrp/b200') diff --git a/host/lib/usrp/b200/b200_impl.cpp b/host/lib/usrp/b200/b200_impl.cpp index eead07e85..e567ff434 100644 --- a/host/lib/usrp/b200/b200_impl.cpp +++ b/host/lib/usrp/b200/b200_impl.cpp @@ -67,7 +67,7 @@ public: digital_interface_delays_t get_digital_interface_timing() { digital_interface_delays_t delays; delays.rx_clk_delay = 0; - delays.rx_data_delay = 0xF; + delays.rx_data_delay = 0x6; delays.tx_clk_delay = 0; delays.tx_data_delay = 0xF; return delays; -- cgit v1.2.3