From 12dfb97c8efce40494efb35bdd81d06b6f8b9b62 Mon Sep 17 00:00:00 2001 From: Michael West Date: Sun, 15 Mar 2020 01:17:50 -0700 Subject: DUC/DDC: Add variable time increment Sets time increment based on tick rate and sample rate instead of assuming one tick per sample. Defaults to legacy behavior. Minor compat number bumped on DUC and DDC blocks. Signed-off-by: Michael West --- host/lib/rfnoc/ddc_block_control.cpp | 26 ++++++++++++++------------ host/lib/rfnoc/duc_block_control.cpp | 21 ++++++++++++--------- 2 files changed, 26 insertions(+), 21 deletions(-) (limited to 'host/lib/rfnoc') diff --git a/host/lib/rfnoc/ddc_block_control.cpp b/host/lib/rfnoc/ddc_block_control.cpp index abf8d1f7b..99a00dd1d 100644 --- a/host/lib/rfnoc/ddc_block_control.cpp +++ b/host/lib/rfnoc/ddc_block_control.cpp @@ -34,21 +34,22 @@ constexpr uint32_t REG_CHAN_OFFSET = 2048; using namespace uhd::rfnoc; -const uint16_t ddc_block_control::MINOR_COMPAT = 0; +const uint16_t ddc_block_control::MINOR_COMPAT = 1; const uint16_t ddc_block_control::MAJOR_COMPAT = 0; const uint32_t ddc_block_control::RB_COMPAT_NUM = 0; // read this first const uint32_t ddc_block_control::RB_NUM_HB = 8; const uint32_t ddc_block_control::RB_CIC_MAX_DECIM = 16; -const uint32_t ddc_block_control::SR_N_ADDR = 128 * 8; -const uint32_t ddc_block_control::SR_M_ADDR = 129 * 8; -const uint32_t ddc_block_control::SR_CONFIG_ADDR = 130 * 8; -const uint32_t ddc_block_control::SR_FREQ_ADDR = 132 * 8; -const uint32_t ddc_block_control::SR_SCALE_IQ_ADDR = 133 * 8; -const uint32_t ddc_block_control::SR_DECIM_ADDR = 134 * 8; -const uint32_t ddc_block_control::SR_MUX_ADDR = 135 * 8; -const uint32_t ddc_block_control::SR_COEFFS_ADDR = 136 * 8; +const uint32_t ddc_block_control::SR_N_ADDR = 128 * 8; +const uint32_t ddc_block_control::SR_M_ADDR = 129 * 8; +const uint32_t ddc_block_control::SR_CONFIG_ADDR = 130 * 8; +const uint32_t ddc_block_control::SR_FREQ_ADDR = 132 * 8; +const uint32_t ddc_block_control::SR_SCALE_IQ_ADDR = 133 * 8; +const uint32_t ddc_block_control::SR_DECIM_ADDR = 134 * 8; +const uint32_t ddc_block_control::SR_MUX_ADDR = 135 * 8; +const uint32_t ddc_block_control::SR_COEFFS_ADDR = 136 * 8; +const uint32_t ddc_block_control::SR_TIME_INCR_ADDR = 137 * 8; class ddc_block_control_impl : public ddc_block_control { @@ -478,11 +479,12 @@ private: // Rate change = M/N _ddc_reg_iface.poke32(SR_N_ADDR, decim, chan); - // FIXME: - // - eiscat DDC had a real mode, where M needed to be 2 - // - TwinRX had some issues with M == 1 _ddc_reg_iface.poke32(SR_M_ADDR, 1, chan); + // Configure time increment in ticks per M output samples + _ddc_reg_iface.poke32(SR_TIME_INCR_ADDR, + uint32_t(get_tick_rate()/get_output_rate(chan)), chan); + if (cic_decim > 1 and hb_enable == 0) { RFNOC_LOG_WARNING( "The requested decimation is odd; the user should expect passband " diff --git a/host/lib/rfnoc/duc_block_control.cpp b/host/lib/rfnoc/duc_block_control.cpp index 5888e300e..c5dd2ff02 100644 --- a/host/lib/rfnoc/duc_block_control.cpp +++ b/host/lib/rfnoc/duc_block_control.cpp @@ -34,19 +34,20 @@ constexpr uint32_t REG_CHAN_OFFSET = 2048; using namespace uhd::rfnoc; -const uint16_t duc_block_control::MINOR_COMPAT = 0; +const uint16_t duc_block_control::MINOR_COMPAT = 1; const uint16_t duc_block_control::MAJOR_COMPAT = 0; const uint32_t duc_block_control::RB_COMPAT_NUM = 0; // read this first const uint32_t duc_block_control::RB_NUM_HB = 8; const uint32_t duc_block_control::RB_CIC_MAX_INTERP = 16; -const uint32_t duc_block_control::SR_N_ADDR = 128 * 8; -const uint32_t duc_block_control::SR_M_ADDR = 129 * 8; -const uint32_t duc_block_control::SR_CONFIG_ADDR = 130 * 8; -const uint32_t duc_block_control::SR_INTERP_ADDR = 131 * 8; -const uint32_t duc_block_control::SR_FREQ_ADDR = 132 * 8; -const uint32_t duc_block_control::SR_SCALE_IQ_ADDR = 133 * 8; +const uint32_t duc_block_control::SR_N_ADDR = 128 * 8; +const uint32_t duc_block_control::SR_M_ADDR = 129 * 8; +const uint32_t duc_block_control::SR_CONFIG_ADDR = 130 * 8; +const uint32_t duc_block_control::SR_INTERP_ADDR = 131 * 8; +const uint32_t duc_block_control::SR_FREQ_ADDR = 132 * 8; +const uint32_t duc_block_control::SR_SCALE_IQ_ADDR = 133 * 8; +const uint32_t duc_block_control::SR_TIME_INCR_ADDR = 137 * 8; class duc_block_control_impl : public duc_block_control { @@ -464,10 +465,12 @@ private: // Rate change = M/N, where N = 1 _duc_reg_iface.poke32(SR_M_ADDR, interp, chan); - // FIXME: - // - TwinRX had some issues with N == 1 _duc_reg_iface.poke32(SR_N_ADDR, 1, chan); + // Configure time increment in ticks per M output samples + _duc_reg_iface.poke32(SR_TIME_INCR_ADDR, + uint32_t(get_tick_rate()/get_output_rate(chan)), chan); + if (cic_interp > 1 and hb_enable == 0) { RFNOC_LOG_WARNING( "The requested interpolation is odd; the user should expect passband " -- cgit v1.2.3