From eff796f64b1e05036b7eca2185f53528a0de870b Mon Sep 17 00:00:00 2001
From: Martin Braun <martin.braun@ettus.com>
Date: Mon, 22 Jan 2018 09:47:21 -0800
Subject: rfnoc: Factored out FPGA compat check

- Applied changes to DUC and DDC blocks
- Fixed minor formatting
---
 host/lib/include/uhdlib/utils/compat_check.hpp | 30 ++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 host/lib/include/uhdlib/utils/compat_check.hpp

(limited to 'host/lib/include')

diff --git a/host/lib/include/uhdlib/utils/compat_check.hpp b/host/lib/include/uhdlib/utils/compat_check.hpp
new file mode 100644
index 000000000..acdf97340
--- /dev/null
+++ b/host/lib/include/uhdlib/utils/compat_check.hpp
@@ -0,0 +1,30 @@
+//
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: GPL-3.0
+//
+
+#ifndef INCLUDED_UHDLIB_UTILS_COMPATCHECK_HPP
+#define INCLUDED_UHDLIB_UTILS_COMPATCHECK_HPP
+
+#include <cstddef>
+#include <string>
+
+namespace uhd {
+
+    /*! Checks for FPGA compatibility, and throws an exception on mismatch.
+     *
+     * \throws uhd::runtime_error on mismatch.
+     */
+    void assert_fpga_compat(
+        const size_t uhd_major,
+        const size_t uhd_minor,
+        const uint64_t fpga_compat,
+        const std::string& fpga_component,
+        const std::string& log_component,
+        const bool fail_on_minor_behind=false
+    );
+
+} /* namespace uhd */
+
+#endif /* INCLUDED_UHDLIB_UTILS_COMPATCHECK_HPP */
-- 
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