From 1f6f07b3d42dc763ff1a9ba75fb15463bb338ae0 Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Wed, 12 Oct 2011 12:32:24 -0700 Subject: Default adf4350 PLL to fast-lock mode. --- host/lib/ic_reg_maps/gen_adf4350_regs.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'host/lib/ic_reg_maps') diff --git a/host/lib/ic_reg_maps/gen_adf4350_regs.py b/host/lib/ic_reg_maps/gen_adf4350_regs.py index e97772843..bccdb2edf 100755 --- a/host/lib/ic_reg_maps/gen_adf4350_regs.py +++ b/host/lib/ic_reg_maps/gen_adf4350_regs.py @@ -55,7 +55,7 @@ low_noise_and_spur 2[29:30] 3 low_noise, reserved0, reserved1, low ## address 3 ######################################################################## clock_divider_12_bit 3[3:14] 0 -clock_div_mode 3[15:16] 0 clock_divider_off, fast_lock, resync_enable, reserved +clock_div_mode 3[15:16] 1 clock_divider_off, fast_lock, resync_enable, reserved ##reserved 3[17] 0 cycle_slip_reduction 3[18] 0 disabled, enabled ##reserved 3[19:20] 0 -- cgit v1.2.3