From 4b18ab84921a88f0448632355e8165ecaff4ed6f Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 1 May 2011 09:38:30 -0700 Subject: uhd: fixed typo in tune request/result inter_freq -> rf_freq For some reason, the code said intermediate frequency, however, it was used and treated as RF frequency. It was always intended to be the RF frequency, but was misnamed due to a cognitive distortion. --- host/include/uhd/types/tune_request.hpp | 12 ++++++------ host/include/uhd/types/tune_result.hpp | 10 +++------- 2 files changed, 9 insertions(+), 13 deletions(-) (limited to 'host/include') diff --git a/host/include/uhd/types/tune_request.hpp b/host/include/uhd/types/tune_request.hpp index b59f37c2e..9c498bfe9 100644 --- a/host/include/uhd/types/tune_request.hpp +++ b/host/include/uhd/types/tune_request.hpp @@ -32,7 +32,7 @@ namespace uhd{ struct UHD_API tune_request_t{ /*! * Make a new tune request for a particular center frequency. - * Use an automatic policy for the intermediate and DSP frequency + * Use an automatic policy for the RF and DSP frequency * to tune the chain as close as possible to the target frequency. * \param target_freq the target frequency in Hz */ @@ -40,7 +40,7 @@ namespace uhd{ /*! * Make a new tune request for a particular center frequency. - * Use a manual policy for the intermediate frequency, + * Use a manual policy for the RF frequency, * and an automatic policy for the DSP frequency, * to tune the chain as close as possible to the target frequency. * \param target_freq the target frequency in Hz @@ -65,16 +65,16 @@ namespace uhd{ double target_freq; /*! - * The policy for the intermediate frequency. + * The policy for the RF frequency. * Automatic behavior: the target frequency + default LO offset. */ - policy_t inter_freq_policy; + policy_t rf_freq_policy; /*! - * The intermediate frequency in Hz. + * The RF frequency in Hz. * Set when the policy is set to manual. */ - double inter_freq; + double rf_freq; /*! * The policy for the DSP frequency. diff --git a/host/include/uhd/types/tune_result.hpp b/host/include/uhd/types/tune_result.hpp index 9eebc161a..e51473085 100644 --- a/host/include/uhd/types/tune_result.hpp +++ b/host/include/uhd/types/tune_result.hpp @@ -24,15 +24,11 @@ namespace uhd{ /*! - * The tune result struct holds result of a 2-phase tuning: - * The struct hold the result of tuning the dboard as - * the target and actual intermediate frequency. - * The struct hold the result of tuning the DSP as - * the target and actual digital converter frequency. + * The tune result struct holds result of a 2-phase tuning. */ struct UHD_API tune_result_t{ - double target_inter_freq; - double actual_inter_freq; + double target_rf_freq; + double actual_rf_freq; double target_dsp_freq; double actual_dsp_freq; -- cgit v1.2.3 From b4fc0d61bb6cbd1a5614745bab9aeb0abc22cb6f Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 3 May 2011 13:35:15 -0700 Subject: usrp2: added REF_MIMO and PPS_MIMO for USRP2 clock config Basically, one can tell a MIMO master to lock to MIMO ref and/or time. This is an alternative to the mimo_mode=slave/master device args. When using this alternative, one should always set the mimo_mode to maser. When in master mode, any clock config settings can be used. When in slave mode, the clock config setting are forced to MIMO_REF/PPS --- host/include/uhd/types/clock_config.hpp | 2 ++ host/lib/usrp/usrp2/mboard_impl.cpp | 38 ++++++++++++++++++++------------- 2 files changed, 25 insertions(+), 15 deletions(-) (limited to 'host/include') diff --git a/host/include/uhd/types/clock_config.hpp b/host/include/uhd/types/clock_config.hpp index 577416d77..24bd96d14 100644 --- a/host/include/uhd/types/clock_config.hpp +++ b/host/include/uhd/types/clock_config.hpp @@ -44,10 +44,12 @@ namespace uhd{ REF_AUTO = int('a'), //automatic (device specific) REF_INT = int('i'), //internal reference REF_SMA = int('s'), //external sma port + REF_MIMO = int('m'), //reference from mimo cable } ref_source; enum pps_source_t { PPS_INT = int('i'), //there is no internal PPS_SMA = int('s'), //external sma port + PPS_MIMO = int('m'), //time sync from mimo cable } pps_source; enum pps_polarity_t { PPS_NEG = int('n'), //negative edge diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index ae098dba6..d4ae27763 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -191,9 +191,25 @@ usrp2_mboard_impl::~usrp2_mboard_impl(void){ void usrp2_mboard_impl::update_clock_config(void){ boost::uint32_t pps_flags = 0; + //slave mode overrides clock config settings + if (not _mimo_clocking_mode_is_master){ + _clock_config.ref_source = clock_config_t::REF_MIMO; + _clock_config.pps_source = clock_config_t::PPS_MIMO; + } + //translate pps source enums switch(_clock_config.pps_source){ - case clock_config_t::PPS_SMA: pps_flags |= U2_FLAG_TIME64_PPS_SMA; break; + case clock_config_t::PPS_MIMO: + _iface->poke32(_iface->regs.time64_mimo_sync, + (1 << 8) | (mimo_clock_sync_delay_cycles & 0xff) + ); + break; + + case clock_config_t::PPS_SMA: + _iface->poke32(_iface->regs.time64_mimo_sync, 0); + pps_flags |= U2_FLAG_TIME64_PPS_SMA; + break; + default: throw uhd::value_error("unhandled clock configuration pps source"); } @@ -214,6 +230,7 @@ void usrp2_mboard_impl::update_clock_config(void){ switch(_clock_config.ref_source){ case clock_config_t::REF_INT : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x12); break; case clock_config_t::REF_SMA : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x1C); break; + case clock_config_t::REF_MIMO: _iface->poke32(_iface->regs.misc_ctrl_clock, 0x15); break; default: throw uhd::value_error("unhandled clock configuration reference source"); } _clock_ctrl->enable_external_ref(true); //USRP2P has an internal 10MHz TCXO @@ -224,6 +241,7 @@ void usrp2_mboard_impl::update_clock_config(void){ switch(_clock_config.ref_source){ case clock_config_t::REF_INT : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x10); break; case clock_config_t::REF_SMA : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x1C); break; + case clock_config_t::REF_MIMO: _iface->poke32(_iface->regs.misc_ctrl_clock, 0x15); break; default: throw uhd::value_error("unhandled clock configuration reference source"); } _clock_ctrl->enable_external_ref(_clock_config.ref_source != clock_config_t::REF_INT); @@ -232,12 +250,11 @@ void usrp2_mboard_impl::update_clock_config(void){ case usrp2_iface::USRP_NXXX: break; } - //Handle the serdes clocking based on master/slave mode: - // - Masters always drive the clock over serdes. - // - Slaves always lock to this serdes clock. - // - Slaves lock their time over the serdes. + //masters always drive the clock over serdes + _clock_ctrl->enable_mimo_clock_out(_mimo_clocking_mode_is_master); + + //set the mimo clock delay over the serdes if (_mimo_clocking_mode_is_master){ - _clock_ctrl->enable_mimo_clock_out(true); switch(_iface->get_rev()){ case usrp2_iface::USRP_N200: case usrp2_iface::USRP_N210: @@ -250,15 +267,6 @@ void usrp2_mboard_impl::update_clock_config(void){ default: break; //not handled } - _iface->poke32(_iface->regs.time64_mimo_sync, 0); - } - else{ - _iface->poke32(_iface->regs.misc_ctrl_clock, 0x15); - _clock_ctrl->enable_external_ref(true); - _clock_ctrl->enable_mimo_clock_out(false); - _iface->poke32(_iface->regs.time64_mimo_sync, - (1 << 8) | (mimo_clock_sync_delay_cycles & 0xff) - ); } } -- cgit v1.2.3