From 1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4 Mon Sep 17 00:00:00 2001
From: Wade Fife <wade.fife@ettus.com>
Date: Fri, 19 Jun 2020 15:40:12 -0500
Subject: fpga: rfnoc: Add Signal Generator RFNoC block

---
 host/include/uhd/rfnoc/blocks/siggen.yml | 55 ++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 host/include/uhd/rfnoc/blocks/siggen.yml

(limited to 'host/include')

diff --git a/host/include/uhd/rfnoc/blocks/siggen.yml b/host/include/uhd/rfnoc/blocks/siggen.yml
new file mode 100644
index 000000000..78a778479
--- /dev/null
+++ b/host/include/uhd/rfnoc/blocks/siggen.yml
@@ -0,0 +1,55 @@
+schema: rfnoc_modtool_args
+module_name: siggen
+version: 1.0
+rfnoc_version: 1.0
+chdr_width: 64
+noc_id: 0x51663110
+makefile_srcs: "${fpga_lib_dir}/blocks/rfnoc_block_siggen/Makefile.srcs"
+
+parameters:
+  NUM_PORTS: 1
+
+clocks:
+  - name: rfnoc_chdr
+    freq: "[]"
+  - name: rfnoc_ctrl
+    freq: "[]"
+  - name: ce
+    freq: "[]"
+
+control:
+  sw_iface: nocscript
+  fpga_iface: ctrlport
+  interface_direction: slave
+  fifo_depth: 32
+  clk_domain: ce
+  ctrlport:
+    byte_mode: False
+    timed: False
+    has_status: False
+
+data:
+  fpga_iface: axis_data
+  clk_domain: ce
+  inputs:
+    unused:
+      item_width: 32
+      nipc: 1
+      info_fifo_depth: 1
+      payload_fifo_depth: 1
+      format: sc16
+      mdata_sig: ~
+  outputs:
+    out:
+      num_ports: NUM_PORTS
+      item_width: 32
+      nipc: 1
+      info_fifo_depth: 32
+      payload_fifo_depth: 32
+      sideband_at_end: 0
+      format: sc16
+      mdata_sig: ~
+
+registers:
+
+properties:
-- 
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