From 11a20a10c78d494036ef2edf4d6197bbb59dd3fc Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Tue, 7 Sep 2021 08:52:03 -0500 Subject: examples: Show how to use in-tree Verilog header Adds example showing how to `include an in-tree Verilog header file in the rfnoc_block_gain example. --- .../fpga/rfnoc_block_gain/rfnoc_block_gain.v | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'host/examples/rfnoc-example/fpga') diff --git a/host/examples/rfnoc-example/fpga/rfnoc_block_gain/rfnoc_block_gain.v b/host/examples/rfnoc-example/fpga/rfnoc_block_gain/rfnoc_block_gain.v index 6f050e8bc..c6f0bcfbb 100644 --- a/host/examples/rfnoc-example/fpga/rfnoc_block_gain/rfnoc_block_gain.v +++ b/host/examples/rfnoc-example/fpga/rfnoc_block_gain/rfnoc_block_gain.v @@ -61,6 +61,23 @@ module rfnoc_block_gain #( input wire m_rfnoc_ctrl_tready ); + // These are examples of how to include an in-tree header file. UHD_FPGA_DIR + // is defined automatically and can be referenced as needed. Tools vary + // somewhat in how they support using macros in `include statements. + // + // This works in Vivado: + // + // `include `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" + // + // Some tools allow this: + // + // `define INCLUDE_UHD_FILE(REL_PATH) `"`UHD_FPGA_DIR/REL_PATH`" + // `include `INCLUDE_UHD_FILE(usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh) + // + // This should work in most tools: + `define RFNOC_CHDR_UTILS_PATH `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" + `include `RFNOC_CHDR_UTILS_PATH + //--------------------------------------------------------------------------- // Signal Declarations //--------------------------------------------------------------------------- -- cgit v1.2.3