From dfacf7d9963b58d77b0c173f10d3cd7623f970e3 Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Thu, 8 Feb 2018 22:46:29 +0100 Subject: docs: Add N310 FPGA reg map to manual --- host/docs/usrp_n3xx.dox | 151 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) (limited to 'host/docs') diff --git a/host/docs/usrp_n3xx.dox b/host/docs/usrp_n3xx.dox index 8d37d9fa3..a03b69c76 100644 --- a/host/docs/usrp_n3xx.dox +++ b/host/docs/usrp_n3xx.dox @@ -499,5 +499,156 @@ Storing data on the EEPROM is done by loading a uhd::eeprom_map_t object into the property tree. On writing this property, the driver code will serialize the map into a binary representation that can be stored on the EEPROM. +\subsection n3xx_mg_regmap FPGA Register Map + +The following tables describe how FPGA registers are mapped into the PS. +This is for reference only, most users will not even have to know about this table. + + +AXI Slave | Address Range | UIO Label | Description +----------|-----------------------|------------------|----------------------------------- +Slave 0 | 4000_0000 - 4000_3fff | - | Ethernet DMA SFP0 +Slave 1 | 4000_4000 - 4000_4fff | misc-enet-regs0 | Ethernet registers SFP0 +Slave 2 | 4000_8000 - 4000_bfff | - | Ethernet DMA SFP1 +Slave 3 | 4000_c000 - 4000_cfff | misc-enet-regs1 | Ethernet registers SFP1 +Slave 4 | 4001_0000 - 4001_3fff | mboard-regs | Motherboard control +Slave 5 | 4001_4000 - 4001_41ff | dboard-regs0 | Daughterboard control, slot A +Slave 6 | 4001_8000 - 4001_bfff | dboard-regs1 | Daughterboard control, slot B + + + + +
N310 Register Map
AXI Slave Module Address Name Read/Write Description +
Slave 0 axi_eth_dma0 4000_0000 - 4000_4fff Ethernet DMA RW See Linux Driver +
Slave 1 n3xx_mgt_io_core 4000_4000 PORT_INFO RO SFP port information +
[31:24] COMPAT_NUM RO - +
[23:18] 6'h0 RO - +
[17] activity RO - +
[16] link_up RO - +
[15:8] mgt_protocol RO 0 - None, 1 - 1G, 2 - XG, 3 - Aurora +
[7:0] PORTNUM RO - +
n3xx_mgt_io_core 4000_4004 MAC_CTRL_STATUS RW Control 10gE and Aurora mac +
[0] ctrl_tx_enable (PROTOCOL = "10GbE")RW- +
[0] bist_checker_en (PROTOCOL = "Aurora")RW- +
[1] bist_gen_en RW - +
[2] bist_loopback_enRW - +
[8:3] bist_gen_rate RW - +
[9] phy_areset RW - +
[10] mac_clear RW - +
n3xx_mgt_io_core 4000_4008 PHY_CTRL_STATUS RW Phy reset control +
n3xx_mgt_io_core 4000_400C MAC_LED_CTL RW Used by ethtool to indicate port +
[1] identify_enable RW - +
[0] identify_value RW - +
mdio_master 4000_4010 MDIO_DATA RW - +
4000_4014 MDIO_ADDR RW - +
4000_4018 MDIO_OP RW - +
4000_401C MDIO_CTRL_STATUSRW - +
n3xx_mgt_io_core 4000_4020 AURORA_OVERUNS RO - +
4000_4024 AURORA_CHECKSUM_ERRORSRO - +
4000_4028 AURORA_BIST_CHECKER_SAMPSRO - +
4000_402C AURORA_BIST_CHECKER_ERRORSRO- +
eth_switch 4000_5000 MAC_LSB RW Device MAC LSB +
4000_5004 MAC_MSB RW Device MAC MSB +
4000_6000 IP RW Device IP +
4000_6004 PORT1, PORT0 RW Device UDP port +
eth_dispatch 4000_6008 [1] ndest, [0] bcastRW Enable Crossover +
4000_600c [1] my_icmp_type, [0] my_icmp_code +
eth_switch 4000_6010 BRIDGE_MAC_LSB Bridge SFP ports in ARM +
4000_6014 BRIDGE_MAC_MSB - +
4000_6018 BRIDGE_IP - +
4000_601c BRIDGE_PORT1, BRIDGE_PORT0 - +
4000_6020 BRIDGE_EN - +
chdr_eth_framer 4000_6108 onwards LOCAL_DST_IP W Destination IP, MAC, UDP for Outgoing Packet for 256 SIDs +
4000_6208 onwards LOCAL_DST_UDP_MAC_MSBW Destination MAC for outgoing packets (MSB) +
4000_6308 onwards LOCAL_DST_MAC_LSBW Destination MAC for outgoing packets (LSB) +
4000_7000 onwards REMOTE_DST_IP W Destination IP, MAC, UDP for Outgoing Packet for 16 local addrs +
4000_7400 onwards REMOTE_DST_UDP_MAC_HIW Destination MAC (MSB) +
4000_7800 onwards REMOTE_DST_MAC_LOW Destination MAC (LSB) + +
Slave 2 axi_eth_dma1 4000_8000 - Same as Slave 0, different base address + +
Slave 3 n3xx_mgt_io_core 4000_c001 - 4000_cfff - - Same as Slave 1, different base address +
eth_dispatch 4000_d000 - 4000_dfff - - Same as Slave 1, different base address +
eth_switch 4000_e000 - 4000_efff - - Same as Slave 1, different base address + +
Slave 4 n310_core 4001_0000 COMPAT_NUM R FPGA Compat Number +
[31:16] Major RO - +
[15:0] Minor RO - +
4001_0004 DATESTAMP RO - +
4001_0008 GIT_HASH RO - +
4001_000C SCRATCH RO - +
4001_0010 NUM_CE RO Number of Computation Engines (RFNoC Blocks) +
4001_0014 NUM_IO_CE RO Number of fixed IO CEs - Radios + DMA Fifo +
4001_0018 CLOCK_CTRL +
[0] pps select (internal 10 MHz)RWOne-hot encoded pps_select to use the external PPS input. +
[1] pps select (internal 25 MHz)RWOne-hot encoded pps_select to use the internally generated PPS with a 10 MHz ref_clk. +
[2] pps select (external)RW One-hot encoded pps_select to use the internally generated PPS with a 25 MHz ref_clk. +
[3] pps select (GPSDO)RW One-hot encoded pps_select to use the PPS from the GPSDO input to the FPGA. +
[4] pps output enableRW +
[8] ref clk mmcm resetWO - +
[9] ref clk mmcm lockedRO - +
[12] meas clk mmcm resetWO - +
[13] meas clk mmcm lockedRO - +
4001_001C XADC_READBACK RO - +
[11:0] FPGA temperatureRO +
4001_0020 BUS_CLK_RATE RO - +
4001_0024 BUS_CLK_COUNT RO - +
axi_crossbar 4001_1010 XBAR_VERSION RO See crossbar kernel driver +
4001_1014 XBAR_NUM_PORTS RO See crossbar kernel driver +
4001_1018 LOCAL_ADDR RW See crossbar kernel driver +
4001_1020 remote_offset WO XBAR settings reg +
4001_1420 local_offset WO XBAR settings reg +
n3xx_mgt_io_core (NPIO0) 4001_0200 PORT_INFO RO +
4001_0204 MAC_CTRL_STATUS RW +
4001_0208 PHY_CTRL_STATUS RW +
4001_0220 AURORA_OVERUNS RO +
4001_0224 AURORA_CHECKSUM_ERRORSRO +
4001_0228 AURORA_BIST_CHECKER_SAMPSRO +
4001_022c AURORA_BIST_CHECKER_ERRORSRO +
n3xx_mgt_io_core (NPIO1) 4001_0240 PORT_INFO RO +
4001_0244 MAC_CTRL_STATUS RW +
4001_0248 PHY_CTRL_STATUS RW +
4001_0260 AURORA_OVERUNS RO +
4001_0264 AURORA_CHECKSUM_ERRORSRO +
4001_0268 AURORA_BIST_CHECKER_SAMPSRO +
4001_026c AURORA_BIST_CHECKER_ERRORSRO +
n3xx_mgt_io_core (QSFP0) 4001_0280 PORT_INFORO +
4001_0284 MAC_CTRL_STATUSRW +
4001_0288 PHY_CTRL_STATUSRW +
4001_02a0 AURORA_OVERUNSRO +
4001_02a4 AURORA_CHECKSUM_ERRORSRO +
4001_02a8 AURORA_BIST_CHECKER_SAMPSRO +
4001_02ac AURORA_BIST_CHECKER_ERRORSRO +
n3xx_mgt_io_core (QSFP1) 4001_02c0 PORT_INFORO +
4001_02c4 MAC_CTRL_STATUSRW +
4001_02c8 PHY_CTRL_STATUSRW +
4001_02e0 AURORA_OVERUNSRO +
4001_02e4 AURORA_CHECKSUM_ERRORSRO +
4001_02e8 AURORA_BIST_CHECKER_SAMPSRO +
4001_02ec AURORA_BIST_CHECKER_ERRORSRO +
n3xx_mgt_io_core (QSFP2) 4001_0300 PORT_INFORO +
4001_0304 MAC_CTRL_STATUSRW +
4001_0308 PHY_CTRL_STATUSRW +
4001_0320 AURORA_OVERUNSRO +
4001_0324 AURORA_CHECKSUM_ERRORSRO +
4001_0328 AURORA_BIST_CHECKER_SAMPSRO +
4001_032c AURORA_BIST_CHECKER_ERRORSRO +
n3xx_mgt_io_core (QSFP3) 4001_0340 PORT_INFORO +
4001_0344 MAC_CTRL_STATUSRW +
4001_0348 PHY_CTRL_STATUSRW +
4001_0360 AURORA_OVERUNSRO +
4001_0364 AURORA_CHECKSUM_ERRORSRO +
4001_0368 AURORA_BIST_CHECKER_SAMPSRO +
4001_036C AURORA_BIST_CHECKER_ERRORSRO + +
Slave 5 4001_40004001_41FFClockingsee Clocking regmap +
4001_42004001_43FFSyncsee Sync regmap +
4001_44004001_45FFopenopenopen +
4001_46004001_47FFDaughterboard see Daughterboard regmap (EISCAT) +
4001_60004001_6FFFJESD Core 0see JESD regmap (EISCAT) +
4001_70004001_7FFFJESD Core 1see JESD regmap (EISCAT) +
Slave 6 4001_8000 - 4001_bfff see above -same as Slave 5 +
+ */ // vim:ft=doxygen: -- cgit v1.2.3