From c5207ff2834c2ff9012d59b94e29d90573e9277f Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 17 Jul 2012 16:32:59 -0700 Subject: docs: added comparative features list at top of each --- host/docs/CMakeLists.txt | 6 +- host/docs/index.rst | 6 +- host/docs/usrp1.rst | 11 ++++ host/docs/usrp2.rst | 18 +++++- host/docs/usrp_b100.rst | 101 +++++++++++++++++++++++++++++++ host/docs/usrp_b1xx.rst | 87 --------------------------- host/docs/usrp_e1x0.rst | 150 +++++++++++++++++++++++++++++++++++++++++++++++ host/docs/usrp_e1xx.rst | 135 ------------------------------------------ 8 files changed, 285 insertions(+), 229 deletions(-) create mode 100644 host/docs/usrp_b100.rst delete mode 100644 host/docs/usrp_b1xx.rst create mode 100644 host/docs/usrp_e1x0.rst delete mode 100644 host/docs/usrp_e1xx.rst (limited to 'host/docs') diff --git a/host/docs/CMakeLists.txt b/host/docs/CMakeLists.txt index e393a79f0..f56358ca9 100644 --- a/host/docs/CMakeLists.txt +++ b/host/docs/CMakeLists.txt @@ -1,5 +1,5 @@ # -# Copyright 2010-2011 Ettus Research LLC +# Copyright 2010-2012 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -33,8 +33,8 @@ SET(manual_sources transport.rst usrp1.rst usrp2.rst - usrp_b1xx.rst - usrp_e1xx.rst + usrp_b100.rst + usrp_e1x0.rst ) ######################################################################## diff --git a/host/docs/index.rst b/host/docs/index.rst index 8649e7ce3..00b1c9618 100644 --- a/host/docs/index.rst +++ b/host/docs/index.rst @@ -25,9 +25,9 @@ Application Notes * `Firmware and FPGA Image Notes <./images.html>`_ * `USRP1 Application Notes <./usrp1.html>`_ * `USRP2 Application Notes <./usrp2.html>`_ -* `USRP-N2XX Series Application Notes <./usrp2.html>`_ -* `USRP-B1XX Series Application Notes <./usrp_b1xx.html>`_ -* `USRP-E1XX Series Application Notes <./usrp_e1xx.html>`_ +* `USRP-N2X0 Series Application Notes <./usrp2.html>`_ +* `USRP-B100 Series Application Notes <./usrp_b100.html>`_ +* `USRP-E1X0 Series Application Notes <./usrp_e1x0.html>`_ * `Daughterboard Application Notes <./dboards.html>`_ * `Transport Application Notes <./transport.html>`_ * `Synchronization Application Notes <./sync.html>`_ diff --git a/host/docs/usrp1.rst b/host/docs/usrp1.rst index 6242ccb6a..c1fdec146 100644 --- a/host/docs/usrp1.rst +++ b/host/docs/usrp1.rst @@ -4,6 +4,17 @@ UHD - USRP1 Application Notes .. contents:: Table of Contents +------------------------------------------------------------------------ +Comparative features list +------------------------------------------------------------------------ + +* 2 transceiver card slots +* 2 RX DDC chains in FPGA +* 2 TX DUC chains in FPGA (no TX CORDIC -> uses DAC) +* 64 MHz fixed clock rate +* sc16 sample modes +* sc8 sample mode - RX only + ------------------------------------------------------------------------ Specify a Non-standard Image ------------------------------------------------------------------------ diff --git a/host/docs/usrp2.rst b/host/docs/usrp2.rst index d70a08cd7..8e9aa6d50 100644 --- a/host/docs/usrp2.rst +++ b/host/docs/usrp2.rst @@ -1,9 +1,25 @@ ======================================================================== -UHD - USRP2 and N Series Application Notes +UHD - USRP2 and N2X0 Series Application Notes ======================================================================== .. contents:: Table of Contents +------------------------------------------------------------------------ +Comparative features list +------------------------------------------------------------------------ + +* 1 transceiver card slot +* 2 RX DDC chains in FPGA +* 1 TX DUC chain in FPGA +* Timed commands in FPGA (N2x0 only) +* Timed sampling in FPGA +* External PPS reference +* External 10MHz reference +* MIMO cable shared reference +* Fixed 100 MHz clock rate +* Internal GPSDO option (N2x0 only) +* sc8 and sc16 sample modes + ------------------------------------------------------------------------ Load the Images onto the SD card (USRP2 only) ------------------------------------------------------------------------ diff --git a/host/docs/usrp_b100.rst b/host/docs/usrp_b100.rst new file mode 100644 index 000000000..cdb853b61 --- /dev/null +++ b/host/docs/usrp_b100.rst @@ -0,0 +1,101 @@ +======================================================================== +UHD - USRP-B100 Series Application Notes +======================================================================== + +.. contents:: Table of Contents + +------------------------------------------------------------------------ +Comparative features list +------------------------------------------------------------------------ + +* 1 transceiver card slot +* 1 RX DDC chain in FPGA +* 1 TX DUC chain in FPGA +* Timed commands in FPGA +* Timed sampling in FPGA +* External PPS reference +* External 10MHz reference +* Configurable clock rate (defaults 64 MHz) +* sc8 and sc16 sample modes + +------------------------------------------------------------------------ +Specify a Non-standard Image +------------------------------------------------------------------------ +UHD will automatically select the USRP B-Series images from the installed images package. +The image selection can be overridden with the **--fpga=** and **--fw=** device address parameters. + +Example device address string representations to specify non-standard images: + +:: + + fpga=usrp_b100_fpga_firmware.bin + + -- OR -- + + fw=usrp_b100_fw_firmware.ihx + +------------------------------------------------------------------------ +Changing the Master Clock Rate +------------------------------------------------------------------------ +The master clock rate of the USRP embedded feeds both the FPGA DSP and the codec chip. +Hundreds of rates between 32MHz and 64MHz are available. +A few notable rates are: + +* **64MHz:** maximum rate of the codec chip +* **61.44MHz:** good for UMTS/WCDMA applications +* **52Mhz:** good for GSM applications + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Set 61.44MHz - uses external VCXO +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +To use the 61.44MHz clock rate, the USRP embedded will require one jumper to be moved, +and X4 must be populated with a 61.44 MHz oscillator. + +* **J15** is a three pin header, move the jumper to (pin1, pin2) +* **357LB3I061M4400** is the recommended oscillator for X4 + +**Note:** See instructions below to communicate the desired clock rate into UHD. + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Set other rates - uses internal VCO +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +To use other clock rates, the jumper will need to be in the default position. + +* **J15** is a three pin header, move the jumper to (pin2, pin3) + +To communicate the desired clock rate into UHD, +specify the a special device address argument, +where the key is **master_clock_rate** and the value is a rate in Hz. +Example: +:: + + uhd_usrp_probe --args="master_clock_rate=52e6" + +------------------------------------------------------------------------ +Hardware setup notes +------------------------------------------------------------------------ + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Front panel LEDs +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +The LEDs on the front panel can be useful in debugging hardware and software issues. +The LEDs reveal the following about the state of the device: + +* **LED A:** transmitting +* **LED B:** fpga loaded +* **LED C:** receiving +* **LED D:** fpga loaded +* **LED E:** reference lock +* **LED F:** board power + +------------------------------------------------------------------------ +Miscellaneous +------------------------------------------------------------------------ + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Available Sensors +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +The following sensors are available; +they can be queried through the API. + +* **ref_locked:** clock reference locked (internal/external) diff --git a/host/docs/usrp_b1xx.rst b/host/docs/usrp_b1xx.rst deleted file mode 100644 index 08eeb441b..000000000 --- a/host/docs/usrp_b1xx.rst +++ /dev/null @@ -1,87 +0,0 @@ -======================================================================== -UHD - USRP-B1XX Series Application Notes -======================================================================== - -.. contents:: Table of Contents - ------------------------------------------------------------------------- -Specify a Non-standard Image ------------------------------------------------------------------------- -UHD will automatically select the USRP B-Series images from the installed images package. -The image selection can be overridden with the **--fpga=** and **--fw=** device address parameters. - -Example device address string representations to specify non-standard images: - -:: - - fpga=usrp_b100_fpga_firmware.bin - - -- OR -- - - fw=usrp_b100_fw_firmware.ihx - ------------------------------------------------------------------------- -Changing the Master Clock Rate ------------------------------------------------------------------------- -The master clock rate of the USRP embedded feeds both the FPGA DSP and the codec chip. -Hundreds of rates between 32MHz and 64MHz are available. -A few notable rates are: - -* **64MHz:** maximum rate of the codec chip -* **61.44MHz:** good for UMTS/WCDMA applications -* **52Mhz:** good for GSM applications - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Set 61.44MHz - uses external VCXO -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -To use the 61.44MHz clock rate, the USRP embedded will require one jumper to be moved, -and X4 must be populated with a 61.44 MHz oscillator. - -* **J15** is a three pin header, move the jumper to (pin1, pin2) -* **357LB3I061M4400** is the recommended oscillator for X4 - -**Note:** See instructions below to communicate the desired clock rate into UHD. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Set other rates - uses internal VCO -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -To use other clock rates, the jumper will need to be in the default position. - -* **J15** is a three pin header, move the jumper to (pin2, pin3) - -To communicate the desired clock rate into UHD, -specify the a special device address argument, -where the key is **master_clock_rate** and the value is a rate in Hz. -Example: -:: - - uhd_usrp_probe --args="master_clock_rate=52e6" - ------------------------------------------------------------------------- -Hardware setup notes ------------------------------------------------------------------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Front panel LEDs -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The LEDs on the front panel can be useful in debugging hardware and software issues. -The LEDs reveal the following about the state of the device: - -* **LED A:** transmitting -* **LED B:** fpga loaded -* **LED C:** receiving -* **LED D:** fpga loaded -* **LED E:** reference lock -* **LED F:** board power - ------------------------------------------------------------------------- -Miscellaneous ------------------------------------------------------------------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Available Sensors -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The following sensors are available; -they can be queried through the API. - -* **ref_locked:** clock reference locked (internal/external) diff --git a/host/docs/usrp_e1x0.rst b/host/docs/usrp_e1x0.rst new file mode 100644 index 000000000..9373e5255 --- /dev/null +++ b/host/docs/usrp_e1x0.rst @@ -0,0 +1,150 @@ +======================================================================== +UHD - USRP-E1X0 Series Application Notes +======================================================================== + +.. contents:: Table of Contents + +------------------------------------------------------------------------ +Comparative features list +------------------------------------------------------------------------ + +* 1 transceiver card slot +* 2 RX DDC chains in FPGA +* 1 TX DUC chain in FPGA +* Timed commands in FPGA +* Timed sampling in FPGA +* Internal PPS reference +* Internal 10MHz reference +* Configurable clock rate (defaults 64 MHz) +* Internal GPSDO option +* sc8 and sc16 sample modes + +------------------------------------------------------------------------ +Specify a Non-standard Image +------------------------------------------------------------------------ +UHD will automatically select the USRP-Embedded FPGA image from the +installed images package. The FPGA image selection can be overridden with the +**--fpga=** device address parameter. + +Example device address string representations to specify non-standard FPGA +image: + +:: + + fpga=usrp_e100_custom.bin + +------------------------------------------------------------------------ +Changing the Master Clock Rate +------------------------------------------------------------------------ +The master clock rate of the USRP-Embedded feeds both the FPGA DSP and the codec +chip. Hundreds of rates between 32MHz and 64MHz are available. A few notable +rates are: + +* **64MHz:** maximum rate of the codec chip +* **61.44MHz:** good for UMTS/WCDMA applications +* **52Mhz:** good for GSM applications + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Set 61.44MHz - uses external VCXO +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +To use the 61.44MHz clock rate with the USRP-Embedded, two jumpers must be moved +on the device. + +* **J16** is a two pin header; remove the jumper (or leave it on pin1 only). +* **J15** is a three pin header; move the jumper to (pin1, pin2). + +**Note:** See instructions below to communicate the desired clock rate UHD. + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Set other rates - uses internal VCO +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +To use other clock rates, the jumpers will need to be in the default position. + +* **J16** is a two pin header; move the jumper to (pin1, pin2). +* **J15** is a three pin header; move the jumper to (pin2, pin3). + +To communicate the desired clock rate into UHD, +specify the a special device address argument, +where the key is **master_clock_rate** and the value is a rate in Hz. +Example: +:: + + uhd_usrp_probe --args="master_clock_rate=52e6" + +------------------------------------------------------------------------ +Clock Synchronization +------------------------------------------------------------------------ + + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Ref Clock - 10MHz +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +The E1xx has a 10MHz TCXO which can be used to discipline the flexible clocking +by selecting **REF_INT** for the **clock_config_t**. + +Alternately, an external 10MHz reference clock can be supplied by soldering +a connector. + +* Connector **J10** (REF_IN) needs MCX connector **WM5541-ND** or similar. +* Square wave will offer the best phase noise performance, but sinusoid is acceptable. +* **Power level:** 0 to 15dBm +* Select **REF_SMA** in **clock_config_t**. + + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +PPS - Pulse Per Second +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +An exteral PPS signal for timestamp synchronization can be supplied by soldering +a connector. + +* Connector **J13** (PPS) needs MCX connector **WM5541-ND** or similar. +* Requires a square wave signal. +* **Amplitude:** 3.3 to 5Vpp + +Test the PPS input with the following app: + +* **/share/uhd/examples + ./test_pps_input --args= + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Internal GPSDO +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Please see the `Internal GPSDO Application Notes <./gpsdo.html>`_ +for information on configuring and using the internal GPSDO. + +UHD will always try to detect an installed GPSDO at runtime. +There is not a special EEPROM value to burn for GPSDO detection. + +------------------------------------------------------------------------ +Hardware Setup Notes +------------------------------------------------------------------------ + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Front panel LEDs +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +The LEDs on the front panel can be useful in debugging hardware and software +issues. The LEDs reveal the following about the state of the device: + +* **LED A:** transmitting +* **LED B:** fpga loaded +* **LED C:** receiving +* **LED D:** fpga loaded +* **LED E:** reference lock +* **LED F:** board power + +------------------------------------------------------------------------ +Miscellaneous +------------------------------------------------------------------------ + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Available Sensors +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +The following sensors are available; +they can be queried through the API. + +* **ref_locked:** clock reference locked (internal/external) +* other sensors are added when the GPSDO is enabled diff --git a/host/docs/usrp_e1xx.rst b/host/docs/usrp_e1xx.rst deleted file mode 100644 index 31a47347f..000000000 --- a/host/docs/usrp_e1xx.rst +++ /dev/null @@ -1,135 +0,0 @@ -======================================================================== -UHD - USRP-E1XX Series Application Notes -======================================================================== - -.. contents:: Table of Contents - ------------------------------------------------------------------------- -Specify a Non-standard Image ------------------------------------------------------------------------- -UHD will automatically select the USRP-Embedded FPGA image from the -installed images package. The FPGA image selection can be overridden with the -**--fpga=** device address parameter. - -Example device address string representations to specify non-standard FPGA -image: - -:: - - fpga=usrp_e100_custom.bin - ------------------------------------------------------------------------- -Changing the Master Clock Rate ------------------------------------------------------------------------- -The master clock rate of the USRP-Embedded feeds both the FPGA DSP and the codec -chip. Hundreds of rates between 32MHz and 64MHz are available. A few notable -rates are: - -* **64MHz:** maximum rate of the codec chip -* **61.44MHz:** good for UMTS/WCDMA applications -* **52Mhz:** good for GSM applications - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Set 61.44MHz - uses external VCXO -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -To use the 61.44MHz clock rate with the USRP-Embedded, two jumpers must be moved -on the device. - -* **J16** is a two pin header; remove the jumper (or leave it on pin1 only). -* **J15** is a three pin header; move the jumper to (pin1, pin2). - -**Note:** See instructions below to communicate the desired clock rate UHD. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Set other rates - uses internal VCO -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -To use other clock rates, the jumpers will need to be in the default position. - -* **J16** is a two pin header; move the jumper to (pin1, pin2). -* **J15** is a three pin header; move the jumper to (pin2, pin3). - -To communicate the desired clock rate into UHD, -specify the a special device address argument, -where the key is **master_clock_rate** and the value is a rate in Hz. -Example: -:: - - uhd_usrp_probe --args="master_clock_rate=52e6" - ------------------------------------------------------------------------- -Clock Synchronization ------------------------------------------------------------------------- - - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Ref Clock - 10MHz -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The E1xx has a 10MHz TCXO which can be used to discipline the flexible clocking -by selecting **REF_INT** for the **clock_config_t**. - -Alternately, an external 10MHz reference clock can be supplied by soldering -a connector. - -* Connector **J10** (REF_IN) needs MCX connector **WM5541-ND** or similar. -* Square wave will offer the best phase noise performance, but sinusoid is acceptable. -* **Power level:** 0 to 15dBm -* Select **REF_SMA** in **clock_config_t**. - - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -PPS - Pulse Per Second -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -An exteral PPS signal for timestamp synchronization can be supplied by soldering -a connector. - -* Connector **J13** (PPS) needs MCX connector **WM5541-ND** or similar. -* Requires a square wave signal. -* **Amplitude:** 3.3 to 5Vpp - -Test the PPS input with the following app: - -* **/share/uhd/examples - ./test_pps_input --args= - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Internal GPSDO -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Please see the `Internal GPSDO Application Notes <./gpsdo.html>`_ -for information on configuring and using the internal GPSDO. - -UHD will always try to detect an installed GPSDO at runtime. -There is not a special EEPROM value to burn for GPSDO detection. - ------------------------------------------------------------------------- -Hardware Setup Notes ------------------------------------------------------------------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Front panel LEDs -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The LEDs on the front panel can be useful in debugging hardware and software -issues. The LEDs reveal the following about the state of the device: - -* **LED A:** transmitting -* **LED B:** fpga loaded -* **LED C:** receiving -* **LED D:** fpga loaded -* **LED E:** reference lock -* **LED F:** board power - ------------------------------------------------------------------------- -Miscellaneous ------------------------------------------------------------------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Available Sensors -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The following sensors are available; -they can be queried through the API. - -* **ref_locked:** clock reference locked (internal/external) -* other sensors are added when the GPSDO is enabled -- cgit v1.2.3