From f239b8517b238923aacc161664857a7d7b830ab0 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 6 Jun 2011 04:58:42 +0100 Subject: usrp-e100: removed clockgen config stuff and docs --- host/docs/usrp_e1xx.rst | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'host/docs') diff --git a/host/docs/usrp_e1xx.rst b/host/docs/usrp_e1xx.rst index fcaa57716..4ac9d133a 100644 --- a/host/docs/usrp_e1xx.rst +++ b/host/docs/usrp_e1xx.rst @@ -53,21 +53,6 @@ Example: uhd_usrp_probe --args="master_clock_rate=52e6" -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Clock rate recovery - unbricking -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -It is possible to set a clock rate such that the UHD can no longer communicate with the FPGA. -When this occurs, it is necessary to use the usrp-e-utility to recover the clock generator. -The recovery utility works by loading a special pass-through FPGA image so the computer -can talk directly to the clock generator over a SPI interface. - -Run the following commands to restore the clock generator to a usable state: -:: - - cd /share/uhd/usrp_e_utilities - ./usrp-e-utility --fpga=../images/usrp_e100_pt_fpga.bin --reclk - - ------------------------------------------------------------------------ Clock Synchronization ------------------------------------------------------------------------ -- cgit v1.2.3