From a520a70c9644e7244b186d9e6089bb25659f6c80 Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Wed, 7 Jan 2015 14:58:46 +0100 Subject: docs: Major revisions and additions --- host/docs/usrp_x3x0.dox | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'host/docs/usrp_x3x0.dox') diff --git a/host/docs/usrp_x3x0.dox b/host/docs/usrp_x3x0.dox index 847efe74e..a9b31df57 100644 --- a/host/docs/usrp_x3x0.dox +++ b/host/docs/usrp_x3x0.dox @@ -378,6 +378,8 @@ Example: - Ethernet interface subnet mask: `255.255.255.0` - USRP-X Series device IPv4 address: `192.168.110.2` +If all devices are to be used in a compound, see also \ref page_multiple. + \subsection x3x0_setup_change_ip Change the USRP's IP address You may need to change the USRP's IP address for several reasons: @@ -436,6 +438,7 @@ Example device address string representation for 2 USRPs with IPv4 addresses **1 addr0=192.168.10.2, addr1=192.168.20.2 +See also \ref page_multiple. \section x3x0_comm_problems Communication Problems @@ -607,6 +610,16 @@ Further information on how to use Chipscope can be found in the Xilinx Chipscope \section x3x0_misc Miscellaneous +\subsection x3x0_misc_settings Configuring the device in an application + +During runtime, the device can be configured in several different ways. + +The following pages may shed some light: + +- \ref page_configuration +- uhd::stream_args_t +- \ref multiple_channumbers + \subsection x3x0_misc_multirx Multiple RX channels There are two complete DDC and DUC DSP chains in the FPGA. In the single channel case, -- cgit v1.2.3