From 2a575bf9b5a4942f60e979161764b9e942699e1e Mon Sep 17 00:00:00 2001 From: Lars Amsel Date: Fri, 4 Jun 2021 08:27:50 +0200 Subject: uhd: Add support for the USRP X410 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Lars Amsel Co-authored-by: Michael Auchter Co-authored-by: Martin Braun Co-authored-by: Paul Butler Co-authored-by: Cristina Fuentes Co-authored-by: Humberto Jimenez Co-authored-by: Virendra Kakade Co-authored-by: Lane Kolbly Co-authored-by: Max Köhler Co-authored-by: Andrew Lynch Co-authored-by: Grant Meyerhoff Co-authored-by: Ciro Nishiguchi Co-authored-by: Thomas Vogel --- host/docs/res/x4xx_block_diagram.svg | 962 +++++++++++++++++++++++++++++++++++ 1 file changed, 962 insertions(+) create mode 100644 host/docs/res/x4xx_block_diagram.svg (limited to 'host/docs/res/x4xx_block_diagram.svg') diff --git a/host/docs/res/x4xx_block_diagram.svg b/host/docs/res/x4xx_block_diagram.svg new file mode 100644 index 000000000..760b2f442 --- /dev/null +++ b/host/docs/res/x4xx_block_diagram.svg @@ -0,0 +1,962 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + Xilinx RFSoC- Embedded Linux- Programmable Logic + + + ControlCPLD + + DB0 DigitalInterface + DB1 DigitalInterface + + + + DB1 RFInterface + DB0 RFInterface + ADCsDACs + + + + + DIOBoard + + + + + ClockingBoard + + + SCU + + + + + + + + + + + + DDR Bank 1 + + + + DDR Bank 0 + + DDR44 GB + + + DDR44 GB + + + + + DDR44 GB + + + + + DDR Bank 2 + + + + + + + SPI + + + + + SPI + + + + + + + + QSFP28Port 0 + QSFP28Port 1 + + + + Clock / TimeReference + 4x 25 Gbps + 4x 25 Gbps + + + RJ45 + + + I2C + + + + PL DRAM + PS DRAM + + -- cgit v1.2.3