From 99b841c75aa91709090cbf4046bf51b7ffb4f612 Mon Sep 17 00:00:00 2001 From: Javier Valenzuela Date: Fri, 5 Feb 2021 13:15:02 -0600 Subject: fpga: x400: zbx: Add support for ZBX CPLD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Cherwa Vang Co-authored-by: Martin Braun Co-authored-by: Max Köhler Co-authored-by: Paul Butler --- fpga/usrp3/top/x400/dboards/zbx/cpld/.gitignore | 7 + fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile | 90 + .../top/x400/dboards/zbx/cpld/ctrlport_window.v | 73 + .../top/x400/dboards/zbx/cpld/doc/ZBX_CPLD.htm | 10 + .../x400/dboards/zbx/cpld/doc/ZBX_CPLD_left.htm | 338 + .../x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm | 9799 ++++++++++++++++++++ .../top/x400/dboards/zbx/cpld/ip/flash/.gitignore | 3 + .../dboards/zbx/cpld/ip/flash/on_chip_flash.qsys | 90 + .../top/x400/dboards/zbx/cpld/ip/osc/.gitignore | 3 + .../top/x400/dboards/zbx/cpld/ip/osc/osc.qsys | 63 + .../top/x400/dboards/zbx/cpld/raw_conversion.cof | 39 + .../dboards/zbx/cpld/register_endpoints/README.md | 10 + .../zbx/cpld/register_endpoints/atr_controller.v | 341 + .../zbx/cpld/register_endpoints/basic_regs.v | 219 + .../zbx/cpld/register_endpoints/dsa_control.v | 736 ++ .../zbx/cpld/register_endpoints/led_control.v | 259 + .../zbx/cpld/register_endpoints/lo_control.v | 568 ++ .../memory_init_files/.gitignore | 2 + .../memory_init_files/gen_defaults.py | 65 + .../zbx/cpld/register_endpoints/power_regs.v | 211 + .../zbx/cpld/register_endpoints/switch_control.v | 918 ++ .../register_endpoints/utils/spi_control_utils.vh | 30 + .../dboards/zbx/cpld/regmap/atr_regmap_utils.vh | 81 + .../zbx/cpld/regmap/basic_regs_regmap_utils.vh | 75 + .../zbx/cpld/regmap/db_control_regmap_utils.vh | 58 + .../zbx/cpld/regmap/dsa_setup_regmap_utils.vh | 162 + .../dboards/zbx/cpld/regmap/gpio_regmap_utils.vh | 31 + .../zbx/cpld/regmap/led_setup_regmap_utils.vh | 46 + .../zbx/cpld/regmap/lo_control_regmap_utils.vh | 110 + .../zbx/cpld/regmap/power_regs_regmap_utils.vh | 57 + .../dboards/zbx/cpld/regmap/spi_regmap_utils.vh | 41 + .../zbx/cpld/regmap/switch_setup_regmap_utils.vh | 131 + .../top/x400/dboards/zbx/cpld/zbx_cpld_core.v | 463 + .../top/x400/dboards/zbx/cpld/zbx_top_cpld.qpf | 30 + .../top/x400/dboards/zbx/cpld/zbx_top_cpld.qsf | 889 ++ .../top/x400/dboards/zbx/cpld/zbx_top_cpld.sdc | 374 + .../usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.v | 1305 +++ 37 files changed, 17727 insertions(+) create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/.gitignore create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ctrlport_window.v create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD.htm create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_left.htm create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/.gitignore create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/on_chip_flash.qsys create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ip/osc/.gitignore create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ip/osc/osc.qsys create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/raw_conversion.cof create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/README.md create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/atr_controller.v create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/led_control.v create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/lo_control.v create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/memory_init_files/.gitignore create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/memory_init_files/gen_defaults.py create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/power_regs.v create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/utils/spi_control_utils.vh create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/atr_regmap_utils.vh create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/db_control_regmap_utils.vh create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/dsa_setup_regmap_utils.vh create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/gpio_regmap_utils.vh create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/led_setup_regmap_utils.vh create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/lo_control_regmap_utils.vh create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/power_regs_regmap_utils.vh create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/spi_regmap_utils.vh create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/switch_setup_regmap_utils.vh create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_cpld_core.v create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qpf create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qsf create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.sdc create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.v (limited to 'fpga') diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/.gitignore b/fpga/usrp3/top/x400/dboards/zbx/cpld/.gitignore new file mode 100644 index 000000000..9fd51d1a5 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/.gitignore @@ -0,0 +1,7 @@ +# Ignore Quartus generated files upon project opening. +*.qws +db/ +doc/*.xml +incremental_db/ +output_files/ +*.sopcinfo diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile b/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile new file mode 100644 index 000000000..878054bd6 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile @@ -0,0 +1,90 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +GIT_HASH = $(shell ../../../../../tools/scripts/git-hash.sh) + +build: cpld_defaults ip + @echo -ne "\n---- Make: Synthesis ...\n\n"; + @quartus_map zbx_top_cpld --verilog_macro="GIT_HASH=32'h$(GIT_HASH)"; + @echo -ne "\n\n---- Make: Implementation ...\n\n"; + @quartus_fit zbx_top_cpld; + @echo -ne "\n\n---- Make: Analyzing timing ...\n\n"; + @quartus_sta zbx_top_cpld; + @# grep for unconstrained path warning + @grep "332102" output_files/zbx_top_cpld.sta.rpt; \ + if [ $$? -eq 0 ]; then false; else true; fi + @# grep for timing closure critical warning + @grep "332148" output_files/zbx_top_cpld.sta.rpt; \ + if [ $$? -eq 0 ]; then false; else true; fi + @# expect no warnings + @grep -iw "warning" output_files/zbx_top_cpld.sta.rpt; \ + if [ $$? -eq 0 ]; then false; else true; fi + @# expect no critical warning except "review power analyzer report file" + @grep -i "critical warning" output_files/* | grep -v 16562; \ + if [ $$? -eq 0 ]; then false; else true; fi + @echo -ne "\n\n---- Make: Generating bitfile...\n\n"; + @quartus_asm zbx_top_cpld; + @echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP enabled)...\n\n"; + @quartus_cpf --convert \ + --frequency 12.5MHz \ + --voltage 2.5 \ + --operation p \ + ./output_files/zbx_top_cpld.pof ./output_files/zbx_top_cpld_isp_on.svf -o background_programming=on; + @echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP disabled)...\n\n"; + @quartus_cpf --convert \ + --frequency 12.5MHz \ + --voltage 2.5 \ + --operation p \ + ./output_files/zbx_top_cpld.pof ./output_files/zbx_top_cpld_isp_off.svf; + @echo -ne "\n\n---- Make: Converting bitfile to rdp format...\n\n"; + @quartus_cpf -c raw_conversion.cof + @echo -ne "\n\n---- Make: Copy final files...\n\n"; + @mkdir -p build + @cp output_files/zbx_top_cpld.pof build/usrp_zbx_cpld.pof + @cp output_files/zbx_top_cpld_isp_off.svf build/usrp_zbx_cpld.svf + @cp output_files/zbx_top_cpld_isp_on.svf build/usrp_zbx_cpld_isp_on.svf + @cp output_files/zbx_top_cpld_converted_cfm0_auto.rpd build/usrp_zbx_cpld.rpd + @echo -ne "\n\n---- Make: ZBX CPLD ready!\n"; + @echo -ne " Use build/usrp_zbx_cpld.pof via JTAG programmer or\n" + @echo -ne " build/usrp_zbx_cpld.svf (ISP off) via MB CPLD JTAG engine or\n" + @echo -ne " build/usrp_zbx_cpld.rpd via reconfig engine or\n" + @echo -ne " build/usrp_zbx_cpld_isp_on.rpd via MB CPLD JTAG engine.\n" + +clean: + @echo -ne "\nCleaning ZBX CPLD...\n"; + @git clean -Xdf + +QSYS_PATH=$(subst \,/,$(QUARTUS_ROOTDIR))/sopc_builder/bin + +ROOT_DIR:=$(shell dirname $(realpath $(firstword $(MAKEFILE_LIST)))) + +REGS_PY_FILE=$(ROOT_DIR)/../../../../../../../host/lib/ic_reg_maps/gen_zbx_cpld_regs.py +REGS_PY_MODULE=register_endpoints/memory_init_files/zbx_cpld_regs_t.py + +$(REGS_PY_MODULE): $(REGS_PY_FILE) + @python3 $(REGS_PY_FILE) $(REGS_PY_MODULE) + +# Using one of the files as a dependency (all files are generated at the same time) +INIT_FILES := $(ROOT_DIR)/register_endpoints/memory_init_files/rx0_path_defaults.hex + +$(INIT_FILES): register_endpoints/memory_init_files/gen_defaults.py $(REGS_PY_MODULE) + @python3 $(ROOT_DIR)/register_endpoints/memory_init_files/gen_defaults.py + +cpld_defaults: $(INIT_FILES) + +ip: ip/flash/on_chip_flash/simulation/on_chip_flash.v \ + ip/osc/osc/simulation/osc.v + @make -C ../../../cpld ip + +ip/flash/on_chip_flash/simulation/on_chip_flash.v: + $(QSYS_PATH)/qsys-generate ip/flash/on_chip_flash.qsys --simulation=VERILOG + +ip/osc/osc/simulation/osc.v: + $(QSYS_PATH)/qsys-generate ip/osc/osc.qsys --simulation=VERILOG + +all: build + +.PHONY: all build clean ip diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ctrlport_window.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/ctrlport_window.v new file mode 100644 index 000000000..4a886d34d --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ctrlport_window.v @@ -0,0 +1,73 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: ctrlport_window +// +// Description: +// Copy requests from slave to master interface when s_ctrlport_req_addr is in +// address range specified by BASE_ADDRESS and WINDOW_SIZE. The modules does +// not use any registers and therefore does not need ctrlport_clk and +// ctrlport_rst. +// + +`default_nettype none + +module ctrlport_window #( + parameter BASE_ADDRESS = 0, + parameter WINDOW_SIZE = 32 +) ( + // Slave Interface + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [ 9:0] s_ctrlport_req_portid, + input wire [15:0] s_ctrlport_req_rem_epid, + input wire [ 9:0] s_ctrlport_req_rem_portid, + input wire [31:0] s_ctrlport_req_data, + input wire [ 3:0] s_ctrlport_req_byte_en, + input wire s_ctrlport_req_has_time, + input wire [63:0] s_ctrlport_req_time, + output wire s_ctrlport_resp_ack, + output wire [ 1:0] s_ctrlport_resp_status, + output wire [31:0] s_ctrlport_resp_data, + + // Master Interface + output wire m_ctrlport_req_wr, + output wire m_ctrlport_req_rd, + output wire [19:0] m_ctrlport_req_addr, + output wire [ 9:0] m_ctrlport_req_portid, + output wire [15:0] m_ctrlport_req_rem_epid, + output wire [ 9:0] m_ctrlport_req_rem_portid, + output wire [31:0] m_ctrlport_req_data, + output wire [ 3:0] m_ctrlport_req_byte_en, + output wire m_ctrlport_req_has_time, + output wire [63:0] m_ctrlport_req_time, + input wire m_ctrlport_resp_ack, + input wire [ 1:0] m_ctrlport_resp_status, + input wire [31:0] m_ctrlport_resp_data +); + + // Mask write and read flag + wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + WINDOW_SIZE); + assign m_ctrlport_req_wr = s_ctrlport_req_wr & address_in_range; + assign m_ctrlport_req_rd = s_ctrlport_req_rd & address_in_range; + + // Forward all other signals untouched. + assign m_ctrlport_req_addr = s_ctrlport_req_addr; + assign m_ctrlport_req_portid = s_ctrlport_req_portid; + assign m_ctrlport_req_rem_epid = s_ctrlport_req_rem_epid; + assign m_ctrlport_req_rem_portid = s_ctrlport_req_rem_portid; + assign m_ctrlport_req_data = s_ctrlport_req_data; + assign m_ctrlport_req_byte_en = s_ctrlport_req_byte_en; + assign m_ctrlport_req_has_time = s_ctrlport_req_has_time; + assign m_ctrlport_req_time = s_ctrlport_req_time; + + assign s_ctrlport_resp_ack = m_ctrlport_resp_ack; + assign s_ctrlport_resp_status = m_ctrlport_resp_status; + assign s_ctrlport_resp_data = m_ctrlport_resp_data; + +endmodule + +`default_nettype wire diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD.htm b/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD.htm new file mode 100644 index 000000000..ac280959d --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD.htm @@ -0,0 +1,10 @@ + + + ZBX_CPLD + + + + + + + \ No newline at end of file diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_left.htm b/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_left.htm new file mode 100644 index 000000000..be5ae68a8 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_left.htm @@ -0,0 +1,338 @@ + + + + + + + +
+

+ + + ZBX_CPLD +

+
+

+ + + P1 Content +

+
+
+

+ + + ports +

+
+

GPIO

+

SPI

+
+
+

+ + + ATR_REGMAP +

+

+ + + ATR_REGISTERS +

+
+

enum ATR_OPTIONS

+

CURRENT_CONFIG_REG

+

OPTION_REG

+

SW_CONFIG_REG

+
+
+

+ + + BASIC_REGS_REGMAP +

+

+ + + BASIC_REGS_REGISTERS +

+
+

enum BASIC_REGISTERS_VALUES

+

SLAVE_SIGNATURE

+

SLAVE_REVISION

+

SLAVE_OLDEST_REVISION

+

SLAVE_SCRATCH

+

GIT_HASH_REGISTER

+
+
+

+ + + DB_CONTROL_REGMAP +

+

+ + + DB_CONTROL_WINDOWS +

+
+

ATR_CONTROLLER_REGS

+

LO_CONTROL_REGS

+

LED_SETUP_REGS

+

SWITCH_SETUP_REGS

+

DSA_SETUP_REGS

+
+

+ + + REGISTER_ENDPOINTS +

+
+

enum REGISTER_BLOCKS

+
+
+

+ + + DSA_SETUP_REGMAP +

+

+ + + DSA_SETUP_REGISTERS +

+
+

TX0_DSA_ATR

+

TX1_DSA_ATR

+

RX0_DSA_ATR

+

RX1_DSA_ATR

+

TX0_DSA_TABLE_SELECT

+

TX1_DSA_TABLE_SELECT

+

RX0_DSA_TABLE_SELECT

+

RX1_DSA_TABLE_SELECT

+

TX0_DSA_TABLE

+

TX1_DSA_TABLE

+

RX0_DSA_TABLE

+

RX1_DSA_TABLE

+
+
+

+ + + GPIO_REGMAP +

+

+ + + GPIO_REGMAP_WINDOWS +

+
+

BASE_WINDOW_GPIO

+

DB_CONTROL_WINDOW_GPIO

+
+
+

+ + + LED_SETUP_REGMAP +

+

+ + + LED_SETUP_REGISTERS +

+
+

LED_CONTROL

+
+
+

+ + + LO_CONTROL_REGMAP +

+

+ + + LO_SPI_REGISTERS +

+
+

enum LO_CHIP_SELECT

+

LO_SPI_SETUP

+

LO_SPI_STATUS

+
+

+ + + LO_SYNC_REGS +

+
+

LO_PULSE_SYNC

+
+
+

+ + + POWER_REGS_REGMAP +

+

+ + + POWER_REGS_REGISTERS +

+
+

RF_POWER_CONTROL

+

RF_POWER_STATUS

+

PRC_CONTROL

+
+
+

+ + + RECONFIG_REGMAP +

+

+ + + RECONFIG_REGS +

+
+

enum FLASH_PRIMARY_IMAGE_ADDR_ENUM

+

FLASH_STATUS_REG

+

FLASH_CONTROL_REG

+

FLASH_ADDR_REG

+

FLASH_WRITE_DATA_REG

+

FLASH_READ_DATA_REG

+

FLASH_CFM0_START_ADDR_REG

+

FLASH_CFM0_END_ADDR_REG

+
+
+

+ + + SPI_REGMAP +

+

+ + + SPI_REGMAP_WINDOWS +

+
+

BASE_WINDOW_SPI

+

RECONFIG

+

POWER_REGS

+

DB_CONTROL_WINDOW_SPI

+
+
+

+ + + SWITCH_SETUP_REGMAP +

+

+ + + SWITCH_SETUP_REGISTERS +

+
+

TX0_PATH_CONTROL

+

TX1_PATH_CONTROL

+

RX0_PATH_CONTROL

+

RX1_PATH_CONTROL

+
+
+
+ + \ No newline at end of file diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm b/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm new file mode 100644 index 000000000..97bd80ee4 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm @@ -0,0 +1,9799 @@ + + + + + + + +
+ +

ZBX_CPLD

+ +

The top is defined in HDL source file zbx_top_cpld.v.

+

P1 Content

+

Register map for 'ZBX_CPLD' core team members

+ This content is intended solely for use by core team members of the 'ZBX_CPLD' project. + Do not distribute or otherwise forward this content. If you believe you have acquired + access to this content in error, delete it immediately and notify the sender that you + are not intended to have access to this content.

"All content provided is NI Confidential and Copyright 2021 National Instruments Corporation. +For information on NI trademark guidelines, please see http://www.ni.com/legal/trademarks/. For the NI Patent Notice, please see http://www.ni.com/legal/patents/." +

+
+ +

ports

+ This section lists all common communication interfaces of the ZBX CPLD. + Each input port will point to a regmap. The SPI port can reach out to + each register. The GPIO port can access a subset of all register, where + the use case is mainly RF configuration to enable fast changes. +
+ + +

Port GPIO (input)

+ +

+ + Target Regmap = GPIO_REGMAP + +

+ +
+ +Controlport requests from the FPGA GPIO lines. + +
+ +

+ This port is defined in HDL source file zbx_top_cpld.v. +

+ +
+ +
+ + +

Port SPI (input)

+ +

+ + Target Regmap = SPI_REGMAP + +

+ +
+ +Controlport requests from this SPI interface are driven by the PL part + of the RFSoC via the MB CPLD. + +
+ +

+ This port is defined in HDL source file zbx_top_cpld.v. +

+ +
+ +
+ +
+ +
+ +

ATR_REGMAP

+ +

ATR_REGISTERS

+ This regmap contains settings for the active configuration of RF 0 and 1. + There are two sets of configurations. One set comprises RF switches and + LEDs, the other set comprises the attenuators (DSA). +
+ + +

ATR_OPTIONS Enumeration

+Contains the options available for RF 0 and RF 1. The chosen setting + affects how the active configuration of up to 8 bits is derived. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Name
0 +

SW_DEFINED

+ +

Uses the respective value of SW_CONFIG_REG as configuration. + +

1 +

CLASSIC_ATR

+ +

This option assumes the FPGA state to be assigned with: Bit 0 = RF 0 + RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3 + = RF 1 TX running. The configuration for each RF chain is built + up of the 2 bits for the RF chain (4 possible states: IDLE, RX only, + TX only, TX/RX). + +

2 +

FPGA_STATE

+ +

The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states. + +

+ +

+ This enumerated type is defined in HDL source file atr_controller.v. +

+ +
+ +
+ + +

Offset 0x0000: CURRENT_CONFIG_REG Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS
  0x000000
+ +		 + + + + +
CURRENT_CONFIG_REG
  offset=0x0000
+ +		 + + + + + +
+ + +Total Offset =
  0x001000 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + +
+ + +Total Offset =
  0x001000 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file atr_controller.v.

+ +
+ +
+ +Contains the current active configuration. + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

CURRENT_RF1_DSA_CONFIG

+

Current active configuration for DSAs of RF 1.

+ +
23..16 +

CURRENT_RF0_DSA_CONFIG

+

Current active configuration for DSAs of RF 0.

+ +
15..8 +

CURRENT_RF1_CONFIG

+

Current active configuration for switches and LEDs of RF 1.

+ +
7..0 +

CURRENT_RF0_CONFIG

+

Current active configuration for switches and LEDs of RF 0.

+ +
+ +
+ +
+ + +

Offset 0x0004: OPTION_REG Register (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS
  0x000000
+ +		 + + + + +
OPTION_REG
  offset=0x0004
+ +		 + + + + + +
+ + +Total Offset =
  0x001004 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + +
+ + +Total Offset =
  0x001004 + +
+ +

+ +

Initial Value = 0x00000000 +

+ +

This register is defined in HDL source file atr_controller.v.

+ +
+ +
+ +Set the option to be used for the RF chains. + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..26 +

Reserved

+

+ +
25..24 +

RF1_DSA_OPTION   (initialvalue=SW_DEFINED)

+

Option used for DSAs of RF 1.

+ +

+ The values for this bitfield are in the ATR_OPTIONS table. + (show here) +

+
+ +
+ + Contains the options available for RF 0 and RF 1. The chosen setting + affects how the active configuration of up to 8 bits is derived. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Name
0 +

SW_DEFINED

+ +

Uses the respective value of SW_CONFIG_REG as configuration. + +

1 +

CLASSIC_ATR

+ +

This option assumes the FPGA state to be assigned with: Bit 0 = RF 0 + RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3 + = RF 1 TX running. The configuration for each RF chain is built + up of the 2 bits for the RF chain (4 possible states: IDLE, RX only, + TX only, TX/RX). + +

2 +

FPGA_STATE

+ +

The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states. + +

+ +

+ This enumerated type is defined in HDL source file atr_controller.v. +

+ +
+ +
+ +
23..18 +

Reserved

+

+ +
17..16 +

RF0_DSA_OPTION   (initialvalue=SW_DEFINED)

+

Option used for DSAs of RF 0.

+ +

+ The values for this bitfield are in the ATR_OPTIONS table. + (show here) +

+
+ +
+ + Contains the options available for RF 0 and RF 1. The chosen setting + affects how the active configuration of up to 8 bits is derived. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Name
0 +

SW_DEFINED

+ +

Uses the respective value of SW_CONFIG_REG as configuration. + +

1 +

CLASSIC_ATR

+ +

This option assumes the FPGA state to be assigned with: Bit 0 = RF 0 + RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3 + = RF 1 TX running. The configuration for each RF chain is built + up of the 2 bits for the RF chain (4 possible states: IDLE, RX only, + TX only, TX/RX). + +

2 +

FPGA_STATE

+ +

The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states. + +

+ +

+ This enumerated type is defined in HDL source file atr_controller.v. +

+ +
+ +
+ +
15..10 +

Reserved

+

+ +
9..8 +

RF1_OPTION   (initialvalue=SW_DEFINED)

+

Option used for switches and LEDs of RF 1.

+ +

+ The values for this bitfield are in the ATR_OPTIONS table. + (show here) +

+
+ +
+ + Contains the options available for RF 0 and RF 1. The chosen setting + affects how the active configuration of up to 8 bits is derived. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Name
0 +

SW_DEFINED

+ +

Uses the respective value of SW_CONFIG_REG as configuration. + +

1 +

CLASSIC_ATR

+ +

This option assumes the FPGA state to be assigned with: Bit 0 = RF 0 + RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3 + = RF 1 TX running. The configuration for each RF chain is built + up of the 2 bits for the RF chain (4 possible states: IDLE, RX only, + TX only, TX/RX). + +

2 +

FPGA_STATE

+ +

The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states. + +

+ +

+ This enumerated type is defined in HDL source file atr_controller.v. +

+ +
+ +
+ +
7..2 +

Reserved

+

+ +
1..0 +

RF0_OPTION   (initialvalue=SW_DEFINED)

+

Option used for switches and LEDs of RF 0.

+ +

+ The values for this bitfield are in the ATR_OPTIONS table. + (show here) +

+
+ +
+ + Contains the options available for RF 0 and RF 1. The chosen setting + affects how the active configuration of up to 8 bits is derived. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Name
0 +

SW_DEFINED

+ +

Uses the respective value of SW_CONFIG_REG as configuration. + +

1 +

CLASSIC_ATR

+ +

This option assumes the FPGA state to be assigned with: Bit 0 = RF 0 + RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3 + = RF 1 TX running. The configuration for each RF chain is built + up of the 2 bits for the RF chain (4 possible states: IDLE, RX only, + TX only, TX/RX). + +

2 +

FPGA_STATE

+ +

The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states. + +

+ +

+ This enumerated type is defined in HDL source file atr_controller.v. +

+ +
+ +
+ +
+ +
+ +
+ + +

Offset 0x0008: SW_CONFIG_REG Register (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS
  0x000000
+ +		 + + + + +
SW_CONFIG_REG
  offset=0x0008
+ +		 + + + + + +
+ + +Total Offset =
  0x001008 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + +
+ + +Total Offset =
  0x001008 + +
+ +

+ +

Initial Value = 0x00000000 +

+ +

This register is defined in HDL source file atr_controller.v.

+ +
+ +
+ +Contains the configuration to be applied in case SW_DEFINED option is + chosen. + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

SW_RF1_DSA_CONFIG   (initialvalue=0)

+

SW defined configuration for DSAs of RF 1.

+ +
23..16 +

SW_RF0_DSA_CONFIG   (initialvalue=0)

+

SW defined configuration for DSAs of RF 0.

+ +
15..8 +

SW_RF1_CONFIG   (initialvalue=0)

+

SW defined configuration for switches and LEDs of RF 1.

+ +
7..0 +

SW_RF0_CONFIG   (initialvalue=0)

+

SW defined configuration for switches and LEDs of RF 0.

+ +
+ +
+ +
+ +
+ +
+ +

BASIC_REGS_REGMAP

+ +

BASIC_REGS_REGISTERS

+ This regmap contains the revision registers, signature register, a scratch register, and a slave control reg. +
+ + +

BASIC_REGISTERS_VALUES Enumeration

+This enum is used to create the constants held in the basic registers in both verilog and vhdl. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Name
Dec Hex
163860x00004002 +

BOARD_ID_VALUE

+ +
5379865770x20110611 +

OLDEST_CPLD_REVISION

+ +
5538488410x21031009 +

CPLD_REVISION

+ +
+ +

+ This enumerated type is defined in HDL source file basic_regs.v. +

+ +
+ +
+ + +

Offset 0x0000: SLAVE_SIGNATURE Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|BASE_WINDOW_GPIO
  0x000000
+ +		 + + + + +
SLAVE_SIGNATURE
  offset=0x0000
+ +		 + + + + + +
+ + +Total Offset =
  0x000000 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|BASE_WINDOW_SPI
  0x000000
+ +		 + + + + + +
+ + +Total Offset =
  0x000000 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file basic_regs.v.

+ +
+ +
+ +This register contains the unique signature of the DB. This signature is the same value as the one + stored on the board ID EEPROM + +
+ + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..0 +

BOARD_ID

+

Board ID corresponds to the las 16 digits of the daughterboard part number.

+ +
+ +
+ +
+ + +

Offset 0x0004: SLAVE_REVISION Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|BASE_WINDOW_GPIO
  0x000000
+ +		 + + + + +
SLAVE_REVISION
  offset=0x0004
+ +		 + + + + + +
+ + +Total Offset =
  0x000004 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|BASE_WINDOW_SPI
  0x000000
+ +		 + + + + + +
+ + +Total Offset =
  0x000004 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file basic_regs.v.

+ +
+ +
+ +This register contains the revision number of the current build + +
+ + + + + + + + + +
BitsName
31..0 +

REVISION_REG

+

Returns the revision in YYMMDDHH format

+ +
+ +
+ +
+ + +

Offset 0x0008: SLAVE_OLDEST_REVISION Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|BASE_WINDOW_GPIO
  0x000000
+ +		 + + + + +
SLAVE_OLDEST_REVISION
  offset=0x0008
+ +		 + + + + + +
+ + +Total Offset =
  0x000008 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|BASE_WINDOW_SPI
  0x000000
+ +		 + + + + + +
+ + +Total Offset =
  0x000008 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file basic_regs.v.

+ +
+ +
+ +This register contains the revision number of the oldest compatible revision + +
+ + + + + + + + + +
BitsName
31..0 +

OLDEST_REVISION_REG

+

Returns the oldest compatible revision in YYMMDDHH format

+ +
+ +
+ +
+ + +

Offset 0x000C: SLAVE_SCRATCH Register (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|BASE_WINDOW_GPIO
  0x000000
+ +		 + + + + +
SLAVE_SCRATCH
  offset=0x000C
+ +		 + + + + + +
+ + +Total Offset =
  0x00000C + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|BASE_WINDOW_SPI
  0x000000
+ +		 + + + + + +
+ + +Total Offset =
  0x00000C + +
+ +

+ +

Initial Value = 0x00000000 +

+ +

This register is defined in HDL source file basic_regs.v.

+ +
+ +
+ +Read/write scratch register + +
+ + + + + + + + + +
BitsName
31..0 +

SCRATCH_REG   (initialvalue=0)

+

Returns the value written here previously.

+ +
+ +
+ +
+ + +

Offset 0x0010: GIT_HASH_REGISTER Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|BASE_WINDOW_GPIO
  0x000000
+ +		 + + + + +
GIT_HASH_REGISTER
  offset=0x0010
+ +		 + + + + + +
+ + +Total Offset =
  0x000010 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|BASE_WINDOW_SPI
  0x000000
+ +		 + + + + + +
+ + +Total Offset =
  0x000010 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file basic_regs.v.

+ +
+ +
+ +Git hash of commit used to build this image.
+ Value equals 0xDEADBEEF if the git hash was not used during synthesis. + +
+ + + + + + + + + + + + + + +
BitsName
31..28 +

GIT_CLEAN

+

0x0 in case the git status was clean
+ 0xF in case there were uncommitted changes

+ +
27..0 +

GIT_HASH

+

7 hex digit hash code of the commit

+ +
+ +
+ +
+ +
+ +
+ +

DB_CONTROL_REGMAP

+ +

DB_CONTROL_WINDOWS

+ Windows need to be without gaps to guarantee response to combiners. +
+ + +

Offset 0x0000: ATR_CONTROLLER_REGS Window (R|W)

+

  Target regmap = ATR_REGMAP

+ (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + + +
ATR_CONTROLLER_REGS
  offset=0x0000
  size=0x20 (32 bytes)
+ +		 + + + + + +
+ + +Total Offset =
  0x001000 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + +
+ + +Total Offset =
  0x001000 + +
+ +

+ +

This window is defined in HDL source file zbx_top_cpld.v.

+ +
+ +
+ + + +
+ +
+ +
+ + +

Offset 0x0020: LO_CONTROL_REGS Window (R|W)

+

  Target regmap = LO_CONTROL_REGMAP

+ (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + + +
LO_CONTROL_REGS
  offset=0x0020
  size=0x3E0 (992 bytes)
+ +		 + + + + + +
+ + +Total Offset =
  0x001020 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + +
+ + +Total Offset =
  0x001020 + +
+ +

+ +

This window is defined in HDL source file zbx_top_cpld.v.

+ +
+ +
+ +Extended original size of 0x20 to fill gap to next window. + +
+ +
+ +
+ + +

Offset 0x0400: LED_SETUP_REGS Window (R|W)

+

  Target regmap = LED_SETUP_REGMAP

+ (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + + +
LED_SETUP_REGS
  offset=0x0400
  size=0xC00 (3 Kbytes)
+ +		 + + + + + +
+ + +Total Offset =
  0x001400 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + +
+ + +Total Offset =
  0x001400 + +
+ +

+ +

This window is defined in HDL source file zbx_top_cpld.v.

+ +
+ +
+ +Extended original size of 0x400 to fill gap to next window. + +
+ +
+ +
+ + +

Offset 0x1000: SWITCH_SETUP_REGS Window (R|W)

+

  Target regmap = SWITCH_SETUP_REGMAP

+ (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + + +
SWITCH_SETUP_REGS
  offset=0x1000
  size=0x1000 (4 Kbytes)
+ +		 + + + + + +
+ + +Total Offset =
  0x002000 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + +
+ + +Total Offset =
  0x002000 + +
+ +

+ +

This window is defined in HDL source file zbx_top_cpld.v.

+ +
+ +
+ + + +
+ +
+ +
+ + +

Offset 0x2000: DSA_SETUP_REGS Window (R|W)

+

  Target regmap = DSA_SETUP_REGMAP

+ (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + + +
DSA_SETUP_REGS
  offset=0x2000
  size=0x3000 (12 Kbytes)
+ +		 + + + + + +
+ + +Total Offset =
  0x003000 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + +
+ + +Total Offset =
  0x003000 + +
+ +

+ +

This window is defined in HDL source file zbx_top_cpld.v.

+ +
+ +
+ + + +
+ +
+ +
+ +

REGISTER_ENDPOINTS

+ +
+ + +

REGISTER_BLOCKS Enumeration

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Name
0 +

ATR_REGISTERS

+ +
1 +

LED_REGISTERS

+ +
2 +

LO_SPI

+ +
3 +

SW_CONTROL

+ +
4 +

DSA_CONTROL

+ +
+ +

+ This enumerated type is defined in HDL source file zbx_cpld_core.v. +

+ +
+ +
+ +
+ +
+ +

DSA_SETUP_REGMAP

+
+
+

DSA_SETUP_REGISTERS

+
+

The following registers control the digital step attenuators (DSA).

+

There are two ways to set the DSA values, which are applied to the DB ICs.

+
    +
  1. +

    The ...DSA_ATR registers can be used to access the raw +values of each ATR configuration.

    +
    2. +
  2. +

    Gain tables can be used as intermediate step to abstract from the +raw DB values. This gain table can be modified using the ...DSA_TABLE +registers according to the content of the registers from the first +option. Initially each gain table is empty (all zeros). Each gain +table entry can be accessed at any time. Once the table is filled with +values the ...DSA_TABLE_SELECT registers can be used to get one gain +table entry with index TABLE_INDEX and write it to the appropriate ATR +configuration given by the address (see show extended info link below +the register array headlines)

    +
    3. +
+
+ + +

Offset 0x0000: TX0_DSA_ATR(255:0) Register Array (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|DSA_SETUP_REGS
  0x002000
+ +		 + + + + +
TX0_DSA_ATR
  offset=0x0000 + i*4
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x003000 + i*4 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x003000 + i*4 + +
+ +

+ +

Initial Values
+ + +
default=>0x00001F1F
+

+ +

This register is defined in HDL source file dsa_control.v.
+It uses RegType TX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

+ +
+ +
+ +
+

+
+

Controls the Tx0 DSAs by accessing the raw attenuation levels.

+

This register array can hold settings for all ATR configurations. +The register index equals the ATR configuration. +The active configuration can be selected in ATR_REGMAP. +Independently all configurations can be read/written at any time.

+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..13 +

Reserved

+

+ +
12..8 +

TX_DSA2   (initialvalue=31)

+

+

Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
7..5 +

Reserved

+

+ +
4..0 +

TX_DSA1   (initialvalue=31)

+

+

Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
+ +
+ +
+ + +

Offset 0x0400: TX1_DSA_ATR(255:0) Register Array (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|DSA_SETUP_REGS
  0x002000
+ +		 + + + + +
TX1_DSA_ATR
  offset=0x0400 + i*4
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x003400 + i*4 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x003400 + i*4 + +
+ +

+ +

Initial Values
+ + +
default=>0x00001F1F
+

+ +

This register is defined in HDL source file dsa_control.v.
+It uses RegType TX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

+ +
+ +
+ +
+

+
+

Controls the Tx1 DSAs by accessing the raw attenuation levels.

+

This register array can hold settings for all ATR configurations. +The register index equals the ATR configuration. +The active configuration can be selected in ATR_REGMAP. +Independently all configurations can be read/written at any time.

+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..13 +

Reserved

+

+ +
12..8 +

TX_DSA2   (initialvalue=31)

+

+

Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
7..5 +

Reserved

+

+ +
4..0 +

TX_DSA1   (initialvalue=31)

+

+

Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
+ +
+ +
+ + +

Offset 0x0800: RX0_DSA_ATR(255:0) Register Array (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|DSA_SETUP_REGS
  0x002000
+ +		 + + + + +
RX0_DSA_ATR
  offset=0x0800 + i*4
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x003800 + i*4 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x003800 + i*4 + +
+ +

+ +

Initial Values
+ + +
default=>0x0000FFFF
+

+ +

This register is defined in HDL source file dsa_control.v.
+It uses RegType RX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

+ +
+ +
+ +
+

+
+

Controls the Rx0 DSAs by accessing the raw attenuation levels.

+

This register array can hold settings for all ATR configurations. +The register index equals the ATR configuration. +The active configuration can be selected in ATR_REGMAP. +Independently all configurations can be read/written at any time.

+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..12 +

RX_DSA3_B   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/}

+ +
11..8 +

RX_DSA3_A   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
7..4 +

RX_DSA2   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
3..0 +

RX_DSA1   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
+ +
+ +
+ + +

Offset 0x0C00: RX1_DSA_ATR(255:0) Register Array (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|DSA_SETUP_REGS
  0x002000
+ +		 + + + + +
RX1_DSA_ATR
  offset=0x0C00 + i*4
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x003C00 + i*4 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x003C00 + i*4 + +
+ +

+ +

Initial Values
+ + +
default=>0x0000FFFF
+

+ +

This register is defined in HDL source file dsa_control.v.
+It uses RegType RX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

+ +
+ +
+ +
+

+
+

Controls the Rx1 DSAs by accessing the raw attenuation levels.

+

This register array can hold settings for all ATR configurations. +The register index equals the ATR configuration. +The active configuration can be selected in ATR_REGMAP. +Independently all configurations can be read/written at any time.

+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..12 +

RX_DSA3_B   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/}

+ +
11..8 +

RX_DSA3_A   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
7..4 +

RX_DSA2   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
3..0 +

RX_DSA1   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
+ +
+ +
+ + +

Offset 0x1000: TX0_DSA_TABLE_SELECT(255:0) Register Array (W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|DSA_SETUP_REGS
  0x002000
+ +		 + + + + +
TX0_DSA_TABLE_SELECT
  offset=0x1000 + i*4
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x004000 + i*4 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x004000 + i*4 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file dsa_control.v.
+It uses RegType DSA_TABLE_CONTROL which is defined in HDL source file dsa_control.v.

+ +
+ +
+ +
+

+
+

Controls the Tx0 DSAs by using the gain table to translate the table +index to raw attenuation levels. The register offset (i) is targeting +an ATR configuration to store the values from the gain table.

+ +
+ + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..8 +

Reserved

+

+ +
7..0w +

TABLE_INDEX

+

+

Gain table index to be used for getting the raw attenuation values.

+ +
+ +
+ +
+ + +

Offset 0x1400: TX1_DSA_TABLE_SELECT(255:0) Register Array (W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|DSA_SETUP_REGS
  0x002000
+ +		 + + + + +
TX1_DSA_TABLE_SELECT
  offset=0x1400 + i*4
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x004400 + i*4 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x004400 + i*4 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file dsa_control.v.
+It uses RegType DSA_TABLE_CONTROL which is defined in HDL source file dsa_control.v.

+ +
+ +
+ +
+

+
+

Controls the Tx1 DSAs by using the gain table to translate the table +index to raw attenuation levels. The register offset (i) is targeting +an ATR configuration to store the values from the gain table.

+ +
+ + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..8 +

Reserved

+

+ +
7..0w +

TABLE_INDEX

+

+

Gain table index to be used for getting the raw attenuation values.

+ +
+ +
+ +
+ + +

Offset 0x1800: RX0_DSA_TABLE_SELECT(255:0) Register Array (W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|DSA_SETUP_REGS
  0x002000
+ +		 + + + + +
RX0_DSA_TABLE_SELECT
  offset=0x1800 + i*4
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x004800 + i*4 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x004800 + i*4 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file dsa_control.v.
+It uses RegType DSA_TABLE_CONTROL which is defined in HDL source file dsa_control.v.

+ +
+ +
+ +
+

+
+

Controls the Rx0 DSAs by using the gain table to translate the table +index to raw attenuation levels. The register offset (i) is targeting +an ATR configuration to store the values from the gain table.

+ +
+ + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..8 +

Reserved

+

+ +
7..0w +

TABLE_INDEX

+

+

Gain table index to be used for getting the raw attenuation values.

+ +
+ +
+ +
+ + +

Offset 0x1C00: RX1_DSA_TABLE_SELECT(255:0) Register Array (W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|DSA_SETUP_REGS
  0x002000
+ +		 + + + + +
RX1_DSA_TABLE_SELECT
  offset=0x1C00 + i*4
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x004C00 + i*4 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x004C00 + i*4 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file dsa_control.v.
+It uses RegType DSA_TABLE_CONTROL which is defined in HDL source file dsa_control.v.

+ +
+ +
+ +
+

+
+

Controls the Rx1 DSAs by using the gain table to translate the table +index to raw attenuation levels. The register offset (i) is targeting +an ATR configuration to store the values from the gain table.

+ +
+ + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..8 +

Reserved

+

+ +
7..0w +

TABLE_INDEX

+

+

Gain table index to be used for getting the raw attenuation values.

+ +
+ +
+ +
+ + +

Offset 0x2000: TX0_DSA_TABLE(255:0) Register Array (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|DSA_SETUP_REGS
  0x002000
+ +		 + + + + +
TX0_DSA_TABLE
  offset=0x2000 + i*4
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x005000 + i*4 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x005000 + i*4 + +
+ +

+ +

Initial Values
+ + +
default=>0x00001F1F
+

+ +

This register is defined in HDL source file dsa_control.v.
+It uses RegType TX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

+ +
+ +
+ +
+

+
+

Provides access to the gain table for Tx0.

+

Each entry i will be saved in the gain table without any implications +on HW. Enables SW to use the table index in TX0_DSA_TABLE_SELECT to +modify the ATR configurations.

+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..13 +

Reserved

+

+ +
12..8 +

TX_DSA2   (initialvalue=31)

+

+

Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
7..5 +

Reserved

+

+ +
4..0 +

TX_DSA1   (initialvalue=31)

+

+

Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
+ +
+ +
+ + +

Offset 0x2400: TX1_DSA_TABLE(255:0) Register Array (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|DSA_SETUP_REGS
  0x002000
+ +		 + + + + +
TX1_DSA_TABLE
  offset=0x2400 + i*4
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x005400 + i*4 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x005400 + i*4 + +
+ +

+ +

Initial Values
+ + +
default=>0x00001F1F
+

+ +

This register is defined in HDL source file dsa_control.v.
+It uses RegType TX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

+ +
+ +
+ +
+

+
+

Provides access to the gain table for Tx1.

+

Each entry i will be saved in the gain table without any implications +on HW. Enables SW to use the table index in TX1_DSA_TABLE_SELECT to +modify the ATR configurations.

+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..13 +

Reserved

+

+ +
12..8 +

TX_DSA2   (initialvalue=31)

+

+

Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
7..5 +

Reserved

+

+ +
4..0 +

TX_DSA1   (initialvalue=31)

+

+

Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
+ +
+ +
+ + +

Offset 0x2800: RX0_DSA_TABLE(255:0) Register Array (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|DSA_SETUP_REGS
  0x002000
+ +		 + + + + +
RX0_DSA_TABLE
  offset=0x2800 + i*4
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x005800 + i*4 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x005800 + i*4 + +
+ +

+ +

Initial Values
+ + +
default=>0x0000FFFF
+

+ +

This register is defined in HDL source file dsa_control.v.
+It uses RegType RX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

+ +
+ +
+ +
+

+
+

Provides access to the gain table for Rx0.

+

Each entry i will be saved in the gain table without any implications +on HW. Enables SW to use the table index in RX0_DSA_TABLE_SELECT to +modify the ATR configurations.

+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..12 +

RX_DSA3_B   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/}

+ +
11..8 +

RX_DSA3_A   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
7..4 +

RX_DSA2   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
3..0 +

RX_DSA1   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
+ +
+ +
+ + +

Offset 0x2C00: RX1_DSA_TABLE(255:0) Register Array (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|DSA_SETUP_REGS
  0x002000
+ +		 + + + + +
RX1_DSA_TABLE
  offset=0x2C00 + i*4
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x005C00 + i*4 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x005C00 + i*4 + +
+ +

+ +

Initial Values
+ + +
default=>0x0000FFFF
+

+ +

This register is defined in HDL source file dsa_control.v.
+It uses RegType RX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

+ +
+ +
+ +
+

+
+

Provides access to the gain table for Rx1.

+

Each entry i will be saved in the gain table without any implications +on HW. Enables SW to use the table index in RX1_DSA_TABLE_SELECT to +modify the ATR configurations.

+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..12 +

RX_DSA3_B   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/}

+ +
11..8 +

RX_DSA3_A   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
7..4 +

RX_DSA2   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
3..0 +

RX_DSA1   (initialvalue=15)

+

+

Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

+ +
+ +
+ +
+ +
+ +
+ +

GPIO_REGMAP

+ +

GPIO_REGMAP_WINDOWS

+ +
+ + +

Offset 0x0000: BASE_WINDOW_GPIO Window (R|W)

+

  Target regmap = BASIC_REGS_REGMAP

+ (show extended info) +
+ + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + + +
BASE_WINDOW_GPIO
  offset=0x0000
  size=0x20 (32 bytes)
+ +		 + + + + + +
+ + +Total Offset =
  0x000000 + +
+ +

+ +

This window is defined in HDL source file zbx_top_cpld.v.

+ +
+ +
+ + + +
+ +
+ +
+ + +

Offset 0x1000: DB_CONTROL_WINDOW_GPIO Window (R|W)

+

  Target regmap = DB_CONTROL_REGMAP

+ (show extended info) +
+ + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + + +
DB_CONTROL_WINDOW_GPIO
  offset=0x1000
  size=0x5000 (20 Kbytes)
+ +		 + + + + + +
+ + +Total Offset =
  0x001000 + +
+ +

+ +

This window is defined in HDL source file zbx_top_cpld.v.

+ +
+ +
+ + + +
+ +
+ +
+ +
+ +
+ +

LED_SETUP_REGMAP

+ +

LED_SETUP_REGISTERS

+ Contains registers that control the LEDs. +
+ + +

Offset 0x0000: LED_CONTROL(255:0) Register Array (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|LED_SETUP_REGS
  0x000400
+ +		 + + + + +
LED_CONTROL
  offset=0x0000 + i*4
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x001400 + i*4 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x001400 + i*4 + +
+ +

+ +

Initial Values
+ + +
default=>0x00000000
+

+ +

This register is defined in HDL source file led_control.v.
+It uses RegType LED_CONTROL_TYPE which is defined in HDL source file led_control.v.

+ +
+ +
+ +Defines LED functionality.
+This register array can hold settings for all ATR configurations. + The register index equals the ATR configuration. + The active configuration can be selected in ATR_REGMAP. + Independently all configurations can be read/written at any time. + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..19 +

Reserved

+

+ +
18..17 +

CH1_TRX1_LED_EN   (initialvalue=0)

+

This bitfield controls the RG LED
+ Bit 15 controls the Ch1 Rx Green LED
+ Bit 14 controls the Ch1 Tx Red LED

+ +
16 +

CH1_RX2_LED_EN   (initialvalue=0)

+

Enables the Ch1 Rx2 Green LED

+ +
15..8 +

Reserved

+

+ +
7..3 +

Reserved

+

+ +
2..1 +

CH0_TRX1_LED_EN   (initialvalue=0)

+

This bitfield controls the RG LED
+ Bit 6 controls the Ch0 Rx Green LED
+ Bit 7 controls the Ch0 Tx Red LED

+ +
0 +

CH0_RX2_LED_EN   (initialvalue=0)

+

Enables the Ch0 Rx2 Green LED

+ +
+ +
+ +
+ +
+ +
+ +

LO_CONTROL_REGMAP

+ +

LO_SPI_REGISTERS

+ Controls the SPI transaction to the LMX2572 +
+ + +

LO_CHIP_SELECT Enumeration

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Name
0 +

TX0_LO1

+ +
1 +

TX0_LO2

+ +
2 +

TX1_LO1

+ +
3 +

TX1_LO2

+ +
4 +

RX0_LO1

+ +
5 +

RX0_LO2

+ +
6 +

RX1_LO1

+ +
7 +

RX1_LO2

+ +
+ +

+ This enumerated type is defined in HDL source file lo_control.v. +

+ +
+ +
+ + +

Offset 0x0000: LO_SPI_SETUP Register (W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|LO_CONTROL_REGS
  0x000020
+ +		 + + + + +
LO_SPI_SETUP
  offset=0x0000
+ +		 + + + + + +
+ + +Total Offset =
  0x001020 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + +
+ + +Total Offset =
  0x001020 + +
+ +

+ +

Initial Value = 0x00000000 +

+ +

This register is defined in HDL source file lo_control.v.

+ +
+ +
+ +This register sets up the SPI transaction to read/write to/from to the LMX2572. + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..29 +

Reserved

+

+ +
28w +

LO_SPI_START_TRANSACTION   (Strobe, initialvalue=0)

+

Strobe this bit high to start the SPI transaction with the bitfields below

+ +
27 +

Reserved

+

+ +
26..24w +

LO_SELECT   (Strobe, initialvalue=TX0_LO1)

+

Sets the CS to the selected LO. The CS will assert until after LO_SPI_START_TRANSACTION has been asserted.

+ +

+ The values for this bitfield are in the LO_CHIP_SELECT table. + (show here) +

+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Name
0 +

TX0_LO1

+ +
1 +

TX0_LO2

+ +
2 +

TX1_LO1

+ +
3 +

TX1_LO2

+ +
4 +

RX0_LO1

+ +
5 +

RX0_LO2

+ +
6 +

RX1_LO1

+ +
7 +

RX1_LO2

+ +
+ +

+ This enumerated type is defined in HDL source file lo_control.v. +

+ +
+ +
+ +
23w +

LO_SPI_RD   (initialvalue=0)

+

Set this bit to '1' to read from the LMX2572. Set this bit to '0' to write to the LMX2572.

+ +
22..16w +

LO_SPI_WT_ADDR   (initialvalue=0)

+

7 bit address of the LMX2572

+ +
15..0w +

LO_SPI_WT_DATA   (initialvalue=0)

+

Write Data to the LMX2572

+ +
+ +
+ +
+ + +

Offset 0x0000: LO_SPI_STATUS Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|LO_CONTROL_REGS
  0x000020
+ +		 + + + + +
LO_SPI_STATUS
  offset=0x0000
+ +		 + + + + + +
+ + +Total Offset =
  0x001020 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + +
+ + +Total Offset =
  0x001020 + +
+ +

+ +

Initial Value = 0x00000000 +

+ +

This register is defined in HDL source file lo_control.v.

+ +
+ +
+ +This register returns the SPI master status, and also returns the read data from the LMX2572 + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31 +

LO_SPI_DATA_VALID   (initialvalue=0)

+

Returns '1' when a read SPI transaction is complete. This bit will remain high until a new SPI transaction has started. + i.e. LO_SPI_START_TRANSACTION is strobed. Poll this when expecting data from a read transaction.

+ +
30 +

LO_SPI_READY   (initialvalue=0)

+

If this bit returns '1' then LMX2572 is ready for transaction. If it returns '0' then it is busy with a previous SPI transaction. + Poll this bit before starting a SPI transaction.

+ +
29..27 +

Reserved

+

+ +
26..24 +

LO_SELECT_STATUS   (initialvalue=TX0_LO1)

+

Returns the current selected CS. This bitfield will return the value written to LO_SELECT bitfield in the LO_SPI_SETUP reg.

+ +

+ The values for this bitfield are in the LO_CHIP_SELECT table. + (show here) +

+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Name
0 +

TX0_LO1

+ +
1 +

TX0_LO2

+ +
2 +

TX1_LO1

+ +
3 +

TX1_LO2

+ +
4 +

RX0_LO1

+ +
5 +

RX0_LO2

+ +
6 +

RX1_LO1

+ +
7 +

RX1_LO2

+ +
+ +

+ This enumerated type is defined in HDL source file lo_control.v. +

+ +
+ +
+ +
23 +

Reserved

+

+ +
22..16 +

LO_SPI_RD_ADDR   (initialvalue=0)

+

Returns the address of the current SPI address setup

+ +
15..0 +

LO_SPI_RD_DATA   (initialvalue=0)

+

Returns the data of the SPI read. This bitfield will return 0x0000 until LO_SPI_DATA_VALID is true. This bit field will maintain it's + read value until a new SPI transaction has started. i.e. LO_SPI_START_TRANSACTION is strobed.

+ +
+ +
+ +
+ +

LO_SYNC_REGS

+ Contains registers that control the logic lines in charge of synchronization +
+ + +

Offset 0x0004: LO_PULSE_SYNC Register (W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
  0x001000
+ +		 + + + + +
DB_CONTROL_REGMAP|LO_CONTROL_REGS
  0x000020
+ +		 + + + + +
LO_PULSE_SYNC
  offset=0x0004
+ +		 + + + + + +
+ + +Total Offset =
  0x001024 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
  0x001000
+ +		 + + + + + +
+ + +Total Offset =
  0x001024 + +
+ +

+ +

Initial Value = 0x00000000 +

+ +

This register is defined in HDL source file lo_control.v.

+ +
+ +
+ +Controls pulses driven to the SYNC pins of the LMX2572 chips + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..9 +

Reserved

+

+ +
8w +

BYPASS_SYNC_REGISTER   (initialvalue=0)

+

Setting this bit to '1' will ignore writes to the PULSE_X_SYNC fields and allow + a buffered input SYNC pulse to be driven out instead.

+ +
7w +

PULSE_RX1_LO2_SYNC   (Strobe, initialvalue=0)

+

Creates a single cycle pulse on the RX1_LO2_SYNC line.

+ +
6w +

PULSE_RX1_LO1_SYNC   (Strobe, initialvalue=0)

+

Creates a single cycle pulse on the RX1_LO1_SYNC line.

+ +
5w +

PULSE_RX0_LO2_SYNC   (Strobe, initialvalue=0)

+

Creates a single cycle pulse on the RX0_LO2_SYNC line.

+ +
4w +

PULSE_RX0_LO1_SYNC   (Strobe, initialvalue=0)

+

Creates a single cycle pulse on the RX0_LO1_SYNC line.

+ +
3w +

PULSE_TX1_LO2_SYNC   (Strobe, initialvalue=0)

+

Creates a single cycle pulse on the TX1_LO2_SYNC line.

+ +
2w +

PULSE_TX1_LO1_SYNC   (Strobe, initialvalue=0)

+

Creates a single cycle pulse on the TX1_LO1_SYNC line.

+ +
1w +

PULSE_TX0_LO2_SYNC   (Strobe, initialvalue=0)

+

Creates a single cycle pulse on the TX0_LO2_SYNC line.

+ +
0w +

PULSE_TX0_LO1_SYNC   (Strobe, initialvalue=0)

+

Creates a single cycle pulse on the TX0_LO1_SYNC line.

+ +
+ +
+ +
+ +
+ +
+ +

POWER_REGS_REGMAP

+

This regmap has readablestrobes="true", so all strobe bits are readable by +default. This attribute should only be used for older regmaps to maintain +compatibility with previous versions of XmlParse. New regmaps should either +use the 'clearable' attribute or should explicitly define readable bits +in the same bit position as the strobe bits.

+ +

POWER_REGS_REGISTERS

+ This regmap contains the registers to control the power supplies and the clock buffer for PLL reference clock. +
+ + +

Offset 0x0000: RF_POWER_CONTROL Register (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|POWER_REGS
  0x000040
+ +		 + + + + +
RF_POWER_CONTROL
  offset=0x0000
+ +		 + + + + + +
+ + +Total Offset =
  0x000040 + +
+ +

+ +

Initial Value = 0x00000000 +

+ +

This register is defined in HDL source file power_regs.v.

+ +
+ +
+ +This register controls power supply enables to the Tx/Rx amps, switch control, and clk buffers. During normal + operations, all three power supplies should be enabled. + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..8 +

Reserved

+

+ +
7..3 +

Reserved

+

+ +
2 +

ENABLE_3v3   (initialvalue=0)

+

This power supply sources the switch control, and the clock buffers. By default this power supply is off. + The internal LOs will not work unless this bit is enabled.

+ +
1 +

ENABLE_RX_7V0   (initialvalue=0)

+

This power supply sources the Rx0 and Rx1 amps. By default this power supply is off.The Rx0/1 path will not + be active unless this power supply is enabled. Disabling this bit is similar to RX RF blanking
+ note to digital engineer, this is Pos7v0B

+ +
0 +

ENABLE_TX_7V0   (initialvalue=0)

+

This power supply sources the Tx0 and Tx1 amps. By default this power supply is off. The Tx0/1 path will not + be active unless this power supply is enabled. Disabling this bit is similar to TX RF blanking
+ note to digital engineer, this is Pos7v0A

+ +
+ +
+ +
+ + +

Offset 0x0004: RF_POWER_STATUS Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|POWER_REGS
  0x000040
+ +		 + + + + +
RF_POWER_STATUS
  offset=0x0004
+ +		 + + + + + +
+ + +Total Offset =
  0x000044 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file power_regs.v.

+ +
+ +
+ +Returns status of PowerGood indicators across the daughterboard. + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..8 +

Reserved

+

+ +
7..2 +

Reserved

+

+ +
1 +

P7V_B_STATUS

+

Returns status of 7V switching regulator B.

+ +
0 +

P7V_A_STATUS

+

Returns status of 7V switching regulator A.

+ +
+ +
+ +
+ + +

Offset 0x0008: PRC_CONTROL Register (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|POWER_REGS
  0x000040
+ +		 + + + + +
PRC_CONTROL
  offset=0x0008
+ +		 + + + + + +
+ + +Total Offset =
  0x000048 + +
+ +

+ +

Initial Value = 0x00000000 +

+ +

This register is defined in HDL source file power_regs.v.

+ +
+ +
+ +Offers ability to enable or disable the PLL reference clock. + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..8 +

Reserved

+

+ +
7..1 +

Reserved

+

+ +
0 +

PLL_REF_CLOCK_ENABLE   (initialvalue=0)

+

If set PLL reference clock is enabled.

+ +
+ +
+ +
+ +
+ +
+ +

RECONFIG_REGMAP

+ +

RECONFIG_REGS

+ These registers are used to upload and verify a new primary image to the + Max 10 FPGA on-chip flash when configured to support dual configuration + images. The steps below outline the process of verifying/preparing the + new image to be written, erasing the current image, writing the new + image, and verifying the new image was successfully written. +

Prepare the data... +

  1. The Max 10 FPGA build should generate a *cfm0_auto.rpd + file The *.rpd file is a "raw programming + data" file holding all data related to the + configuration image (CFM0). There are two + important items to note regarding the addresses. + First the *rpd data uses byte addresses. + Second, the start/end addresses defined by + FLASH_PRIMARY_IMAGE_ADDR_ENUM are 32-bit word addresses

    2. +

  2. As a sanity check, verify the size of the raw + programming data for CFM0 correspond to the address + range of FLASH_PRIMARY_IMAGE_ADDR_ENUM. Do this by + reading the values from FLASH_CFM0_START_ADDR_REG and + FLASH_CFM0_END_ADDR, subtract both values, add one and + multiply by four. +

    3. +

  3. Having passed the sanity check the *.rpd data must + now be manipulated into the form required by Altera's + on-chip flash IP. Two operations must be performed. + First the data must be converted from bytes to 32-bit + words. Second the bit order must be reversed. This is + illustrated in in the following table which shows byte + address and data from the *.rpd file compared to the + word address and data to be written to the on-chip + flash. + + + + + + + + + + +
    .Map Addr.Map DataFlash AddrFlash Data
    0x2B8000x010xAC000x8040C020
    0x2B8010x02
    0x2B8020x03
    0x2B8030x04
    0x2B8040x050xAC010xA060E010
    0x2B8050x06
    0x2B8060x07
    0x2B8070x08
    +

    4. +

  4. The resulting set of flash address data pairs should + be used when writing FLASH_ADDR_REG and + FLASH_WRITE_DATA_REG to update the CFM0 image. + However, prior to writing the new image the old image + must be erased. +

    5. +
+

+

Erase the current primary flash image... +

  1. Read FLASH_STATUS_REG and verify no error bits are + asserted and that all read, write, and erase operations + are idle.

    2. +

  2. Disable write protection of the flash by strobing the + FLASH_DISABLE_WP_STB bit of FLASH_CONTROL_REG. +

    3. +

  3. Verify write protection is disabled and no errors are + present by reading FLASH_STATUS_REG.

    4. +

  4. Initiate the erase operation by setting + FLASH_ERASE_SECTOR and strobing FLASH_ERASE_STB of + FLASH_CONTROL_REG.

    5. +

  5. Poll the FLASH_ERASE_IDLE bit of + FLASH_STATUS_REG until it de-asserts indicating the + erase operation is complete, then verify the operation + was successful by checking that the FLASH_ERASE_ERR + bit is de-asserted. Erase operations are expected to + take a maximum of 350 msec. Upon completion of the erase + operation write protection will remain disabled. +

    6. +

  6. Erase additional sectors as required (see + FLASH_ERASE_SECTOR for details) by restarting with first + step.

    7. +
+

+

Write the new primary flash image... +

  1. Read FLASH_STATUS_REG and verify no error bits are + asserted, all read, write, and erase operations are + idle, and write protection is disabled.
    2. +

  2. Set the target address for the write to the Max 10 + on-chip flash by writing value from + FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.

    3. +

  3. Set the data to be written to this address by writing + the new 32-bit word of the new image to + FLASH_WRITE_DATA_REG.

    4. +

  4. Initiate the write by strobing FLASH_WRITE_STB of + FLASH_CONTROL_REG.

    5. +

  5. Poll the FLASH_WRITE_IDLE bit of + FLASH_STATUS_REG until it de-asserts indicating the + write operation is complete, then verify the operation + was successful by checking that the FLASH_WRITE_ERR + bit is de-asserted. Write operations are expected to + take a maximum of 550 usec.

    6. +

  6. Upon completion of the write operation return to step + 2, incrementing the target address by one, and writing + the next 32-bit word to Max10FlashWriteDatReg. If this + was the last write, indicated by writing to + FLASH_PRIMARY_IMAGE_END_ADDR, proceed to the next step + to enable write protection.

    7. +

  7. After writing the new image enable write protection + by strobing the FLASH_ENABLE_WP_STB bit of + FLASH_CONTROL_REG.

    8. +
+

+

Verify the new primary flash image... +

  1. Read FLASH_STATUS_REG and verify no error bits are + asserted and that all read, write, and erase operations + are idle.

    2. +

  2. Set the target address for the read in the Max 10 + on-chip flash by writing value from + FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.

    3. +

  3. Initiate the read by strobing FLASH_READ_STB of + FLASH_CONTROL_REG.

    4. +

  4. Poll the FLASH_READ_IDLE bit of + FLASH_STATUS_REG until it de-asserts indicating the + read operation is complete, then verify the operation + was successful by checking that the FLASH_READ_ERR + bit is de-asserted. There is no guidance on exactly how + long reads take to complete, but they are expected to be + fairly quick. A very conservative timeout on this + polling would be similar to that used for write + operations.

    5. +

  5. Upon completion of the read operation the resulting + data returned by the on-chip flash will be available in + Max10FlashReadDatReg. Read this register, compare to + expected value previously written, and ensure they + match.

    6. +

  6. Return to step 2, incrementing the target + address by one. If this was the last read verification + is complete and no further action is required.

    7. +
+

+

After the flash has been erased, programmed, and verified, a power + cycle is required for the new image to become active. +

+
+ + +

FLASH_PRIMARY_IMAGE_ADDR_ENUM Enumeration

+Those values are the start and end address of the CFM image flash + sector from Intel's On-Chip Flash IP Generator. Note that the values + given in the IP generator are byte based where the values of this enum + are U32 based (divided by 4). + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Name
Dec Hex
40960x01000 +

FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT

+ +
399360x09C00 +

FLASH_PRIMARY_IMAGE_START_ADDR

+ +
757750x127FF +

FLASH_PRIMARY_IMAGE_END_ADDR

+ +
+ +

+ This enumerated type is defined in HDL source file reconfig_engine.v. +

+ +
+ +
+ + +

Offset 0x0000: FLASH_STATUS_REG Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|RECONFIG
  0x000020
+ +		 + + + + +
FLASH_STATUS_REG
  offset=0x0000
+ +		 + + + + + +
+ + +Total Offset =
  0x000020 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file reconfig_engine.v.

+ +
+ +
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..17 +

Reserved

+

+ +
16 +

FLASH_MEM_INIT_ENABLED

+

This bit is asserted when the flash can hold an image with memory + initialization.

+ +
15..14 +

Reserved

+

+ +
13 +

FLASH_WRITE_ERR

+

This bit is asserted when write operation fails. Clear this error + by strobing the CLEAR_FLASH_WRITE_ERROR_STB bit of this register. In + the event of a write error... +

  • the primary configuration image may be corrupted, and + power cycling the board may result unknown behavior.
    • +
  • write protection of the flash will automatically be + re-enabled.
    • +
  • attempts to disable write protection will be ignored.
    • +
  • attempts to read/write/erase the flash will be ignored.

    • + +
    12 +

    FLASH_WRITE_IDLE

    +

    This bit is de-asserted when a write operation is in progress. Poll + this bit after strobing the FLASH_WRITE_STB bit of + FLASH_CONTROL_REG to determine when the write operation has + completed, then check the FLASH_WRITE_ERR bit to verify the + operation was successful.

    + +
    11..10 +

    Reserved

    +

    + +
    9 +

    FLASH_ERASE_ERR

    +

    This bit is asserted when an erase operation fails. Clear this + error by strobing CLEAR_FLASH_ERASE_ERROR_STB of this register. In + the event of an erase error... +

  • the primary configuration image may be corrupted, and + power cycling the board may result in unknown behavior.
    • +
  • write protection of the flash will automatically be + re-enabled.
    • +
  • attempts to disable write protection will be ignored.
    • +
  • attempts to read/write/erase the flash will be ignored.

    • + +
    8 +

    FLASH_ERASE_IDLE

    +

    This bit is de-asserted when an erase operation is in progress. Poll + this bit after strobing the FLASH_ERASE_STB bit of + FLASH_CONTROL_REG to determine when the erase operation has + completed, then check the FLASH_ERASE_ERR bit to verify the + operation was successful.

    + +
    7..6 +

    Reserved

    +

    + +
    5 +

    FLASH_READ_ERR

    +

    This bit is asserted when a read operation fails. Clear this error + by strobing the CLEAR_FLASH_READ_ERROR_STB of this register. In the + event of a read error... +

  • the data in FLASH_READ_DATA_REG is invalid.
    • +
  • attempts to disable write protection will be ignored.
    • +
  • attempts to read/write/erase the flash will be ignored.

    • + +
    4 +

    FLASH_READ_IDLE

    +

    This bit is de-asserted when a read operation is in progress. Poll + this bit after strobing the FLASH_READ_STB bit of + FLASH_CONTROL_REG to determine when the read operation has + completed, then check the FLASH_READ_ERR bit to verify the + operation was successful.

    + +
    3..1 +

    Reserved

    +

    + +
    0 +

    FLASH_WP_ENABLED

    +

    This bit is asserted when the flash is write protected and + de-asserted when write protection is disabled. +

  • Write protection must be enabled prior to performing read + operations.
    • +
  • Write protection must be disabled prior to performing write and + erase operations.

    • + +
    + +
    + +
    + + +

    Offset 0x0004: FLASH_CONTROL_REG Register (W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port SPI
    + +    		 + + + + +
    SPI_REGMAP|RECONFIG
      0x000020
    + +    		 + + + + +
    FLASH_CONTROL_REG
      offset=0x0004
    + +    		 + + + + + +
    + + +Total Offset =
      0x000024 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file reconfig_engine.v.

    + +
    + +
    + + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..11 +

    Reserved

    +

    + +
    10w +

    CLEAR_FLASH_ERASE_ERROR_STB   (Strobe)

    +

    Strobe this bit to clear an erase error.

    + +
    9w +

    CLEAR_FLASH_WRITE_ERROR_STB   (Strobe)

    +

    Strobe this bit to clear a write error.

    + +
    8w +

    CLEAR_FLASH_READ_ERROR_STB   (Strobe)

    +

    Strobe this bit to clear a read error.

    + +
    7..5w +

    FLASH_ERASE_SECTOR   (Strobe)

    +

    Defines the sector to be erased. Has to be set latest with the + write access which starts the erase operation by strobing + FLASH_ERASE_STB.
    + If the flash is configured to support memory initialization (see + FLASH_MEM_INIT_ENABLED flag) the sectors 2 to 4 have to be erased. + If the flag is not asserted only sector 4 has to be erased.

    + +
    4w +

    FLASH_ERASE_STB   (Strobe)

    +

    Strobe this bit to erase the primary Max10 configuration image + (CFM0). +

  • Prior to strobing this bit verify no other write or erase + operations are in progress, write protection is disabled, and no + error bits are asserted by reading FLASH_STATUS_REG.
    • +
  • Attempts to erase the primary image while other write or erase + operations are in progress will be ignored. +
  • Attempts to erase the primary image when write protection is + enabled will be ignored.
    • +
  • Strobing this bit and FLASH_WRITE_STB simultaneously will + result both the erase and the write operation being ignored, both + corresponding error bits being set, and write protection being + re-enabled.
    • +
  • After strobing this bit poll the FLASH_ERASE_IDLE and + FLASH_ERASE_ERR bits of FLASH_STATUS_REG to determine when + the erase operation is complete and if it was successful.

    • + +
    3w +

    FLASH_WRITE_STB   (Strobe)

    +

    Strobe this bit to write the data contained in + FLASH_WRITE_DATA_REG to the flash address identified in + FLASH_ADDR_REG. +

  • The flash must be erased before writing new data.
    • +
  • Prior to strobing this bit verify write protection is + disabled, no other write or erase operations are in progress, and + no error bits are asserted by reading FLASH_STATUS_REG.
    • +
  • Attempts to write data while other write or erase operations + are in progress will be ignored.
    • +
  • Attempts to write data with write protection enabled will be + ignored.
    • +
  • Strobing this bit and FLASH_ERASE_STB simultaneously will + result in both the write and erase operation being ignored, + both corresponding error bits being set, and write protection + being re-enabled.
    • +
  • After strobing this bit poll theMax10FlashWriteIdle and + FLASH_WRITE_ERR bits of FLASH_STATUS_REG to determine when + the write operation is complete and if it was successful.

    • + +
    2w +

    FLASH_READ_STB   (Strobe)

    +

    Strobe this bit to read data from the flash address identified in + FLASH_ADDR_REG. +

  • Prior to strobing this bit verify no read, write, or erase + operations are in progress, no error bits are asserted, and + write protection is enabled by reading FLASH_STATUS_REG.
    • +
  • Attempts to read data while other operations are in progress + or while write protection is disabled will be ignored.
    • +
  • After strobing this bit poll the FLASH_READ_IDLE and + FLASH_READ_ERR bits of FLASH_STATUS_REG to determine when + the read operation is complete and if it was successful.
    • +
  • Upon successful completion the data read from flash will be + available in FLASH_READ_DATA_REG.

    • + +
    1w +

    FLASH_DISABLE_WP_STB   (Strobe)

    +

    Strobe this bit to disable write protection to the section of the + Max 10 on-chip flash storing the primary configuration image + (CFM0). +

  • Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to + determine the current state of write protection.
    • +
  • Prior to strobing this bit verify no read operations are in + progress and no error bits are asserted by reading + FLASH_STATUS_REG.
    • +
  • Attempts to disable write protection while a read is in + progress will be ignored.
    • +
  • Attempts to disable write protection will be ignored if + this bit is strobed simultaneously with either FLASH_READ_STB + or FLASH_ENABLE_WP_STB.
    • +
  • Write protection must be disabled prior to performing erase or + write operations.
    • +
  • Upon completion of erase/write operations write protection + will remain disabled. When not actively erasing or writing a new + image write protection should be enabled to avoid data + corruption.

    • + +
    0w +

    FLASH_ENABLE_WP_STB   (Strobe)

    +

    Strobe this bit to enable write protection to the section of the + Max 10 on-chip flash storing the primary configuration image + (CFM0). +

  • Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to + determine the current state of write protection.
    • +
  • Prior to strobing this bit verify no write or erase operations + are in progress and no error bits are asserted by reading + FLASH_STATUS_REG.
    • +
  • Attempts to enable write protection while erase or write + operations are in progress will be ignored.
    • +
  • Write protection must be enabled prior to performing + read operations.
    • +
  • Write protection should be enabled after completing + write or erase operations to prevent data corruption.

    • + +
    + +
    + +
    + + +

    Offset 0x0008: FLASH_ADDR_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port SPI
    + +    		 + + + + +
    SPI_REGMAP|RECONFIG
      0x000020
    + +    		 + + + + +
    FLASH_ADDR_REG
      offset=0x0008
    + +    		 + + + + + +
    + + +Total Offset =
      0x000028 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file reconfig_engine.v.

    + +
    + +
    + + + +
    + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..17 +

    Reserved

    +

    + +
    16..0 +

    FLASH_ADDR

    +

    This field holds the target address for the next read or + write operation. Set this field prior to strobing the + FLASH_WRITE_STB and FLASH_READ_STB bits of + FLASH_CONTROL_REG. Valid addresses are defined by the + FLASH_PRIMARY_IMAGE_ADDR_ENUM enumeration.

    + +
    + +
    + +
    + + +

    Offset 0x000C: FLASH_WRITE_DATA_REG Register (W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port SPI
    + +    		 + + + + +
    SPI_REGMAP|RECONFIG
      0x000020
    + +    		 + + + + +
    FLASH_WRITE_DATA_REG
      offset=0x000C
    + +    		 + + + + + +
    + + +Total Offset =
      0x00002C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file reconfig_engine.v.

    + +
    + +
    + + + +
    + + + + + + + + + +
    BitsName
    31..0w +

    FLASH_WRITE_DATA

    +

    Data in this register will be written to the flash at the address + identified in FLASH_ADDR_REG when a successful write operation + is executed.

    + +
    + +
    + +
    + + +

    Offset 0x0010: FLASH_READ_DATA_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port SPI
    + +    		 + + + + +
    SPI_REGMAP|RECONFIG
      0x000020
    + +    		 + + + + +
    FLASH_READ_DATA_REG
      offset=0x0010
    + +    		 + + + + + +
    + + +Total Offset =
      0x000030 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file reconfig_engine.v.

    + +
    + +
    + + + +
    + + + + + + + + + +
    BitsName
    31..0 +

    FLASH_READ_DATA

    +

    This register contains data read from the flash address identified + in FLASH_ADDR_REG after a successful read operation is executed.

    + +
    + +
    + +
    + + +

    Offset 0x0014: FLASH_CFM0_START_ADDR_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port SPI
    + +    		 + + + + +
    SPI_REGMAP|RECONFIG
      0x000020
    + +    		 + + + + +
    FLASH_CFM0_START_ADDR_REG
      offset=0x0014
    + +    		 + + + + + +
    + + +Total Offset =
      0x000034 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file reconfig_engine.v.

    + +
    + +
    + + + +
    + + + + + + + + + +
    BitsName
    31..0 +

    FLASH_CFM0_START_ADDR

    +

    Start address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM).

    + +
    + +
    + +
    + + +

    Offset 0x0018: FLASH_CFM0_END_ADDR_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port SPI
    + +    		 + + + + +
    SPI_REGMAP|RECONFIG
      0x000020
    + +    		 + + + + +
    FLASH_CFM0_END_ADDR_REG
      offset=0x0018
    + +    		 + + + + + +
    + + +Total Offset =
      0x000038 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file reconfig_engine.v.

    + +
    + +
    + + + +
    + + + + + + + + + +
    BitsName
    31..0 +

    FLASH_CFM0_END_ADDR

    +

    Last address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM).

    + +
    + +
    + +
    + +
    + +
    + +

    SPI_REGMAP

    + +

    SPI_REGMAP_WINDOWS

    + +
    + + +

    Offset 0x0000: BASE_WINDOW_SPI Window (R|W)

    +

      Target regmap = BASIC_REGS_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port SPI
    + +    		 + + + + + +
    BASE_WINDOW_SPI
      offset=0x0000
      size=0x20 (32 bytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x000000 + +
    + +

    + +

    This window is defined in HDL source file zbx_top_cpld.v.

    + +
    + +
    + + + +
    + +
    + +
    + + +

    Offset 0x0020: RECONFIG Window (R|W)

    +

      Target regmap = RECONFIG_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port SPI
    + +    		 + + + + + +
    RECONFIG
      offset=0x0020
      size=0x20 (32 bytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x000020 + +
    + +

    + +

    This window is defined in HDL source file zbx_top_cpld.v.

    + +
    + +
    + + + +
    + +
    + +
    + + +

    Offset 0x0040: POWER_REGS Window (R|W)

    +

      Target regmap = POWER_REGS_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port SPI
    + +    		 + + + + + +
    POWER_REGS
      offset=0x0040
      size=0x20 (32 bytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x000040 + +
    + +

    + +

    This window is defined in HDL source file zbx_top_cpld.v.

    + +
    + +
    + + + +
    + +
    + +
    + + +

    Offset 0x1000: DB_CONTROL_WINDOW_SPI Window (R|W)

    +

      Target regmap = DB_CONTROL_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port SPI
    + +    		 + + + + + +
    DB_CONTROL_WINDOW_SPI
      offset=0x1000
      size=0x5000 (20 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x001000 + +
    + +

    + +

    This window is defined in HDL source file zbx_top_cpld.v.

    + +
    + +
    + + + +
    + +
    + +
    + +
    + +
    + +

    SWITCH_SETUP_REGMAP

    + +

    SWITCH_SETUP_REGISTERS

    + The following registers are used to control the path that the RF signal + takes for both Tx and Rx

    +
    + + +

    Offset 0x0000: TX0_PATH_CONTROL(255:0) Register Array (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port GPIO
    + +    		 + + + + +
    GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
      0x001000
    + +    		 + + + + +
    DB_CONTROL_REGMAP|SWITCH_SETUP_REGS
      0x001000
    + +    		 + + + + +
    TX0_PATH_CONTROL
      offset=0x0000 + i*4
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x002000 + i*4 + +
    + +
    + + + +
    Port SPI
    + +    		 + + + + +
    SPI_REGMAP|DB_CONTROL_WINDOW_SPI
      0x001000
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x002000 + i*4 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file switch_control.v.
    +It uses RegType TX_PATH_CONTROL which is defined in HDL source file switch_control.v.

    + +
    + +
    + +This Register controls the switches along the Tx path. Note: default + values refer to the RX0 path. RX1 has the same defaults, but their + bit values may differ.
    +This Register controls the Tx0 paths.
    + This register array can hold settings for all ATR configurations. + The register index equals the ATR configuration. + The active configuration can be selected in ATR_REGMAP. + Independently all configurations can be read/written at any time. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..27 +

    Reserved

    +

    + +
    26 +

    TX_SWITCH_14   (initialvalue=0)

    +

    Control for Tx Switch 13 LO path. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx external LO path
    + Write 1 to select Tx internal LO path
    + FOR TX1:
    + Write 0 to select Tx internal LO path
    + Write 1 to select Tx external LO path

    + +
    25 +

    Reserved

    +

    + +
    24 +

    TX_SWITCH_13   (initialvalue=0)

    +

    Control for Tx0 Switch 13 LO path. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx0 internal LO path
    + Write 1 to select Tx0 external LO path
    + FOR TX1:
    + Write 0 to select Tx0 external LO path
    + Write 1 to select Tx0 internal LO path

    + +
    23..22 +

    Reserved

    +

    + +
    21..20 +

    TX_SWITCH_11   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 11. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx Rx path, RX_SWITCH_1 must also select the correct path
    + Write 1 to select Tx highband amp path. TX_SWITCH_10 must also match this path.
    + Write 2 to select Tx lowband amp path. TX_SWITCH_10 must also match this path.
    + Write 3 to select Tx amplifier bypass path
    + FOR TX1:
    + Write 0 to select Tx Rx path, RX_SWITCH_1 must also select the correct path
    + Write 1 to select Tx amplifier bypass path
    + Write 2 to select Tx lowband amp path. TX_SWITCH_10 must also match this path.
    + Write 3 to select Tx highband amp path. TX_SWITCH_10 must also match this path.

    + +
    19..18 +

    TX_SWITCH_10   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 10. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx amplifier bypass path
    + Write 1 to select Tx calibration loopback path
    + Write 2 to select Tx lowband amp path. TX_Switch_11 must also match this path.
    + Write 3 to select Tx highband amp path. TX_Switch_11 must also match this path.
    + FOR TX1:
    + Write 0 to select Tx highband amp path. TX_Switch_11 must also match this path.
    + Write 1 to select Tx lowband amp path. TX_Switch_11 must also match this path.
    + Write 2 to select Tx amplifier bypass path
    + Write 3 to select Tx calibration loopback path

    + +
    17..16 +

    TX_SWITCH_9   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 9. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx RF3 path, 2.3 GHz to 3.1 GHz
    + Write 1 to select Tx RF1 path, 1.0 MHz to 1.95 GHz
    + Write 2 to select Tx RF2 path, 1.95 GHz to 2.3 GHz
    + Write 3 to select Tx RF4 path, 3.1 GHz to 8.0 GHz
    + FOR TX1:
    + Write 0 to select Tx RF4 path, 3.1 GHz to 8.0 GHz
    + Write 1 to select Tx RF2 path, 1.95 GHz to 2.3 GHz
    + Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz
    + Write 3 to select Tx RF3 path, 2.3 GHz to 3.1 GHz

    + +
    15 +

    Reserved

    +

    + +
    14..12 +

    TX_SWITCH_8   (initialvalue=0)

    +

    Control for Tx Switch 8, note this is one hot encoding and not binary. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 1 to select Tx RF3 path, 2.3 GHz to 3.1 GHz
    + Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz
    + Write 4 to select Tx RF2 path, 1.95 GHz to 2.3 GHz
    + FOR TX1:
    + Write 1 to select Tx RF2 path, 1.95 GHz to 2.3 GHz
    + Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz
    + Write 4 to select Tx RF3 path, 2.3 GHz to 3.1 GHz
    + *All other values are invalid

    + +
    11..10 +

    TX_SWITCH_7   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 7. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select 50 ohm termination
    + Write 1 to select no connect
    + Write 2 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz
    + Write 3 to select Tx lowbands RF1, RF2, RF3 path. See TX_SWITCH_8 for those controls
    + FOR TX1:
    + Write 0 to select Tx lowbands RF1, RF2, RF3 path. See TX_SWITCH_8 for those controls
    + Write 1 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz
    + Write 2 to select no connect
    + Write 3 to select 50 ohm termination

    + +
    9..8 +

    TX_SWITCH_6   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 6. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz
    + Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz
    + Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz
    + Write 3 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See TX_SWITCH_5 for those controls
    + FOR TX1:
    + Write 0 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See TX_SWITCH_5 for those controls
    + Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz
    + Write 2 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz
    + Write 3 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz

    + +
    7..6 +

    TX_SWITCH_5   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 5. This switch path is only taken if TX_SWITCH_6 is set to 0. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz
    + Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz
    + Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz
    + Write 3 to select Tx If1 Filter 50 ohm termination
    + FOR TX1:
    + Write 0 to select Tx If1 Filter 50 ohm termination
    + Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz
    + Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz
    + Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz

    + +
    5..4 +

    TX_SWITCH_4   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 4. This switch path is only taken if TX_SWITCH_4 is set to 0. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select 50 ohm termination
    + Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz
    + Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz
    + Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz
    + FOR TX1:
    + Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz
    + Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz
    + Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz
    + Write 3 to select 50 ohm termination

    + +
    3..2 +

    TX_SWITCH_3   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 3. The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See TX_SWITCH_4 for those controls
    + Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz
    + Write 2 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz
    + Write 3 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz
    + FOR TX1:
    + Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz
    + Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz
    + Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz
    + Write 3 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See TX_SWITCH_4 for those controls

    + +
    1 +

    Reserved

    +

    + +
    0 +

    TX_SWITCH_1_2   (initialvalue=0)

    +

    Write 0 to select Tx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz
    + Write 1 to select Tx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz

    + +
    + +
    + +
    + + +

    Offset 0x0400: TX1_PATH_CONTROL(255:0) Register Array (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port GPIO
    + +    		 + + + + +
    GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
      0x001000
    + +    		 + + + + +
    DB_CONTROL_REGMAP|SWITCH_SETUP_REGS
      0x001000
    + +    		 + + + + +
    TX1_PATH_CONTROL
      offset=0x0400 + i*4
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x002400 + i*4 + +
    + +
    + + + +
    Port SPI
    + +    		 + + + + +
    SPI_REGMAP|DB_CONTROL_WINDOW_SPI
      0x001000
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x002400 + i*4 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file switch_control.v.
    +It uses RegType TX_PATH_CONTROL which is defined in HDL source file switch_control.v.

    + +
    + +
    + +This Register controls the switches along the Tx path. Note: default + values refer to the RX0 path. RX1 has the same defaults, but their + bit values may differ.
    +This Register controls the Tx1 paths.
    + This register array can hold settings for all ATR configurations. + The register index equals the ATR configuration. + The active configuration can be selected in ATR_REGMAP. + Independently all configurations can be read/written at any time. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..27 +

    Reserved

    +

    + +
    26 +

    TX_SWITCH_14   (initialvalue=0)

    +

    Control for Tx Switch 13 LO path. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx external LO path
    + Write 1 to select Tx internal LO path
    + FOR TX1:
    + Write 0 to select Tx internal LO path
    + Write 1 to select Tx external LO path

    + +
    25 +

    Reserved

    +

    + +
    24 +

    TX_SWITCH_13   (initialvalue=0)

    +

    Control for Tx0 Switch 13 LO path. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx0 internal LO path
    + Write 1 to select Tx0 external LO path
    + FOR TX1:
    + Write 0 to select Tx0 external LO path
    + Write 1 to select Tx0 internal LO path

    + +
    23..22 +

    Reserved

    +

    + +
    21..20 +

    TX_SWITCH_11   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 11. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx Rx path, RX_SWITCH_1 must also select the correct path
    + Write 1 to select Tx highband amp path. TX_SWITCH_10 must also match this path.
    + Write 2 to select Tx lowband amp path. TX_SWITCH_10 must also match this path.
    + Write 3 to select Tx amplifier bypass path
    + FOR TX1:
    + Write 0 to select Tx Rx path, RX_SWITCH_1 must also select the correct path
    + Write 1 to select Tx amplifier bypass path
    + Write 2 to select Tx lowband amp path. TX_SWITCH_10 must also match this path.
    + Write 3 to select Tx highband amp path. TX_SWITCH_10 must also match this path.

    + +
    19..18 +

    TX_SWITCH_10   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 10. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx amplifier bypass path
    + Write 1 to select Tx calibration loopback path
    + Write 2 to select Tx lowband amp path. TX_Switch_11 must also match this path.
    + Write 3 to select Tx highband amp path. TX_Switch_11 must also match this path.
    + FOR TX1:
    + Write 0 to select Tx highband amp path. TX_Switch_11 must also match this path.
    + Write 1 to select Tx lowband amp path. TX_Switch_11 must also match this path.
    + Write 2 to select Tx amplifier bypass path
    + Write 3 to select Tx calibration loopback path

    + +
    17..16 +

    TX_SWITCH_9   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 9. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx RF3 path, 2.3 GHz to 3.1 GHz
    + Write 1 to select Tx RF1 path, 1.0 MHz to 1.95 GHz
    + Write 2 to select Tx RF2 path, 1.95 GHz to 2.3 GHz
    + Write 3 to select Tx RF4 path, 3.1 GHz to 8.0 GHz
    + FOR TX1:
    + Write 0 to select Tx RF4 path, 3.1 GHz to 8.0 GHz
    + Write 1 to select Tx RF2 path, 1.95 GHz to 2.3 GHz
    + Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz
    + Write 3 to select Tx RF3 path, 2.3 GHz to 3.1 GHz

    + +
    15 +

    Reserved

    +

    + +
    14..12 +

    TX_SWITCH_8   (initialvalue=0)

    +

    Control for Tx Switch 8, note this is one hot encoding and not binary. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 1 to select Tx RF3 path, 2.3 GHz to 3.1 GHz
    + Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz
    + Write 4 to select Tx RF2 path, 1.95 GHz to 2.3 GHz
    + FOR TX1:
    + Write 1 to select Tx RF2 path, 1.95 GHz to 2.3 GHz
    + Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz
    + Write 4 to select Tx RF3 path, 2.3 GHz to 3.1 GHz
    + *All other values are invalid

    + +
    11..10 +

    TX_SWITCH_7   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 7. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select 50 ohm termination
    + Write 1 to select no connect
    + Write 2 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz
    + Write 3 to select Tx lowbands RF1, RF2, RF3 path. See TX_SWITCH_8 for those controls
    + FOR TX1:
    + Write 0 to select Tx lowbands RF1, RF2, RF3 path. See TX_SWITCH_8 for those controls
    + Write 1 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz
    + Write 2 to select no connect
    + Write 3 to select 50 ohm termination

    + +
    9..8 +

    TX_SWITCH_6   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 6. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz
    + Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz
    + Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz
    + Write 3 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See TX_SWITCH_5 for those controls
    + FOR TX1:
    + Write 0 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See TX_SWITCH_5 for those controls
    + Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz
    + Write 2 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz
    + Write 3 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz

    + +
    7..6 +

    TX_SWITCH_5   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 5. This switch path is only taken if TX_SWITCH_6 is set to 0. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz
    + Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz
    + Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz
    + Write 3 to select Tx If1 Filter 50 ohm termination
    + FOR TX1:
    + Write 0 to select Tx If1 Filter 50 ohm termination
    + Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz
    + Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz
    + Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz

    + +
    5..4 +

    TX_SWITCH_4   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 4. This switch path is only taken if TX_SWITCH_4 is set to 0. + The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select 50 ohm termination
    + Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz
    + Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz
    + Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz
    + FOR TX1:
    + Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz
    + Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz
    + Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz
    + Write 3 to select 50 ohm termination

    + +
    3..2 +

    TX_SWITCH_3   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Tx Switch 3. The configuration of this switch changes between TX paths.
    + FOR TX0:
    + Write 0 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See TX_SWITCH_4 for those controls
    + Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz
    + Write 2 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz
    + Write 3 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz
    + FOR TX1:
    + Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz
    + Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz
    + Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz
    + Write 3 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See TX_SWITCH_4 for those controls

    + +
    1 +

    Reserved

    +

    + +
    0 +

    TX_SWITCH_1_2   (initialvalue=0)

    +

    Write 0 to select Tx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz
    + Write 1 to select Tx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz

    + +
    + +
    + +
    + + +

    Offset 0x0800: RX0_PATH_CONTROL(255:0) Register Array (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port GPIO
    + +    		 + + + + +
    GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
      0x001000
    + +    		 + + + + +
    DB_CONTROL_REGMAP|SWITCH_SETUP_REGS
      0x001000
    + +    		 + + + + +
    RX0_PATH_CONTROL
      offset=0x0800 + i*4
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x002800 + i*4 + +
    + +
    + + + +
    Port SPI
    + +    		 + + + + +
    SPI_REGMAP|DB_CONTROL_WINDOW_SPI
      0x001000
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x002800 + i*4 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file switch_control.v.
    +It uses RegType RX_PATH_CONTROL which is defined in HDL source file switch_control.v.

    + +
    + +
    + +This Register controls switches along Rx paths. Note: default + values refer to the RX0 path. RX1 has the same defaults, but their + bit values may differ.
    +This Register controls the Rx0 paths.
    + This register array can hold settings for all ATR configurations. + The register index equals the ATR configuration. + The active configuration can be selected in ATR_REGMAP. + Independently all configurations can be read/written at any time. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23 +

    Reserved

    +

    + +
    22..20 +

    RX_SWITCH_11   (initialvalue=0)

    +

    Control for Rx Switch 11, note to digital designer: Control V2 is pulled to ground.

    + The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 1 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz
    + Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz
    + Write 4 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz
    + FOR RX1:
    + Write 1 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz
    + Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz
    + Write 4 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz

    + +
    19 +

    Reserved

    +

    + +
    18 +

    RX_SWITCH_10   (initialvalue=0)

    +

    Control for Rx Switch 10 LO path. The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 0 to select Rx internal LO path
    + Write 1 to select Rx external LO path
    + FOR RX1:
    + Write 0 to select Rx external LO path
    + Write 1 to select Rx internal LO path

    + +
    17 +

    Reserved

    +

    + +
    16 +

    RX_SWITCH_9   (initialvalue=0)

    +

    Control for Rx Switch 9 LO path. The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 0 to select Rx internal LO path
    + Write 1 to select Rx external LO path
    + FOR RX1:
    + Write 0 to select Rx external LO path
    + Write 1 to select Rx internal LO path

    + +
    15 +

    Reserved

    +

    + +
    14 +

    RX_SWITCH_7_8   (initialvalue=0)

    +

    Shared control for Rx switch 7 and switch 8.
    + FOR RX0:
    + Write 0 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz
    + Write 1 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz
    + FOR RX1:
    + Write 0 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz
    + Write 1 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz

    + +
    13..12 +

    RX_SWITCH_6   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB

    + + Control for Rx Switch 6. The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path
    + Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path
    + Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path
    + Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path
    + FOR RX1:
    + Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path
    + Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path
    + Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path
    + Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path

    + +
    11..10 +

    RX_SWITCH_5   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB

    + + Control for Rx Switch 5. The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path
    + Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path
    + Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path
    + Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path
    + FOR RX1:
    + Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path
    + Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path
    + Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path
    + Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path

    + +
    9 +

    Reserved

    +

    + +
    8 +

    RX_SWITCH_4   (initialvalue=0)

    +

    note to digital designer: control A is the only control, and control B is tied to ground
    + Control for Rx Switch 4.
    + Write 0 to select Rx RF1/2 lowband path
    + Write 1 to select Rx RF3 highband path

    + +
    7 +

    Reserved

    +

    + +
    6..4 +

    RX_SWITCH_3   (initialvalue=0)

    +

    Control for Rx Switch 3, note this is one hot encoding and not binary. + The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 1 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz
    + Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz
    + Write 4 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz
    + FOR RX1:
    + Write 1 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz
    + Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz
    + Write 4 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz
    + *All other values are invalid

    + +
    3 +

    Reserved

    +

    + +
    2 +

    RX_SWITCH_2   (initialvalue=0)

    +

    note to digital designer: control A is the only control, and control B is pulled high
    + Control for Rx Switch 2. The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 0 to select Rx RF3 highband path
    + Write 1 to select Rx RF1/2 lowband path
    + FOR RX1:
    + Write 0 to select Rx RF1/2 lowband path
    + Write 1 to select Rx RF3 highband path

    + +
    1..0 +

    RX_SWITCH_1   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Rx Switch 1. + The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 0 to select Rx calibration loopback
    + Write 1 to select Rx 50 ohm termination path
    + Write 2 to select Tx Rx path, TX_SWITCH_11 must also select the correct path
    + Write 3 to select Rx input port
    + FOR RX1:
    + Write 0 to select Rx calibration loopback
    + Write 1 to select Tx Rx path, TX_SWITCH_11 must also select the correct path
    + Write 2 to select Rx input port
    + Write 3 to select Rx 50 ohm termination path

    + +
    + +
    + +
    + + +

    Offset 0x0C00: RX1_PATH_CONTROL(255:0) Register Array (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port GPIO
    + +    		 + + + + +
    GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
      0x001000
    + +    		 + + + + +
    DB_CONTROL_REGMAP|SWITCH_SETUP_REGS
      0x001000
    + +    		 + + + + +
    RX1_PATH_CONTROL
      offset=0x0C00 + i*4
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x002C00 + i*4 + +
    + +
    + + + +
    Port SPI
    + +    		 + + + + +
    SPI_REGMAP|DB_CONTROL_WINDOW_SPI
      0x001000
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x002C00 + i*4 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file switch_control.v.
    +It uses RegType RX_PATH_CONTROL which is defined in HDL source file switch_control.v.

    + +
    + +
    + +This Register controls switches along Rx paths. Note: default + values refer to the RX0 path. RX1 has the same defaults, but their + bit values may differ.
    +This Register controls the Rx1 paths.
    + This register array can hold settings for all ATR configurations. + The register index equals the ATR configuration. + The active configuration can be selected in ATR_REGMAP. + Independently all configurations can be read/written at any time. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23 +

    Reserved

    +

    + +
    22..20 +

    RX_SWITCH_11   (initialvalue=0)

    +

    Control for Rx Switch 11, note to digital designer: Control V2 is pulled to ground.

    + The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 1 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz
    + Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz
    + Write 4 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz
    + FOR RX1:
    + Write 1 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz
    + Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz
    + Write 4 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz

    + +
    19 +

    Reserved

    +

    + +
    18 +

    RX_SWITCH_10   (initialvalue=0)

    +

    Control for Rx Switch 10 LO path. The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 0 to select Rx internal LO path
    + Write 1 to select Rx external LO path
    + FOR RX1:
    + Write 0 to select Rx external LO path
    + Write 1 to select Rx internal LO path

    + +
    17 +

    Reserved

    +

    + +
    16 +

    RX_SWITCH_9   (initialvalue=0)

    +

    Control for Rx Switch 9 LO path. The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 0 to select Rx internal LO path
    + Write 1 to select Rx external LO path
    + FOR RX1:
    + Write 0 to select Rx external LO path
    + Write 1 to select Rx internal LO path

    + +
    15 +

    Reserved

    +

    + +
    14 +

    RX_SWITCH_7_8   (initialvalue=0)

    +

    Shared control for Rx switch 7 and switch 8.
    + FOR RX0:
    + Write 0 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz
    + Write 1 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz
    + FOR RX1:
    + Write 0 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz
    + Write 1 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz

    + +
    13..12 +

    RX_SWITCH_6   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB

    + + Control for Rx Switch 6. The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path
    + Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path
    + Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path
    + Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path
    + FOR RX1:
    + Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path
    + Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path
    + Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path
    + Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path

    + +
    11..10 +

    RX_SWITCH_5   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB

    + + Control for Rx Switch 5. The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path
    + Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path
    + Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path
    + Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path
    + FOR RX1:
    + Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path
    + Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path
    + Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path
    + Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path

    + +
    9 +

    Reserved

    +

    + +
    8 +

    RX_SWITCH_4   (initialvalue=0)

    +

    note to digital designer: control A is the only control, and control B is tied to ground
    + Control for Rx Switch 4.
    + Write 0 to select Rx RF1/2 lowband path
    + Write 1 to select Rx RF3 highband path

    + +
    7 +

    Reserved

    +

    + +
    6..4 +

    RX_SWITCH_3   (initialvalue=0)

    +

    Control for Rx Switch 3, note this is one hot encoding and not binary. + The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 1 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz
    + Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz
    + Write 4 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz
    + FOR RX1:
    + Write 1 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz
    + Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz
    + Write 4 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz
    + *All other values are invalid

    + +
    3 +

    Reserved

    +

    + +
    2 +

    RX_SWITCH_2   (initialvalue=0)

    +

    note to digital designer: control A is the only control, and control B is pulled high
    + Control for Rx Switch 2. The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 0 to select Rx RF3 highband path
    + Write 1 to select Rx RF1/2 lowband path
    + FOR RX1:
    + Write 0 to select Rx RF1/2 lowband path
    + Write 1 to select Rx RF3 highband path

    + +
    1..0 +

    RX_SWITCH_1   (initialvalue=0)

    +

    note to digital designer: control A is LSB, and control B is MSB
    + Control for Rx Switch 1. + The configuration of this switch changes between RX paths.
    + FOR RX0:
    + Write 0 to select Rx calibration loopback
    + Write 1 to select Rx 50 ohm termination path
    + Write 2 to select Tx Rx path, TX_SWITCH_11 must also select the correct path
    + Write 3 to select Rx input port
    + FOR RX1:
    + Write 0 to select Rx calibration loopback
    + Write 1 to select Tx Rx path, TX_SWITCH_11 must also select the correct path
    + Write 2 to select Rx input port
    + Write 3 to select Rx 50 ohm termination path

    + +
    + +
    + +
    + +
    + + + \ No newline at end of file diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/.gitignore b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/.gitignore new file mode 100644 index 000000000..585bc126d --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/.gitignore @@ -0,0 +1,3 @@ +# generate files +on_chip_flash/ +on_chip_flash.sopcinfo diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/on_chip_flash.qsys b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/on_chip_flash.qsys new file mode 100644 index 000000000..6598d63cb --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/on_chip_flash.qsys @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Single Compressed Image with Memory Initialization + Internal Configuration + + + + + + Read and write,Read and write,Read and write,Read and write,Read and write + $${FILENAME}_onchip_flash_0 + + altera_onchip_flash.hex + altera_onchip_flash.dat + + + + + + + diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/osc/.gitignore b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/osc/.gitignore new file mode 100644 index 000000000..3f8a0c3fc --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/osc/.gitignore @@ -0,0 +1,3 @@ +# generate files +osc/ +osc.sopcinfo diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/osc/osc.qsys b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/osc/osc.qsys new file mode 100644 index 000000000..88cb15646 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/osc/osc.qsys @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/raw_conversion.cof b/fpga/usrp3/top/x400/dboards/zbx/cpld/raw_conversion.cof new file mode 100644 index 000000000..dc74498aa --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/raw_conversion.cof @@ -0,0 +1,39 @@ + + + output_files/zbx_top_cpld_converted.pof + 1 + 1 + 14 + + Page_0 + 1 + + output_files/zbx_top_cpld.sof1 + + + 10 + 0 + 0 + 1 + 1 + + 1 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + + + 1 + 2 + 0 + -1 + -1 + 1 + + \ No newline at end of file diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/README.md b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/README.md new file mode 100644 index 000000000..d83d11a19 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/README.md @@ -0,0 +1,10 @@ +# CPLD Default values + +The memory of the CPLD is configured to set all the RF components to safe +values. That means: +- LEDs off +- DSAs are set to maximum attenuation + +The Python script `memory_init_files/gen_defaults.py` creates the .hex files +that get read into the CPLD bitfile. This is run as part of the Makefile +process, and the script does not have to be executed manually. diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/atr_controller.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/atr_controller.v new file mode 100644 index 000000000..abdf9983f --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/atr_controller.v @@ -0,0 +1,341 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: atr_controller +// +// Description: +// Controller of the ATR state configuration for the other register endpoints. +// + +`default_nettype none + +module atr_controller #( + parameter [19:0] BASE_ADDRESS = 0, + parameter [19:0] SIZE_ADDRESS = 0 +) ( + // Clock and reset + input wire ctrlport_clk, + input wire ctrlport_rst, + + // Request + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + + // Response + output reg s_ctrlport_resp_ack, + output reg [ 1:0] s_ctrlport_resp_status, + output reg [31:0] s_ctrlport_resp_data, + + // ATR state of FPGA + // Assumes the following assignment on the FPGA: + // {tx_running[1], rx_running[1], tx_running[0], rx_running[0]} + // where the array index indicates the RF chain. + input wire [ 3:0] atr_fpga_state, + + // derived configuration + output reg [ 7:0] atr_config_dsa_rf0 = 8'b0, + output reg [ 7:0] atr_config_dsa_rf1 = 8'b0, + output reg [ 7:0] atr_config_rf0 = 8'b0, + output reg [ 7:0] atr_config_rf1 = 8'b0 +); + + `include "../regmap/atr_regmap_utils.vh" + `include "../../../../../../lib/rfnoc/core/ctrlport.vh" + + //---------------------------------------------------------- + // Internal registers + //---------------------------------------------------------- + reg [ RF0_OPTION_SIZE-1:0] option_rf0 = SW_DEFINED; + reg [ RF1_OPTION_SIZE-1:0] option_rf1 = SW_DEFINED; + reg [RF0_DSA_OPTION_SIZE-1:0] option_dsa_rf0 = SW_DEFINED; + reg [RF1_DSA_OPTION_SIZE-1:0] option_dsa_rf1 = SW_DEFINED; + + reg [ SW_RF0_CONFIG_SIZE-1:0] sw_atr_config_rf0 = {SW_RF0_CONFIG_SIZE {1'b0}}; + reg [ SW_RF1_CONFIG_SIZE-1:0] sw_atr_config_rf1 = {SW_RF1_CONFIG_SIZE {1'b0}}; + reg [SW_RF0_DSA_CONFIG_SIZE-1:0] sw_atr_config_dsa_rf0 = {SW_RF0_DSA_CONFIG_SIZE {1'b0}}; + reg [SW_RF1_DSA_CONFIG_SIZE-1:0] sw_atr_config_dsa_rf1 = {SW_RF1_DSA_CONFIG_SIZE {1'b0}}; + + //---------------------------------------------------------- + // Handling of CtrlPort + //---------------------------------------------------------- + wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS); + + always @(posedge ctrlport_clk) begin + // reset internal registers and responses + if (ctrlport_rst) begin + option_rf0 <= SW_DEFINED; + option_rf1 <= SW_DEFINED; + option_dsa_rf0 <= SW_DEFINED; + option_dsa_rf1 <= SW_DEFINED; + + sw_atr_config_rf0 <= {SW_RF0_CONFIG_SIZE {1'b0}}; + sw_atr_config_rf1 <= {SW_RF1_CONFIG_SIZE {1'b0}}; + sw_atr_config_dsa_rf0 <= {SW_RF0_DSA_CONFIG_SIZE {1'b0}}; + sw_atr_config_dsa_rf1 <= {SW_RF1_DSA_CONFIG_SIZE {1'b0}}; + + s_ctrlport_resp_ack <= 1'b0; + s_ctrlport_resp_data <= {32{1'bx}}; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + end else begin + + // write requests + if (s_ctrlport_req_wr) begin + // always issue an ack and no data + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_data <= {32{1'bx}}; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + case (s_ctrlport_req_addr) + BASE_ADDRESS + OPTION_REG: begin + option_rf0 <= s_ctrlport_req_data[RF0_OPTION_MSB : RF0_OPTION]; + option_rf1 <= s_ctrlport_req_data[RF1_OPTION_MSB : RF1_OPTION]; + option_dsa_rf0 <= s_ctrlport_req_data[RF0_DSA_OPTION_MSB : RF0_DSA_OPTION]; + option_dsa_rf1 <= s_ctrlport_req_data[RF1_DSA_OPTION_MSB : RF1_DSA_OPTION]; + end + + BASE_ADDRESS + SW_CONFIG_REG: begin + sw_atr_config_rf0 <= s_ctrlport_req_data[SW_RF0_CONFIG_MSB : SW_RF0_CONFIG]; + sw_atr_config_rf1 <= s_ctrlport_req_data[SW_RF1_CONFIG_MSB : SW_RF1_CONFIG]; + sw_atr_config_dsa_rf0 <= s_ctrlport_req_data[SW_RF0_DSA_CONFIG_MSB : SW_RF0_DSA_CONFIG]; + sw_atr_config_dsa_rf1 <= s_ctrlport_req_data[SW_RF1_DSA_CONFIG_MSB : SW_RF1_DSA_CONFIG]; + end + + // error on undefined address + default: begin + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // read requests + end else if (s_ctrlport_req_rd) begin + // default assumption: valid request + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + s_ctrlport_resp_data <= {32{1'b0}}; + + case (s_ctrlport_req_addr) + BASE_ADDRESS + CURRENT_CONFIG_REG: begin + s_ctrlport_resp_data[CURRENT_RF0_CONFIG_MSB : CURRENT_RF0_CONFIG] <= atr_config_rf0; + s_ctrlport_resp_data[CURRENT_RF1_CONFIG_MSB : CURRENT_RF1_CONFIG] <= atr_config_rf1; + s_ctrlport_resp_data[CURRENT_RF0_DSA_CONFIG_MSB : CURRENT_RF0_DSA_CONFIG] <= atr_config_dsa_rf0; + s_ctrlport_resp_data[CURRENT_RF1_DSA_CONFIG_MSB : CURRENT_RF1_DSA_CONFIG] <= atr_config_dsa_rf1; + end + + BASE_ADDRESS + OPTION_REG: begin + s_ctrlport_resp_data[RF0_OPTION_MSB : RF0_OPTION] <= option_rf0; + s_ctrlport_resp_data[RF1_OPTION_MSB : RF1_OPTION] <= option_rf1; + s_ctrlport_resp_data[RF0_DSA_OPTION_MSB : RF0_DSA_OPTION] <= option_dsa_rf0; + s_ctrlport_resp_data[RF1_DSA_OPTION_MSB : RF1_DSA_OPTION] <= option_dsa_rf1; + end + + BASE_ADDRESS + SW_CONFIG_REG: begin + s_ctrlport_resp_data[SW_RF0_CONFIG_MSB : SW_RF0_CONFIG] <= sw_atr_config_rf0; + s_ctrlport_resp_data[SW_RF1_CONFIG_MSB : SW_RF1_CONFIG] <= sw_atr_config_rf1; + s_ctrlport_resp_data[SW_RF0_DSA_CONFIG_MSB : SW_RF0_DSA_CONFIG] <= sw_atr_config_dsa_rf0; + s_ctrlport_resp_data[SW_RF1_DSA_CONFIG_MSB : SW_RF1_DSA_CONFIG] <= sw_atr_config_dsa_rf1; + end + + // error on undefined address + default: begin + s_ctrlport_resp_data <= {32{1'b0}}; + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // no request + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + end + + //---------------------------------------------------------- + // derive configuration + //---------------------------------------------------------- + always @(posedge ctrlport_clk) begin + case (option_rf0) + SW_DEFINED: begin + atr_config_rf0 <= sw_atr_config_rf0; + end + CLASSIC_ATR: begin + atr_config_rf0 <= {6'b0, atr_fpga_state[1:0]}; + end + FPGA_STATE: begin + atr_config_rf0 <= {4'b0, atr_fpga_state}; + end + endcase + + case (option_rf1) + SW_DEFINED: begin + atr_config_rf1 <= sw_atr_config_rf1; + end + CLASSIC_ATR: begin + atr_config_rf1 <= {6'b0, atr_fpga_state[3:2]}; + end + FPGA_STATE: begin + atr_config_rf1 <= {4'b0, atr_fpga_state}; + end + endcase + + case (option_dsa_rf0) + SW_DEFINED: begin + atr_config_dsa_rf0 <= sw_atr_config_dsa_rf0; + end + CLASSIC_ATR: begin + atr_config_dsa_rf0 <= {6'b0, atr_fpga_state[1:0]}; + end + FPGA_STATE: begin + atr_config_dsa_rf0 <= {4'b0, atr_fpga_state}; + end + endcase + + case (option_dsa_rf1) + SW_DEFINED: begin + atr_config_dsa_rf1 <= sw_atr_config_dsa_rf1; + end + CLASSIC_ATR: begin + atr_config_dsa_rf1 <= {6'b0, atr_fpga_state[3:2]}; + end + FPGA_STATE: begin + atr_config_dsa_rf1 <= {4'b0, atr_fpga_state}; + end + endcase + end + +endmodule + +`default_nettype wire + +//XmlParse xml_on +// +// +// +// This regmap contains settings for the active configuration of RF 0 and 1. +// There are two sets of configurations. One set comprises RF switches and +// LEDs, the other set comprises the attenuators (DSA). +// +// +// +// +// Contains the options available for RF 0 and RF 1. The chosen setting +// affects how the active configuration of up to 8 bits is derived. +// +// +// +// Uses the respective value of @.SW_CONFIG_REG as configuration. +// +// +// +// +// This option assumes the FPGA state to be assigned with: Bit 0 = RF 0 +// RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3 +// = RF 1 TX running. The configuration for each RF chain is built +// up of the 2 bits for the RF chain (4 possible states: IDLE, RX only, +// TX only, TX/RX). +// 0 +// +// +// +// The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states. +// +// +// +// +// +// +// Contains the current active configuration. +// +// +// +// Current active configuration for switches and LEDs of RF 0. +// +// +// +// +// Current active configuration for switches and LEDs of RF 1. +// +// +// +// +// Current active configuration for DSAs of RF 0. +// +// +// +// +// Current active configuration for DSAs of RF 1. +// +// +// +// +// +// +// Set the option to be used for the RF chains. +// +// +// +// Option used for switches and LEDs of RF 0. +// +// +// +// +// Option used for switches and LEDs of RF 1. +// +// +// +// +// Option used for DSAs of RF 0. +// +// +// +// +// Option used for DSAs of RF 1. +// +// +// +// +// +// +// Contains the configuration to be applied in case SW_DEFINED option is +// chosen. +// +// +// +// SW defined configuration for switches and LEDs of RF 0. +// +// +// +// +// SW defined configuration for switches and LEDs of RF 1. +// +// +// +// +// SW defined configuration for DSAs of RF 0. +// +// +// +// +// SW defined configuration for DSAs of RF 1. +// +// +// +// +// +//XmlParse xml_off diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v new file mode 100644 index 000000000..3c218de17 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v @@ -0,0 +1,219 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: basic_regs +// +// Description: +// Basic Registers to inform software about version and capabilities. +// + +`default_nettype none + +module basic_regs #( + parameter [19:0] BASE_ADDRESS = 0, + parameter [19:0] SIZE_ADDRESS = 0 +) ( + // Request + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + // Response + output reg s_ctrlport_resp_ack, + output reg [ 1:0] s_ctrlport_resp_status, + output reg [31:0] s_ctrlport_resp_data, + + //reg clk domain + input wire ctrlport_clk, + input wire ctrlport_rst +); + + `include "../regmap/basic_regs_regmap_utils.vh" + `include "../../../../../../lib/rfnoc/core/ctrlport.vh" + + //---------------------------------------------------------- + // Internal registers + //---------------------------------------------------------- + reg [SCRATCH_REG_SIZE-1:0] scratch_reg = {SCRATCH_REG_SIZE {1'b0}}; + + //---------------------------------------------------------- + // Handling of CtrlPort + //---------------------------------------------------------- + wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS); + + always @(posedge ctrlport_clk) begin + // reset internal registers and responses + if (ctrlport_rst) begin + scratch_reg <= {SCRATCH_REG_SIZE {1'b0}}; + + s_ctrlport_resp_ack <= 1'b0; + s_ctrlport_resp_data <= {32{1'bx}}; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + end else begin + + // write requests + if (s_ctrlport_req_wr) begin + // always issue an ack and no data + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_data <= {32{1'bx}}; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + case (s_ctrlport_req_addr) + BASE_ADDRESS + SLAVE_SCRATCH: begin + scratch_reg <= s_ctrlport_req_data[ SCRATCH_REG_MSB : SCRATCH_REG]; + end + + // error on undefined address + default: begin + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // read requests + end else if (s_ctrlport_req_rd) begin + // default assumption: valid request + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + s_ctrlport_resp_data <= {32{1'b0}}; + + case (s_ctrlport_req_addr) + BASE_ADDRESS + SLAVE_SIGNATURE: begin + s_ctrlport_resp_data[BOARD_ID_MSB : BOARD_ID] + <= BOARD_ID_VALUE[BOARD_ID_SIZE-1:0]; + end + + BASE_ADDRESS + SLAVE_REVISION: begin + s_ctrlport_resp_data[REVISION_REG_MSB : REVISION_REG] + <= CPLD_REVISION[REVISION_REG_SIZE-1:0]; + end + + BASE_ADDRESS + SLAVE_OLDEST_REVISION: begin + s_ctrlport_resp_data[OLDEST_REVISION_REG_MSB : OLDEST_REVISION_REG] + <= OLDEST_CPLD_REVISION[OLDEST_REVISION_REG_SIZE-1:0]; + end + + BASE_ADDRESS + SLAVE_SCRATCH: begin + s_ctrlport_resp_data[SCRATCH_REG_MSB : SCRATCH_REG] <= scratch_reg; + end + + + BASE_ADDRESS + GIT_HASH_REGISTER: begin + `ifdef GIT_HASH + s_ctrlport_resp_data <= `GIT_HASH; + `else + s_ctrlport_resp_data <= 32'hDEADBEEF; + `endif + end + + // error on undefined address + default: begin + s_ctrlport_resp_data <= {32{1'b0}}; + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // no request + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + end + +endmodule + +`default_nettype wire + +//XmlParse xml_on +// +// +// +// This regmap contains the revision registers, signature register, a scratch register, and a slave control reg. +// +// +// +// +// This enum is used to create the constants held in the basic registers in both verilog and vhdl. +// +// +// +// +// +// +// +// +// This register contains the unique signature of the DB. This signature is the same value as the one +// stored on the board ID EEPROM +// +// +// +// Board ID corresponds to the las 16 digits of the daughterboard part number. +// +// +// +// +// +// +// This register contains the revision number of the current build +// +// +// +// Returns the revision in YYMMDDHH format +// +// +// +// +// +// +// This register contains the revision number of the oldest compatible revision +// +// +// +// Returns the oldest compatible revision in YYMMDDHH format +// +// +// +// +// +// +// Read/write scratch register +// +// +// +// Returns the value written here previously. +// +// +// +// +// +// +// Git hash of commit used to build this image.{br} +// Value equals 0xDEADBEEF if the git hash was not used during synthesis. +// +// +// +// 0x0 in case the git status was clean{br} +// 0xF in case there were uncommitted changes +// +// +// +// 7 hex digit hash code of the commit +// +// +// +// +//XmlParse xml_off diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v new file mode 100644 index 000000000..abc4b62f9 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v @@ -0,0 +1,736 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: dsa_control +// +// Description: +// Implements control over Digital Step Attenuators via CtrlPort. Uses RAM to +// store multiple ATR configurations. Provides gain table to abstract from raw +// DSA values. +// +// IMPORTANT: The default values here must be synchronized with the default +// values in gen_defaults.py, they are not automatically kept in sync. +// + +`default_nettype none + +module dsa_control #( + parameter [19:0] BASE_ADDRESS = 0, + parameter [19:0] SIZE_ADDRESS = 0 +) ( + // Clock and reset + input wire ctrlport_clk, + input wire ctrlport_rst, + + // Request + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + + // Response + output reg s_ctrlport_resp_ack, + output reg [ 1:0] s_ctrlport_resp_status = 2'b0, + output reg [31:0] s_ctrlport_resp_data = 32'b0, + + // ATR switching + input wire [ 7:0] atr_config_rf0, + input wire [ 7:0] atr_config_rf1, + + // The attenuation setting for TX paths is indexed from two, + // to match schematic naming. In this case, the two LSBs + // for parallel control going into the DSA chips are connected + // to ground(those bits control fractional attenuation). + + //Tx0 DSA control (domain: ctrl_reg_clk) + output wire [6:2] tx0_dsa1, + output wire [6:2] tx0_dsa2, + + //Tx1 DSA control (domain: ctrl_reg_clk) + output wire [6:2] tx1_dsa1, + output wire [6:2] tx1_dsa2, + + // The attenuation setting for RX paths is indexed from one, + // to match schematic naming. In this case, the LSB controls + // the highest value, so re reverse the order of the vector. + // Note the these signals are active low. + + //Rx0 DSA control (domain: ctrl_reg_clk) + output wire [1:4] rx0_dsa1_n, + output wire [1:4] rx0_dsa2_n, + output wire [1:4] rx0_dsa3_a_n, + output wire [1:4] rx0_dsa3_b_n, + + //Rx1 DSA control (domain: ctrl_reg_clk) + output wire [1:4] rx1_dsa1_n, + output wire [1:4] rx1_dsa2_n, + output wire [1:4] rx1_dsa3_a_n, + output wire [1:4] rx1_dsa3_b_n +); + + `include "../regmap/dsa_setup_regmap_utils.vh" + `include "../../../../../../lib/rfnoc/core/ctrlport.vh" + + //--------------------------------------------------------------- + // register bitfields + //--------------------------------------------------------------- + reg [TX_DSA1_SIZE -1:0] tx0_dsa_1_reg = {TX_DSA1_SIZE{1'b1}}; + reg [TX_DSA2_SIZE -1:0] tx0_dsa_2_reg = {TX_DSA2_SIZE{1'b1}}; + + reg [TX_DSA1_SIZE -1:0] tx1_dsa_1_reg = {TX_DSA1_SIZE{1'b1}}; + reg [TX_DSA2_SIZE -1:0] tx1_dsa_2_reg = {TX_DSA2_SIZE{1'b1}}; + + reg [RX_DSA1_SIZE -1:0] rx0_dsa_1_reg = {RX_DSA1_SIZE{1'b1}}; + reg [RX_DSA2_SIZE -1:0] rx0_dsa_2_reg = {RX_DSA2_SIZE{1'b1}}; + reg [RX_DSA3_A_SIZE -1:0] rx0_dsa_3_a_reg = {RX_DSA3_A_SIZE{1'b1}}; + reg [RX_DSA3_B_SIZE -1:0] rx0_dsa_3_b_reg = {RX_DSA3_B_SIZE{1'b1}}; + + reg [RX_DSA1_SIZE -1:0] rx1_dsa_1_reg = {RX_DSA1_SIZE{1'b1}}; + reg [RX_DSA2_SIZE -1:0] rx1_dsa_2_reg = {RX_DSA2_SIZE{1'b1}}; + reg [RX_DSA3_A_SIZE -1:0] rx1_dsa_3_a_reg = {RX_DSA3_A_SIZE{1'b1}}; + reg [RX_DSA3_B_SIZE -1:0] rx1_dsa_3_b_reg = {RX_DSA3_B_SIZE{1'b1}}; + + //--------------------------------------------------------------- + // ATR memory signals + //--------------------------------------------------------------- + reg ram_tx0_wea = 1'b0; + wire [31:0] ram_tx0_doa; + wire [31:0] ram_tx0_dob; + reg ram_tx1_wea = 1'b0; + wire [31:0] ram_tx1_doa; + wire [31:0] ram_tx1_dob; + reg ram_rx0_wea = 1'b0; + wire [31:0] ram_rx0_doa; + wire [31:0] ram_rx0_dob; + reg ram_rx1_wea = 1'b0; + wire [31:0] ram_rx1_doa; + wire [31:0] ram_rx1_dob; + + reg table_tx0_wea = 1'b0; + wire [31:0] table_tx0_doa; + reg table_tx1_wea = 1'b0; + wire [31:0] table_tx1_doa; + reg table_rx0_wea = 1'b0; + wire [31:0] table_rx0_doa; + reg table_rx1_wea = 1'b0; + wire [31:0] table_rx1_doa; + + //--------------------------------------------------------------- + // Handling of CtrlPort + //--------------------------------------------------------------- + // Check of request address is targeted for this module. + wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS); + // Read request shift register to align memory read and response generation. + reg [ 1:0] read_req_shift_reg = 2'b0; + // Write request shift register to align gain table memory read and ATR memory + // write operation. + reg [ 1:0] write_req_shift_reg = 2'b0; + // Mask out 8 bits for ATR configurations to be able to compare all ATR + // configurations against the same base register address. + wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]}; + // Extract masked out bits from the address, which represent the register + // array index = ATR configuration index + wire [ 7:0] register_index = s_ctrlport_req_addr[9:2]; + // switch between CtrlPort data and gain table data for ATR memories + reg select_gain_table = 1'b0; + + always @(posedge ctrlport_clk) begin + // reset internal registers and responses + if (ctrlport_rst) begin + s_ctrlport_resp_ack <= 1'b0; + + read_req_shift_reg <= 2'b0; + write_req_shift_reg <= 2'b0; + + ram_tx0_wea <= 1'b0; + ram_tx1_wea <= 1'b0; + ram_rx0_wea <= 1'b0; + ram_rx1_wea <= 1'b0; + + table_tx0_wea <= 1'b0; + table_tx1_wea <= 1'b0; + table_rx0_wea <= 1'b0; + table_rx1_wea <= 1'b0; + + select_gain_table <= 1'b0; + + end else begin + // default assignments + read_req_shift_reg <= { read_req_shift_reg[0], s_ctrlport_req_rd}; + write_req_shift_reg <= {write_req_shift_reg[0], s_ctrlport_req_wr}; + + ram_tx0_wea <= 1'b0; + ram_tx1_wea <= 1'b0; + ram_rx0_wea <= 1'b0; + ram_rx1_wea <= 1'b0; + + table_tx0_wea <= 1'b0; + table_tx1_wea <= 1'b0; + table_rx0_wea <= 1'b0; + table_rx1_wea <= 1'b0; + + select_gain_table <= 1'b0; + + // Answer write requests delayed by 2 clock cycles. This compensated for + // register ram_addr and the memory internal address register to make sure + // gain table output data is up to date when forwarding data to ATR memory + if (write_req_shift_reg[1]) begin + // always issue an ack and no data + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_data <= {32{1'bx}}; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + case (register_base_address) + BASE_ADDRESS + TX0_DSA_ATR(0): begin + ram_tx0_wea <= 1'b1; + end + BASE_ADDRESS + TX1_DSA_ATR(0): begin + ram_tx1_wea <= 1'b1; + end + BASE_ADDRESS + RX0_DSA_ATR(0): begin + ram_rx0_wea <= 1'b1; + end + BASE_ADDRESS + RX1_DSA_ATR(0): begin + ram_rx1_wea <= 1'b1; + end + + BASE_ADDRESS + TX0_DSA_TABLE(0): begin + table_tx0_wea <= 1'b1; + end + BASE_ADDRESS + TX1_DSA_TABLE(0): begin + table_tx1_wea <= 1'b1; + end + BASE_ADDRESS + RX0_DSA_TABLE(0): begin + table_rx0_wea <= 1'b1; + end + BASE_ADDRESS + RX1_DSA_TABLE(0): begin + table_rx1_wea <= 1'b1; + end + + BASE_ADDRESS + TX0_DSA_TABLE_SELECT(0): begin + ram_tx0_wea <= 1'b1; + select_gain_table <= 1'b1; + end + BASE_ADDRESS + TX1_DSA_TABLE_SELECT(0): begin + ram_tx1_wea <= 1'b1; + select_gain_table <= 1'b1; + end + BASE_ADDRESS + RX0_DSA_TABLE_SELECT(0): begin + ram_rx0_wea <= 1'b1; + select_gain_table <= 1'b1; + end + BASE_ADDRESS + RX1_DSA_TABLE_SELECT(0): begin + ram_rx1_wea <= 1'b1; + select_gain_table <= 1'b1; + end + + // error on undefined address + default: begin + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // Answer read requests delayed by 2 clock cycles. This compensated for + // register ram_addr and the memory internal address register to make sure + // ram_ch0_doa is up to date when generating the response. + end else if (read_req_shift_reg[1]) begin + // default assumption: valid request + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + s_ctrlport_resp_data <= {32{1'b0}}; + + case (register_base_address) + BASE_ADDRESS + TX0_DSA_ATR(0): begin + s_ctrlport_resp_data <= ram_tx0_doa & TX_DSA_CONTROL_MASK; + end + BASE_ADDRESS + TX1_DSA_ATR(0): begin + s_ctrlport_resp_data <= ram_tx1_doa & TX_DSA_CONTROL_MASK; + end + BASE_ADDRESS + RX0_DSA_ATR(0): begin + s_ctrlport_resp_data <= ram_rx0_doa & RX_DSA_CONTROL_MASK; + end + BASE_ADDRESS + RX1_DSA_ATR(0): begin + s_ctrlport_resp_data <= ram_rx1_doa & RX_DSA_CONTROL_MASK; + end + BASE_ADDRESS + TX0_DSA_TABLE(0): begin + s_ctrlport_resp_data <= table_tx0_doa & TX_DSA_CONTROL_MASK; + end + BASE_ADDRESS + TX1_DSA_TABLE(0): begin + s_ctrlport_resp_data <= table_tx1_doa & TX_DSA_CONTROL_MASK; + end + BASE_ADDRESS + RX0_DSA_TABLE(0): begin + s_ctrlport_resp_data <= table_rx0_doa & RX_DSA_CONTROL_MASK; + end + BASE_ADDRESS + RX1_DSA_TABLE(0): begin + s_ctrlport_resp_data <= table_rx1_doa & RX_DSA_CONTROL_MASK; + end + + default: begin + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // no request + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + end + + // register without reset + reg [ 7:0] ram_addr = 8'b0; + reg [ 7:0] gain_table_addr = 8'b0; + reg [31:0] ram_datain = 32'b0; + always @(posedge ctrlport_clk) begin + // Capture CtrlPort data and address on requests as only in this clock cycle + // the data is valid. + if (s_ctrlport_req_wr || s_ctrlport_req_rd) begin + ram_addr <= register_index; + ram_datain <= s_ctrlport_req_data; + + case (register_base_address) + BASE_ADDRESS + TX0_DSA_TABLE_SELECT(0), + BASE_ADDRESS + TX1_DSA_TABLE_SELECT(0), + BASE_ADDRESS + RX0_DSA_TABLE_SELECT(0), + BASE_ADDRESS + RX1_DSA_TABLE_SELECT(0): begin + gain_table_addr <= s_ctrlport_req_data[TABLE_INDEX_MSB:TABLE_INDEX]; + end + default: begin + gain_table_addr <= register_index; + end + endcase + end + + // outputs + tx0_dsa_1_reg <= ram_tx0_dob[ TX_DSA1_MSB : TX_DSA1]; + tx0_dsa_2_reg <= ram_tx0_dob[ TX_DSA2_MSB : TX_DSA2]; + + tx1_dsa_1_reg <= ram_tx1_dob[ TX_DSA1_MSB : TX_DSA1]; + tx1_dsa_2_reg <= ram_tx1_dob[ TX_DSA2_MSB : TX_DSA2]; + + rx0_dsa_1_reg <= ram_rx0_dob[ RX_DSA1_MSB : RX_DSA1]; + rx0_dsa_2_reg <= ram_rx0_dob[ RX_DSA2_MSB : RX_DSA2]; + rx0_dsa_3_a_reg <= ram_rx0_dob[RX_DSA3_A_MSB : RX_DSA3_A]; + rx0_dsa_3_b_reg <= ram_rx0_dob[RX_DSA3_B_MSB : RX_DSA3_B]; + + rx1_dsa_1_reg <= ram_rx1_dob[ RX_DSA1_MSB : RX_DSA1]; + rx1_dsa_2_reg <= ram_rx1_dob[ RX_DSA2_MSB : RX_DSA2]; + rx1_dsa_3_a_reg <= ram_rx1_dob[RX_DSA3_A_MSB : RX_DSA3_A]; + rx1_dsa_3_b_reg <= ram_rx1_dob[RX_DSA3_B_MSB : RX_DSA3_B]; + end + + assign tx0_dsa1[6:2] = tx0_dsa_1_reg; + assign tx0_dsa2[6:2] = tx0_dsa_2_reg; + + assign tx1_dsa1[6:2] = tx1_dsa_1_reg; + assign tx1_dsa2[6:2] = tx1_dsa_2_reg; + + //Rx DSAs behave differently from Tx DSAs + //Flip MSB/LSB, and invert + + genvar vi; + // take care of inverting the active low logic and bit-reversing + // the DSA controls for RX paths. + generate + for (vi=1; vi<=4; vi=vi+1) begin : reverselogic + // [1:4] [3:0] + assign rx0_dsa1_n[vi] = !rx0_dsa_1_reg[4-vi]; + assign rx0_dsa2_n[vi] = !rx0_dsa_2_reg[4-vi]; + assign rx0_dsa3_a_n[vi] = !rx0_dsa_3_a_reg[4-vi]; + assign rx0_dsa3_b_n[vi] = !rx0_dsa_3_b_reg[4-vi]; + + assign rx1_dsa1_n[vi] = !rx1_dsa_1_reg[4-vi]; + assign rx1_dsa2_n[vi] = !rx1_dsa_2_reg[4-vi]; + assign rx1_dsa3_a_n[vi] = !rx1_dsa_3_a_reg[4-vi]; + assign rx1_dsa3_b_n[vi] = !rx1_dsa_3_b_reg[4-vi]; + end + endgenerate + + //--------------------------------------------------------------- + // ATR memories + //--------------------------------------------------------------- + // Choose data source for ATR configurations from CtrlPort or gain table. + wire [31:0] ram_rx0_dia = select_gain_table ? table_rx0_doa : ram_datain; + wire [31:0] ram_rx1_dia = select_gain_table ? table_rx1_doa : ram_datain; + wire [31:0] ram_tx0_dia = select_gain_table ? table_tx0_doa : ram_datain; + wire [31:0] ram_tx1_dia = select_gain_table ? table_tx1_doa : ram_datain; + + ram_2port #( + .DWIDTH (32), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0), + .INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex") + ) ram_tx0_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_tx0_wea), + .addra (ram_addr), + .dia (ram_tx0_dia), + .doa (ram_tx0_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_rf0), + .dib (0), + .dob (ram_tx0_dob) + ); + + ram_2port #( + .DWIDTH (32), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0), + .INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex") + ) ram_tx1_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_tx1_wea), + .addra (ram_addr), + .dia (ram_tx1_dia), + .doa (ram_tx1_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_rf1), + .dib (0), + .dob (ram_tx1_dob) + ); + + ram_2port #( + .DWIDTH (32), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0), + .INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex") + ) ram_rx0_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_rx0_wea), + .addra (ram_addr), + .dia (ram_rx0_dia), + .doa (ram_rx0_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_rf0), + .dib (0), + .dob (ram_rx0_dob) + ); + + ram_2port #( + .DWIDTH (32), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0), + .INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex") + ) ram_rx1_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_rx1_wea), + .addra (ram_addr), + .dia (ram_rx1_dia), + .doa (ram_rx1_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_rf1), + .dib (0), + .dob (ram_rx1_dob) + ); + + //--------------------------------------------------------------- + // Gain tables + //--------------------------------------------------------------- + + ram_2port #( + .DWIDTH (32), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0), + .INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex") + ) table_tx0_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (table_tx0_wea), + .addra (gain_table_addr), + .dia (ram_datain), + .doa (table_tx0_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (8'b0), + .dib (32'b0), + .dob () + ); + + ram_2port #( + .DWIDTH (32), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0), + .INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex") + ) table_tx1_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (table_tx1_wea), + .addra (gain_table_addr), + .dia (ram_datain), + .doa (table_tx1_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (8'b0), + .dib (32'b0), + .dob () + ); + + ram_2port #( + .DWIDTH (32), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0), + .INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex") + ) table_rx0_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (table_rx0_wea), + .addra (gain_table_addr), + .dia (ram_datain), + .doa (table_rx0_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (8'b0), + .dib (32'b0), + .dob () + ); + + ram_2port #( + .DWIDTH (32), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0), + .INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex") + ) table_rx1_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (table_rx1_wea), + .addra (gain_table_addr), + .dia (ram_datain), + .doa (table_rx1_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (8'b0), + .dib (32'b0), + .dob () + ); + +endmodule + +`default_nettype wire + +//XmlParse xml_on +// +// +// +// The following registers control the digital step attenuators (DSA). +// +// There are two ways to set the DSA values, which are applied to the DB ICs. +// +// 1. The ...DSA_ATR registers can be used to access the raw +// values of each ATR configuration. +// +// 2. Gain tables can be used as intermediate step to abstract from the +// raw DB values. This gain table can be modified using the ...DSA_TABLE +// registers according to the content of the registers from the first +// option. Initially each gain table is empty (all zeros). Each gain +// table entry can be accessed at any time. Once the table is filled with +// values the ...DSA_TABLE_SELECT registers can be used to get one gain +// table entry with index TABLE_INDEX and write it to the appropriate ATR +// configuration given by the address (see _show extended info_ link below +// the register array headlines) +// +// +// +// +// Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +// attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). +// +// +// +// +// Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +// attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). +// +// +// +// +// +// +// +// Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +// attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). +// +// +// +// +// Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +// attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). +// +// +// +// +// Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +// attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). +// +// +// +// +// Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +// attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/} +// +// +// +// +// +// +// +// Gain table index to be used for getting the raw attenuation values. +// +// +// +// +// +// +// Controls the Tx0 DSAs by accessing the raw attenuation levels. +// +// This register array can hold settings for all ATR configurations. +// The register index equals the ATR configuration. +// The active configuration can be selected in @.ATR_REGMAP. +// Independently all configurations can be read/written at any time. +// +// +// +// +// Controls the Tx1 DSAs by accessing the raw attenuation levels. +// +// This register array can hold settings for all ATR configurations. +// The register index equals the ATR configuration. +// The active configuration can be selected in @.ATR_REGMAP. +// Independently all configurations can be read/written at any time. +// +// +// +// +// +// Controls the Rx0 DSAs by accessing the raw attenuation levels. +// +// This register array can hold settings for all ATR configurations. +// The register index equals the ATR configuration. +// The active configuration can be selected in @.ATR_REGMAP. +// Independently all configurations can be read/written at any time. +// +// +// +// +// Controls the Rx1 DSAs by accessing the raw attenuation levels. +// +// This register array can hold settings for all ATR configurations. +// The register index equals the ATR configuration. +// The active configuration can be selected in @.ATR_REGMAP. +// Independently all configurations can be read/written at any time. +// +// +// +// +// +// Controls the Tx0 DSAs by using the gain table to translate the table +// index to raw attenuation levels. The register offset (i) is targeting +// an ATR configuration to store the values from the gain table. +// +// +// +// +// Controls the Tx1 DSAs by using the gain table to translate the table +// index to raw attenuation levels. The register offset (i) is targeting +// an ATR configuration to store the values from the gain table. +// +// +// +// +// Controls the Rx0 DSAs by using the gain table to translate the table +// index to raw attenuation levels. The register offset (i) is targeting +// an ATR configuration to store the values from the gain table. +// +// +// +// +// Controls the Rx1 DSAs by using the gain table to translate the table +// index to raw attenuation levels. The register offset (i) is targeting +// an ATR configuration to store the values from the gain table. +// +// +// +// +// +// Provides access to the gain table for Tx0. +// +// Each entry i will be saved in the gain table without any implications +// on HW. Enables SW to use the table index in @.TX0_DSA_TABLE_SELECT to +// modify the ATR configurations. +// +// +// +// +// Provides access to the gain table for Tx1. +// +// Each entry i will be saved in the gain table without any implications +// on HW. Enables SW to use the table index in @.TX1_DSA_TABLE_SELECT to +// modify the ATR configurations. +// +// +// +// +// Provides access to the gain table for Rx0. +// +// Each entry i will be saved in the gain table without any implications +// on HW. Enables SW to use the table index in @.RX0_DSA_TABLE_SELECT to +// modify the ATR configurations. +// +// +// +// +// Provides access to the gain table for Rx1. +// +// Each entry i will be saved in the gain table without any implications +// on HW. Enables SW to use the table index in @.RX1_DSA_TABLE_SELECT to +// modify the ATR configurations. +// +// +// +// +//XmlParse xml_off diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/led_control.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/led_control.v new file mode 100644 index 000000000..5663d348e --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/led_control.v @@ -0,0 +1,259 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: led_control +// +// Description: +// Implements control over LED state via CtrlPort. The default state +// has the LEDs disabled. Uses RAM to store multiple ATR configurations. +// + +`default_nettype none + +module led_control #( + parameter [19:0] BASE_ADDRESS = 0, + parameter [19:0] SIZE_ADDRESS = 0 +) ( + // Clock and reset + input wire ctrlport_clk, + input wire ctrlport_rst, + + // Request + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + // Response + output reg s_ctrlport_resp_ack, + output reg [ 1:0] s_ctrlport_resp_status = 2'b0, + output reg [31:0] s_ctrlport_resp_data = 32'b0, + + // LED Control (domain: ctrlport_clk) + output reg ch0_rx2_led, + output reg ch0_tx_led, + output reg ch0_rx_led, + output reg ch1_rx2_led, + output reg ch1_tx_led, + output reg ch1_rx_led, + + // ATR switching + input wire [ 7:0] atr_config_rf0, + input wire [ 7:0] atr_config_rf1 +); + + `include "../regmap/led_setup_regmap_utils.vh" + `include "../../../../../../lib/rfnoc/core/ctrlport.vh" + + //--------------------------------------------------------------- + // ATR memory signals + //--------------------------------------------------------------- + reg ram_ch0_wea; + wire [31:0] ram_ch0_doa; + wire [31:0] ram_ch0_dob; + + reg ram_ch1_wea; + wire [31:0] ram_ch1_dob; + + //--------------------------------------------------------------- + // Handling of CtrlPort + //--------------------------------------------------------------- + // Check of request address is targeted for this module. + wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS); + // Read request shift register to align memory read and response generation. + reg [ 1:0] read_req_shift_reg = 2'b0; + // Mask out 8 bits for ATR configurations to be able to compare all ATR + // configurations against the same base register address. + wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]}; + // Extract masked out bits from the address, which represent the register + // array index = ATR configuration index + wire [ 7:0] register_index = s_ctrlport_req_addr[9:2]; + + always @(posedge ctrlport_clk) begin + // reset internal registers and responses + if (ctrlport_rst) begin + s_ctrlport_resp_ack <= 1'b0; + + read_req_shift_reg <= 2'b0; + + ram_ch0_wea <= 1'b0; + ram_ch1_wea <= 1'b0; + + end else begin + // default assignments + read_req_shift_reg <= {read_req_shift_reg[0], s_ctrlport_req_rd}; + + ram_ch0_wea <= 1'b0; + ram_ch1_wea <= 1'b0; + + // write requests + if (s_ctrlport_req_wr) begin + // always issue an ack and no data + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_data <= {32{1'bx}}; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + case (register_base_address) + BASE_ADDRESS + LED_CONTROL(0): begin + ram_ch0_wea <= 1'b1; + ram_ch1_wea <= 1'b1; + end + + // error on undefined address + default: begin + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // Answer read requests delayed by 2 clock cycles. This compensated for + // register ram_addr and the memory internal address register to make sure + // ram_ch0_doa is up to date when generating the response. + end else if (read_req_shift_reg[1]) begin + // default assumption: valid request + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + s_ctrlport_resp_data <= {32{1'b0}}; + + case (register_base_address) + BASE_ADDRESS + LED_CONTROL(0): begin + s_ctrlport_resp_data <= ram_ch0_doa & LED_CONTROL_TYPE_MASK; + end + + // error on undefined address + default: begin + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // no request + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + end + + // register without reset + reg [ 7:0] ram_addr = 8'b0; + reg [31:0] ram_datain = 32'b0; + always @(posedge ctrlport_clk) begin + // memories + ram_addr <= register_index; + ram_datain <= s_ctrlport_req_data; + + //outputs + ch0_rx2_led <= ram_ch0_dob[CH0_RX2_LED_EN]; + ch0_tx_led <= ram_ch0_dob[CH0_TRX1_LED_EN + 1]; + ch0_rx_led <= ram_ch0_dob[CH0_TRX1_LED_EN + 0]; + + ch1_rx2_led <= ram_ch1_dob[CH1_RX2_LED_EN]; + ch1_tx_led <= ram_ch1_dob[CH1_TRX1_LED_EN + 1]; + ch1_rx_led <= ram_ch1_dob[CH1_TRX1_LED_EN + 0]; + end + + ram_2port #( + .DWIDTH (32), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0), + .INIT_FILE ("") + ) ram_ch0_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_ch0_wea), + .addra (ram_addr), + .dia (ram_datain), + .doa (ram_ch0_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_rf0), + .dib (0), + .dob (ram_ch0_dob) + ); + + ram_2port #( + .DWIDTH (32), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0), + .INIT_FILE ("") + ) ram_ch1_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_ch1_wea), + .addra (ram_addr), + .dia (ram_datain), + .doa (), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_rf1), + .dib (0), + .dob (ram_ch1_dob)); + +endmodule + +`default_nettype wire + +//XmlParse xml_on +// +// +// +// Contains registers that control the LEDs. +// +// +// +// Defines LED functionality. +// +// +// +// Enables the Ch0 Rx2 Green LED +// +// +// +// +// This bitfield controls the RG LED{BR/} +// Bit 6 controls the Ch0 Rx Green LED{BR/} +// Bit 7 controls the Ch0 Tx Red LED{BR/} +// +// +// +// +// Enables the Ch1 Rx2 Green LED +// +// +// +// +// This bitfield controls the RG LED{BR/} +// Bit 15 controls the Ch1 Rx Green LED{BR/} +// Bit 14 controls the Ch1 Tx Red LED{BR/} +// +// +// +// +// +// +// This register array can hold settings for all ATR configurations. +// The register index equals the ATR configuration. +// The active configuration can be selected in @.ATR_REGMAP. +// Independently all configurations can be read/written at any time. +// +// +// +// +//XmlParse xml_off diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/lo_control.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/lo_control.v new file mode 100644 index 000000000..67a2e8c79 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/lo_control.v @@ -0,0 +1,568 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: lo_control +// +// Description: +// Implements control over signals interacting with LMX2572 chips on the +// daughterboard. This includes a CtrlPort based control over a SPI master +// that distributes transactions across the SPI buses of the LMX2572, as +// well as the capability to synchronously generate pulses to their SYNC pins. +// + +`default_nettype none + +module lo_control #( + parameter [19:0] BASE_ADDRESS = 0, + parameter [19:0] SIZE_ADDRESS = 0 +) ( + // Request + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + // Response + output reg s_ctrlport_resp_ack, + output reg [ 1:0] s_ctrlport_resp_status, + output reg [31:0] s_ctrlport_resp_data, + + //reg clk domain + input wire ctrlport_clk, + input wire ctrlport_rst, + + // LO SPI for LMX2572 + input wire [7:0] miso, + output reg [7:0] ss = {8{1'b1}}, + output wire sclk, + output reg mosi = 1'b0, + + // Incoming SYNC + input wire mb_synth_sync, + + // SYNC for LMX2572 + output wire tx0_lo1_sync, + output wire tx0_lo2_sync, + output wire tx1_lo1_sync, + output wire tx1_lo2_sync, + output wire rx0_lo1_sync, + output wire rx0_lo2_sync, + output wire rx1_lo1_sync, + output wire rx1_lo2_sync +); + + `include "../regmap/lo_control_regmap_utils.vh" + `include "../../../../../../lib/rfnoc/core/ctrlport.vh" + + //--------------------------------------------------------------- + // register bitfields + //--------------------------------------------------------------- + + reg spi_start; + reg [LO_SELECT_SIZE-1:0] spi_cs; + reg spi_rd; + reg [LO_SPI_WT_ADDR_SIZE-1:0] spi_addr; + reg [LO_SPI_WT_DATA_SIZE-1:0] spi_data; + reg spi_data_valid; + reg spi_ready = 1'b1; + reg [LO_SPI_RD_DATA_SIZE-1:0] spi_rd_data; + reg [LO_CHIP_SELECT_SIZE-1:0] lo_sync_reg = 8'b0; + reg bypass_sync = 1'b0; + + //--------------------------------------------------------------- + // Handling of CtrlPort + //--------------------------------------------------------------- + wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS); + + always @(posedge ctrlport_clk) begin + // reset internal registers and responses + if (ctrlport_rst) begin + spi_start <= 1'b0; + spi_cs <= 3'b0; + spi_rd <= 1'b0; + spi_addr <= {LO_SPI_WT_ADDR_SIZE{1'b0}}; + spi_data <= {LO_SPI_WT_DATA_SIZE{1'b0}}; + lo_sync_reg <= 8'b0; + bypass_sync <= 1'b0; + + s_ctrlport_resp_ack <= 1'b0; + s_ctrlport_resp_data <= {32{1'bx}}; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + end else begin + + //send only a pulse + spi_start <= 1'b0; + + //pulse sync lines for a maximum of one cycle + lo_sync_reg <= 8'b0; + + // write requests + if (s_ctrlport_req_wr) begin + // always issue an ack and no data + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_data <= {32{1'bx}}; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + case (s_ctrlport_req_addr) + BASE_ADDRESS + LO_SPI_SETUP: begin + spi_start <= s_ctrlport_req_data[LO_SPI_START_TRANSACTION]; + spi_cs <= s_ctrlport_req_data[LO_SELECT_MSB : LO_SELECT]; + spi_rd <= s_ctrlport_req_data[LO_SPI_RD]; + spi_addr <= s_ctrlport_req_data[LO_SPI_WT_ADDR_MSB : LO_SPI_WT_ADDR]; + spi_data <= s_ctrlport_req_data[LO_SPI_WT_DATA_MSB : LO_SPI_WT_DATA]; + end + + BASE_ADDRESS + LO_PULSE_SYNC: begin + bypass_sync <= s_ctrlport_req_data[BYPASS_SYNC_REGISTER]; + lo_sync_reg[TX0_LO1] <= s_ctrlport_req_data[PULSE_TX0_LO1_SYNC]; + lo_sync_reg[TX0_LO2] <= s_ctrlport_req_data[PULSE_TX0_LO2_SYNC]; + lo_sync_reg[TX1_LO1] <= s_ctrlport_req_data[PULSE_TX1_LO1_SYNC]; + lo_sync_reg[TX1_LO2] <= s_ctrlport_req_data[PULSE_TX1_LO2_SYNC]; + lo_sync_reg[RX0_LO1] <= s_ctrlport_req_data[PULSE_RX0_LO1_SYNC]; + lo_sync_reg[RX0_LO2] <= s_ctrlport_req_data[PULSE_RX0_LO2_SYNC]; + lo_sync_reg[RX1_LO1] <= s_ctrlport_req_data[PULSE_RX1_LO1_SYNC]; + lo_sync_reg[RX1_LO2] <= s_ctrlport_req_data[PULSE_RX1_LO2_SYNC]; + end + + // error on undefined address + default: begin + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // read requests + end else if (s_ctrlport_req_rd) begin + // default assumption: valid request + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + s_ctrlport_resp_data <= {32{1'b0}}; + + case (s_ctrlport_req_addr) + BASE_ADDRESS + LO_SPI_STATUS: begin //same address as *_status form regmap + s_ctrlport_resp_data[LO_SPI_DATA_VALID] <= spi_data_valid; + s_ctrlport_resp_data[LO_SELECT_MSB : LO_SELECT] <= spi_cs; + s_ctrlport_resp_data[LO_SPI_READY] <= spi_ready; + s_ctrlport_resp_data[LO_SPI_RD_ADDR_MSB : LO_SPI_RD_ADDR] <= spi_addr; + s_ctrlport_resp_data[LO_SPI_RD_DATA_MSB : LO_SPI_RD_DATA] <= spi_rd_data; + end + + // error on undefined address + default: begin + s_ctrlport_resp_data <= {32{1'b0}}; + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // no request + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + end + + // Spi_top controls + reg [4:0] wb_adr_i; + reg wb_cyc_i; + reg [31:0] wb_dat_i; + reg wb_we_i; + + // Spi_top outputs + wire wb_ack_o; + wire [31:0] wb_dat_o; + wire wb_int_o; + + wire [15:0] ss_pad_o; + wire mosi_pad_o; + wire miso_pad_i; + + // There is a hold requirement of 10ns on the output path. + // To ease meeting this requirement without to much routing added to the lines + // these registers shift the output by 10ns (half 50 MHz period). + always @(negedge ctrlport_clk) begin + if (ctrlport_rst) begin + ss <= {8{1'b1}}; + mosi <= 1'b0; + end + else begin + ss <= ss_pad_o[LO_CHIP_SELECT_SIZE-1:0]; + mosi <= mosi_pad_o; + end + end + + assign miso_pad_i = ( ~ss[TX0_LO1] ) ? miso[TX0_LO1] : + ( ~ss[TX0_LO2] ) ? miso[TX0_LO2] : + ( ~ss[TX1_LO1] ) ? miso[TX1_LO1] : + ( ~ss[TX1_LO2] ) ? miso[TX1_LO2] : + ( ~ss[RX0_LO1] ) ? miso[RX0_LO1] : + ( ~ss[RX0_LO2] ) ? miso[RX0_LO2] : + ( ~ss[RX1_LO1] ) ? miso[RX1_LO1] : + ( ~ss[RX1_LO2] ) ? miso[RX1_LO2] : + 1'b0; + + // Import offsets and functions to interact with spi_top + `include "utils/spi_control_utils.vh" + + // The sclk signal generated by this spi engine will be constrained to be 1/4 of the + // ctrl port frequency. The effective frequency of the clock output of spi_top is determined + // by the equation wb_clk_i/((CLOCK_DIVIDER_VALUE+1)*2), so the value required for the clock + // divider register is 1. + localparam CLOCK_DIVIDER_VALUE = 32'h1; + + // Base Configuration for the control register. To start a transaction + // modify this value to include the GO_BUSY bit set to high. The mapping of the + // macro goes as follows: + `define CONTROL_DATA(GO_BUSY) { 18'b0, /* Reserved */ \ + 1'b1, /* Automatic SS(13) */ \ + 1'b1, /* Interrupt Enable */ \ + 1'b0, /* LSB */ \ + 1'b1, /* TX_NEG (10) */ \ + 1'b0, /* RX_NEG (9) */ \ + GO_BUSY, /* GO_BUSY (8) */ \ + 1'b0, /* Reserved (7) */ \ + 7'd24} /* Length of spi transaction */ + + // Declare the different state-machine states. + localparam RESET_STATE = 0; + localparam CONFIG_DIVIDER = 1; + localparam INIT_CONTROL = 2; + localparam IDLE = 3; + localparam LOAD_CS = 4; + localparam LOAD_DATA = 5; + localparam SEND_TRANSACTION = 6; + localparam WAIT_FOR_COMPLETION = 7; + localparam RETRIEVE_DATA = 8; + + // FSM state variable + reg [3:0] spi_state = RESET_STATE; + + always @(posedge ctrlport_clk) begin + if (ctrlport_rst) begin + // SPI_STATUS for CtrlPort + spi_state <= RESET_STATE; + spi_ready <= 1'b1; + spi_data_valid <= 1'b0; + spi_rd_data <= {LO_SPI_RD_DATA_SIZE{1'b0}}; + + // SPI_TOP Bus access control. + wb_we_i <= 1'b0; + wb_cyc_i <= 1'b0; + wb_adr_i <= 5'h00; + wb_dat_i <= 32'h00; + end else begin + case (spi_state) + RESET_STATE: + if (spi_start) begin + spi_state <= CONFIG_DIVIDER; + end + + // keep driving a write to the CLOCK_DIVIDER Register until access is acknowledged. + CONFIG_DIVIDER: + if (wb_ack_o) begin + spi_state <= INIT_CONTROL; + wb_we_i <= 1'b0; + wb_cyc_i <= 1'b0; + end else begin + wb_we_i <= 1'b1; + wb_cyc_i <= 1'b1; + wb_adr_i <= CLOCK_DIVIDER_REG; // CLOCK DIVIDER register offset + wb_dat_i <= CLOCK_DIVIDER_VALUE; + end + + // keep driving a write to the CONTROL Register until access is acknowledged. + INIT_CONTROL: + if (wb_ack_o) begin + spi_state <= LOAD_CS; + wb_we_i <= 1'b0; + wb_cyc_i <= 1'b0; + end else begin + wb_we_i <= 1'b1; + wb_cyc_i <= 1'b1; + wb_adr_i <= CONTROL_REG; //CONTROL register offset + wb_dat_i <= `CONTROL_DATA(1'b0); //Write control register value with no GO_BUSY + end + + // Wait for CtrlPort operation to trigger a SPI transaction. + IDLE : + if (spi_start) begin + spi_state <= LOAD_CS; + spi_ready <= 1'b0; + spi_data_valid <= 1'b0; + // Clear data to be written next. This will make it so that the next state(LOAD_CS) + // will only have to set the bits of the pertinent SS lines. + wb_dat_i <= 32'h00; + end else begin + spi_ready <= 1'b1; + wb_dat_i <= 32'h00; + end + + // keep driving a write to the SLAVE SELECT Register until access is acknowledged. + LOAD_CS : + if (wb_ack_o) begin + spi_state <= LOAD_DATA; + wb_we_i <= 1'b0; + wb_cyc_i <= 1'b0; + end else begin + wb_we_i <= 1'b1; + wb_cyc_i <= 1'b1; + wb_adr_i <= SS_REG; // SS Register offset. + wb_dat_i <= set_ss_bit(spi_cs); // Assign single bit. + end + + // keep driving a write to the DATA TRANSMIT Register until access is acknowledged. + // This includes the combination of CMD+ADDR+DATA to be driven on the MOSI lines. + LOAD_DATA : + if (wb_ack_o) begin + spi_state <= SEND_TRANSACTION; + wb_we_i <= 1'b0; + wb_cyc_i <= 1'b0; + end else begin + wb_we_i <= 1'b1; + wb_cyc_i <= 1'b1; + wb_adr_i <= TX_DATA_REG; // Data Transmit register offset. + wb_dat_i <= { + 8'b0, + spi_rd, + spi_addr, + spi_data + }; + end + + // Per indication in the SPI_TOP documentation, we write the same configuration as before to the + // CONTROL register, with the addition of the GO bit. + SEND_TRANSACTION : + if (wb_ack_o) begin + spi_state <= WAIT_FOR_COMPLETION; + wb_we_i <= 1'b0; + wb_cyc_i <= 1'b0; + end else begin + wb_we_i <= 1'b1; + wb_cyc_i <= 1'b1; + wb_adr_i <= CONTROL_REG; + wb_dat_i <= `CONTROL_DATA(1'b1); //Write control register value with GO_BUSY set. + end + + // This state waits until SPI access is complete + WAIT_FOR_COMPLETION: + if (wb_int_o) begin + if (spi_rd) begin // If reading, do an extra step + spi_state <= RETRIEVE_DATA; + end else begin + spi_state <= IDLE; // If not reading, wait for next transaction + end + wb_we_i <= 1'b0; + wb_cyc_i <= 1'b0; + end else begin // Keep polling CONTROL register. + wb_we_i <= 1'b0; + wb_cyc_i <= 1'b0; + end + + RETRIEVE_DATA: + if (wb_ack_o) begin + spi_state <= IDLE; // as soon as data is available, record it and go back + spi_rd_data <= wb_dat_o[LO_SPI_RD_DATA_SIZE-1:0]; // to idle. + spi_data_valid <= 1'b1; + wb_we_i <= 1'b0; + wb_cyc_i <= 1'b0; + end else begin + wb_we_i <= 1'b0; // Drive bus access. + wb_cyc_i <= 1'b1; + wb_adr_i <= RX_DATA_REG; // DATA RETRIEVE Register offset + wb_dat_i <= {LO_SPI_WT_DATA_SIZE{1'b0}}; + end + + endcase + end + end + + spi_top spi_top_i ( + .wb_clk_i (ctrlport_clk), + .wb_rst_i (ctrlport_rst), + .wb_adr_i (wb_adr_i), + .wb_dat_i (wb_dat_i), + .wb_dat_o (wb_dat_o), + .wb_sel_i (4'hF), + .wb_we_i (wb_we_i), + .wb_stb_i (wb_cyc_i), + .wb_cyc_i (wb_cyc_i), + .wb_ack_o (wb_ack_o), + .wb_err_o (), + .wb_int_o (wb_int_o), + .ss_pad_o (ss_pad_o), + .sclk_pad_o (sclk), + .mosi_pad_o (mosi_pad_o), + .miso_pad_i (miso_pad_i)); + + reg mb_sync_reg = 1'b0; + + // align incoming signal to clock + always @(posedge ctrlport_clk) begin + mb_sync_reg <= mb_synth_sync; + end + + // Select between bypassing into input signal or registered pulse + assign tx0_lo1_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[TX0_LO1]; + assign tx0_lo2_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[TX0_LO2]; + assign tx1_lo1_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[TX1_LO1]; + assign tx1_lo2_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[TX1_LO2]; + assign rx0_lo1_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[RX0_LO1]; + assign rx0_lo2_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[RX0_LO2]; + assign rx1_lo1_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[RX1_LO1]; + assign rx1_lo2_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[RX1_LO2]; + +endmodule + +`default_nettype wire + +//XmlParse xml_on +// +// +// +// Controls the SPI transaction to the LMX2572 +// +// +// +// +// +// +// +// +// +// +// +// +// +// This register sets up the SPI transaction to read/write to/from to the LMX2572. +// +// +// +// Strobe this bit high to start the SPI transaction with the bitfields below +// +// +// +// +// Sets the CS to the selected LO. The CS will assert until after @.LO_SPI_START_TRANSACTION has been asserted. +// +// +// +// +// Set this bit to '1' to read from the LMX2572. Set this bit to '0' to write to the LMX2572. +// +// +// +// +// 7 bit address of the LMX2572 +// +// +// +// +// Write Data to the LMX2572 +// +// +// +// +// +// +// This register returns the SPI master status, and also returns the read data from the LMX2572 +// +// +// +// Returns '1' when a read SPI transaction is complete. This bit will remain high until a new SPI transaction has started. +// i.e. @.LO_SPI_START_TRANSACTION is strobed. Poll this when expecting data from a read transaction. +// +// +// +// +// If this bit returns '1' then LMX2572 is ready for transaction. If it returns '0' then it is busy with a previous SPI transaction. +// Poll this bit before starting a SPI transaction. +// +// +// +// +// Returns the current selected CS. This bitfield will return the value written to @.LO_SELECT bitfield in the @.LO_SPI_SETUP reg. +// +// +// +// +// Returns the address of the current SPI address setup +// +// +// +// +// Returns the data of the SPI read. This bitfield will return 0x0000 until @.LO_SPI_DATA_VALID is true. This bit field will maintain it's +// read value until a new SPI transaction has started. i.e. @.LO_SPI_START_TRANSACTION is strobed. +// +// +// +// +// +// +// Contains registers that control the logic lines in charge of synchronization +// +// +// +// Controls pulses driven to the SYNC pins of the LMX2572 chips +// +// +// +// Creates a single cycle pulse on the TX0_LO1_SYNC line. +// +// +// +// +// Creates a single cycle pulse on the TX0_LO2_SYNC line. +// +// +// +// +// Creates a single cycle pulse on the TX1_LO1_SYNC line. +// +// +// +// +// Creates a single cycle pulse on the TX1_LO2_SYNC line. +// +// +// +// +// Creates a single cycle pulse on the RX0_LO1_SYNC line. +// +// +// +// +// Creates a single cycle pulse on the RX0_LO2_SYNC line. +// +// +// +// +// Creates a single cycle pulse on the RX1_LO1_SYNC line. +// +// +// +// +// Creates a single cycle pulse on the RX1_LO2_SYNC line. +// +// +// +// +// Setting this bit to '1' will ignore writes to the PULSE_X_SYNC fields and allow +// a buffered input SYNC pulse to be driven out instead. +// +// +// +// +// +//XmlParse xml_off diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/memory_init_files/.gitignore b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/memory_init_files/.gitignore new file mode 100644 index 000000000..3eee46e45 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/memory_init_files/.gitignore @@ -0,0 +1,2 @@ +zbx_cpld_regs_t.py +*.hex diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/memory_init_files/gen_defaults.py b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/memory_init_files/gen_defaults.py new file mode 100644 index 000000000..35e1e74bd --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/memory_init_files/gen_defaults.py @@ -0,0 +1,65 @@ +#!/usr/bin/env python3 +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: GPL-3.0-or-later +# +""" +Helper script to generate memory init files for the ZBX CPLD. +""" + +import os +import pathlib + +# This is generated by running +# $ python3 /path/to/gen_zbx_cpld_regs.py zbx_cpld_regs_t.py +import zbx_cpld_regs_t + +def main(): + """ + Main function + """ + cur_dir = str(pathlib.Path(__file__).resolve().parent) + + zbx_regs = zbx_cpld_regs_t.zbx_cpld_regs_t() + + # The file dsa_control.v lists default values for documentation purposes. When + # changing these values, make sure to also update the 'initialvalue' documentation + # attributes in dsa_control.v + zbx_regs.TX0_DSA1[0] = 31 + zbx_regs.TX0_DSA2[0] = 31 + + zbx_regs.RX0_DSA1[0] = 15 + zbx_regs.RX0_DSA2[0] = 15 + zbx_regs.RX0_DSA3_A[0] = 15 + zbx_regs.RX0_DSA3_B[0] = 15 + + # Path control defaults + with open(os.path.join(cur_dir, "tx0_path_defaults.hex"), "w") as outfile: + outfile.write("\n".join([ + "{:08X}".format(zbx_regs.get_reg(zbx_regs.get_addr('TX0_IF2_1_2'))), + ] * len(zbx_regs.TX0_IF2_1_2))) + with open(os.path.join(cur_dir, "tx1_path_defaults.hex"), "w") as outfile: + outfile.write("\n".join([ + "{:08X}".format(zbx_regs.get_reg(zbx_regs.get_addr('TX1_IF2_1_2'))), + ] * len(zbx_regs.TX1_IF2_1_2))) + with open(os.path.join(cur_dir, "rx0_path_defaults.hex"), "w") as outfile: + outfile.write("\n".join([ + "{:08X}".format(zbx_regs.get_reg(zbx_regs.get_addr('RX0_ANT_1'))), + ] * len(zbx_regs.RX0_ANT_1))) + with open(os.path.join(cur_dir, "rx1_path_defaults.hex"), "w") as outfile: + outfile.write("\n".join([ + "{:08X}".format(zbx_regs.get_reg(zbx_regs.get_addr('RX1_ANT_1'))), + ] * len(zbx_regs.RX1_ANT_1))) + # DSA defaults + with open(os.path.join(cur_dir, "tx_dsa_defaults.hex"), "w") as outfile: + outfile.write("\n".join([ + "{:08X}".format(zbx_regs.get_reg(zbx_regs.get_addr('TX0_DSA1'))), + ] * len(zbx_regs.TX0_DSA1))) + with open(os.path.join(cur_dir, "rx_dsa_defaults.hex"), "w") as outfile: + outfile.write("\n".join([ + "{:08X}".format(zbx_regs.get_reg(zbx_regs.get_addr('RX0_DSA1'))), + ] * len(zbx_regs.RX0_DSA1))) + +if __name__ == "__main__": + main() diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/power_regs.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/power_regs.v new file mode 100644 index 000000000..f5fb6b81e --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/power_regs.v @@ -0,0 +1,211 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: power_regs +// +// Description: +// Registers to control the power supplies and the PLL ref clock buffer. +// + +`default_nettype none + +module power_regs #( + parameter [19:0] BASE_ADDRESS = 0, + parameter [19:0] SIZE_ADDRESS = 0 +) ( + // Request + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + // Response + output reg s_ctrlport_resp_ack, + output reg [ 1:0] s_ctrlport_resp_status, + output reg [31:0] s_ctrlport_resp_data, + + //reg clk domain + input wire ctrlport_clk, + input wire ctrlport_rst, + + //Power Control + output wire enable_tx_7v0, + output wire enable_rx_7v0, + output wire enable_3v3, + + //Power Good Indicators + input wire p7v_pg_b, + input wire p7v_pg_a, + + //PRC buffer + output reg pll_ref_clk_enable = 1'b0 +); + + `include "../regmap/power_regs_regmap_utils.vh" + `include "../../../../../../lib/rfnoc/core/ctrlport.vh" + + //---------------------------------------------------------- + // Internal registers + //---------------------------------------------------------- + reg enable_3v3_reg = {ENABLE_3V3_SIZE {1'b0}}; + reg enable_rx_7v0_reg = {ENABLE_RX_7V0_SIZE {1'b0}}; + reg enable_tx_7v0_reg = {ENABLE_TX_7V0_SIZE {1'b0}}; + + //---------------------------------------------------------- + // Handling of CtrlPort + //---------------------------------------------------------- + wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS); + + always @(posedge ctrlport_clk) begin + // reset internal registers and responses + if (ctrlport_rst) begin + s_ctrlport_resp_ack <= 1'b0; + s_ctrlport_resp_data <= {32{1'bx}}; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + enable_3v3_reg <= {ENABLE_3V3_SIZE {1'b0}}; + enable_rx_7v0_reg <= {ENABLE_RX_7V0_SIZE {1'b0}}; + enable_tx_7v0_reg <= {ENABLE_TX_7V0_SIZE {1'b0}}; + + end else begin + + // write requests + if (s_ctrlport_req_wr) begin + // always issue an ack and no data + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_data <= {32{1'bx}}; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + case (s_ctrlport_req_addr) + BASE_ADDRESS + RF_POWER_CONTROL: begin + enable_3v3_reg <= s_ctrlport_req_data[ENABLE_3V3]; + enable_rx_7v0_reg <= s_ctrlport_req_data[ENABLE_RX_7V0]; + enable_tx_7v0_reg <= s_ctrlport_req_data[ENABLE_TX_7V0]; + end + + BASE_ADDRESS + PRC_CONTROL: begin + pll_ref_clk_enable <= s_ctrlport_req_data[PLL_REF_CLOCK_ENABLE]; + end + + // error on undefined address + default: begin + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // read requests + end else if (s_ctrlport_req_rd) begin + // default assumption: valid request + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + s_ctrlport_resp_data <= {32{1'b0}}; + + case (s_ctrlport_req_addr) + BASE_ADDRESS + RF_POWER_CONTROL: begin + s_ctrlport_resp_data[ENABLE_3V3] <= enable_3v3_reg; + s_ctrlport_resp_data[ENABLE_RX_7V0] <= enable_rx_7v0_reg; + s_ctrlport_resp_data[ENABLE_TX_7V0] <= enable_tx_7v0_reg; + end + + BASE_ADDRESS + RF_POWER_STATUS: begin + s_ctrlport_resp_data[P7V_A_STATUS] <= p7v_pg_a; + s_ctrlport_resp_data[P7V_B_STATUS] <= p7v_pg_b; + end + + BASE_ADDRESS + PRC_CONTROL: begin + s_ctrlport_resp_data[PLL_REF_CLOCK_ENABLE] <= pll_ref_clk_enable; + end + + // error on undefined address + default: begin + s_ctrlport_resp_data <= {32{1'b0}}; + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // no request + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + end + + assign enable_tx_7v0 = enable_tx_7v0_reg; + assign enable_rx_7v0 = enable_rx_7v0_reg; + assign enable_3v3 = enable_3v3_reg; + +endmodule + +`default_nettype wire + +//XmlParse xml_on +// +// +// +// This regmap contains the registers to control the power supplies and the clock buffer for PLL reference clock. +// +// +// +// This register controls power supply enables to the Tx/Rx amps, switch control, and clk buffers. During normal +// operations, all three power supplies should be enabled. +// +// +// +// This power supply sources the switch control, and the clock buffers. By default this power supply is off. +// The internal LOs will not work unless this bit is enabled.{BR/} +// +// +// +// +// This power supply sources the Rx0 and Rx1 amps. By default this power supply is off.The Rx0/1 path will not +// be active unless this power supply is enabled. Disabling this bit is similar to RX RF blanking{BR/} +// {font color="red"}note to digital engineer, this is Pos7v0B{/font} +// +// +// +// +// This power supply sources the Tx0 and Tx1 amps. By default this power supply is off. The Tx0/1 path will not +// be active unless this power supply is enabled. Disabling this bit is similar to TX RF blanking{BR/} +// {font color="red"}note to digital engineer, this is Pos7v0A{/font} +// +// +// +// +// +// Returns status of PowerGood indicators across the daughterboard. +// +// +// +// Returns status of 7V switching regulator A.{BR/} +// +// +// +// +// Returns status of 7V switching regulator B.{BR/} +// +// +// +// +// +// Offers ability to enable or disable the PLL reference clock. +// +// +// If set PLL reference clock is enabled. +// +// +// +// +//XmlParse xml_off diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v new file mode 100644 index 000000000..63ce251b3 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v @@ -0,0 +1,918 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: switch_control +// +// Description: +// Implements control over RF switches via CtrlPort. Uses RAM to store multiple +// ATR configurations. +// + +`default_nettype none + +module switch_control #( + parameter [19:0] BASE_ADDRESS = 0, + parameter [19:0] SIZE_ADDRESS = 0 +) ( + // Clock and reset + input wire ctrlport_clk, + input wire ctrlport_rst, + + // Request + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + + // Response + output reg s_ctrlport_resp_ack, + output reg [ 1:0] s_ctrlport_resp_status = 2'b0, + output reg [31:0] s_ctrlport_resp_data = 32'b0, + + // ATR switching + input wire [ 7:0] atr_config_rf0, + input wire [ 7:0] atr_config_rf1, + + //Tx0 Switch control (domain: ctrl_reg_clk) + output wire tx0_sw1_sw2_ctrl, + output wire tx0_sw3_a, + output wire tx0_sw3_b, + output wire tx0_sw4_a, + output wire tx0_sw4_b, + output wire tx0_sw5_a, + output wire tx0_sw5_b, + output wire tx0_sw6_a, + output wire tx0_sw6_b, + output wire tx0_sw7_a, + output wire tx0_sw7_b, + output wire tx0_sw8_v1, + output wire tx0_sw8_v2, + output wire tx0_sw8_v3, + output wire tx0_sw9_a, + output wire tx0_sw9_b, + output wire tx0_sw10_a, + output wire tx0_sw10_b, + output wire tx0_sw11_a, + output wire tx0_sw11_b, + output wire tx0_sw13_v1, + output wire tx0_sw14_v1, + + //Tx1 Switch control (domain: ctrl_reg_clk) + output wire tx1_sw1_sw2_ctrl, + output wire tx1_sw3_a, + output wire tx1_sw3_b, + output wire tx1_sw4_a, + output wire tx1_sw4_b, + output wire tx1_sw5_a, + output wire tx1_sw5_b, + output wire tx1_sw6_a, + output wire tx1_sw6_b, + output wire tx1_sw7_a, + output wire tx1_sw7_b, + output wire tx1_sw8_v1, + output wire tx1_sw8_v2, + output wire tx1_sw8_v3, + output wire tx1_sw9_a, + output wire tx1_sw9_b, + output wire tx1_sw10_a, + output wire tx1_sw10_b, + output wire tx1_sw11_a, + output wire tx1_sw11_b, + output wire tx1_sw13_v1, + output wire tx1_sw14_v1, + + //Rx0 Switch control (domain: ctrl_reg_clk) + output wire rx0_sw1_a, + output wire rx0_sw1_b, + output wire rx0_sw2_a, + output wire rx0_sw3_v1, + output wire rx0_sw3_v2, + output wire rx0_sw3_v3, + output wire rx0_sw4_a, + output wire rx0_sw5_a, + output wire rx0_sw5_b, + output wire rx0_sw6_a, + output wire rx0_sw6_b, + output wire rx0_sw7_sw8_ctrl, + output wire rx0_sw9_v1, + output wire rx0_sw10_v1, + output wire rx0_sw11_v3, + output wire rx0_sw11_v2, + output wire rx0_sw11_v1, + + //Rx1 Switch control (domain: ctrl_reg_clk) + output wire rx1_sw1_a, + output wire rx1_sw1_b, + output wire rx1_sw2_a, + output wire rx1_sw3_v1, + output wire rx1_sw3_v2, + output wire rx1_sw3_v3, + output wire rx1_sw4_a, + output wire rx1_sw5_a, + output wire rx1_sw5_b, + output wire rx1_sw6_a, + output wire rx1_sw6_b, + output wire rx1_sw7_sw8_ctrl, + output wire rx1_sw9_v1, + output wire rx1_sw10_v1, + output wire rx1_sw11_v3, + output wire rx1_sw11_v2, + output wire rx1_sw11_v1 +); + + `include "../regmap/switch_setup_regmap_utils.vh" + `include "../../../../../../lib/rfnoc/core/ctrlport.vh" + + //--------------------------------------------------------------- + // register bitfields + //--------------------------------------------------------------- + //Tx0PathControl Register + reg [ TX_SWITCH_1_2_SIZE-1:0] tx0_switch_1_2_reg; + reg [ TX_SWITCH_3_SIZE-1:0] tx0_switch_3_reg; + reg [ TX_SWITCH_4_SIZE-1:0] tx0_switch_4_reg; + reg [ TX_SWITCH_5_SIZE-1:0] tx0_switch_5_reg; + reg [ TX_SWITCH_6_SIZE-1:0] tx0_switch_6_reg; + reg [ TX_SWITCH_7_SIZE-1:0] tx0_switch_7_reg; + reg [ TX_SWITCH_8_SIZE-1:0] tx0_switch_8_reg; + reg [ TX_SWITCH_9_SIZE-1:0] tx0_switch_9_reg; + reg [ TX_SWITCH_10_SIZE-1:0] tx0_switch_10_reg; + reg [ TX_SWITCH_11_SIZE-1:0] tx0_switch_11_reg; + reg [ TX_SWITCH_13_SIZE-1:0] tx0_switch_13_reg; + reg [ TX_SWITCH_14_SIZE-1:0] tx0_switch_14_reg; + + //Tx1PathControl Register + reg [ TX_SWITCH_1_2_SIZE-1:0] tx1_switch_1_2_reg; + reg [ TX_SWITCH_3_SIZE-1:0] tx1_switch_3_reg; + reg [ TX_SWITCH_4_SIZE-1:0] tx1_switch_4_reg; + reg [ TX_SWITCH_5_SIZE-1:0] tx1_switch_5_reg; + reg [ TX_SWITCH_6_SIZE-1:0] tx1_switch_6_reg; + reg [ TX_SWITCH_7_SIZE-1:0] tx1_switch_7_reg; + reg [ TX_SWITCH_8_SIZE-1:0] tx1_switch_8_reg; + reg [ TX_SWITCH_9_SIZE-1:0] tx1_switch_9_reg; + reg [ TX_SWITCH_10_SIZE-1:0] tx1_switch_10_reg; + reg [ TX_SWITCH_11_SIZE-1:0] tx1_switch_11_reg; + reg [ TX_SWITCH_13_SIZE-1:0] tx1_switch_13_reg; + reg [ TX_SWITCH_14_SIZE-1:0] tx1_switch_14_reg; + + //Rx0PathControl Register + reg [ RX_SWITCH_1_SIZE-1:0] rx0_switch_1_reg; + reg [ RX_SWITCH_2_SIZE-1:0] rx0_switch_2_reg; + reg [ RX_SWITCH_3_SIZE-1:0] rx0_switch_3_reg; + reg [ RX_SWITCH_4_SIZE-1:0] rx0_switch_4_reg; + reg [ RX_SWITCH_5_SIZE-1:0] rx0_switch_5_reg; + reg [ RX_SWITCH_6_SIZE-1:0] rx0_switch_6_reg; + reg [ RX_SWITCH_7_8_SIZE-1:0] rx0_switch_7_8_reg; + reg [ RX_SWITCH_9_SIZE-1:0] rx0_switch_9_reg; + reg [ RX_SWITCH_10_SIZE-1:0] rx0_switch_10_reg; + reg [ RX_SWITCH_11_SIZE-1:0] rx0_switch_11_reg; + + //Rx1PathControl Register + reg [ RX_SWITCH_1_SIZE-1:0] rx1_switch_1_reg; + reg [ RX_SWITCH_2_SIZE-1:0] rx1_switch_2_reg; + reg [ RX_SWITCH_3_SIZE-1:0] rx1_switch_3_reg; + reg [ RX_SWITCH_4_SIZE-1:0] rx1_switch_4_reg; + reg [ RX_SWITCH_5_SIZE-1:0] rx1_switch_5_reg; + reg [ RX_SWITCH_6_SIZE-1:0] rx1_switch_6_reg; + reg [ RX_SWITCH_7_8_SIZE-1:0] rx1_switch_7_8_reg; + reg [ RX_SWITCH_9_SIZE-1:0] rx1_switch_9_reg; + reg [ RX_SWITCH_10_SIZE-1:0] rx1_switch_10_reg; + reg [ RX_SWITCH_11_SIZE-1:0] rx1_switch_11_reg; + + //--------------------------------------------------------------- + // ATR memory signals + //--------------------------------------------------------------- + reg ram_rx0_wea; + wire [31:0] ram_rx0_doa; + wire [31:0] ram_rx0_dob; + + reg ram_rx1_wea; + wire [31:0] ram_rx1_doa; + wire [31:0] ram_rx1_dob; + + reg ram_tx0_wea; + wire [31:0] ram_tx0_doa; + wire [31:0] ram_tx0_dob; + + reg ram_tx1_wea; + wire [31:0] ram_tx1_doa; + wire [31:0] ram_tx1_dob; + + + //--------------------------------------------------------------- + // Handling of CtrlPort + //--------------------------------------------------------------- + // Check of request address is targeted for this module. + wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS); + // Read request shift register to align memory read and response generation. + reg [ 1:0] read_req_shift_reg = 2'b0; + // Mask out 8 bits for ATR configurations to be able to compare all ATR + // configurations against the same base register address. + wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]}; + // Extract masked out bits from the address, which represent the register + // array index = ATR configuration index + wire [ 7:0] register_index = s_ctrlport_req_addr[9:2]; + + always @(posedge ctrlport_clk) begin + // reset internal registers and responses + if (ctrlport_rst) begin + s_ctrlport_resp_ack <= 1'b0; + + read_req_shift_reg <= 2'b0; + + ram_tx0_wea <= 1'b0; + ram_tx1_wea <= 1'b0; + ram_rx0_wea <= 1'b0; + ram_rx1_wea <= 1'b0; + + end else begin + // default assignments + read_req_shift_reg <= {read_req_shift_reg[0], s_ctrlport_req_rd}; + + ram_tx0_wea <= 1'b0; + ram_tx1_wea <= 1'b0; + ram_rx0_wea <= 1'b0; + ram_rx1_wea <= 1'b0; + + // write requests + if (s_ctrlport_req_wr) begin + // always issue an ack and no data + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_data <= {32{1'bx}}; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + case (register_base_address) + BASE_ADDRESS + TX0_PATH_CONTROL(0): begin + ram_tx0_wea <= 1'b1; + end + + BASE_ADDRESS + TX1_PATH_CONTROL(0): begin + ram_tx1_wea <= 1'b1; + end + + BASE_ADDRESS + RX0_PATH_CONTROL(0): begin + ram_rx0_wea <= 1'b1; + end + + BASE_ADDRESS + RX1_PATH_CONTROL(0): begin + ram_rx1_wea <= 1'b1; + end + + // error on undefined address + default: begin + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // Answer read requests delayed by 2 clock cycles. This compensated for + // register ram_addr and the memory internal address register to make sure + // ram_ch0_doa is up to date when generating the response. + end else if (read_req_shift_reg[1]) begin + // default assumption: valid request + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + s_ctrlport_resp_data <= {32{1'b0}}; + + case (register_base_address) + BASE_ADDRESS + TX0_PATH_CONTROL(0): begin + s_ctrlport_resp_data <= ram_tx0_doa & TX_PATH_CONTROL_MASK; + end + BASE_ADDRESS + TX1_PATH_CONTROL(0): begin + s_ctrlport_resp_data <= ram_tx1_doa & TX_PATH_CONTROL_MASK; + end + BASE_ADDRESS + RX0_PATH_CONTROL(0): begin + s_ctrlport_resp_data <= ram_rx0_doa & RX_PATH_CONTROL_MASK; + end + BASE_ADDRESS + RX1_PATH_CONTROL(0): begin + s_ctrlport_resp_data <= ram_rx1_doa & RX_PATH_CONTROL_MASK; + end + + default: begin + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // no request + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + end + + // register without reset + reg [ 7:0] ram_addr = 8'b0; + reg [31:0] ram_datain = 32'b0; + always @(posedge ctrlport_clk) begin + // memories + ram_addr <= register_index; + ram_datain <= s_ctrlport_req_data; + + // outputs + tx0_switch_1_2_reg <= ram_tx0_dob[TX_SWITCH_1_2]; + tx0_switch_3_reg <= ram_tx0_dob[TX_SWITCH_3_MSB : TX_SWITCH_3]; + tx0_switch_4_reg <= ram_tx0_dob[TX_SWITCH_4_MSB : TX_SWITCH_4]; + tx0_switch_5_reg <= ram_tx0_dob[TX_SWITCH_5_MSB : TX_SWITCH_5]; + tx0_switch_6_reg <= ram_tx0_dob[TX_SWITCH_6_MSB : TX_SWITCH_6]; + tx0_switch_7_reg <= ram_tx0_dob[TX_SWITCH_7_MSB : TX_SWITCH_7]; + tx0_switch_8_reg <= ram_tx0_dob[TX_SWITCH_8_MSB : TX_SWITCH_8]; + tx0_switch_9_reg <= ram_tx0_dob[TX_SWITCH_9_MSB : TX_SWITCH_9]; + tx0_switch_10_reg <= ram_tx0_dob[TX_SWITCH_10_MSB : TX_SWITCH_10]; + tx0_switch_11_reg <= ram_tx0_dob[TX_SWITCH_11_MSB : TX_SWITCH_11]; + tx0_switch_13_reg <= ram_tx0_dob[TX_SWITCH_13]; + tx0_switch_14_reg <= ram_tx0_dob[TX_SWITCH_14]; + + tx1_switch_1_2_reg <= ram_tx1_dob[TX_SWITCH_1_2]; + tx1_switch_3_reg <= ram_tx1_dob[TX_SWITCH_3_MSB : TX_SWITCH_3]; + tx1_switch_4_reg <= ram_tx1_dob[TX_SWITCH_4_MSB : TX_SWITCH_4]; + tx1_switch_5_reg <= ram_tx1_dob[TX_SWITCH_5_MSB : TX_SWITCH_5]; + tx1_switch_6_reg <= ram_tx1_dob[TX_SWITCH_6_MSB : TX_SWITCH_6]; + tx1_switch_7_reg <= ram_tx1_dob[TX_SWITCH_7_MSB : TX_SWITCH_7]; + tx1_switch_8_reg <= ram_tx1_dob[TX_SWITCH_8_MSB : TX_SWITCH_8]; + tx1_switch_9_reg <= ram_tx1_dob[TX_SWITCH_9_MSB : TX_SWITCH_9]; + tx1_switch_10_reg <= ram_tx1_dob[TX_SWITCH_10_MSB : TX_SWITCH_10]; + tx1_switch_11_reg <= ram_tx1_dob[TX_SWITCH_11_MSB : TX_SWITCH_11]; + tx1_switch_13_reg <= ram_tx1_dob[TX_SWITCH_13]; + tx1_switch_14_reg <= ram_tx1_dob[TX_SWITCH_14]; + + rx0_switch_1_reg <= ram_rx0_dob[RX_SWITCH_1_MSB : RX_SWITCH_1]; + rx0_switch_2_reg <= ram_rx0_dob[RX_SWITCH_2]; + rx0_switch_3_reg <= ram_rx0_dob[RX_SWITCH_3_MSB : RX_SWITCH_3]; + rx0_switch_4_reg <= ram_rx0_dob[RX_SWITCH_4]; + rx0_switch_5_reg <= ram_rx0_dob[RX_SWITCH_5_MSB : RX_SWITCH_5]; + rx0_switch_6_reg <= ram_rx0_dob[RX_SWITCH_6_MSB : RX_SWITCH_6]; + rx0_switch_7_8_reg <= ram_rx0_dob[RX_SWITCH_7_8]; + rx0_switch_9_reg <= ram_rx0_dob[RX_SWITCH_9]; + rx0_switch_10_reg <= ram_rx0_dob[RX_SWITCH_10]; + rx0_switch_11_reg <= ram_rx0_dob[RX_SWITCH_11_MSB: RX_SWITCH_11]; + + rx1_switch_1_reg <= ram_rx1_dob[RX_SWITCH_1_MSB : RX_SWITCH_1]; + rx1_switch_2_reg <= ram_rx1_dob[RX_SWITCH_2]; + rx1_switch_3_reg <= ram_rx1_dob[RX_SWITCH_3_MSB : RX_SWITCH_3]; + rx1_switch_4_reg <= ram_rx1_dob[RX_SWITCH_4]; + rx1_switch_5_reg <= ram_rx1_dob[RX_SWITCH_5_MSB : RX_SWITCH_5]; + rx1_switch_6_reg <= ram_rx1_dob[RX_SWITCH_6_MSB : RX_SWITCH_6]; + rx1_switch_7_8_reg <= ram_rx1_dob[RX_SWITCH_7_8]; + rx1_switch_9_reg <= ram_rx1_dob[RX_SWITCH_9]; + rx1_switch_10_reg <= ram_rx1_dob[RX_SWITCH_10]; + rx1_switch_11_reg <= ram_rx1_dob[RX_SWITCH_11_MSB: RX_SWITCH_11]; + end + + ram_2port #( + .DWIDTH (32), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0), + .INIT_FILE ("register_endpoints/memory_init_files/tx0_path_defaults.hex") + ) ram_tx0_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_tx0_wea), + .addra (ram_addr), + .dia (ram_datain), + .doa (ram_tx0_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_rf0), + .dib (0), + .dob (ram_tx0_dob)); + + ram_2port #( + .DWIDTH (32), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0), + .INIT_FILE ("register_endpoints/memory_init_files/tx1_path_defaults.hex") + ) ram_tx1_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_tx1_wea), + .addra (ram_addr), + .dia (ram_datain), + .doa (ram_tx1_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_rf1), + .dib (0), + .dob (ram_tx1_dob)); + + ram_2port #( + .DWIDTH (32), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0), + .INIT_FILE ("register_endpoints/memory_init_files/rx0_path_defaults.hex") + ) ram_rx0_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_rx0_wea), + .addra (ram_addr), + .dia (ram_datain), + .doa (ram_rx0_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_rf0), + .dib (0), + .dob (ram_rx0_dob)); + + ram_2port #( + .DWIDTH (32), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0), + .INIT_FILE ("register_endpoints/memory_init_files/rx1_path_defaults.hex") + ) ram_rx1_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_rx1_wea), + .addra (ram_addr), + .dia (ram_datain), + .doa (ram_rx1_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_rf1), + .dib (0), + .dob (ram_rx1_dob)); + + assign tx0_sw1_sw2_ctrl = tx0_switch_1_2_reg; + assign tx0_sw3_a = tx0_switch_3_reg[0]; + assign tx0_sw3_b = tx0_switch_3_reg[1]; + assign tx0_sw4_a = tx0_switch_4_reg[0]; + assign tx0_sw4_b = tx0_switch_4_reg[1]; + assign tx0_sw5_a = tx0_switch_5_reg[0]; + assign tx0_sw5_b = tx0_switch_5_reg[1]; + assign tx0_sw6_a = tx0_switch_6_reg[0]; + assign tx0_sw6_b = tx0_switch_6_reg[1]; + assign tx0_sw7_a = tx0_switch_7_reg[0]; + assign tx0_sw7_b = tx0_switch_7_reg[1]; + assign tx0_sw8_v1 = tx0_switch_8_reg[0]; + assign tx0_sw8_v2 = tx0_switch_8_reg[1]; + assign tx0_sw8_v3 = tx0_switch_8_reg[2]; + assign tx0_sw9_a = tx0_switch_9_reg[0]; + assign tx0_sw9_b = tx0_switch_9_reg[1]; + assign tx0_sw10_a = tx0_switch_10_reg[0]; + assign tx0_sw10_b = tx0_switch_10_reg[1]; + assign tx0_sw11_a = tx0_switch_11_reg[0]; + assign tx0_sw11_b = tx0_switch_11_reg[1]; + assign tx0_sw13_v1 = tx0_switch_13_reg; + assign tx0_sw14_v1 = tx0_switch_14_reg; + + assign tx1_sw1_sw2_ctrl = tx1_switch_1_2_reg; + assign tx1_sw3_a = tx1_switch_3_reg[0]; + assign tx1_sw3_b = tx1_switch_3_reg[1]; + assign tx1_sw4_a = tx1_switch_4_reg[0]; + assign tx1_sw4_b = tx1_switch_4_reg[1]; + assign tx1_sw5_a = tx1_switch_5_reg[0]; + assign tx1_sw5_b = tx1_switch_5_reg[1]; + assign tx1_sw6_a = tx1_switch_6_reg[0]; + assign tx1_sw6_b = tx1_switch_6_reg[1]; + assign tx1_sw7_a = tx1_switch_7_reg[0]; + assign tx1_sw7_b = tx1_switch_7_reg[1]; + assign tx1_sw8_v1 = tx1_switch_8_reg[0]; + assign tx1_sw8_v2 = tx1_switch_8_reg[1]; + assign tx1_sw8_v3 = tx1_switch_8_reg[2]; + assign tx1_sw9_a = tx1_switch_9_reg[0]; + assign tx1_sw9_b = tx1_switch_9_reg[1]; + assign tx1_sw10_a = tx1_switch_10_reg[0]; + assign tx1_sw10_b = tx1_switch_10_reg[1]; + assign tx1_sw11_a = tx1_switch_11_reg[0]; + assign tx1_sw11_b = tx1_switch_11_reg[1]; + assign tx1_sw13_v1 = tx1_switch_13_reg; + assign tx1_sw14_v1 = tx1_switch_14_reg; + + assign rx0_sw1_a = rx0_switch_1_reg[0]; + assign rx0_sw1_b = rx0_switch_1_reg[1]; + assign rx0_sw2_a = rx0_switch_2_reg; + assign rx0_sw3_v1 = rx0_switch_3_reg[0]; + assign rx0_sw3_v2 = rx0_switch_3_reg[1]; + assign rx0_sw3_v3 = rx0_switch_3_reg[2]; + assign rx0_sw4_a = rx0_switch_4_reg; + assign rx0_sw5_a = rx0_switch_5_reg[0]; + assign rx0_sw5_b = rx0_switch_5_reg[1]; + assign rx0_sw6_a = rx0_switch_6_reg[0]; + assign rx0_sw6_b = rx0_switch_6_reg[1]; + assign rx0_sw7_sw8_ctrl = rx0_switch_7_8_reg; + assign rx0_sw9_v1 = rx0_switch_9_reg; + assign rx0_sw10_v1 = rx0_switch_10_reg; + assign rx0_sw11_v1 = rx0_switch_11_reg[0]; + assign rx0_sw11_v2 = rx0_switch_11_reg[1]; + assign rx0_sw11_v3 = rx0_switch_11_reg[2]; + + assign rx1_sw1_a = rx1_switch_1_reg[0]; + assign rx1_sw1_b = rx1_switch_1_reg[1]; + assign rx1_sw2_a = rx1_switch_2_reg; + assign rx1_sw3_v1 = rx1_switch_3_reg[0]; + assign rx1_sw3_v2 = rx1_switch_3_reg[1]; + assign rx1_sw3_v3 = rx1_switch_3_reg[2]; + assign rx1_sw4_a = rx1_switch_4_reg; + assign rx1_sw5_a = rx1_switch_5_reg[0]; + assign rx1_sw5_b = rx1_switch_5_reg[1]; + assign rx1_sw6_a = rx1_switch_6_reg[0]; + assign rx1_sw6_b = rx1_switch_6_reg[1]; + assign rx1_sw7_sw8_ctrl = rx1_switch_7_8_reg; + assign rx1_sw9_v1 = rx1_switch_9_reg; + assign rx1_sw10_v1 = rx1_switch_10_reg; + assign rx1_sw11_v1 = rx1_switch_11_reg[0]; + assign rx1_sw11_v2 = rx1_switch_11_reg[1]; + assign rx1_sw11_v3 = rx1_switch_11_reg[2]; + +endmodule + +`default_nettype wire + +//XmlParse xml_on +// +// +// +// The following registers are used to control the path that the RF signal +// takes for both Tx and Rx{BR/}{BR/} +// +// +// +// This Register controls the switches along the Tx path. Note: default +// values refer to the RX0 path. RX1 has the same defaults, but their +// bit values may differ. +// +// +// +// Write 0 to select Tx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz{BR/} +// Write 1 to select Tx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz{BR/} +// +// +// +// +// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/} +// Control for Tx Switch 3. The configuration of this switch changes between TX paths.{BR/} +// {b}FOR TX0:{/b}{BR/} +// Write 0 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See @.TX_SWITCH_4 for those controls{BR/} +// Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz{BR/} +// Write 2 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz{BR/} +// Write 3 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz{BR/} +// {b}FOR TX1:{/b}{BR/} +// Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz{BR/} +// Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz{BR/} +// Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz{BR/} +// Write 3 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See @.TX_SWITCH_4 for those controls{BR/} +// +// +// +// +// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/} +// Control for Tx Switch 4. This switch path is only taken if @.TX_SWITCH_4 is set to 0. +// The configuration of this switch changes between TX paths.{BR/} +// {b}FOR TX0:{/b}{BR/} +// Write 0 to select 50 ohm termination{BR/} +// Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz{BR/} +// Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz{BR/} +// Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz{BR/} +// {b}FOR TX1:{/b}{BR/} +// Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz{BR/} +// Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz{BR/} +// Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz{BR/} +// Write 3 to select 50 ohm termination{BR/} +// +// +// +// +// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/} +// Control for Tx Switch 5. This switch path is only taken if @.TX_SWITCH_6 is set to 0. +// The configuration of this switch changes between TX paths.{BR/} +// {b}FOR TX0:{/b}{BR/} +// Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz{BR/} +// Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz{BR/} +// Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz{BR/} +// Write 3 to select Tx If1 Filter 50 ohm termination{BR/} +// {b}FOR TX1:{/b}{BR/} +// Write 0 to select Tx If1 Filter 50 ohm termination{BR/} +// Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz{BR/} +// Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz{BR/} +// Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz{BR/} +// +// +// +// +// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/} +// Control for Tx Switch 6. +// The configuration of this switch changes between TX paths.{BR/} +// {b}FOR TX0:{/b}{BR/} +// Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz{BR/} +// Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz{BR/} +// Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz{BR/} +// Write 3 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See @.TX_SWITCH_5 for those controls{/font}{BR/} +// {b}FOR TX1:{/b}{BR/} +// Write 0 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See @.TX_SWITCH_5 for those controls{/font}{BR/} +// Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz{BR/} +// Write 2 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz{BR/} +// Write 3 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz{BR/} +// +// +// +// +// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/} +// Control for Tx Switch 7. +// The configuration of this switch changes between TX paths.{BR/} +// {b}FOR TX0:{/b}{BR/} +// Write 0 to select 50 ohm termination{BR/} +// Write 1 to select no connect{BR/} +// Write 2 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz{BR/} +// Write 3 to select Tx lowbands RF1, RF2, RF3 path. See @.TX_SWITCH_8 for those controls{BR/} +// {b}FOR TX1:{/b}{BR/} +// Write 0 to select Tx lowbands RF1, RF2, RF3 path. See @.TX_SWITCH_8 for those controls{BR/} +// Write 1 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz{BR/} +// Write 2 to select no connect{BR/} +// Write 3 to select 50 ohm termination{BR/} +// +// +// +// +// Control for Tx Switch 8, note this is one hot encoding and not binary. +// The configuration of this switch changes between TX paths.{BR/} +// {b}FOR TX0:{/b}{BR/} +// Write 1 to select Tx RF3 path, 2.3 GHz to 3.1 GHz{BR/} +// Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz{BR/} +// Write 4 to select Tx RF2 path, 1.95 GHz to 2.3 GHz{BR/} +// {b}FOR TX1:{/b}{BR/} +// Write 1 to select Tx RF2 path, 1.95 GHz to 2.3 GHz{BR/} +// Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz{BR/} +// Write 4 to select Tx RF3 path, 2.3 GHz to 3.1 GHz{BR/} +// {i}*All other values are invalid{/i}{BR/} +// +// +// +// +// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/} +// Control for Tx Switch 9. +// The configuration of this switch changes between TX paths.{BR/} +// {b}FOR TX0:{/b}{BR/} +// Write 0 to select Tx RF3 path, 2.3 GHz to 3.1 GHz{BR/} +// Write 1 to select Tx RF1 path, 1.0 MHz to 1.95 GHz{BR/} +// Write 2 to select Tx RF2 path, 1.95 GHz to 2.3 GHz{BR/} +// Write 3 to select Tx RF4 path, 3.1 GHz to 8.0 GHz{BR/} +// {b}FOR TX1:{/b}{BR/} +// Write 0 to select Tx RF4 path, 3.1 GHz to 8.0 GHz{BR/} +// Write 1 to select Tx RF2 path, 1.95 GHz to 2.3 GHz{BR/} +// Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz{BR/} +// Write 3 to select Tx RF3 path, 2.3 GHz to 3.1 GHz{BR/} +// +// +// +// +// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/} +// Control for Tx Switch 10. +// The configuration of this switch changes between TX paths.{BR/} +// {b}FOR TX0:{/b}{BR/} +// Write 0 to select Tx amplifier bypass path{BR/} +// Write 1 to select Tx calibration loopback path{BR/} +// Write 2 to select Tx lowband amp path. @.TX_Switch_11 must also match this path.{BR/} +// Write 3 to select Tx highband amp path. @.TX_Switch_11 must also match this path.{BR/} +// {b}FOR TX1:{/b}{BR/} +// Write 0 to select Tx highband amp path. @.TX_Switch_11 must also match this path.{BR/} +// Write 1 to select Tx lowband amp path. @.TX_Switch_11 must also match this path.{BR/} +// Write 2 to select Tx amplifier bypass path{BR/} +// Write 3 to select Tx calibration loopback path{BR/} +// +// +// +// +// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/} +// Control for Tx Switch 11. +// The configuration of this switch changes between TX paths.{BR/} +// {b}FOR TX0:{/b}{BR/} +// Write 0 to select Tx Rx path, @.RX_SWITCH_1 must also select the correct path{BR/} +// Write 1 to select Tx highband amp path. @.TX_SWITCH_10 must also match this path.{BR/} +// Write 2 to select Tx lowband amp path. @.TX_SWITCH_10 must also match this path.{BR/} +// Write 3 to select Tx amplifier bypass path{BR/} +// {b}FOR TX1:{/b}{BR/} +// Write 0 to select Tx Rx path, @.RX_SWITCH_1 must also select the correct path{BR/} +// Write 1 to select Tx amplifier bypass path{BR/} +// Write 2 to select Tx lowband amp path. @.TX_SWITCH_10 must also match this path.{BR/} +// Write 3 to select Tx highband amp path. @.TX_SWITCH_10 must also match this path.{BR/} +// +// +// +// +// Control for Tx0 Switch 13 LO path. +// The configuration of this switch changes between TX paths.{BR/} +// {b}FOR TX0:{/b}{BR/} +// Write 0 to select Tx0 internal LO path{BR/} +// Write 1 to select Tx0 external LO path{BR/} +// {b}FOR TX1:{/b}{BR/} +// Write 0 to select Tx0 external LO path{BR/} +// Write 1 to select Tx0 internal LO path{BR/} +// +// +// +// +// Control for Tx Switch 13 LO path. +// The configuration of this switch changes between TX paths.{BR/} +// {b}FOR TX0:{/b}{BR/} +// Write 0 to select Tx external LO path{BR/} +// Write 1 to select Tx internal LO path{BR/} +// {b}FOR TX1:{/b}{BR/} +// Write 0 to select Tx internal LO path{BR/} +// Write 1 to select Tx external LO path{BR/} +// +// +// +// +// +// +// This Register controls switches along Rx paths. Note: default +// values refer to the RX0 path. RX1 has the same defaults, but their +// bit values may differ. +// +// +// +// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/} +// Control for Rx Switch 1. +// The configuration of this switch changes between RX paths.{BR/} +// {b}FOR RX0:{/b}{BR/} +// Write 0 to select Rx calibration loopback{BR/} +// Write 1 to select Rx 50 ohm termination path{BR/} +// Write 2 to select Tx Rx path, @.TX_SWITCH_11 must also select the correct path{BR/} +// Write 3 to select Rx input port{BR/} +// {b}FOR RX1:{/b}{BR/} +// Write 0 to select Rx calibration loopback{BR/} +// Write 1 to select Tx Rx path, @.TX_SWITCH_11 must also select the correct path{BR/} +// Write 2 to select Rx input port{BR/} +// Write 3 to select Rx 50 ohm termination path{BR/} +// +// +// +// +// {font color="red"}note to digital designer: control A is the only control, and control B is pulled high{/font}{BR/} +// Control for Rx Switch 2. The configuration of this switch changes between RX paths.{BR/} +// {b}FOR RX0:{/b}{BR/} +// Write 0 to select Rx RF3 highband path{BR/} +// Write 1 to select Rx RF1/2 lowband path{BR/} +// {b}FOR RX1:{/b}{BR/} +// Write 0 to select Rx RF1/2 lowband path{BR/} +// Write 1 to select Rx RF3 highband path{BR/} +// +// +// +// +// Control for Rx Switch 3, note this is one hot encoding and not binary. +// The configuration of this switch changes between RX paths.{BR/} +// {b}FOR RX0:{/b}{BR/} +// Write 1 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz{BR/} +// Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz{BR/} +// Write 4 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz{BR/} +// {b}FOR RX1:{/b}{BR/} +// Write 1 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz{BR/} +// Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz{BR/} +// Write 4 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz{BR/} +// {i}*All other values are invalid{/i}{BR/} +// +// +// +// +// {font color="red"}note to digital designer: control A is the only control, and control B is tied to ground{/font}{BR/} +// Control for Rx Switch 4.{BR/} +// Write 0 to select Rx RF1/2 lowband path{BR/} +// Write 1 to select Rx RF3 highband path{BR/} +// +// +// +// +// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/}{BR/} +// +// Control for Rx Switch 5. The configuration of this switch changes between RX paths.{BR/} +// {b}FOR RX0:{/b}{BR/} +// Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, @.RX_SWITCH_6 must also select this path{BR/} +// Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, @.RX_SWITCH_6 must also select this path{BR/} +// Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, @.RX_SWITCH_6 must also select this path{BR/} +// Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, @.RX_SWITCH_6 must also select this path{BR/} +// {b}FOR RX1:{/b}{BR/} +// Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, @.RX_SWITCH_6 must also select this path{BR/} +// Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, @.RX_SWITCH_6 must also select this path{BR/} +// Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, @.RX_SWITCH_6 must also select this path{BR/} +// Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, @.RX_SWITCH_6 must also select this path{BR/} +// +// +// +// +// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/}{BR/} +// +// Control for Rx Switch 6. The configuration of this switch changes between RX paths.{BR/} +// {b}FOR RX0:{/b}{BR/} +// Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, @.RX_SWITCH_6 must also select this path{BR/} +// Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, @.RX_SWITCH_6 must also select this path{BR/} +// Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, @.RX_SWITCH_6 must also select this path{BR/} +// Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, @.RX_SWITCH_6 must also select this path{BR/} +// {b}FOR RX1:{/b}{BR/} +// Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, @.RX_SWITCH_6 must also select this path{BR/} +// Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, @.RX_SWITCH_6 must also select this path{BR/} +// Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, @.RX_SWITCH_6 must also select this path{BR/} +// Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, @.RX_SWITCH_6 must also select this path{BR/} +// +// +// +// +// Shared control for Rx switch 7 and switch 8.{BR/} +// {b}FOR RX0:{/b}{BR/} +// Write 0 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz{BR/} +// Write 1 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz{BR/} +// {b}FOR RX1:{/b}{BR/} +// Write 0 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz{BR/} +// Write 1 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz{BR/} +// +// +// +// +// Control for Rx Switch 9 LO path. The configuration of this switch changes between RX paths.{BR/} +// {b}FOR RX0:{/b}{BR/} +// Write 0 to select Rx internal LO path{BR/} +// Write 1 to select Rx external LO path{BR/} +// {b}FOR RX1:{/b}{BR/} +// Write 0 to select Rx external LO path{BR/} +// Write 1 to select Rx internal LO path{BR/} +// +// +// +// +// Control for Rx Switch 10 LO path. The configuration of this switch changes between RX paths.{BR/} +// {b}FOR RX0:{/b}{BR/} +// Write 0 to select Rx internal LO path{BR/} +// Write 1 to select Rx external LO path{BR/} +// {b}FOR RX1:{/b}{BR/} +// Write 0 to select Rx external LO path{BR/} +// Write 1 to select Rx internal LO path{BR/} +// +// +// +// +// Control for Rx Switch 11, note to digital designer: Control V2 is pulled to ground.{BR/}{BR/} +// The configuration of this switch changes between RX paths.{BR/} +// {b}FOR RX0:{/b}{BR/} +// Write 1 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz{BR/} +// Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz{BR/} +// Write 4 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz{BR/} +// {b}FOR RX1:{/b}{BR/} +// Write 1 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz{BR/} +// Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz{BR/} +// Write 4 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz{BR/} +// +// +// +// +// +// +// This Register controls the Tx0 paths.{br} +// This register array can hold settings for all ATR configurations. +// The register index equals the ATR configuration. +// The active configuration can be selected in @.ATR_REGMAP. +// Independently all configurations can be read/written at any time. +// +// +// +// +// This Register controls the Tx1 paths.{br} +// This register array can hold settings for all ATR configurations. +// The register index equals the ATR configuration. +// The active configuration can be selected in @.ATR_REGMAP. +// Independently all configurations can be read/written at any time. +// +// +// +// +// +// This Register controls the Rx0 paths.{br} +// This register array can hold settings for all ATR configurations. +// The register index equals the ATR configuration. +// The active configuration can be selected in @.ATR_REGMAP. +// Independently all configurations can be read/written at any time. +// +// +// +// +// This Register controls the Rx1 paths.{br} +// This register array can hold settings for all ATR configurations. +// The register index equals the ATR configuration. +// The active configuration can be selected in @.ATR_REGMAP. +// Independently all configurations can be read/written at any time. +// +// +// +// +//XmlParse xml_off diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/utils/spi_control_utils.vh b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/utils/spi_control_utils.vh new file mode 100644 index 000000000..5a6ab27e2 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/utils/spi_control_utils.vh @@ -0,0 +1,30 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: spi_control_utils +// +// Description: +// Contains constants and functions common to blocks that interact +// with the wishbone spi engine. +// + +// SPI Master Control Register Offsets +localparam TX_DATA_REG = 5'h00; +localparam RX_DATA_REG = 5'h00; +localparam CLOCK_DIVIDER_REG = 5'h14; +localparam CONTROL_REG = 5'h10; +localparam SS_REG = 5'h18; + +// Simple function to return a vector of 0's with only position +// ss_input set to 1. +function automatic [31:0] set_ss_bit; +input [3:0] ss_input; +reg [31:0] ss_data; +begin + ss_data = 32'h0; + ss_data[ss_input] = 1'b1; + set_ss_bit = ss_data; +end +endfunction diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/atr_regmap_utils.vh b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/atr_regmap_utils.vh new file mode 100644 index 000000000..c435ab01a --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/atr_regmap_utils.vh @@ -0,0 +1,81 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: atr_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // CURRENT_CONFIG_REG : 0x0 (atr_controller.v) + // OPTION_REG : 0x4 (atr_controller.v) + // SW_CONFIG_REG : 0x8 (atr_controller.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group ATR_REGISTERS +//=============================================================================== + + // Enumerated type ATR_OPTIONS + localparam ATR_OPTIONS_SIZE = 3; + localparam SW_DEFINED = 'h0; // ATR_OPTIONS:SW_DEFINED + localparam CLASSIC_ATR = 'h1; // ATR_OPTIONS:CLASSIC_ATR + localparam FPGA_STATE = 'h2; // ATR_OPTIONS:FPGA_STATE + + // CURRENT_CONFIG_REG Register (from atr_controller.v) + localparam CURRENT_CONFIG_REG = 'h0; // Register Offset + localparam CURRENT_CONFIG_REG_SIZE = 32; // register width in bits + localparam CURRENT_CONFIG_REG_MASK = 32'hFFFFFFFF; + localparam CURRENT_RF0_CONFIG_SIZE = 8; //CURRENT_CONFIG_REG:CURRENT_RF0_CONFIG + localparam CURRENT_RF0_CONFIG_MSB = 7; //CURRENT_CONFIG_REG:CURRENT_RF0_CONFIG + localparam CURRENT_RF0_CONFIG = 0; //CURRENT_CONFIG_REG:CURRENT_RF0_CONFIG + localparam CURRENT_RF1_CONFIG_SIZE = 8; //CURRENT_CONFIG_REG:CURRENT_RF1_CONFIG + localparam CURRENT_RF1_CONFIG_MSB = 15; //CURRENT_CONFIG_REG:CURRENT_RF1_CONFIG + localparam CURRENT_RF1_CONFIG = 8; //CURRENT_CONFIG_REG:CURRENT_RF1_CONFIG + localparam CURRENT_RF0_DSA_CONFIG_SIZE = 8; //CURRENT_CONFIG_REG:CURRENT_RF0_DSA_CONFIG + localparam CURRENT_RF0_DSA_CONFIG_MSB = 23; //CURRENT_CONFIG_REG:CURRENT_RF0_DSA_CONFIG + localparam CURRENT_RF0_DSA_CONFIG = 16; //CURRENT_CONFIG_REG:CURRENT_RF0_DSA_CONFIG + localparam CURRENT_RF1_DSA_CONFIG_SIZE = 8; //CURRENT_CONFIG_REG:CURRENT_RF1_DSA_CONFIG + localparam CURRENT_RF1_DSA_CONFIG_MSB = 31; //CURRENT_CONFIG_REG:CURRENT_RF1_DSA_CONFIG + localparam CURRENT_RF1_DSA_CONFIG = 24; //CURRENT_CONFIG_REG:CURRENT_RF1_DSA_CONFIG + + // OPTION_REG Register (from atr_controller.v) + localparam OPTION_REG = 'h4; // Register Offset + localparam OPTION_REG_SIZE = 32; // register width in bits + localparam OPTION_REG_MASK = 32'h3030303; + localparam RF0_OPTION_SIZE = 2; //OPTION_REG:RF0_OPTION + localparam RF0_OPTION_MSB = 1; //OPTION_REG:RF0_OPTION + localparam RF0_OPTION = 0; //OPTION_REG:RF0_OPTION + localparam RF1_OPTION_SIZE = 2; //OPTION_REG:RF1_OPTION + localparam RF1_OPTION_MSB = 9; //OPTION_REG:RF1_OPTION + localparam RF1_OPTION = 8; //OPTION_REG:RF1_OPTION + localparam RF0_DSA_OPTION_SIZE = 2; //OPTION_REG:RF0_DSA_OPTION + localparam RF0_DSA_OPTION_MSB = 17; //OPTION_REG:RF0_DSA_OPTION + localparam RF0_DSA_OPTION = 16; //OPTION_REG:RF0_DSA_OPTION + localparam RF1_DSA_OPTION_SIZE = 2; //OPTION_REG:RF1_DSA_OPTION + localparam RF1_DSA_OPTION_MSB = 25; //OPTION_REG:RF1_DSA_OPTION + localparam RF1_DSA_OPTION = 24; //OPTION_REG:RF1_DSA_OPTION + + // SW_CONFIG_REG Register (from atr_controller.v) + localparam SW_CONFIG_REG = 'h8; // Register Offset + localparam SW_CONFIG_REG_SIZE = 32; // register width in bits + localparam SW_CONFIG_REG_MASK = 32'hFFFFFFFF; + localparam SW_RF0_CONFIG_SIZE = 8; //SW_CONFIG_REG:SW_RF0_CONFIG + localparam SW_RF0_CONFIG_MSB = 7; //SW_CONFIG_REG:SW_RF0_CONFIG + localparam SW_RF0_CONFIG = 0; //SW_CONFIG_REG:SW_RF0_CONFIG + localparam SW_RF1_CONFIG_SIZE = 8; //SW_CONFIG_REG:SW_RF1_CONFIG + localparam SW_RF1_CONFIG_MSB = 15; //SW_CONFIG_REG:SW_RF1_CONFIG + localparam SW_RF1_CONFIG = 8; //SW_CONFIG_REG:SW_RF1_CONFIG + localparam SW_RF0_DSA_CONFIG_SIZE = 8; //SW_CONFIG_REG:SW_RF0_DSA_CONFIG + localparam SW_RF0_DSA_CONFIG_MSB = 23; //SW_CONFIG_REG:SW_RF0_DSA_CONFIG + localparam SW_RF0_DSA_CONFIG = 16; //SW_CONFIG_REG:SW_RF0_DSA_CONFIG + localparam SW_RF1_DSA_CONFIG_SIZE = 8; //SW_CONFIG_REG:SW_RF1_DSA_CONFIG + localparam SW_RF1_DSA_CONFIG_MSB = 31; //SW_CONFIG_REG:SW_RF1_DSA_CONFIG + localparam SW_RF1_DSA_CONFIG = 24; //SW_CONFIG_REG:SW_RF1_DSA_CONFIG diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh new file mode 100644 index 000000000..0bbbd704e --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh @@ -0,0 +1,75 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: basic_regs_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // SLAVE_SIGNATURE : 0x0 (basic_regs.v) + // SLAVE_REVISION : 0x4 (basic_regs.v) + // SLAVE_OLDEST_REVISION : 0x8 (basic_regs.v) + // SLAVE_SCRATCH : 0xC (basic_regs.v) + // GIT_HASH_REGISTER : 0x10 (basic_regs.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group BASIC_REGS_REGISTERS +//=============================================================================== + + // Enumerated type BASIC_REGISTERS_VALUES + localparam BASIC_REGISTERS_VALUES_SIZE = 3; + localparam BOARD_ID_VALUE = 'h4002; // BASIC_REGISTERS_VALUES:BOARD_ID_VALUE + localparam OLDEST_CPLD_REVISION = 'h20110611; // BASIC_REGISTERS_VALUES:OLDEST_CPLD_REVISION + localparam CPLD_REVISION = 'h21031009; // BASIC_REGISTERS_VALUES:CPLD_REVISION + + // SLAVE_SIGNATURE Register (from basic_regs.v) + localparam SLAVE_SIGNATURE = 'h0; // Register Offset + localparam SLAVE_SIGNATURE_SIZE = 32; // register width in bits + localparam SLAVE_SIGNATURE_MASK = 32'hFFFF; + localparam BOARD_ID_SIZE = 16; //SLAVE_SIGNATURE:BOARD_ID + localparam BOARD_ID_MSB = 15; //SLAVE_SIGNATURE:BOARD_ID + localparam BOARD_ID = 0; //SLAVE_SIGNATURE:BOARD_ID + + // SLAVE_REVISION Register (from basic_regs.v) + localparam SLAVE_REVISION = 'h4; // Register Offset + localparam SLAVE_REVISION_SIZE = 32; // register width in bits + localparam SLAVE_REVISION_MASK = 32'hFFFFFFFF; + localparam REVISION_REG_SIZE = 32; //SLAVE_REVISION:REVISION_REG + localparam REVISION_REG_MSB = 31; //SLAVE_REVISION:REVISION_REG + localparam REVISION_REG = 0; //SLAVE_REVISION:REVISION_REG + + // SLAVE_OLDEST_REVISION Register (from basic_regs.v) + localparam SLAVE_OLDEST_REVISION = 'h8; // Register Offset + localparam SLAVE_OLDEST_REVISION_SIZE = 32; // register width in bits + localparam SLAVE_OLDEST_REVISION_MASK = 32'hFFFFFFFF; + localparam OLDEST_REVISION_REG_SIZE = 32; //SLAVE_OLDEST_REVISION:OLDEST_REVISION_REG + localparam OLDEST_REVISION_REG_MSB = 31; //SLAVE_OLDEST_REVISION:OLDEST_REVISION_REG + localparam OLDEST_REVISION_REG = 0; //SLAVE_OLDEST_REVISION:OLDEST_REVISION_REG + + // SLAVE_SCRATCH Register (from basic_regs.v) + localparam SLAVE_SCRATCH = 'hC; // Register Offset + localparam SLAVE_SCRATCH_SIZE = 32; // register width in bits + localparam SLAVE_SCRATCH_MASK = 32'hFFFFFFFF; + localparam SCRATCH_REG_SIZE = 32; //SLAVE_SCRATCH:SCRATCH_REG + localparam SCRATCH_REG_MSB = 31; //SLAVE_SCRATCH:SCRATCH_REG + localparam SCRATCH_REG = 0; //SLAVE_SCRATCH:SCRATCH_REG + + // GIT_HASH_REGISTER Register (from basic_regs.v) + localparam GIT_HASH_REGISTER = 'h10; // Register Offset + localparam GIT_HASH_REGISTER_SIZE = 32; // register width in bits + localparam GIT_HASH_REGISTER_MASK = 32'hFFFFFFFF; + localparam GIT_HASH_SIZE = 28; //GIT_HASH_REGISTER:GIT_HASH + localparam GIT_HASH_MSB = 27; //GIT_HASH_REGISTER:GIT_HASH + localparam GIT_HASH = 0; //GIT_HASH_REGISTER:GIT_HASH + localparam GIT_CLEAN_SIZE = 4; //GIT_HASH_REGISTER:GIT_CLEAN + localparam GIT_CLEAN_MSB = 31; //GIT_HASH_REGISTER:GIT_CLEAN + localparam GIT_CLEAN = 28; //GIT_HASH_REGISTER:GIT_CLEAN diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/db_control_regmap_utils.vh b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/db_control_regmap_utils.vh new file mode 100644 index 000000000..9df06e446 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/db_control_regmap_utils.vh @@ -0,0 +1,58 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: db_control_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // ATR_CONTROLLER_REGS : 0x0 (zbx_top_cpld.v) + // LO_CONTROL_REGS : 0x20 (zbx_top_cpld.v) + // LED_SETUP_REGS : 0x400 (zbx_top_cpld.v) + // SWITCH_SETUP_REGS : 0x1000 (zbx_top_cpld.v) + // DSA_SETUP_REGS : 0x2000 (zbx_top_cpld.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group DB_CONTROL_WINDOWS +//=============================================================================== + + // ATR_CONTROLLER_REGS Window (from zbx_top_cpld.v) + localparam ATR_CONTROLLER_REGS = 'h0; // Window Offset + localparam ATR_CONTROLLER_REGS_SIZE = 'h20; // size in bytes + + // LO_CONTROL_REGS Window (from zbx_top_cpld.v) + localparam LO_CONTROL_REGS = 'h20; // Window Offset + localparam LO_CONTROL_REGS_SIZE = 'h3E0; // size in bytes + + // LED_SETUP_REGS Window (from zbx_top_cpld.v) + localparam LED_SETUP_REGS = 'h400; // Window Offset + localparam LED_SETUP_REGS_SIZE = 'hC00; // size in bytes + + // SWITCH_SETUP_REGS Window (from zbx_top_cpld.v) + localparam SWITCH_SETUP_REGS = 'h1000; // Window Offset + localparam SWITCH_SETUP_REGS_SIZE = 'h1000; // size in bytes + + // DSA_SETUP_REGS Window (from zbx_top_cpld.v) + localparam DSA_SETUP_REGS = 'h2000; // Window Offset + localparam DSA_SETUP_REGS_SIZE = 'h3000; // size in bytes + +//=============================================================================== +// Register Group REGISTER_ENDPOINTS +//=============================================================================== + + // Enumerated type REGISTER_BLOCKS + localparam REGISTER_BLOCKS_SIZE = 5; + localparam ATR_REGISTERS = 'h0; // REGISTER_BLOCKS:ATR_REGISTERS + localparam LED_REGISTERS = 'h1; // REGISTER_BLOCKS:LED_REGISTERS + localparam LO_SPI = 'h2; // REGISTER_BLOCKS:LO_SPI + localparam SW_CONTROL = 'h3; // REGISTER_BLOCKS:SW_CONTROL + localparam DSA_CONTROL = 'h4; // REGISTER_BLOCKS:DSA_CONTROL diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/dsa_setup_regmap_utils.vh b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/dsa_setup_regmap_utils.vh new file mode 100644 index 000000000..54fc1f892 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/dsa_setup_regmap_utils.vh @@ -0,0 +1,162 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: dsa_setup_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // TX0_DSA_ATR : 0x0 (dsa_control.v) + // TX1_DSA_ATR : 0x400 (dsa_control.v) + // RX0_DSA_ATR : 0x800 (dsa_control.v) + // RX1_DSA_ATR : 0xC00 (dsa_control.v) + // TX0_DSA_TABLE_SELECT : 0x1000 (dsa_control.v) + // TX1_DSA_TABLE_SELECT : 0x1400 (dsa_control.v) + // RX0_DSA_TABLE_SELECT : 0x1800 (dsa_control.v) + // RX1_DSA_TABLE_SELECT : 0x1C00 (dsa_control.v) + // TX0_DSA_TABLE : 0x2000 (dsa_control.v) + // TX1_DSA_TABLE : 0x2400 (dsa_control.v) + // RX0_DSA_TABLE : 0x2800 (dsa_control.v) + // RX1_DSA_TABLE : 0x2C00 (dsa_control.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + + // DSA_TABLE_CONTROL Type (from dsa_control.v) + localparam DSA_TABLE_CONTROL_SIZE = 32; + localparam DSA_TABLE_CONTROL_MASK = 32'hFF; + localparam TABLE_INDEX_SIZE = 8; //DSA_TABLE_CONTROL:TABLE_INDEX + localparam TABLE_INDEX_MSB = 7; //DSA_TABLE_CONTROL:TABLE_INDEX + localparam TABLE_INDEX = 0; //DSA_TABLE_CONTROL:TABLE_INDEX + + // RX_DSA_CONTROL Type (from dsa_control.v) + localparam RX_DSA_CONTROL_SIZE = 32; + localparam RX_DSA_CONTROL_MASK = 32'hFFFF; + localparam RX_DSA1_SIZE = 4; //RX_DSA_CONTROL:RX_DSA1 + localparam RX_DSA1_MSB = 3; //RX_DSA_CONTROL:RX_DSA1 + localparam RX_DSA1 = 0; //RX_DSA_CONTROL:RX_DSA1 + localparam RX_DSA2_SIZE = 4; //RX_DSA_CONTROL:RX_DSA2 + localparam RX_DSA2_MSB = 7; //RX_DSA_CONTROL:RX_DSA2 + localparam RX_DSA2 = 4; //RX_DSA_CONTROL:RX_DSA2 + localparam RX_DSA3_A_SIZE = 4; //RX_DSA_CONTROL:RX_DSA3_A + localparam RX_DSA3_A_MSB = 11; //RX_DSA_CONTROL:RX_DSA3_A + localparam RX_DSA3_A = 8; //RX_DSA_CONTROL:RX_DSA3_A + localparam RX_DSA3_B_SIZE = 4; //RX_DSA_CONTROL:RX_DSA3_B + localparam RX_DSA3_B_MSB = 15; //RX_DSA_CONTROL:RX_DSA3_B + localparam RX_DSA3_B = 12; //RX_DSA_CONTROL:RX_DSA3_B + + // TX_DSA_CONTROL Type (from dsa_control.v) + localparam TX_DSA_CONTROL_SIZE = 32; + localparam TX_DSA_CONTROL_MASK = 32'h1F1F; + localparam TX_DSA1_SIZE = 5; //TX_DSA_CONTROL:TX_DSA1 + localparam TX_DSA1_MSB = 4; //TX_DSA_CONTROL:TX_DSA1 + localparam TX_DSA1 = 0; //TX_DSA_CONTROL:TX_DSA1 + localparam TX_DSA2_SIZE = 5; //TX_DSA_CONTROL:TX_DSA2 + localparam TX_DSA2_MSB = 12; //TX_DSA_CONTROL:TX_DSA2 + localparam TX_DSA2 = 8; //TX_DSA_CONTROL:TX_DSA2 + +//=============================================================================== +// Register Group DSA_SETUP_REGISTERS +//=============================================================================== + + // TX0_DSA_ATR Register (from dsa_control.v) + localparam TX0_DSA_ATR_COUNT = 256; // Number of elements in array + + // TX1_DSA_ATR Register (from dsa_control.v) + localparam TX1_DSA_ATR_COUNT = 256; // Number of elements in array + + // RX0_DSA_ATR Register (from dsa_control.v) + localparam RX0_DSA_ATR_COUNT = 256; // Number of elements in array + + // RX1_DSA_ATR Register (from dsa_control.v) + localparam RX1_DSA_ATR_COUNT = 256; // Number of elements in array + + // TX0_DSA_TABLE_SELECT Register (from dsa_control.v) + localparam TX0_DSA_TABLE_SELECT_COUNT = 256; // Number of elements in array + + // TX1_DSA_TABLE_SELECT Register (from dsa_control.v) + localparam TX1_DSA_TABLE_SELECT_COUNT = 256; // Number of elements in array + + // RX0_DSA_TABLE_SELECT Register (from dsa_control.v) + localparam RX0_DSA_TABLE_SELECT_COUNT = 256; // Number of elements in array + + // RX1_DSA_TABLE_SELECT Register (from dsa_control.v) + localparam RX1_DSA_TABLE_SELECT_COUNT = 256; // Number of elements in array + + // TX0_DSA_TABLE Register (from dsa_control.v) + localparam TX0_DSA_TABLE_COUNT = 256; // Number of elements in array + + // TX1_DSA_TABLE Register (from dsa_control.v) + localparam TX1_DSA_TABLE_COUNT = 256; // Number of elements in array + + // RX0_DSA_TABLE Register (from dsa_control.v) + localparam RX0_DSA_TABLE_COUNT = 256; // Number of elements in array + + // RX1_DSA_TABLE Register (from dsa_control.v) + localparam RX1_DSA_TABLE_COUNT = 256; // Number of elements in array + + // Return the offset of an element of register array TX0_DSA_ATR + function integer TX0_DSA_ATR (input integer i); + TX0_DSA_ATR = (i * 'h4) + 'h0; + endfunction + + // Return the offset of an element of register array TX1_DSA_ATR + function integer TX1_DSA_ATR (input integer i); + TX1_DSA_ATR = (i * 'h4) + 'h400; + endfunction + + // Return the offset of an element of register array RX0_DSA_ATR + function integer RX0_DSA_ATR (input integer i); + RX0_DSA_ATR = (i * 'h4) + 'h800; + endfunction + + // Return the offset of an element of register array RX1_DSA_ATR + function integer RX1_DSA_ATR (input integer i); + RX1_DSA_ATR = (i * 'h4) + 'hC00; + endfunction + + // Return the offset of an element of register array TX0_DSA_TABLE_SELECT + function integer TX0_DSA_TABLE_SELECT (input integer i); + TX0_DSA_TABLE_SELECT = (i * 'h4) + 'h1000; + endfunction + + // Return the offset of an element of register array TX1_DSA_TABLE_SELECT + function integer TX1_DSA_TABLE_SELECT (input integer i); + TX1_DSA_TABLE_SELECT = (i * 'h4) + 'h1400; + endfunction + + // Return the offset of an element of register array RX0_DSA_TABLE_SELECT + function integer RX0_DSA_TABLE_SELECT (input integer i); + RX0_DSA_TABLE_SELECT = (i * 'h4) + 'h1800; + endfunction + + // Return the offset of an element of register array RX1_DSA_TABLE_SELECT + function integer RX1_DSA_TABLE_SELECT (input integer i); + RX1_DSA_TABLE_SELECT = (i * 'h4) + 'h1C00; + endfunction + + // Return the offset of an element of register array TX0_DSA_TABLE + function integer TX0_DSA_TABLE (input integer i); + TX0_DSA_TABLE = (i * 'h4) + 'h2000; + endfunction + + // Return the offset of an element of register array TX1_DSA_TABLE + function integer TX1_DSA_TABLE (input integer i); + TX1_DSA_TABLE = (i * 'h4) + 'h2400; + endfunction + + // Return the offset of an element of register array RX0_DSA_TABLE + function integer RX0_DSA_TABLE (input integer i); + RX0_DSA_TABLE = (i * 'h4) + 'h2800; + endfunction + + // Return the offset of an element of register array RX1_DSA_TABLE + function integer RX1_DSA_TABLE (input integer i); + RX1_DSA_TABLE = (i * 'h4) + 'h2C00; + endfunction diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/gpio_regmap_utils.vh b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/gpio_regmap_utils.vh new file mode 100644 index 000000000..af9ca4e9a --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/gpio_regmap_utils.vh @@ -0,0 +1,31 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: gpio_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // BASE_WINDOW_GPIO : 0x0 (zbx_top_cpld.v) + // DB_CONTROL_WINDOW_GPIO : 0x1000 (zbx_top_cpld.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group GPIO_REGMAP_WINDOWS +//=============================================================================== + + // BASE_WINDOW_GPIO Window (from zbx_top_cpld.v) + localparam BASE_WINDOW_GPIO = 'h0; // Window Offset + localparam BASE_WINDOW_GPIO_SIZE = 'h20; // size in bytes + + // DB_CONTROL_WINDOW_GPIO Window (from zbx_top_cpld.v) + localparam DB_CONTROL_WINDOW_GPIO = 'h1000; // Window Offset + localparam DB_CONTROL_WINDOW_GPIO_SIZE = 'h5000; // size in bytes diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/led_setup_regmap_utils.vh b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/led_setup_regmap_utils.vh new file mode 100644 index 000000000..b482eca60 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/led_setup_regmap_utils.vh @@ -0,0 +1,46 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: led_setup_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // LED_CONTROL : 0x0 (led_control.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + + // LED_CONTROL_TYPE Type (from led_control.v) + localparam LED_CONTROL_TYPE_SIZE = 32; + localparam LED_CONTROL_TYPE_MASK = 32'h70007; + localparam CH0_RX2_LED_EN_SIZE = 1; //LED_CONTROL_TYPE:CH0_RX2_LED_EN + localparam CH0_RX2_LED_EN_MSB = 0; //LED_CONTROL_TYPE:CH0_RX2_LED_EN + localparam CH0_RX2_LED_EN = 0; //LED_CONTROL_TYPE:CH0_RX2_LED_EN + localparam CH0_TRX1_LED_EN_SIZE = 2; //LED_CONTROL_TYPE:CH0_TRX1_LED_EN + localparam CH0_TRX1_LED_EN_MSB = 2; //LED_CONTROL_TYPE:CH0_TRX1_LED_EN + localparam CH0_TRX1_LED_EN = 1; //LED_CONTROL_TYPE:CH0_TRX1_LED_EN + localparam CH1_RX2_LED_EN_SIZE = 1; //LED_CONTROL_TYPE:CH1_RX2_LED_EN + localparam CH1_RX2_LED_EN_MSB = 16; //LED_CONTROL_TYPE:CH1_RX2_LED_EN + localparam CH1_RX2_LED_EN = 16; //LED_CONTROL_TYPE:CH1_RX2_LED_EN + localparam CH1_TRX1_LED_EN_SIZE = 2; //LED_CONTROL_TYPE:CH1_TRX1_LED_EN + localparam CH1_TRX1_LED_EN_MSB = 18; //LED_CONTROL_TYPE:CH1_TRX1_LED_EN + localparam CH1_TRX1_LED_EN = 17; //LED_CONTROL_TYPE:CH1_TRX1_LED_EN + +//=============================================================================== +// Register Group LED_SETUP_REGISTERS +//=============================================================================== + + // LED_CONTROL Register (from led_control.v) + localparam LED_CONTROL_COUNT = 256; // Number of elements in array + + // Return the offset of an element of register array LED_CONTROL + function integer LED_CONTROL (input integer i); + LED_CONTROL = (i * 'h4) + 'h0; + endfunction diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/lo_control_regmap_utils.vh b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/lo_control_regmap_utils.vh new file mode 100644 index 000000000..3c1f27af6 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/lo_control_regmap_utils.vh @@ -0,0 +1,110 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: lo_control_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // LO_SPI_SETUP/LO_SPI_STATUS : 0x0 (lo_control.v, lo_control.v) + // LO_PULSE_SYNC : 0x4 (lo_control.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group LO_SPI_REGISTERS +//=============================================================================== + + // Enumerated type LO_CHIP_SELECT + localparam LO_CHIP_SELECT_SIZE = 8; + localparam TX0_LO1 = 'h0; // LO_CHIP_SELECT:TX0_LO1 + localparam TX0_LO2 = 'h1; // LO_CHIP_SELECT:TX0_LO2 + localparam TX1_LO1 = 'h2; // LO_CHIP_SELECT:TX1_LO1 + localparam TX1_LO2 = 'h3; // LO_CHIP_SELECT:TX1_LO2 + localparam RX0_LO1 = 'h4; // LO_CHIP_SELECT:RX0_LO1 + localparam RX0_LO2 = 'h5; // LO_CHIP_SELECT:RX0_LO2 + localparam RX1_LO1 = 'h6; // LO_CHIP_SELECT:RX1_LO1 + localparam RX1_LO2 = 'h7; // LO_CHIP_SELECT:RX1_LO2 + + // LO_SPI_SETUP Register (from lo_control.v) + localparam LO_SPI_SETUP = 'h0; // Register Offset + localparam LO_SPI_SETUP_SIZE = 32; // register width in bits + localparam LO_SPI_SETUP_MASK = 32'h17FFFFFF; + localparam LO_SPI_WT_DATA_SIZE = 16; //LO_SPI_SETUP:LO_SPI_WT_DATA + localparam LO_SPI_WT_DATA_MSB = 15; //LO_SPI_SETUP:LO_SPI_WT_DATA + localparam LO_SPI_WT_DATA = 0; //LO_SPI_SETUP:LO_SPI_WT_DATA + localparam LO_SPI_WT_ADDR_SIZE = 7; //LO_SPI_SETUP:LO_SPI_WT_ADDR + localparam LO_SPI_WT_ADDR_MSB = 22; //LO_SPI_SETUP:LO_SPI_WT_ADDR + localparam LO_SPI_WT_ADDR = 16; //LO_SPI_SETUP:LO_SPI_WT_ADDR + localparam LO_SPI_RD_SIZE = 1; //LO_SPI_SETUP:LO_SPI_RD + localparam LO_SPI_RD_MSB = 23; //LO_SPI_SETUP:LO_SPI_RD + localparam LO_SPI_RD = 23; //LO_SPI_SETUP:LO_SPI_RD + localparam LO_SELECT_SIZE = 3; //LO_SPI_SETUP:LO_SELECT + localparam LO_SELECT_MSB = 26; //LO_SPI_SETUP:LO_SELECT + localparam LO_SELECT = 24; //LO_SPI_SETUP:LO_SELECT + localparam LO_SPI_START_TRANSACTION_SIZE = 1; //LO_SPI_SETUP:LO_SPI_START_TRANSACTION + localparam LO_SPI_START_TRANSACTION_MSB = 28; //LO_SPI_SETUP:LO_SPI_START_TRANSACTION + localparam LO_SPI_START_TRANSACTION = 28; //LO_SPI_SETUP:LO_SPI_START_TRANSACTION + + // LO_SPI_STATUS Register (from lo_control.v) + localparam LO_SPI_STATUS = 'h0; // Register Offset + localparam LO_SPI_STATUS_SIZE = 32; // register width in bits + localparam LO_SPI_STATUS_MASK = 32'hC77FFFFF; + localparam LO_SPI_RD_DATA_SIZE = 16; //LO_SPI_STATUS:LO_SPI_RD_DATA + localparam LO_SPI_RD_DATA_MSB = 15; //LO_SPI_STATUS:LO_SPI_RD_DATA + localparam LO_SPI_RD_DATA = 0; //LO_SPI_STATUS:LO_SPI_RD_DATA + localparam LO_SPI_RD_ADDR_SIZE = 7; //LO_SPI_STATUS:LO_SPI_RD_ADDR + localparam LO_SPI_RD_ADDR_MSB = 22; //LO_SPI_STATUS:LO_SPI_RD_ADDR + localparam LO_SPI_RD_ADDR = 16; //LO_SPI_STATUS:LO_SPI_RD_ADDR + localparam LO_SELECT_STATUS_SIZE = 3; //LO_SPI_STATUS:LO_SELECT_STATUS + localparam LO_SELECT_STATUS_MSB = 26; //LO_SPI_STATUS:LO_SELECT_STATUS + localparam LO_SELECT_STATUS = 24; //LO_SPI_STATUS:LO_SELECT_STATUS + localparam LO_SPI_READY_SIZE = 1; //LO_SPI_STATUS:LO_SPI_READY + localparam LO_SPI_READY_MSB = 30; //LO_SPI_STATUS:LO_SPI_READY + localparam LO_SPI_READY = 30; //LO_SPI_STATUS:LO_SPI_READY + localparam LO_SPI_DATA_VALID_SIZE = 1; //LO_SPI_STATUS:LO_SPI_DATA_VALID + localparam LO_SPI_DATA_VALID_MSB = 31; //LO_SPI_STATUS:LO_SPI_DATA_VALID + localparam LO_SPI_DATA_VALID = 31; //LO_SPI_STATUS:LO_SPI_DATA_VALID + +//=============================================================================== +// Register Group LO_SYNC_REGS +//=============================================================================== + + // LO_PULSE_SYNC Register (from lo_control.v) + localparam LO_PULSE_SYNC = 'h4; // Register Offset + localparam LO_PULSE_SYNC_SIZE = 32; // register width in bits + localparam LO_PULSE_SYNC_MASK = 32'h1FF; + localparam PULSE_TX0_LO1_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_TX0_LO1_SYNC + localparam PULSE_TX0_LO1_SYNC_MSB = 0; //LO_PULSE_SYNC:PULSE_TX0_LO1_SYNC + localparam PULSE_TX0_LO1_SYNC = 0; //LO_PULSE_SYNC:PULSE_TX0_LO1_SYNC + localparam PULSE_TX0_LO2_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_TX0_LO2_SYNC + localparam PULSE_TX0_LO2_SYNC_MSB = 1; //LO_PULSE_SYNC:PULSE_TX0_LO2_SYNC + localparam PULSE_TX0_LO2_SYNC = 1; //LO_PULSE_SYNC:PULSE_TX0_LO2_SYNC + localparam PULSE_TX1_LO1_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_TX1_LO1_SYNC + localparam PULSE_TX1_LO1_SYNC_MSB = 2; //LO_PULSE_SYNC:PULSE_TX1_LO1_SYNC + localparam PULSE_TX1_LO1_SYNC = 2; //LO_PULSE_SYNC:PULSE_TX1_LO1_SYNC + localparam PULSE_TX1_LO2_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_TX1_LO2_SYNC + localparam PULSE_TX1_LO2_SYNC_MSB = 3; //LO_PULSE_SYNC:PULSE_TX1_LO2_SYNC + localparam PULSE_TX1_LO2_SYNC = 3; //LO_PULSE_SYNC:PULSE_TX1_LO2_SYNC + localparam PULSE_RX0_LO1_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_RX0_LO1_SYNC + localparam PULSE_RX0_LO1_SYNC_MSB = 4; //LO_PULSE_SYNC:PULSE_RX0_LO1_SYNC + localparam PULSE_RX0_LO1_SYNC = 4; //LO_PULSE_SYNC:PULSE_RX0_LO1_SYNC + localparam PULSE_RX0_LO2_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_RX0_LO2_SYNC + localparam PULSE_RX0_LO2_SYNC_MSB = 5; //LO_PULSE_SYNC:PULSE_RX0_LO2_SYNC + localparam PULSE_RX0_LO2_SYNC = 5; //LO_PULSE_SYNC:PULSE_RX0_LO2_SYNC + localparam PULSE_RX1_LO1_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_RX1_LO1_SYNC + localparam PULSE_RX1_LO1_SYNC_MSB = 6; //LO_PULSE_SYNC:PULSE_RX1_LO1_SYNC + localparam PULSE_RX1_LO1_SYNC = 6; //LO_PULSE_SYNC:PULSE_RX1_LO1_SYNC + localparam PULSE_RX1_LO2_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_RX1_LO2_SYNC + localparam PULSE_RX1_LO2_SYNC_MSB = 7; //LO_PULSE_SYNC:PULSE_RX1_LO2_SYNC + localparam PULSE_RX1_LO2_SYNC = 7; //LO_PULSE_SYNC:PULSE_RX1_LO2_SYNC + localparam BYPASS_SYNC_REGISTER_SIZE = 1; //LO_PULSE_SYNC:BYPASS_SYNC_REGISTER + localparam BYPASS_SYNC_REGISTER_MSB = 8; //LO_PULSE_SYNC:BYPASS_SYNC_REGISTER + localparam BYPASS_SYNC_REGISTER = 8; //LO_PULSE_SYNC:BYPASS_SYNC_REGISTER diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/power_regs_regmap_utils.vh b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/power_regs_regmap_utils.vh new file mode 100644 index 000000000..0d02b6391 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/power_regs_regmap_utils.vh @@ -0,0 +1,57 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: power_regs_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // RF_POWER_CONTROL : 0x0 (power_regs.v) + // RF_POWER_STATUS : 0x4 (power_regs.v) + // PRC_CONTROL : 0x8 (power_regs.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group POWER_REGS_REGISTERS +//=============================================================================== + + // RF_POWER_CONTROL Register (from power_regs.v) + localparam RF_POWER_CONTROL = 'h0; // Register Offset + localparam RF_POWER_CONTROL_SIZE = 32; // register width in bits + localparam RF_POWER_CONTROL_MASK = 32'h7; + localparam ENABLE_TX_7V0_SIZE = 1; //RF_POWER_CONTROL:ENABLE_TX_7V0 + localparam ENABLE_TX_7V0_MSB = 0; //RF_POWER_CONTROL:ENABLE_TX_7V0 + localparam ENABLE_TX_7V0 = 0; //RF_POWER_CONTROL:ENABLE_TX_7V0 + localparam ENABLE_RX_7V0_SIZE = 1; //RF_POWER_CONTROL:ENABLE_RX_7V0 + localparam ENABLE_RX_7V0_MSB = 1; //RF_POWER_CONTROL:ENABLE_RX_7V0 + localparam ENABLE_RX_7V0 = 1; //RF_POWER_CONTROL:ENABLE_RX_7V0 + localparam ENABLE_3V3_SIZE = 1; //RF_POWER_CONTROL:ENABLE_3v3 + localparam ENABLE_3V3_MSB = 2; //RF_POWER_CONTROL:ENABLE_3v3 + localparam ENABLE_3V3 = 2; //RF_POWER_CONTROL:ENABLE_3v3 + + // RF_POWER_STATUS Register (from power_regs.v) + localparam RF_POWER_STATUS = 'h4; // Register Offset + localparam RF_POWER_STATUS_SIZE = 32; // register width in bits + localparam RF_POWER_STATUS_MASK = 32'h3; + localparam P7V_A_STATUS_SIZE = 1; //RF_POWER_STATUS:P7V_A_STATUS + localparam P7V_A_STATUS_MSB = 0; //RF_POWER_STATUS:P7V_A_STATUS + localparam P7V_A_STATUS = 0; //RF_POWER_STATUS:P7V_A_STATUS + localparam P7V_B_STATUS_SIZE = 1; //RF_POWER_STATUS:P7V_B_STATUS + localparam P7V_B_STATUS_MSB = 1; //RF_POWER_STATUS:P7V_B_STATUS + localparam P7V_B_STATUS = 1; //RF_POWER_STATUS:P7V_B_STATUS + + // PRC_CONTROL Register (from power_regs.v) + localparam PRC_CONTROL = 'h8; // Register Offset + localparam PRC_CONTROL_SIZE = 32; // register width in bits + localparam PRC_CONTROL_MASK = 32'h1; + localparam PLL_REF_CLOCK_ENABLE_SIZE = 1; //PRC_CONTROL:PLL_REF_CLOCK_ENABLE + localparam PLL_REF_CLOCK_ENABLE_MSB = 0; //PRC_CONTROL:PLL_REF_CLOCK_ENABLE + localparam PLL_REF_CLOCK_ENABLE = 0; //PRC_CONTROL:PLL_REF_CLOCK_ENABLE diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/spi_regmap_utils.vh b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/spi_regmap_utils.vh new file mode 100644 index 000000000..04e2b6569 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/spi_regmap_utils.vh @@ -0,0 +1,41 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: spi_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // BASE_WINDOW_SPI : 0x0 (zbx_top_cpld.v) + // RECONFIG : 0x20 (zbx_top_cpld.v) + // POWER_REGS : 0x40 (zbx_top_cpld.v) + // DB_CONTROL_WINDOW_SPI : 0x1000 (zbx_top_cpld.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group SPI_REGMAP_WINDOWS +//=============================================================================== + + // BASE_WINDOW_SPI Window (from zbx_top_cpld.v) + localparam BASE_WINDOW_SPI = 'h0; // Window Offset + localparam BASE_WINDOW_SPI_SIZE = 'h20; // size in bytes + + // RECONFIG Window (from zbx_top_cpld.v) + localparam RECONFIG = 'h20; // Window Offset + localparam RECONFIG_SIZE = 'h20; // size in bytes + + // POWER_REGS Window (from zbx_top_cpld.v) + localparam POWER_REGS = 'h40; // Window Offset + localparam POWER_REGS_SIZE = 'h20; // size in bytes + + // DB_CONTROL_WINDOW_SPI Window (from zbx_top_cpld.v) + localparam DB_CONTROL_WINDOW_SPI = 'h1000; // Window Offset + localparam DB_CONTROL_WINDOW_SPI_SIZE = 'h5000; // size in bytes diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/switch_setup_regmap_utils.vh b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/switch_setup_regmap_utils.vh new file mode 100644 index 000000000..03fae8c9d --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/switch_setup_regmap_utils.vh @@ -0,0 +1,131 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: switch_setup_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // TX0_PATH_CONTROL : 0x0 (switch_control.v) + // TX1_PATH_CONTROL : 0x400 (switch_control.v) + // RX0_PATH_CONTROL : 0x800 (switch_control.v) + // RX1_PATH_CONTROL : 0xC00 (switch_control.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + + // RX_PATH_CONTROL Type (from switch_control.v) + localparam RX_PATH_CONTROL_SIZE = 32; + localparam RX_PATH_CONTROL_MASK = 32'h757D77; + localparam RX_SWITCH_1_SIZE = 2; //RX_PATH_CONTROL:RX_SWITCH_1 + localparam RX_SWITCH_1_MSB = 1; //RX_PATH_CONTROL:RX_SWITCH_1 + localparam RX_SWITCH_1 = 0; //RX_PATH_CONTROL:RX_SWITCH_1 + localparam RX_SWITCH_2_SIZE = 1; //RX_PATH_CONTROL:RX_SWITCH_2 + localparam RX_SWITCH_2_MSB = 2; //RX_PATH_CONTROL:RX_SWITCH_2 + localparam RX_SWITCH_2 = 2; //RX_PATH_CONTROL:RX_SWITCH_2 + localparam RX_SWITCH_3_SIZE = 3; //RX_PATH_CONTROL:RX_SWITCH_3 + localparam RX_SWITCH_3_MSB = 6; //RX_PATH_CONTROL:RX_SWITCH_3 + localparam RX_SWITCH_3 = 4; //RX_PATH_CONTROL:RX_SWITCH_3 + localparam RX_SWITCH_4_SIZE = 1; //RX_PATH_CONTROL:RX_SWITCH_4 + localparam RX_SWITCH_4_MSB = 8; //RX_PATH_CONTROL:RX_SWITCH_4 + localparam RX_SWITCH_4 = 8; //RX_PATH_CONTROL:RX_SWITCH_4 + localparam RX_SWITCH_5_SIZE = 2; //RX_PATH_CONTROL:RX_SWITCH_5 + localparam RX_SWITCH_5_MSB = 11; //RX_PATH_CONTROL:RX_SWITCH_5 + localparam RX_SWITCH_5 = 10; //RX_PATH_CONTROL:RX_SWITCH_5 + localparam RX_SWITCH_6_SIZE = 2; //RX_PATH_CONTROL:RX_SWITCH_6 + localparam RX_SWITCH_6_MSB = 13; //RX_PATH_CONTROL:RX_SWITCH_6 + localparam RX_SWITCH_6 = 12; //RX_PATH_CONTROL:RX_SWITCH_6 + localparam RX_SWITCH_7_8_SIZE = 1; //RX_PATH_CONTROL:RX_SWITCH_7_8 + localparam RX_SWITCH_7_8_MSB = 14; //RX_PATH_CONTROL:RX_SWITCH_7_8 + localparam RX_SWITCH_7_8 = 14; //RX_PATH_CONTROL:RX_SWITCH_7_8 + localparam RX_SWITCH_9_SIZE = 1; //RX_PATH_CONTROL:RX_SWITCH_9 + localparam RX_SWITCH_9_MSB = 16; //RX_PATH_CONTROL:RX_SWITCH_9 + localparam RX_SWITCH_9 = 16; //RX_PATH_CONTROL:RX_SWITCH_9 + localparam RX_SWITCH_10_SIZE = 1; //RX_PATH_CONTROL:RX_SWITCH_10 + localparam RX_SWITCH_10_MSB = 18; //RX_PATH_CONTROL:RX_SWITCH_10 + localparam RX_SWITCH_10 = 18; //RX_PATH_CONTROL:RX_SWITCH_10 + localparam RX_SWITCH_11_SIZE = 3; //RX_PATH_CONTROL:RX_SWITCH_11 + localparam RX_SWITCH_11_MSB = 22; //RX_PATH_CONTROL:RX_SWITCH_11 + localparam RX_SWITCH_11 = 20; //RX_PATH_CONTROL:RX_SWITCH_11 + + // TX_PATH_CONTROL Type (from switch_control.v) + localparam TX_PATH_CONTROL_SIZE = 32; + localparam TX_PATH_CONTROL_MASK = 32'h53F7FFD; + localparam TX_SWITCH_1_2_SIZE = 1; //TX_PATH_CONTROL:TX_SWITCH_1_2 + localparam TX_SWITCH_1_2_MSB = 0; //TX_PATH_CONTROL:TX_SWITCH_1_2 + localparam TX_SWITCH_1_2 = 0; //TX_PATH_CONTROL:TX_SWITCH_1_2 + localparam TX_SWITCH_3_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_3 + localparam TX_SWITCH_3_MSB = 3; //TX_PATH_CONTROL:TX_SWITCH_3 + localparam TX_SWITCH_3 = 2; //TX_PATH_CONTROL:TX_SWITCH_3 + localparam TX_SWITCH_4_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_4 + localparam TX_SWITCH_4_MSB = 5; //TX_PATH_CONTROL:TX_SWITCH_4 + localparam TX_SWITCH_4 = 4; //TX_PATH_CONTROL:TX_SWITCH_4 + localparam TX_SWITCH_5_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_5 + localparam TX_SWITCH_5_MSB = 7; //TX_PATH_CONTROL:TX_SWITCH_5 + localparam TX_SWITCH_5 = 6; //TX_PATH_CONTROL:TX_SWITCH_5 + localparam TX_SWITCH_6_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_6 + localparam TX_SWITCH_6_MSB = 9; //TX_PATH_CONTROL:TX_SWITCH_6 + localparam TX_SWITCH_6 = 8; //TX_PATH_CONTROL:TX_SWITCH_6 + localparam TX_SWITCH_7_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_7 + localparam TX_SWITCH_7_MSB = 11; //TX_PATH_CONTROL:TX_SWITCH_7 + localparam TX_SWITCH_7 = 10; //TX_PATH_CONTROL:TX_SWITCH_7 + localparam TX_SWITCH_8_SIZE = 3; //TX_PATH_CONTROL:TX_SWITCH_8 + localparam TX_SWITCH_8_MSB = 14; //TX_PATH_CONTROL:TX_SWITCH_8 + localparam TX_SWITCH_8 = 12; //TX_PATH_CONTROL:TX_SWITCH_8 + localparam TX_SWITCH_9_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_9 + localparam TX_SWITCH_9_MSB = 17; //TX_PATH_CONTROL:TX_SWITCH_9 + localparam TX_SWITCH_9 = 16; //TX_PATH_CONTROL:TX_SWITCH_9 + localparam TX_SWITCH_10_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_10 + localparam TX_SWITCH_10_MSB = 19; //TX_PATH_CONTROL:TX_SWITCH_10 + localparam TX_SWITCH_10 = 18; //TX_PATH_CONTROL:TX_SWITCH_10 + localparam TX_SWITCH_11_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_11 + localparam TX_SWITCH_11_MSB = 21; //TX_PATH_CONTROL:TX_SWITCH_11 + localparam TX_SWITCH_11 = 20; //TX_PATH_CONTROL:TX_SWITCH_11 + localparam TX_SWITCH_13_SIZE = 1; //TX_PATH_CONTROL:TX_SWITCH_13 + localparam TX_SWITCH_13_MSB = 24; //TX_PATH_CONTROL:TX_SWITCH_13 + localparam TX_SWITCH_13 = 24; //TX_PATH_CONTROL:TX_SWITCH_13 + localparam TX_SWITCH_14_SIZE = 1; //TX_PATH_CONTROL:TX_SWITCH_14 + localparam TX_SWITCH_14_MSB = 26; //TX_PATH_CONTROL:TX_SWITCH_14 + localparam TX_SWITCH_14 = 26; //TX_PATH_CONTROL:TX_SWITCH_14 + +//=============================================================================== +// Register Group SWITCH_SETUP_REGISTERS +//=============================================================================== + + // TX0_PATH_CONTROL Register (from switch_control.v) + localparam TX0_PATH_CONTROL_COUNT = 256; // Number of elements in array + + // TX1_PATH_CONTROL Register (from switch_control.v) + localparam TX1_PATH_CONTROL_COUNT = 256; // Number of elements in array + + // RX0_PATH_CONTROL Register (from switch_control.v) + localparam RX0_PATH_CONTROL_COUNT = 256; // Number of elements in array + + // RX1_PATH_CONTROL Register (from switch_control.v) + localparam RX1_PATH_CONTROL_COUNT = 256; // Number of elements in array + + // Return the offset of an element of register array TX0_PATH_CONTROL + function integer TX0_PATH_CONTROL (input integer i); + TX0_PATH_CONTROL = (i * 'h4) + 'h0; + endfunction + + // Return the offset of an element of register array TX1_PATH_CONTROL + function integer TX1_PATH_CONTROL (input integer i); + TX1_PATH_CONTROL = (i * 'h4) + 'h400; + endfunction + + // Return the offset of an element of register array RX0_PATH_CONTROL + function integer RX0_PATH_CONTROL (input integer i); + RX0_PATH_CONTROL = (i * 'h4) + 'h800; + endfunction + + // Return the offset of an element of register array RX1_PATH_CONTROL + function integer RX1_PATH_CONTROL (input integer i); + RX1_PATH_CONTROL = (i * 'h4) + 'hC00; + endfunction diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_cpld_core.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_cpld_core.v new file mode 100644 index 000000000..7a003ab40 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_cpld_core.v @@ -0,0 +1,463 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: zbx_cpld_core +// +// Description: +// Wrapper containing multiple register blocks, each in charge of controlling +// different features/signals across the daughterboard. Currently, the following +// blocks supported are: +// - Scratch/Signature/Revision(Basic Regs) register block +// - Led Control block +// - TX/RX path switch control block +// - TX/RX DSA control block +// - Local Oscillator SPI control block +// + +`default_nettype none + +module zbx_cpld_core #( + parameter [19:0] BASE_ADDRESS = 0 +) ( + ///////////////////////////////////////////////////////////////////////////// + // CtrlPort access + ///////////////////////////////////////////////////////////////////////////// + // Request + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + + // Response + output wire s_ctrlport_resp_ack, + output wire [ 1:0] s_ctrlport_resp_status, + output wire [31:0] s_ctrlport_resp_data, + + //reg clk domain + input wire ctrlport_clk, + input wire ctrlport_rst, + + ///////////////////////////////////////////////////////////////////////////// + // ATR controls + ///////////////////////////////////////////////////////////////////////////// + input wire [3:0] atr_fpga_state, + + ///////////////////////////////////////////////////////////////////////////// + //// LO SPI signals + ///////////////////////////////////////////////////////////////////////////// + // LO SPI for LMX2572 + input wire [7:0] lo_miso, + output wire [7:0] lo_csb, + + output wire lo_sclk, + output wire lo_mosi, + + ///////////////////////////////////////////////////////////////////////////// + //// LO SYNC signals + ///////////////////////////////////////////////////////////////////////////// + // Incoming SYNC + input wire mb_synth_sync, + + // SYNC for LMX2572 + output wire tx0_lo1_sync, + output wire tx0_lo2_sync, + output wire tx1_lo1_sync, + output wire tx1_lo2_sync, + output wire rx0_lo1_sync, + output wire rx0_lo2_sync, + output wire rx1_lo1_sync, + output wire rx1_lo2_sync, + + ///////////////////////////////////////////////////////////////////////////// + //// TX0 Controls + ///////////////////////////////////////////////////////////////////////////// + + //Tx0 Switch control + output wire tx0_sw1_sw2_ctrl, + output wire tx0_sw3_a, + output wire tx0_sw3_b, + output wire tx0_sw4_a, + output wire tx0_sw4_b, + output wire tx0_sw5_a, + output wire tx0_sw5_b, + output wire tx0_sw6_a, + output wire tx0_sw6_b, + output wire tx0_sw7_a, + output wire tx0_sw7_b, + output wire tx0_sw8_v1, + output wire tx0_sw8_v2, + output wire tx0_sw8_v3, + output wire tx0_sw9_a, + output wire tx0_sw9_b, + output wire tx0_sw10_a, + output wire tx0_sw10_b, + output wire tx0_sw11_a, + output wire tx0_sw11_b, + output wire tx0_sw13_v1, + output wire tx0_sw14_v1, + + //Tx0 DSA control + output wire [6:2] tx0_dsa1, + output wire [6:2] tx0_dsa2, + + ///////////////////////////////////////////////////////////////////////////// + //// TX1 Controls + ///////////////////////////////////////////////////////////////////////////// + + //Tx1 Switch control + output wire tx1_sw1_sw2_ctrl, + output wire tx1_sw3_a, + output wire tx1_sw3_b, + output wire tx1_sw4_a, + output wire tx1_sw4_b, + output wire tx1_sw5_a, + output wire tx1_sw5_b, + output wire tx1_sw6_a, + output wire tx1_sw6_b, + output wire tx1_sw7_a, + output wire tx1_sw7_b, + output wire tx1_sw8_v1, + output wire tx1_sw8_v2, + output wire tx1_sw8_v3, + output wire tx1_sw9_a, + output wire tx1_sw9_b, + output wire tx1_sw10_a, + output wire tx1_sw10_b, + output wire tx1_sw11_a, + output wire tx1_sw11_b, + output wire tx1_sw13_v1, + output wire tx1_sw14_v1, + + //Tx1 DSA control + output wire [6:2] tx1_dsa1, + output wire [6:2] tx1_dsa2, + + ///////////////////////////////////////////////////////////////////////////// + //// RX0 Controls + ///////////////////////////////////////////////////////////////////////////// + + //Rx0 Switch control + output wire rx0_sw1_a, + output wire rx0_sw1_b, + output wire rx0_sw2_a, + output wire rx0_sw3_v1, + output wire rx0_sw3_v2, + output wire rx0_sw3_v3, + output wire rx0_sw4_a, + output wire rx0_sw5_a, + output wire rx0_sw5_b, + output wire rx0_sw6_a, + output wire rx0_sw6_b, + output wire rx0_sw7_sw8_ctrl, + output wire rx0_sw9_v1, + output wire rx0_sw10_v1, + output wire rx0_sw11_v3, + output wire rx0_sw11_v2, + output wire rx0_sw11_v1, + + //Rx0 DSA control + output wire [1:4] rx0_dsa1_n, + output wire [1:4] rx0_dsa2_n, + output wire [1:4] rx0_dsa3_a_n, + output wire [1:4] rx0_dsa3_b_n, + + ///////////////////////////////////////////////////////////////////////////// + //// RX1 Controls + ///////////////////////////////////////////////////////////////////////////// + + //Rx1 Switch Control + output wire rx1_sw1_a, + output wire rx1_sw1_b, + output wire rx1_sw2_a, + output wire rx1_sw3_v1, + output wire rx1_sw3_v2, + output wire rx1_sw3_v3, + output wire rx1_sw4_a, + output wire rx1_sw5_a, + output wire rx1_sw5_b, + output wire rx1_sw6_a, + output wire rx1_sw6_b, + output wire rx1_sw7_sw8_ctrl, + output wire rx1_sw9_v1, + output wire rx1_sw10_v1, + output wire rx1_sw11_v3, + output wire rx1_sw11_v2, + output wire rx1_sw11_v1, + + //Rx1 DSA control + output wire [1:4] rx1_dsa1_n, + output wire [1:4] rx1_dsa2_n, + output wire [1:4] rx1_dsa3_a_n, + output wire [1:4] rx1_dsa3_b_n, + + ///////////////////////////////////////////////////////////////////////////// + // LED Control + ///////////////////////////////////////////////////////////////////////////// + + output wire ch0_rx2_led, + output wire ch0_tx_led, + output wire ch0_rx_led, + output wire ch1_rx2_led, + output wire ch1_tx_led, + output wire ch1_rx_led + +); + + `include "regmap/db_control_regmap_utils.vh" + `include "../../../../../lib/rfnoc/core/ctrlport.vh" + + // internal ATR configuration + wire [7:0] atr_config_rf0; + wire [7:0] atr_config_rf1; + wire [7:0] atr_config_dsa_rf0; + wire [7:0] atr_config_dsa_rf1; + + // Master Interfaces + wire [ REGISTER_BLOCKS_SIZE-1:0] ctrlport_req_wr; + wire [ REGISTER_BLOCKS_SIZE-1:0] ctrlport_req_rd; + wire [CTRLPORT_ADDR_W*REGISTER_BLOCKS_SIZE-1:0] ctrlport_req_addr; + wire [CTRLPORT_DATA_W*REGISTER_BLOCKS_SIZE-1:0] ctrlport_req_data; + wire [ REGISTER_BLOCKS_SIZE-1:0] ctrlport_resp_ack; + wire [ CTRLPORT_STS_W*REGISTER_BLOCKS_SIZE-1:0] ctrlport_resp_status; + wire [CTRLPORT_DATA_W*REGISTER_BLOCKS_SIZE-1:0] ctrlport_resp_data; + + ctrlport_splitter #( + .NUM_SLAVES(REGISTER_BLOCKS_SIZE) + ) ctrlport_splitter_i ( + .ctrlport_clk (ctrlport_clk), + .ctrlport_rst (ctrlport_rst), + .s_ctrlport_req_wr (s_ctrlport_req_wr), + .s_ctrlport_req_rd (s_ctrlport_req_rd), + .s_ctrlport_req_addr (s_ctrlport_req_addr), + .s_ctrlport_req_data (s_ctrlport_req_data), + .s_ctrlport_req_byte_en (), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack (s_ctrlport_resp_ack), + .s_ctrlport_resp_status (s_ctrlport_resp_status), + .s_ctrlport_resp_data (s_ctrlport_resp_data), + .m_ctrlport_req_wr (ctrlport_req_wr), + .m_ctrlport_req_rd (ctrlport_req_rd), + .m_ctrlport_req_addr (ctrlport_req_addr), + .m_ctrlport_req_data (ctrlport_req_data), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (ctrlport_resp_ack), + .m_ctrlport_resp_status (ctrlport_resp_status), + .m_ctrlport_resp_data (ctrlport_resp_data) + ); + + atr_controller #( + .BASE_ADDRESS (ATR_CONTROLLER_REGS + BASE_ADDRESS), + .SIZE_ADDRESS (ATR_CONTROLLER_REGS_SIZE) + ) atr_controller_i ( + .ctrlport_clk (ctrlport_clk), + .ctrlport_rst (ctrlport_rst), + .s_ctrlport_req_wr (ctrlport_req_wr[ATR_REGISTERS]), + .s_ctrlport_req_rd (ctrlport_req_rd[ATR_REGISTERS]), + .s_ctrlport_req_addr (ctrlport_req_addr[CTRLPORT_ADDR_W*(ATR_REGISTERS) +: CTRLPORT_ADDR_W]), + .s_ctrlport_req_data (ctrlport_req_data[CTRLPORT_DATA_W*(ATR_REGISTERS) +: CTRLPORT_DATA_W]), + .s_ctrlport_resp_ack (ctrlport_resp_ack[ATR_REGISTERS]), + .s_ctrlport_resp_status (ctrlport_resp_status[CTRLPORT_STS_W*(ATR_REGISTERS) +: CTRLPORT_STS_W]), + .s_ctrlport_resp_data (ctrlport_resp_data[CTRLPORT_DATA_W*(ATR_REGISTERS) +: CTRLPORT_DATA_W]), + .atr_fpga_state (atr_fpga_state), + .atr_config_dsa_rf0 (atr_config_dsa_rf0), + .atr_config_dsa_rf1 (atr_config_dsa_rf1), + .atr_config_rf0 (atr_config_rf0), + .atr_config_rf1 (atr_config_rf1) + ); + + switch_control #( + .BASE_ADDRESS (SWITCH_SETUP_REGS + BASE_ADDRESS), + .SIZE_ADDRESS (SWITCH_SETUP_REGS_SIZE) + ) switch_control_i ( + .ctrlport_clk (ctrlport_clk), + .ctrlport_rst (ctrlport_rst), + .s_ctrlport_req_wr (ctrlport_req_wr[SW_CONTROL]), + .s_ctrlport_req_rd (ctrlport_req_rd[SW_CONTROL]), + .s_ctrlport_req_addr (ctrlport_req_addr[CTRLPORT_ADDR_W*(SW_CONTROL) +: CTRLPORT_ADDR_W]), + .s_ctrlport_req_data (ctrlport_req_data[CTRLPORT_DATA_W*(SW_CONTROL) +: CTRLPORT_DATA_W]), + .s_ctrlport_resp_ack (ctrlport_resp_ack[SW_CONTROL]), + .s_ctrlport_resp_status (ctrlport_resp_status[CTRLPORT_STS_W*(SW_CONTROL) +: CTRLPORT_STS_W]), + .s_ctrlport_resp_data (ctrlport_resp_data[CTRLPORT_DATA_W*(SW_CONTROL) +: CTRLPORT_DATA_W]), + .atr_config_rf0 (atr_config_rf0), + .atr_config_rf1 (atr_config_rf1), + .tx0_sw1_sw2_ctrl (tx0_sw1_sw2_ctrl), + .tx0_sw3_a (tx0_sw3_a), + .tx0_sw3_b (tx0_sw3_b), + .tx0_sw4_a (tx0_sw4_a), + .tx0_sw4_b (tx0_sw4_b), + .tx0_sw5_a (tx0_sw5_a), + .tx0_sw5_b (tx0_sw5_b), + .tx0_sw6_a (tx0_sw6_a), + .tx0_sw6_b (tx0_sw6_b), + .tx0_sw7_a (tx0_sw7_a), + .tx0_sw7_b (tx0_sw7_b), + .tx0_sw8_v1 (tx0_sw8_v1), + .tx0_sw8_v2 (tx0_sw8_v2), + .tx0_sw8_v3 (tx0_sw8_v3), + .tx0_sw9_a (tx0_sw9_a), + .tx0_sw9_b (tx0_sw9_b), + .tx0_sw10_a (tx0_sw10_a), + .tx0_sw10_b (tx0_sw10_b), + .tx0_sw11_a (tx0_sw11_a), + .tx0_sw11_b (tx0_sw11_b), + .tx0_sw13_v1 (tx0_sw13_v1), + .tx0_sw14_v1 (tx0_sw14_v1), + .tx1_sw1_sw2_ctrl (tx1_sw1_sw2_ctrl), + .tx1_sw3_a (tx1_sw3_a), + .tx1_sw3_b (tx1_sw3_b), + .tx1_sw4_a (tx1_sw4_a), + .tx1_sw4_b (tx1_sw4_b), + .tx1_sw5_a (tx1_sw5_a), + .tx1_sw5_b (tx1_sw5_b), + .tx1_sw6_a (tx1_sw6_a), + .tx1_sw6_b (tx1_sw6_b), + .tx1_sw7_a (tx1_sw7_a), + .tx1_sw7_b (tx1_sw7_b), + .tx1_sw8_v1 (tx1_sw8_v1), + .tx1_sw8_v2 (tx1_sw8_v2), + .tx1_sw8_v3 (tx1_sw8_v3), + .tx1_sw9_a (tx1_sw9_a), + .tx1_sw9_b (tx1_sw9_b), + .tx1_sw10_a (tx1_sw10_a), + .tx1_sw10_b (tx1_sw10_b), + .tx1_sw11_a (tx1_sw11_a), + .tx1_sw11_b (tx1_sw11_b), + .tx1_sw13_v1 (tx1_sw13_v1), + .tx1_sw14_v1 (tx1_sw14_v1), + .rx0_sw1_a (rx0_sw1_a), + .rx0_sw1_b (rx0_sw1_b), + .rx0_sw2_a (rx0_sw2_a), + .rx0_sw3_v1 (rx0_sw3_v1), + .rx0_sw3_v2 (rx0_sw3_v2), + .rx0_sw3_v3 (rx0_sw3_v3), + .rx0_sw4_a (rx0_sw4_a), + .rx0_sw5_a (rx0_sw5_a), + .rx0_sw5_b (rx0_sw5_b), + .rx0_sw6_a (rx0_sw6_a), + .rx0_sw6_b (rx0_sw6_b), + .rx0_sw7_sw8_ctrl (rx0_sw7_sw8_ctrl), + .rx0_sw9_v1 (rx0_sw9_v1), + .rx0_sw10_v1 (rx0_sw10_v1), + .rx0_sw11_v3 (rx0_sw11_v3), + .rx0_sw11_v2 (rx0_sw11_v2), + .rx0_sw11_v1 (rx0_sw11_v1), + .rx1_sw1_a (rx1_sw1_a), + .rx1_sw1_b (rx1_sw1_b), + .rx1_sw2_a (rx1_sw2_a), + .rx1_sw3_v1 (rx1_sw3_v1), + .rx1_sw3_v2 (rx1_sw3_v2), + .rx1_sw3_v3 (rx1_sw3_v3), + .rx1_sw4_a (rx1_sw4_a), + .rx1_sw5_a (rx1_sw5_a), + .rx1_sw5_b (rx1_sw5_b), + .rx1_sw6_a (rx1_sw6_a), + .rx1_sw6_b (rx1_sw6_b), + .rx1_sw7_sw8_ctrl (rx1_sw7_sw8_ctrl), + .rx1_sw9_v1 (rx1_sw9_v1), + .rx1_sw10_v1 (rx1_sw10_v1), + .rx1_sw11_v3 (rx1_sw11_v3), + .rx1_sw11_v2 (rx1_sw11_v2), + .rx1_sw11_v1 (rx1_sw11_v1) + ); + + dsa_control #( + .BASE_ADDRESS (DSA_SETUP_REGS + BASE_ADDRESS), + .SIZE_ADDRESS (DSA_SETUP_REGS_SIZE) + ) dsa_control_i ( + .ctrlport_clk (ctrlport_clk), + .ctrlport_rst (ctrlport_rst), + .s_ctrlport_req_wr (ctrlport_req_wr[DSA_CONTROL]), + .s_ctrlport_req_rd (ctrlport_req_rd[DSA_CONTROL]), + .s_ctrlport_req_addr (ctrlport_req_addr[CTRLPORT_ADDR_W*(DSA_CONTROL) +:CTRLPORT_ADDR_W]), + .s_ctrlport_req_data (ctrlport_req_data[CTRLPORT_DATA_W*(DSA_CONTROL) +:CTRLPORT_DATA_W]), + .s_ctrlport_resp_ack (ctrlport_resp_ack[DSA_CONTROL]), + .s_ctrlport_resp_status (ctrlport_resp_status[CTRLPORT_STS_W*(DSA_CONTROL) +:CTRLPORT_STS_W]), + .s_ctrlport_resp_data (ctrlport_resp_data[CTRLPORT_DATA_W*(DSA_CONTROL) +:CTRLPORT_DATA_W]), + .atr_config_rf0 (atr_config_dsa_rf0), + .atr_config_rf1 (atr_config_dsa_rf1), + .tx0_dsa1 (tx0_dsa1), + .tx0_dsa2 (tx0_dsa2), + .tx1_dsa1 (tx1_dsa1), + .tx1_dsa2 (tx1_dsa2), + .rx0_dsa1_n (rx0_dsa1_n), + .rx0_dsa2_n (rx0_dsa2_n), + .rx0_dsa3_a_n (rx0_dsa3_a_n), + .rx0_dsa3_b_n (rx0_dsa3_b_n), + .rx1_dsa1_n (rx1_dsa1_n), + .rx1_dsa2_n (rx1_dsa2_n), + .rx1_dsa3_a_n (rx1_dsa3_a_n), + .rx1_dsa3_b_n (rx1_dsa3_b_n) + ); + + led_control #( + .BASE_ADDRESS (LED_SETUP_REGS + BASE_ADDRESS), + .SIZE_ADDRESS (LED_SETUP_REGS_SIZE) + ) led_control_i ( + .ctrlport_clk (ctrlport_clk), + .ctrlport_rst (ctrlport_rst), + .s_ctrlport_req_wr (ctrlport_req_wr[LED_REGISTERS]), + .s_ctrlport_req_rd (ctrlport_req_rd[LED_REGISTERS]), + .s_ctrlport_req_addr (ctrlport_req_addr[CTRLPORT_ADDR_W*(LED_REGISTERS) +: CTRLPORT_ADDR_W]), + .s_ctrlport_req_data (ctrlport_req_data[CTRLPORT_DATA_W*(LED_REGISTERS) +: CTRLPORT_DATA_W]), + .s_ctrlport_resp_ack (ctrlport_resp_ack[LED_REGISTERS]), + .s_ctrlport_resp_status (ctrlport_resp_status[CTRLPORT_STS_W*(LED_REGISTERS) +: CTRLPORT_STS_W]), + .s_ctrlport_resp_data (ctrlport_resp_data[CTRLPORT_DATA_W*(LED_REGISTERS) +: CTRLPORT_DATA_W]), + .ch0_rx2_led (ch0_rx2_led), + .ch0_tx_led (ch0_tx_led), + .ch0_rx_led (ch0_rx_led), + .ch1_rx2_led (ch1_rx2_led), + .ch1_tx_led (ch1_tx_led), + .ch1_rx_led (ch1_rx_led), + .atr_config_rf0 (atr_config_rf0), + .atr_config_rf1 (atr_config_rf1) + ); + + lo_control #( + .BASE_ADDRESS (LO_CONTROL_REGS + BASE_ADDRESS), + .SIZE_ADDRESS (LO_CONTROL_REGS_SIZE) + ) lo_control_i ( + .s_ctrlport_req_wr (ctrlport_req_wr[LO_SPI]), + .s_ctrlport_req_rd (ctrlport_req_rd[LO_SPI]), + .s_ctrlport_req_addr (ctrlport_req_addr[CTRLPORT_ADDR_W*(LO_SPI) +: CTRLPORT_ADDR_W]), + .s_ctrlport_req_data (ctrlport_req_data[CTRLPORT_DATA_W*(LO_SPI) +: CTRLPORT_DATA_W]), + .s_ctrlport_resp_ack (ctrlport_resp_ack[LO_SPI]), + .s_ctrlport_resp_status (ctrlport_resp_status[CTRLPORT_STS_W*(LO_SPI) +: CTRLPORT_STS_W]), + .s_ctrlport_resp_data (ctrlport_resp_data[CTRLPORT_DATA_W*(LO_SPI) +: CTRLPORT_DATA_W]), + .ctrlport_clk (ctrlport_clk), + .ctrlport_rst (ctrlport_rst), + .miso (lo_miso), + .ss (lo_csb), + .sclk (lo_sclk), + .mosi (lo_mosi), + .mb_synth_sync (mb_synth_sync), + .tx0_lo1_sync (tx0_lo1_sync), + .tx0_lo2_sync (tx0_lo2_sync), + .tx1_lo1_sync (tx1_lo1_sync), + .tx1_lo2_sync (tx1_lo2_sync), + .rx0_lo1_sync (rx0_lo1_sync), + .rx0_lo2_sync (rx0_lo2_sync), + .rx1_lo1_sync (rx1_lo1_sync), + .rx1_lo2_sync (rx1_lo2_sync)); + +endmodule + +`default_nettype wire + +//XmlParse xml_on +// +// +// +// +// +// +// +// +// +// +// +//XmlParse xml_off diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qpf b/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qpf new file mode 100644 index 000000000..972f9788d --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition +# Date created = 17:19:38 August 16, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.1" +DATE = "17:19:38 August 16, 2019" + +# Revisions + +PROJECT_REVISION = "zbx_top_cpld" diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qsf b/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qsf new file mode 100644 index 000000000..141cfa9a4 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qsf @@ -0,0 +1,889 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 15:10:13 February 02, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# TopCpld_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" + +# Device that is being used in production run +set_global_assignment -name DEVICE 10M04SAU324I7G + +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:10:13 FEBRUARY 02, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name GENERATE_SVF_FILE OFF +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +set_global_assignment -name NUM_PARALLEL_PROCESSORS 2 + +set_location_assignment PIN_P2 -to CTRL_REG_ARST +set_instance_assignment -name IO_STANDARD "1.8 V" -to CTRL_REG_ARST + +set_location_assignment PIN_M4 -to CTRL_REG_CLK +set_instance_assignment -name IO_STANDARD "1.8 V" -to CTRL_REG_CLK + +set_location_assignment PIN_N1 -to MB_CTRL_CS +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_CS + +set_location_assignment PIN_U2 -to MB_CTRL_MISO +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_MISO + +set_location_assignment PIN_N3 -to MB_CTRL_MOSI +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_MOSI + +set_location_assignment PIN_L3 -to MB_CTRL_SCK +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_SCK + +# The digital daughterboard connector has 120 pins [A-F][1-20]. +# The assignment below orders the CPLD IOs MSB first and connects it to the DB +# connection with increasing letter and increasing number. +# This results in: +# FPGA Bit 13 = A14 (trace: MB_FPGA_GPIO_A14) +# FPGA Bit 12 = A16 (trace: MB_FPGA_GPIO_A16) +# ... +# FPGA Bit 0 = C19 (trace: MB_FPGA_GPIO_C19) +set_location_assignment PIN_R2 -to MB_FPGA_GPIO[13] +# Workaround for missing pull down resistor: +# Use pull up and schmitt trigger to detect FPGA reload by line going high unexpectedly +set_instance_assignment -name IO_STANDARD "1.8 V SCHMITT TRIGGER" -to MB_FPGA_GPIO[13] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MB_FPGA_GPIO[13] + +set_location_assignment PIN_N4 -to MB_FPGA_GPIO[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[12] + +set_location_assignment PIN_K8 -to MB_FPGA_GPIO[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[11] + +set_location_assignment PIN_M2 -to MB_FPGA_GPIO[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[10] + +set_location_assignment PIN_M1 -to MB_FPGA_GPIO[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[9] + +set_location_assignment PIN_T1 -to MB_FPGA_GPIO[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[8] + +set_location_assignment PIN_U1 -to MB_FPGA_GPIO[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[7] + +set_location_assignment PIN_P1 -to MB_FPGA_GPIO[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[6] + +set_location_assignment PIN_R3 -to MB_FPGA_GPIO[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[5] + +set_location_assignment PIN_M7 -to MB_FPGA_GPIO[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[4] + +set_location_assignment PIN_T3 -to MB_FPGA_GPIO[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[3] + +set_location_assignment PIN_P4 -to MB_FPGA_GPIO[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[2] + +set_location_assignment PIN_L7 -to MB_FPGA_GPIO[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[1] + +set_location_assignment PIN_L8 -to MB_FPGA_GPIO[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[0] + +set_location_assignment PIN_M3 -to MB_SYNTH_SYNC +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_SYNTH_SYNC + +set_location_assignment PIN_G18 -to RX0_LO1_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_CSB + +set_location_assignment PIN_J18 -to RX0_LO1_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_SCK + +set_location_assignment PIN_F16 -to RX0_LO1_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_SDI + +set_location_assignment PIN_H17 -to RX0_LO1_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_SYNC + +set_location_assignment PIN_J12 -to RX0_LO2_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_CSB + +set_location_assignment PIN_J15 -to RX0_LO2_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_SCK + +set_location_assignment PIN_J16 -to RX0_LO2_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_SDI + +set_location_assignment PIN_K18 -to RX0_LO2_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_SYNC + +set_location_assignment PIN_F15 -to RX1_LO1_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_CSB + +set_location_assignment PIN_K17 -to RX1_LO1_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_SCK + +set_location_assignment PIN_G15 -to RX1_LO1_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_SDI + +set_location_assignment PIN_H18 -to RX1_LO1_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_SYNC + +set_location_assignment PIN_H15 -to RX1_LO2_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_CSB + +set_location_assignment PIN_L17 -to RX1_LO2_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_SCK + +set_location_assignment PIN_M17 -to RX1_LO2_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_SDI + +set_location_assignment PIN_L18 -to RX1_LO2_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_SYNC + +set_location_assignment PIN_C18 -to TX0_LO1_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_CSB + +set_location_assignment PIN_H12 -to TX0_LO1_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_SCK + +set_location_assignment PIN_D15 -to TX0_LO1_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_SDI + +set_location_assignment PIN_E15 -to TX0_LO1_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_SYNC + +set_location_assignment PIN_E18 -to TX0_LO2_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_CSB + +set_location_assignment PIN_G17 -to TX0_LO2_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_SCK + +set_location_assignment PIN_C17 -to TX0_LO2_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_SDI + +set_location_assignment PIN_D17 -to TX0_LO2_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_SYNC + +set_location_assignment PIN_G11 -to TX1_LO1_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_CSB + +set_location_assignment PIN_D16 -to TX1_LO1_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_SCK + +set_location_assignment PIN_E16 -to TX1_LO1_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_SDI + +set_location_assignment PIN_B18 -to TX1_LO1_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_SYNC + +set_location_assignment PIN_E17 -to TX1_LO2_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_CSB + +set_location_assignment PIN_G16 -to TX1_LO2_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_SCK + +set_location_assignment PIN_D18 -to TX1_LO2_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_SDI + +set_location_assignment PIN_H16 -to TX1_LO2_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_SYNC + +set_location_assignment PIN_M12 -to RX0_DSA3_A_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[1] + +set_location_assignment PIN_T16 -to RX0_DSA3_A_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[2] + +set_location_assignment PIN_N15 -to RX0_DSA3_A_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[3] + +set_location_assignment PIN_M15 -to RX0_DSA3_A_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[4] + +set_location_assignment PIN_L12 -to RX1_DSA3_A_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[1] + +set_location_assignment PIN_L15 -to RX1_DSA3_A_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[2] + +set_location_assignment PIN_L16 -to RX1_DSA3_A_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[3] + +set_location_assignment PIN_K15 -to RX1_DSA3_A_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[4] + +set_location_assignment PIN_R18 -to P7V_PG_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_PG_A + +set_location_assignment PIN_N18 -to P7V_PG_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_PG_B + +set_location_assignment PIN_K12 -to CPLD_REFCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CPLD_REFCLK + +set_location_assignment PIN_R16 -to P3D3VA_ENABLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P3D3VA_ENABLE +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to P3D3VA_ENABLE + +set_location_assignment PIN_P16 -to P7V_ENABLE_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_ENABLE_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to P7V_ENABLE_A + +set_location_assignment PIN_R17 -to P7V_ENABLE_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_ENABLE_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to P7V_ENABLE_B + +set_location_assignment PIN_H6 -to RX0_DSA1_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[1] + +set_location_assignment PIN_J3 -to RX0_DSA1_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[2] + +set_location_assignment PIN_J4 -to RX0_DSA1_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[3] + +set_location_assignment PIN_K4 -to RX0_DSA1_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[4] + +set_location_assignment PIN_T4 -to RX0_DSA2_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[1] + +set_location_assignment PIN_N8 -to RX0_DSA2_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[2] + +set_location_assignment PIN_T5 -to RX0_DSA2_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[3] + +set_location_assignment PIN_T6 -to RX0_DSA2_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[4] + +set_location_assignment PIN_V2 -to RX0_DSA3_B_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[1] + +set_location_assignment PIN_U5 -to RX0_DSA3_B_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[2] + +set_location_assignment PIN_V5 -to RX0_DSA3_B_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[3] + +set_location_assignment PIN_V6 -to RX0_DSA3_B_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[4] + +set_location_assignment PIN_T15 -to RX0_LO1_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_LO1_MUXOUT + +set_location_assignment PIN_T14 -to RX0_LO2_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_LO2_MUXOUT + +set_location_assignment PIN_U8 -to RX0_SW1_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW1_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW1_A + +set_location_assignment PIN_V8 -to RX0_SW1_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW1_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW1_B + +set_location_assignment PIN_T12 -to RX0_SW10_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW10_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW10_V1 + +set_location_assignment PIN_P10 -to RX0_SW11_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW11_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW11_V1 + +set_location_assignment PIN_U17 -to RX0_SW11_V2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW11_V2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW11_V2 + +set_location_assignment PIN_F5 -to RX0_SW11_V3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW11_V3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW11_V3 + +set_location_assignment PIN_R8 -to RX0_SW2_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW2_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW2_A + +set_location_assignment PIN_U15 -to RX0_SW3_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW3_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW3_V1 + +set_location_assignment PIN_P14 -to RX0_SW3_V2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW3_V2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW3_V2 + +set_location_assignment PIN_T11 -to RX0_SW3_V3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW3_V3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW3_V3 + +set_location_assignment PIN_L11 -to RX0_SW4_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW4_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW4_A + +set_location_assignment PIN_P5 -to RX0_SW5_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW5_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW5_A + +set_location_assignment PIN_N7 -to RX0_SW5_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW5_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW5_B + +set_location_assignment PIN_U13 -to RX0_SW6_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW6_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW6_A + +set_location_assignment PIN_V10 -to RX0_SW6_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW6_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW6_B + +set_location_assignment PIN_D13 -to RX0_SW7_SW8_CTRL +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW7_SW8_CTRL +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW7_SW8_CTRL + +set_location_assignment PIN_R15 -to RX0_SW9_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW9_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW9_V1 + +set_location_assignment PIN_R9 -to RX1_DSA1_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[1] + +set_location_assignment PIN_P6 -to RX1_DSA1_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[2] + +set_location_assignment PIN_R6 -to RX1_DSA1_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[3] + +set_location_assignment PIN_M10 -to RX1_DSA1_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[4] + +set_location_assignment PIN_T7 -to RX1_DSA2_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[1] + +set_location_assignment PIN_M9 -to RX1_DSA2_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[2] + +set_location_assignment PIN_R5 -to RX1_DSA2_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[3] + +set_location_assignment PIN_R4 -to RX1_DSA2_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[4] + +set_location_assignment PIN_U6 -to RX1_DSA3_B_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[1] + +set_location_assignment PIN_V4 -to RX1_DSA3_B_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[2] + +set_location_assignment PIN_V3 -to RX1_DSA3_B_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[3] + +set_location_assignment PIN_U3 -to RX1_DSA3_B_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[4] + +set_location_assignment PIN_P15 -to RX1_LO1_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_LO1_MUXOUT + +set_location_assignment PIN_R14 -to RX1_LO2_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_LO2_MUXOUT + +set_location_assignment PIN_D7 -to RX1_SW1_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW1_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW1_A + +set_location_assignment PIN_D8 -to RX1_SW1_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW1_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW1_B + +set_location_assignment PIN_R12 -to RX1_SW10_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW10_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW10_V1 + +set_location_assignment PIN_V17 -to RX1_SW11_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW11_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW11_V1 + +set_location_assignment PIN_R10 -to RX1_SW11_V2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW11_V2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW11_V2 + +set_location_assignment PIN_F2 -to RX1_SW11_V3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW11_V3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW11_V3 + +set_location_assignment PIN_T8 -to RX1_SW2_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW2_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW2_A + +set_location_assignment PIN_T10 -to RX1_SW3_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW3_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW3_V1 + +set_location_assignment PIN_V16 -to RX1_SW3_V2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW3_V2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW3_V2 + +set_location_assignment PIN_U16 -to RX1_SW3_V3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW3_V3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW3_V3 + +set_location_assignment PIN_K7 -to RX1_SW4_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW4_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW4_A + +set_location_assignment PIN_M11 -to RX1_SW5_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW5_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW5_A + +set_location_assignment PIN_M8 -to RX1_SW5_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW5_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW5_B + +set_location_assignment PIN_U9 -to RX1_SW6_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW6_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW6_A + +set_location_assignment PIN_V9 -to RX1_SW6_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW6_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW6_B + +set_location_assignment PIN_E14 -to RX1_SW7_SW8_CTRL +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW7_SW8_CTRL +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW7_SW8_CTRL + +set_location_assignment PIN_N14 -to RX1_SW9_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW9_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW9_V1 + +set_location_assignment PIN_C13 -to TX0_DSA1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[2] + +set_location_assignment PIN_D14 -to TX0_DSA1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[3] + +set_location_assignment PIN_A15 -to TX0_DSA1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[4] + +set_location_assignment PIN_B14 -to TX0_DSA1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[5] + +set_location_assignment PIN_C16 -to TX0_DSA1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[6] + +set_location_assignment PIN_A2 -to TX0_DSA2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[2] + +set_location_assignment PIN_C5 -to TX0_DSA2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[3] + +set_location_assignment PIN_C4 -to TX0_DSA2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[4] + +set_location_assignment PIN_D10 -to TX0_DSA2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[5] + +set_location_assignment PIN_B2 -to TX0_DSA2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[6] + +set_location_assignment PIN_A8 -to TX0_LO1_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_LO1_MUXOUT + +set_location_assignment PIN_F12 -to TX0_LO2_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_LO2_MUXOUT + +set_location_assignment PIN_A14 -to TX0_SW1_SW2_CTRL +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW1_SW2_CTRL +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW1_SW2_CTRL + +set_location_assignment PIN_U7 -to TX0_SW10_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW10_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW10_A + +set_location_assignment PIN_V7 -to TX0_SW10_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW10_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW10_B + +set_location_assignment PIN_V15 -to TX0_SW11_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW11_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW11_A + +set_location_assignment PIN_V14 -to TX0_SW11_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW11_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW11_B + +set_location_assignment PIN_F11 -to TX0_SW13_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW13_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW13_V1 + +set_location_assignment PIN_B9 -to TX0_SW14_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW14_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW14_V1 + +set_location_assignment PIN_E4 -to TX0_SW3_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW3_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW3_A + +set_location_assignment PIN_D1 -to TX0_SW3_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW3_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW3_B + +set_location_assignment PIN_J1 -to TX0_SW4_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW4_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW4_A + +set_location_assignment PIN_H2 -to TX0_SW4_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW4_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW4_B + +set_location_assignment PIN_K3 -to TX0_SW5_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW5_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW5_A + +set_location_assignment PIN_L2 -to TX0_SW5_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW5_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW5_B + +set_location_assignment PIN_G1 -to TX0_SW6_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW6_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW6_A + +set_location_assignment PIN_G3 -to TX0_SW6_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW6_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW6_B + +set_location_assignment PIN_C1 -to TX0_SW7_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW7_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW7_A + +set_location_assignment PIN_D4 -to TX0_SW7_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW7_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW7_B + +set_location_assignment PIN_C8 -to TX0_SW8_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW8_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW8_V1 + +set_location_assignment PIN_C6 -to TX0_SW8_V2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW8_V2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW8_V2 + +set_location_assignment PIN_B4 -to TX0_SW8_V3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW8_V3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW8_V3 + +set_location_assignment PIN_A4 -to TX0_SW9_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW9_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW9_A + +set_location_assignment PIN_A3 -to TX0_SW9_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW9_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW9_B + +set_location_assignment PIN_C14 -to TX1_DSA1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[2] + +set_location_assignment PIN_C15 -to TX1_DSA1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[3] + +set_location_assignment PIN_B17 -to TX1_DSA1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[4] + +set_location_assignment PIN_A17 -to TX1_DSA1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[5] + +set_location_assignment PIN_A16 -to TX1_DSA1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[6] + +set_location_assignment PIN_J6 -to TX1_DSA2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[2] + +set_location_assignment PIN_F10 -to TX1_DSA2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[3] + +set_location_assignment PIN_G10 -to TX1_DSA2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[4] + +set_location_assignment PIN_L10 -to TX1_DSA2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[5] + +set_location_assignment PIN_D9 -to TX1_DSA2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[6] + +set_location_assignment PIN_C9 -to TX1_LO1_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_LO1_MUXOUT + +set_location_assignment PIN_B13 -to TX1_LO2_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_LO2_MUXOUT + +set_location_assignment PIN_B16 -to TX1_SW1_SW2_CTRL +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW1_SW2_CTRL +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW1_SW2_CTRL + +set_location_assignment PIN_G7 -to TX1_SW10_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW10_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW10_A + +set_location_assignment PIN_D5 -to TX1_SW10_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW10_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW10_B + +set_location_assignment PIN_D6 -to TX1_SW11_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW11_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW11_A + +set_location_assignment PIN_E5 -to TX1_SW11_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW11_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW11_B + +set_location_assignment PIN_A9 -to TX1_SW13_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW13_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW13_V1 + +set_location_assignment PIN_B8 -to TX1_SW14_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW14_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW14_V1 + +set_location_assignment PIN_E1 -to TX1_SW3_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW3_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW3_A + +set_location_assignment PIN_D2 -to TX1_SW3_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW3_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW3_B + +set_location_assignment PIN_J2 -to TX1_SW4_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW4_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW4_A + +set_location_assignment PIN_K1 -to TX1_SW4_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW4_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW4_B + +set_location_assignment PIN_L1 -to TX1_SW5_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW5_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW5_A + +set_location_assignment PIN_K2 -to TX1_SW5_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW5_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW5_B + +set_location_assignment PIN_H1 -to TX1_SW6_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW6_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW6_A + +set_location_assignment PIN_F1 -to TX1_SW6_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW6_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW6_B + +set_location_assignment PIN_B1 -to TX1_SW7_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW7_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW7_A + +set_location_assignment PIN_C2 -to TX1_SW7_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW7_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW7_B + +set_location_assignment PIN_B7 -to TX1_SW8_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW8_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW8_V1 + +set_location_assignment PIN_C7 -to TX1_SW8_V2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW8_V2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW8_V2 + +set_location_assignment PIN_A6 -to TX1_SW8_V3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW8_V3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW8_V3 + +set_location_assignment PIN_B3 -to TX1_SW9_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW9_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW9_A + +set_location_assignment PIN_B5 -to TX1_SW9_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW9_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW9_B + +set_location_assignment PIN_N11 -to CH0_RX2_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH0_RX2_LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH0_RX2_LED + +set_location_assignment PIN_T13 -to CH0_RX_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH0_RX_LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH0_RX_LED + +set_location_assignment PIN_R13 -to CH0_TX_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH0_TX_LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH0_TX_LED + +set_location_assignment PIN_A10 -to CH1_RX2_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_RX2_LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_RX2_LED + +set_location_assignment PIN_H7 -to CH1_RX_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_RX_LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_RX_LED + +set_location_assignment PIN_G6 -to CH1_TX_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_TX_LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_TX_LED + +# The zbx_top_cpld.v has to stand first as it contains a define statement. +set_global_assignment -name VERILOG_FILE ./zbx_top_cpld.v +set_global_assignment -name VERILOG_FILE ../../../../../lib/rfnoc/utils/ctrlport_decoder.v +set_global_assignment -name SDC_FILE ../../../constraints/timing/shared_constants.sdc +set_global_assignment -name SDC_FILE ../../../cpld/db_spi_shared_constants.sdc +set_global_assignment -name SDC_FILE zbx_top_cpld.sdc +set_global_assignment -name VERILOG_FILE ./../../../../../lib/control/synchronizer_impl.v +set_global_assignment -name VERILOG_FILE ./../../../../../lib/control/synchronizer.v +set_global_assignment -name VERILOG_FILE ./../../../../../lib/control/reset_sync.v +set_global_assignment -name VERILOG_FILE ./../../../../../lib/rfnoc/utils/ctrlport_splitter.v +set_global_assignment -name VERILOG_FILE ./../../../cpld/spi_slave.v +set_global_assignment -name VERILOG_FILE ./../../../cpld/spi_slave_to_ctrlport_master.v +set_global_assignment -name VERILOG_FILE ./register_endpoints/basic_regs.v +set_global_assignment -name VERILOG_FILE ./register_endpoints/power_regs.v +set_global_assignment -name VERILOG_FILE ./register_endpoints/switch_control.v +set_global_assignment -name VERILOG_FILE ./register_endpoints/dsa_control.v +set_global_assignment -name VERILOG_FILE ./register_endpoints/led_control.v +set_global_assignment -name VERILOG_FILE ./../../../../../lib/wb_spi/rtl/verilog/spi_top.v +set_global_assignment -name VERILOG_FILE ./../../../../../lib/wb_spi/rtl/verilog/spi_clgen.v +set_global_assignment -name VERILOG_FILE ./../../../../../lib/wb_spi/rtl/verilog/spi_shift.v +set_global_assignment -name VERILOG_FILE ./register_endpoints/lo_control.v +set_global_assignment -name VERILOG_FILE ./zbx_cpld_core.v +set_global_assignment -name VERILOG_FILE ../../ctrlport_byte_deserializer.v +set_global_assignment -name VERILOG_FILE ../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v +set_global_assignment -name VERILOG_FILE ../../../cpld/reconfig_engine.v +set_global_assignment -name VERILOG_FILE ../../../../../lib/rfnoc/utils/ctrlport_combiner.v +set_global_assignment -name VERILOG_FILE register_endpoints/atr_controller.v +set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../lib/control/ram_2port_impl.vh +set_global_assignment -name VERILOG_FILE ../../../../../lib/control/ram_2port.v +set_global_assignment -name VERILOG_FILE ../../../../../lib/control/handshake.v +set_global_assignment -name VERILOG_FILE ../../../../../lib/control/pulse_synchronizer.v +set_global_assignment -name VERILOG_FILE ./ctrlport_window.v + +set_global_assignment -name QSYS_FILE ip/flash/on_chip_flash.qsys +set_global_assignment -name QSYS_FILE ip/osc/osc.qsys +set_global_assignment -name QSYS_FILE ../../../cpld/ip/clkctrl/clkctrl.qsys +set_global_assignment -name SOURCE_FILE db/zbx_top_cpld.cmp.rdb + +set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/tx1_path_defaults.hex +set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/tx0_path_defaults.hex +set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/tx_dsa_defaults.hex +set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/rx1_path_defaults.hex +set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/rx0_path_defaults.hex +set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/rx_dsa_defaults.hex + +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE WITH ERAM" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" + +set_global_assignment -name TOP_LEVEL_ENTITY zbx_top_cpld + + + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.sdc b/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.sdc new file mode 100644 index 000000000..086efb3c0 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.sdc @@ -0,0 +1,374 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Description: +# Timing constraints for the ZBX daughterboard CPLD. +# + +set_time_format -unit ns -decimal_places 3 + +##################################################################### +# Main Clocks +##################################################################### + +## Input clocks. +# Reliable clock: 50.0 MHz +set reliable_clock_period 20.000 +create_clock -name ctrlport_clk -period $reliable_clock_period [get_ports CTRL_REG_CLK] + +# PLL reference clock: 64 MHz (maximum) +# Rounded down from 15.625 as this number divided by 2 has 4 decimal digits +# which produces a warning. +set prc_clock_period 15.62 +create_clock -name pll_ref_clk -period $prc_clock_period [get_ports CPLD_REFCLK] + +# Create clock for the ControlPort SPI interface. +# SPI clock is divided further down but only 3 clock cycles for processing are +# available for this SPI slave +set ctrl_sclk_period [expr {3 * $prc_clock_period}] +create_clock -name mb_ctrl_sck -period $ctrl_sclk_period [get_ports MB_CTRL_SCK] + +# Oscillator clock regenerated as the IP constraint for the "int_osc_clk" is not +# yet available when processing this file. +create_generated_clock -name osc_clk \ + -source [get_pins -compatibility_mode {*oscillator_dut|clkout}] \ + [get_pins {int_osc_clk_ctrl_i|altclkctrl_0|clkctrl_altclkctrl_0_sub_component|clkctrl1|outclk}] + +# required to get rid of Warning (332056): PLL cross checking found inconsistent +# PLL clock settings +derive_pll_clocks + +##################################################################### +# Synthesizer sync interfaces +##################################################################### +# From MB FPGA +# +# ADClk_min and ADClk_max come from the ADCLK944 datasheet. +# The CPLD receives it's clock from ADCLK944 U40. U40 also supplies a +# clock to ADCLK944 U67, which drives clocks to the LO's. Therefore, +# the clock arrives at the LO slightly later than it arrives at the +# CPLD. +# +# The clock input to the CPLD is delayed by one ADCLK944 (U40) compared +# to the input clock to the FPGA. +# +# ADClk_skew is also from the ADCLK944 datasheet,and is the maximum +# difference between outputs in a single ADCLK944, and represents the +# difference in arrival times of the clock at the +# CPLD input and the input to U67. +set ADClk_skew 0.015 +set ADClk_min 0.070 +set ADClk_max 0.130 + +# The longest SYNTH_SYNC trace going into a DB corresponds to DBO +# Longest trace | Trace length | Trace delay +# (multiple paths)| 7.909 in | 1.36 ns +# MB_SYNTH_SYNC, DB0_SYNTH_SYNC_fs, DB0_SYNTH_SYNC +# - for maximum propagation delay, this number will be rounded up +set synth_board_delay 1.4 +# - for minimum propagation delay, we will consider a time of 0. + +# Constrain the sync inputs to the CPLD driven from the MB FPGA. +# synth_sync min/max output delays are defined in +# fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc + +# Assume worst case as data being generated late and receiving an early clock: +# - Max FPGA TCO +# - Max FPGA clock propagation delay and minimum CPLD clock propagation delay +# - Max data propagation delay +# - Minimum delay on MC100EPT23 clock buffer +set_input_delay -clock [get_clocks pll_ref_clk] \ + -max [expr {$prc_clock_period - $synth_sync_setup_requirement \ + + $fpga_prc_clock_prop_max - $db_cpld_prc_clock_prop_min \ + + $synth_board_delay \ + - $clock_translate_min }] \ + [get_ports MB_SYNTH_SYNC] + +# Assume worst case as data being generated early and receiving an late clock: +# - Min FPGA TCO +# - Min data propagation delay (0) +# - Min FPGA clock propagation delay and maximum CPLD clock propagation delay +# - Maximum delay on MC100EPT23 clock buffer +set_input_delay -clock [get_clocks pll_ref_clk] \ + -min [expr {$synth_sync_hold_requirement \ + - 0 \ + - $fpga_prc_clock_prop_min + $db_cpld_prc_clock_prop_max \ + + $clock_translate_max}] \ + [get_ports MB_SYNTH_SYNC] + +set rx_sync_ports {RX0_LO1_SYNC RX0_LO2_SYNC RX1_LO1_SYNC RX1_LO2_SYNC} +set tx_sync_ports {TX0_LO1_SYNC TX0_LO2_SYNC TX1_LO1_SYNC TX1_LO2_SYNC} +set sync_ports [get_ports [concat $rx_sync_ports $tx_sync_ports]] + +# lo_setup and lo_hold are the constraints from the lmx2572 datasheet +# for the LO's SYNC input. +set lo_setup 2.5 +set lo_hold -2.0 +# The delay through an extra ADCLk944 reduces the maximum output delay, +# but the skew of the root ADCLK944 (U40) might work against you, so the +# skew increases the output delay. +set_output_delay -clock [get_clocks pll_ref_clk]\ + -max [expr {$lo_setup - $ADClk_min + $ADClk_skew}] \ + $sync_ports + +# The LO's hold requirement is modeled as a negative output delay. The +# extra ADClk delay and the ADCLK skew can both work against you, so +# they are both added to increase the minimum output delay. +set_output_delay -clock [get_clocks pll_ref_clk]\ + -min [expr {-$lo_hold + $ADClk_max + $ADClk_skew}] \ + $sync_ports + +##################################################################### +# Timing exceptions +##################################################################### +## synchronizers +set_false_path -to [get_registers *synchronizer_false_path\|value\[0\]\[*\]] + +## PS SPI slave +# sclk data to ctrlport_clk +set_false_path -from [get_registers *spi_slave_async\|received_word\[*\]] \ + -to [get_registers *spi_slave_async\|data_out\[*\]] + +# PLL driven data to sclk +set_false_path -from [get_registers *spi_slave_async\|transmit_word\[*\]] \ + -to [get_registers *spi_slave_async\|transmit_bits\[*\]] + +##################################################################### +# MB CPLD <-> DP CPLD CTRL SPI interface +##################################################################### +# The timing constants of the MB CPLD are defined in +# fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc + +# The longest trace on the PL SPI interface is (assuming 170.0 ps/in) +# Longest trace | Trace length | Trace delay +# DB0_SCK | 6.669 in | 1.134 ns +set ctrl_spi_board_delay 1.134 + +# MB an dB CPLD both use PLL reference clock from a common clock chip. +# The traces from that clock chip to the ICs are not length match +# Assume a worst case clock difference of 2.5 ns at the IC inputs. +# There is no direction defined. The clock can arrive faster or slower +# on one IC. +set ctrl_clock_diff 2.500 + +set ctrl_slave_inputs [get_ports {MB_CTRL_MOSI MB_CTRL_CS}] +# calculate output delays back from capturing edge, add board delay and clock difference +set_input_delay -clock mb_ctrl_sck -clock_fall \ + -max [expr {$prc_clock_period - $db_cpld_spi_max_out - $ctrl_spi_board_delay - $ctrl_clock_diff}] \ + $ctrl_slave_inputs +# Assuming data is going without any delay, clock is arriving early at CPLD. +# Negate minimum output delay as it is defined from the change to the start clock edge. +set_input_delay -clock mb_ctrl_sck -clock_fall \ + -min [expr {- $db_cpld_spi_min_out - $ctrl_clock_diff}] \ + $ctrl_slave_inputs + +set ctrl_slave_outputs [get_ports {MB_CTRL_MISO}] +# Calculate remaining time of clock period based on MB CPLD maximum input delay. +# Add board delay and clock difference. +set_output_delay -clock mb_ctrl_sck \ + -max [expr {$prc_clock_period - $db_cpld_spi_max_in + $ctrl_spi_board_delay + $ctrl_clock_diff}] \ + $ctrl_slave_outputs +# Assume no board delay just clock difference with rising edge occurring early at +# DB CPLD and MB CPLD input constraint +set_output_delay -clock mb_ctrl_sck \ + -min [expr {- $db_cpld_spi_min_in - $ctrl_clock_diff}] \ + $ctrl_slave_outputs + +##################################################################### +# LO SPI interface +##################################################################### +set lo_spi_clks [get_ports *X*_LO*_SCK] +set lo_spi_output_ports [get_ports {*X*_LO*_SDI *X*_LO*_CSB}] +set lo_spi_input_ports [get_ports {*X*_LO*_MUXOUT}] + +# Use the worst-case board propagation delay. +# Assuming 170.0 ps/in. +# Longest trace | Trace length | Trace delay +# RX0_LO1_SDI | 8.333 in | 1.416 ns +# -------------------------------------------- +# Since lines are not managed individually, and since we should +# have plenty of slack in this interface, we will conservatively use +# twice the propagation time of the longest trace for all our +# max delay calculations. +set lo_spi_max_sclk_delay 3.000 +set lo_spi_min_sclk_delay 0.000 +set lo_spi_max_signal_delay 3.000 +set lo_spi_min_signal_delay 0.000 + +set lo_spi_min_tco 0.000 +set lo_spi_max_tco 10.000 + +set lo_spi_setup 10.000 +set lo_spi_hold 10.000 + +set lo_spi_clk_div 4 + +set lo_spi_clk_register [get_registers {zbx_cpld_core:zbx_cpld_core_i|lo_control:lo_control_i|spi_top:spi_top_i|spi_clgen:clgen|clk_out}] +create_generated_clock -source [get_ports {CPLD_REFCLK}] \ + -name lo_spi_clk $lo_spi_clk_register \ + -divide_by $lo_spi_clk_div + +create_generated_clock \ + -source $lo_spi_clk_register \ + -name lo_spi_clk_out $lo_spi_clks + +# ---------------------------------------- +# -- Constraint for SPI CS and SDI -- +# ---------------------------------------- + +set_output_delay -clock lo_spi_clk_out \ + -max [expr {$lo_spi_setup + $lo_spi_max_signal_delay - $lo_spi_min_sclk_delay}] \ + $lo_spi_output_ports +set_output_delay -clock lo_spi_clk_out \ + -min [expr {0 - $lo_spi_max_sclk_delay - $lo_spi_hold + $lo_spi_min_signal_delay }] \ + $lo_spi_output_ports + +# -- Multi-cycle path for SPI CS and SDI -- +# ---------------------------------------- +# Both the CSB and SDI timing are defined in reference to the rising edge of SCLK, so we can merge the analysis. +# +# edge # 1 2 3 4 5 +# clk50 __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-- +# sclk __/-----------------------\_______________________/-------------- +# | launch edge (due to negedge reg) +# | | | +# 0 1 2 -- Edge used for setup analysis N = 2 +# +# | | | | +# 3 2 1 0 --(Setup -1) edge, in case of no hold multi-cycle path +# | +# \____ Edge used for hold = 3 +# +# Analyzing this diagram, we can see that the setup edge of interest is located a sclk cycle +# after the launch edge($lo_spi_clk_div) and that the hold margin has setup-1 edges after the launch edge, +# or: lo_spi_clk_div - 1. +set_multicycle_path -setup -start -to $lo_spi_output_ports [expr ($lo_spi_clk_div/2)] +set_multicycle_path -hold -start -to $lo_spi_output_ports [expr ($lo_spi_clk_div-1)] + + +# ---------------------------------------- +# -- Constraint for SPI MUXOUT -- +# ---------------------------------------- + +set_input_delay -clock lo_spi_clk_out -clock_fall \ + -max [expr {$lo_spi_max_sclk_delay + $lo_spi_max_tco + $lo_spi_max_signal_delay}] \ + $lo_spi_input_ports + +set_input_delay -clock lo_spi_clk_out -clock_fall \ + -min [expr {$lo_spi_min_sclk_delay + $lo_spi_min_tco + $lo_spi_min_signal_delay}] \ + $lo_spi_input_ports + +# -- Multi-cycle path for SPI MUXOUT -- +# ---------------------------------------- +# edge # 1 2 3 4 5 6 7 8 +# clk50 __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-- +# sclk __/-----------------------\_______________________/-----------------------\_______________________/-- +# muxout MSB | MSB-1 +# launch edge | +# | | | +# 0 1 2 +# \_ Edge used for setup analysis N = 2 +# | | | | +# 3 2 1 0 - N-1 edge(if no hold is given) +# | +# \____ Edge used for hold = 3 +# +# Analyzing this diagram, we can see that the setup edge of interest is located half a sclk cycle +# after the launch edge($lo_spi_clk_div/2) and that the hold margin has ($lo_spi_clk_div/2) +# of margin before the launch edge and setup-1 edges after the launch edge, to simplify: +# ($lo_spi_clk_div/2+$lo_spi_clk_div/2-1) = lo_spi_clk_div - 1. +set_multicycle_path -setup -end -from $lo_spi_input_ports [expr ($lo_spi_clk_div/2)] +set_multicycle_path -hold -end -from $lo_spi_input_ports [expr ($lo_spi_clk_div-1)] + +##################################################################### +# Asynchronous IO +##################################################################### +# For general I/O that don't have tight timing constraints, we can constrain +# these paths by creating a generic flip-flop that will interface to the +# device. +# For asynchronous outputs +set generic_ext_flop_tsu 1 +set generic_ext_flop_th 0 + +# For asynchronous inputs +set generic_ext_flop_max_tco 2 +set generic_ext_flop_min_tco 0 + +set async_outputs_prc {CH*_*X*_LED \ + RX*_DSA*_*[*] \ + TX*_DSA*[*] \ + *X*_SW*} +set_output_delay -clock pll_ref_clk -max [expr $generic_ext_flop_tsu] \ + [get_ports $async_outputs_prc] +set_output_delay -clock pll_ref_clk -min [expr 0 - $generic_ext_flop_th] \ + [get_ports $async_outputs_prc] + +set_output_delay -clock osc_clk -max [expr $generic_ext_flop_tsu] \ + [get_ports {P*_ENABLE*}] +set_output_delay -clock osc_clk -min [expr 0 - $generic_ext_flop_th] \ + [get_ports {P*_ENABLE*}] + +set async_inputs {CTRL_REG_ARST} +set_input_delay -clock ctrlport_clk -max [expr $generic_ext_flop_max_tco] \ + [get_ports $async_inputs] +set_input_delay -clock ctrlport_clk -min [expr $generic_ext_flop_min_tco] \ + [get_ports $async_inputs] + +set_input_delay -clock osc_clk -max [expr $generic_ext_flop_max_tco] \ + [get_ports {P7V_PG_*}] +set_input_delay -clock osc_clk -min [expr $generic_ext_flop_min_tco] \ + [get_ports {P7V_PG_*}] + +##################################################################### +# MB FPGA GPIO +##################################################################### +# Some timing constants in this section are declared in +# fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc + +set db_gpio_inputs [get_ports {MB_FPGA_GPIO[*]}] +# Assume worst case as data being generated late and receiving an early clock: +# - Max FPGA TCO +# - Max data propagation delay +# - Max FPGA clock propagation delay and minimum CPLD clock propagation delay +# - Minimum delay on MC100EPT23 clock buffer +set_input_delay -clock pll_ref_clk -clock_fall \ + -max [expr { $prc_clock_period/2 - $db_gpio_fpga_max_out \ + + $db_gpio_board_max_delay \ + + $fpga_prc_clock_prop_max - $db_cpld_prc_clock_prop_min \ + - $clock_translate_min}] \ + $db_gpio_inputs +# Assume worst case as data being generated early and receiving an late clock: +# - Min FPGA TCO +# - Min data propagation delay (0) +# - Min FPGA clock propagation delay and maximum CPLD clock propagation delay +# - Maximum delay on MC100EPT23 clock buffer +set_input_delay -clock pll_ref_clk -clock_fall \ + -min [expr {- $db_gpio_fpga_min_out \ + - $db_gpio_board_min_delay \ + - $fpga_prc_clock_prop_min + $db_cpld_prc_clock_prop_max \ + + $clock_translate_max}] \ + $db_gpio_inputs + +# output delay +# maximum integer delays with slack of around 1ns +set_output_delay -clock pll_ref_clk -max $db_gpio_cpld_max_out $db_gpio_inputs +set_output_delay -clock pll_ref_clk -min $db_gpio_cpld_min_out $db_gpio_inputs + +##################################################################### +# Known Issue of On-Chip Flash +##################################################################### +# see https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/2016/warning--332060---node---alteraonchipflash-onchipflash-alteraonc.html +create_generated_clock -name flash_se_neg_reg \ + -source [get_pins { on_chip_flash:flash_i|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|clk }] \ + -divide_by 2 [get_pins { on_chip_flash:flash_i|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|q } ] + +##################################################################### +# Clock uncertainty +##################################################################### +# Assign some uncertainty to all clocks +set clock_uncertainty 0.150 +set_clock_uncertainty -to [get_clocks *] $clock_uncertainty +derive_clock_uncertainty + diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.v new file mode 100644 index 000000000..a688db2ff --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.v @@ -0,0 +1,1305 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: zbx_top_cpld +// +// Description: +// +// Top level file for the ZBX CPLD, enabling multi-purpose control around the +// ZBX board. Main blocks are contained within zbx_cpld_core. +// + +`default_nettype none + +module zbx_top_cpld ( + //LO Clocking + input wire CPLD_REFCLK, + input wire MB_SYNTH_SYNC, + + //Clk and reset for control registers + input wire CTRL_REG_CLK, + input wire CTRL_REG_ARST, + + //SPI in + input wire MB_CTRL_SCK, + input wire MB_CTRL_MOSI, + output wire MB_CTRL_MISO, + input wire MB_CTRL_CS, + + //MB FPGA GPIO + //net name mapping in decreasing order + // MB_FPGA_GPIO_a14 + // MB_FPGA_GPIO_a16 + // MB_FPGA_GPIO_a17 + // MB_FPGA_GPIO_b8 + // MB_FPGA_GPIO_b9 + // MB_FPGA_GPIO_b11 + // MB_FPGA_GPIO_b12 + // MB_FPGA_GPIO_b14 + // MB_FPGA_GPIO_b15 + // MB_FPGA_GPIO_b17 + // MB_FPGA_GPIO_c15 + // MB_FPGA_GPIO_c16 + // MB_FPGA_GPIO_c18 + // MB_FPGA_GPIO_c19 + inout wire [13:0] MB_FPGA_GPIO, + + ///////////////////////////////////////////////////////////////////////////// + // Rf Power Controls + ///////////////////////////////////////////////////////////////////////////// + + output wire P7V_ENABLE_A, + output wire P7V_ENABLE_B, + output wire P3D3VA_ENABLE, + + input wire P7V_PG_A, + input wire P7V_PG_B, + + ///////////////////////////////////////////////////////////////////////////// + // TX0 Controls + ///////////////////////////////////////////////////////////////////////////// + + //Tx0 LO control for LMX2572 + output wire TX0_LO1_SYNC, + input wire TX0_LO1_MUXOUT, + output wire TX0_LO1_CSB, + output wire TX0_LO1_SCK, + output wire TX0_LO1_SDI, + + output wire TX0_LO2_SYNC, + input wire TX0_LO2_MUXOUT, + output wire TX0_LO2_CSB, + output wire TX0_LO2_SCK, + output wire TX0_LO2_SDI, + + //Tx0 Switch control + output wire TX0_SW1_SW2_CTRL, + output wire TX0_SW3_A, + output wire TX0_SW3_B, + output wire TX0_SW4_A, + output wire TX0_SW4_B, + output wire TX0_SW5_A, + output wire TX0_SW5_B, + output wire TX0_SW6_A, + output wire TX0_SW6_B, + output wire TX0_SW7_A, + output wire TX0_SW7_B, + output wire TX0_SW8_V1, + output wire TX0_SW8_V2, + output wire TX0_SW8_V3, + output wire TX0_SW9_A, + output wire TX0_SW9_B, + output wire TX0_SW10_A, + output wire TX0_SW10_B, + output wire TX0_SW11_A, + output wire TX0_SW11_B, + output wire TX0_SW13_V1, + output wire TX0_SW14_V1, + + //Tx0 DSA control + output wire [6:2] TX0_DSA1, + output wire [6:2] TX0_DSA2, + + ///////////////////////////////////////////////////////////////////////////// + // TX1 Controls + ///////////////////////////////////////////////////////////////////////////// + + //Tx1 LO control for LMX2572 + output wire TX1_LO1_SYNC, + input wire TX1_LO1_MUXOUT, + output wire TX1_LO1_CSB, + output wire TX1_LO1_SCK, + output wire TX1_LO1_SDI, + + output wire TX1_LO2_SYNC, + input wire TX1_LO2_MUXOUT, + output wire TX1_LO2_CSB, + output wire TX1_LO2_SCK, + output wire TX1_LO2_SDI, + + //Tx1 Switch control + output wire TX1_SW1_SW2_CTRL, + output wire TX1_SW3_A, + output wire TX1_SW3_B, + output wire TX1_SW4_A, + output wire TX1_SW4_B, + output wire TX1_SW5_A, + output wire TX1_SW5_B, + output wire TX1_SW6_A, + output wire TX1_SW6_B, + output wire TX1_SW7_A, + output wire TX1_SW7_B, + output wire TX1_SW8_V1, + output wire TX1_SW8_V2, + output wire TX1_SW8_V3, + output wire TX1_SW9_A, + output wire TX1_SW9_B, + output wire TX1_SW10_A, + output wire TX1_SW10_B, + output wire TX1_SW11_A, + output wire TX1_SW11_B, + output wire TX1_SW13_V1, + output wire TX1_SW14_V1, + + //Tx1 DSA control + output wire [6:2] TX1_DSA1, + output wire [6:2] TX1_DSA2, + + ///////////////////////////////////////////////////////////////////////////// + // RX0 Controls + ///////////////////////////////////////////////////////////////////////////// + + //Rx0 LO control for LMX2572 + output wire RX0_LO1_SYNC, + input wire RX0_LO1_MUXOUT, + output wire RX0_LO1_CSB, + output wire RX0_LO1_SCK, + output wire RX0_LO1_SDI, + + output wire RX0_LO2_SYNC, + input wire RX0_LO2_MUXOUT, + output wire RX0_LO2_CSB, + output wire RX0_LO2_SCK, + output wire RX0_LO2_SDI, + + //Rx0 Switch control + output wire RX0_SW1_A, + output wire RX0_SW1_B, + output wire RX0_SW2_A, + output wire RX0_SW3_V1, + output wire RX0_SW3_V2, + output wire RX0_SW3_V3, + output wire RX0_SW4_A, + output wire RX0_SW5_A, + output wire RX0_SW5_B, + output wire RX0_SW6_A, + output wire RX0_SW6_B, + output wire RX0_SW7_SW8_CTRL, + output wire RX0_SW9_V1, + output wire RX0_SW10_V1, + output wire RX0_SW11_V3, + output wire RX0_SW11_V2, + output wire RX0_SW11_V1, + + //Rx0 DSA control + output wire [1:4] RX0_DSA1_n, + output wire [1:4] RX0_DSA2_n, + output wire [1:4] RX0_DSA3_A_n, + output wire [1:4] RX0_DSA3_B_n, + + ///////////////////////////////////////////////////////////////////////////// + // RX1 Controls + ///////////////////////////////////////////////////////////////////////////// + + //Rx1 LO control for LMX2572 + output wire RX1_LO1_SYNC, + input wire RX1_LO1_MUXOUT, + output wire RX1_LO1_CSB, + output wire RX1_LO1_SCK, + output wire RX1_LO1_SDI, + + output wire RX1_LO2_SYNC, + input wire RX1_LO2_MUXOUT, + output wire RX1_LO2_CSB, + output wire RX1_LO2_SCK, + output wire RX1_LO2_SDI, + + //Rx1 Switch Control + output wire RX1_SW1_A, + output wire RX1_SW1_B, + output wire RX1_SW2_A, + output wire RX1_SW3_V1, + output wire RX1_SW3_V2, + output wire RX1_SW3_V3, + output wire RX1_SW4_A, + output wire RX1_SW5_A, + output wire RX1_SW5_B, + output wire RX1_SW6_A, + output wire RX1_SW6_B, + output wire RX1_SW7_SW8_CTRL, + output wire RX1_SW9_V1, + output wire RX1_SW10_V1, + output wire RX1_SW11_V3, + output wire RX1_SW11_V2, + output wire RX1_SW11_V1, + + //Rx1 DSA control + output wire [1:4] RX1_DSA1_n, + output wire [1:4] RX1_DSA2_n, + output wire [1:4] RX1_DSA3_A_n, + output wire [1:4] RX1_DSA3_B_n, + + ///////////////////////////////////////////////////////////////////////////// + // LED Control + ///////////////////////////////////////////////////////////////////////////// + + output wire CH0_RX2_LED, + output wire CH0_TX_LED, + output wire CH0_RX_LED, + output wire CH1_RX2_LED, + output wire CH1_TX_LED, + output wire CH1_RX_LED + +); + + // SPI masters (LO and power detection) are limited to a maximum 24 bit + // transmission length + `define SPI_MAX_CHAR_32 + + `include "../../../../../lib/rfnoc/core/ctrlport.vh" + `include "regmap/db_control_regmap_utils.vh" + `include "regmap/lo_control_regmap_utils.vh" + `include "regmap/spi_regmap_utils.vh" + `include "regmap/gpio_regmap_utils.vh" + + // Internal oscillator + // In the used MAX10 device this oscillator produces a clock anywhere in the + // range of 55 to 116 MHz. It drives all logic required for identification and + // to enable the PLL reference clock for the ZBX core registers. + wire clk_osc; + osc int_oscillator_i ( + .clkout (clk_osc), + .oscena (1'b1) + ); + + // Pass oscillator clock through buffer to be able to generate a derived clock + // in the timing constraints + wire clk_int_osc; + clkctrl int_osc_clk_ctrl_i ( + .inclk (clk_osc), + .ena (1'b1), + .outclk (clk_int_osc) + ); + + // Bring pll_ref_clk enable signal to the same clock domain. + wire pll_ref_clk_enable_osc, pll_ref_clk_enable_prc; + + synchronizer #( + .WIDTH (1), + .STAGES (2), + .INITIAL_VAL (1'b1), + .FALSE_PATH_TO_IN (1) + ) pll_ref_clk_enable_sync_i ( + .clk (CPLD_REFCLK), + .rst (1'b0), + .in (pll_ref_clk_enable_osc), + .out (pll_ref_clk_enable_prc) + ); + + // Add clock buffer with option to enable PLL reference clock during SPLL + // reconfiguration + wire pll_ref_clk; + clkctrl pll_ref_clk_ctrl_i ( + .inclk (CPLD_REFCLK), + .ena (pll_ref_clk_enable_prc), + .outclk (pll_ref_clk) + ); + + // Generate synchronous resets + wire ctrlport_rst_osc; + wire ctrlport_rst_prc; + wire ctrlport_rst_crc; + + reset_sync reset_sync_osc_i ( + .clk (clk_int_osc), + .reset_in (CTRL_REG_ARST), + .reset_out (ctrlport_rst_osc) + ); + + reset_sync reset_sync_prc_i ( + .clk (pll_ref_clk), + .reset_in (CTRL_REG_ARST), + .reset_out (ctrlport_rst_prc) + ); + + reset_sync reset_sync_crc_i ( + .clk (CTRL_REG_CLK), + .reset_in (CTRL_REG_ARST), + .reset_out (ctrlport_rst_crc) + ); + + ///////////////////////////////////////////////////////////////////////////// + // ControlPort sources + ///////////////////////////////////////////////////////////////////////////// + wire [19:0] spi_ctrlport_req_addr; + wire [31:0] spi_ctrlport_req_data; + wire spi_ctrlport_req_rd; + wire spi_ctrlport_req_wr; + wire spi_ctrlport_resp_ack; + wire [31:0] spi_ctrlport_resp_data; + wire [ 1:0] spi_ctrlport_resp_status; + + // The clock frequencies given as generics are used within the module to + // determine how many clock cycles are needed to transfer data. The SPI + // frequency is defined by the PLL ref clock driving this interface and the + // clock divider, which should be set to at least 10 (see the constraints file + // for details). Therefore the maximum SPI clock is 6.4MHz. The CtrlPort clock + // is defined by the internal oscillator. 55 MHz is the lowest rate that + // should be accounted for (worst case processing cycles for the SPI command). + + spi_slave_to_ctrlport_master #( + .CLK_FREQUENCY (55_000_000), + .SPI_FREQUENCY (6_400_000) + ) spi_slave_to_ctrlport_master_i ( + .ctrlport_clk (clk_int_osc), + .ctrlport_rst (ctrlport_rst_osc), + .m_ctrlport_req_wr (spi_ctrlport_req_wr), + .m_ctrlport_req_rd (spi_ctrlport_req_rd), + .m_ctrlport_req_addr (spi_ctrlport_req_addr), + .m_ctrlport_req_data (spi_ctrlport_req_data), + .m_ctrlport_resp_ack (spi_ctrlport_resp_ack), + .m_ctrlport_resp_status (spi_ctrlport_resp_status), + .m_ctrlport_resp_data (spi_ctrlport_resp_data), + .sclk (MB_CTRL_SCK), + .cs_n (MB_CTRL_CS), + .mosi (MB_CTRL_MOSI), + .miso (MB_CTRL_MISO) + ); + + wire [19:0] gpio_ctrlport_req_addr; + wire [31:0] gpio_ctrlport_req_data; + wire gpio_ctrlport_req_rd; + wire gpio_ctrlport_req_wr; + wire gpio_ctrlport_resp_ack; + wire [31:0] gpio_ctrlport_resp_data; + wire [ 1:0] gpio_ctrlport_resp_status; + + wire [ 7:0] gpio_data_in; + wire [ 7:0] gpio_data_out; + wire gpio_valid_in; + wire gpio_valid_out; + wire gpio_output_enable; + wire gpio_direction; + + ctrlport_byte_deserializer ctrlport_byte_deserializer_i ( + .ctrlport_clk (pll_ref_clk), + .ctrlport_rst (ctrlport_rst_prc), + .m_ctrlport_req_wr (gpio_ctrlport_req_wr), + .m_ctrlport_req_rd (gpio_ctrlport_req_rd), + .m_ctrlport_req_addr (gpio_ctrlport_req_addr), + .m_ctrlport_req_data (gpio_ctrlport_req_data), + .m_ctrlport_resp_ack (gpio_ctrlport_resp_ack), + .m_ctrlport_resp_status (gpio_ctrlport_resp_status), + .m_ctrlport_resp_data (gpio_ctrlport_resp_data), + .bytestream_data_in (gpio_data_in), + .bytestream_valid_in (gpio_valid_in), + .bytestream_direction (gpio_direction), + .bytestream_data_out (gpio_data_out), + .bytestream_valid_out (gpio_valid_out), + .bytestream_output_enable (gpio_output_enable) + ); + + // connect GPIO related signals + // inputs + assign gpio_direction = MB_FPGA_GPIO[13]; + assign gpio_valid_in = MB_FPGA_GPIO[12]; + assign gpio_data_in = MB_FPGA_GPIO[11:4]; + // outputs + wire [13:0] gpio_out = {1'b0, gpio_valid_out, gpio_data_out, 4'b0}; + wire [13:0] gpio_out_en = {1'b0, {9 {gpio_output_enable}}, 4'b0}; + // GPIO tristate buffers + genvar i; + generate for (i=0; i<14; i=i+1) begin: gpio_tristate_gen + assign MB_FPGA_GPIO[i] = (gpio_out_en[i]) ? gpio_out[i] : 1'bz; + end endgenerate + + ///////////////////////////////////////////////////////////////////////////// + // ControlPort distribution network + ///////////////////////////////////////////////////////////////////////////// + // The network topology is shown below, where S = splitter, C = combiner, + // X = clock domain crossing and F = address filter (ctrlport_window). + // + // The CtrlPort combiner module blocks further requests until a response is + // received. Therefore there has to be a response for each request. Each + // combiner input is therefore guarded by an address filter to make sure the + // request is targeted to the register map behind the combiner. Furthermore + // each address behind the combiner has to be assigned (no gaps allowed). + // + // Requests targeting the reconfig engine are filtered because the reconfig + // engine clock is disabled when unused. + // + // X--------> RECONFIG (CTRL_REG_CLK) + // | + // F -------> POWER_REGS_REGMAP (clk_int_osc) + // |/ + // SPI (clk_int_osc) >---S-F-C----> BASIC_REGS_REGMAP (clk_int_osc) + // | | + // F | + // \ / + // X² + // / \ + // F | + // | | + // GPIO (pll_ref_clk) >--S-F-C----> DB_CONTROL (pll_ref_clk) + + wire [19:0] spi_core_ctrlport_req_addr_osc; + wire [31:0] spi_core_ctrlport_req_data_osc; + wire spi_core_ctrlport_req_rd_osc; + wire spi_core_ctrlport_req_wr_osc; + wire spi_core_ctrlport_resp_ack_osc; + wire [31:0] spi_core_ctrlport_resp_data_osc; + wire [1:0] spi_core_ctrlport_resp_status_osc; + + wire [19:0] spi_base_ctrlport_req_addr; + wire [31:0] spi_base_ctrlport_req_data; + wire spi_base_ctrlport_req_rd; + wire spi_base_ctrlport_req_wr; + wire spi_base_ctrlport_resp_ack; + wire [31:0] spi_base_ctrlport_resp_data; + wire [1:0] spi_base_ctrlport_resp_status; + + wire [19:0] power_ctrlport_req_addr; + wire [31:0] power_ctrlport_req_data; + wire power_ctrlport_req_rd; + wire power_ctrlport_req_wr; + wire power_ctrlport_resp_ack; + wire [31:0] power_ctrlport_resp_data; + wire [1:0] power_ctrlport_resp_status; + + wire [19:0] reconfig_ctrlport_req_addr_osc; + wire [31:0] reconfig_ctrlport_req_data_osc; + wire reconfig_ctrlport_req_rd_osc; + wire reconfig_ctrlport_req_wr_osc; + wire reconfig_ctrlport_resp_ack_osc; + wire [31:0] reconfig_ctrlport_resp_data_osc; + wire [1:0] reconfig_ctrlport_resp_status_osc; + + ctrlport_splitter #( + .NUM_SLAVES(4) + ) spi_splitter_i ( + .ctrlport_clk (clk_int_osc), + .ctrlport_rst (ctrlport_rst_osc), + .s_ctrlport_req_wr (spi_ctrlport_req_wr), + .s_ctrlport_req_rd (spi_ctrlport_req_rd), + .s_ctrlport_req_addr (spi_ctrlport_req_addr), + .s_ctrlport_req_data (spi_ctrlport_req_data), + .s_ctrlport_req_byte_en (), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack (spi_ctrlport_resp_ack), + .s_ctrlport_resp_status (spi_ctrlport_resp_status), + .s_ctrlport_resp_data (spi_ctrlport_resp_data), + .m_ctrlport_req_wr ({spi_core_ctrlport_req_wr_osc, spi_base_ctrlport_req_wr, power_ctrlport_req_wr, reconfig_ctrlport_req_wr_osc}), + .m_ctrlport_req_rd ({spi_core_ctrlport_req_rd_osc, spi_base_ctrlport_req_rd, power_ctrlport_req_rd, reconfig_ctrlport_req_rd_osc}), + .m_ctrlport_req_addr ({spi_core_ctrlport_req_addr_osc, spi_base_ctrlport_req_addr, power_ctrlport_req_addr, reconfig_ctrlport_req_addr_osc}), + .m_ctrlport_req_data ({spi_core_ctrlport_req_data_osc, spi_base_ctrlport_req_data, power_ctrlport_req_data, reconfig_ctrlport_req_data_osc}), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack ({spi_core_ctrlport_resp_ack_osc, spi_base_ctrlport_resp_ack, power_ctrlport_resp_ack, reconfig_ctrlport_resp_ack_osc}), + .m_ctrlport_resp_status ({spi_core_ctrlport_resp_status_osc, spi_base_ctrlport_resp_status, power_ctrlport_resp_status, reconfig_ctrlport_resp_status_osc}), + .m_ctrlport_resp_data ({spi_core_ctrlport_resp_data_osc, spi_base_ctrlport_resp_data, power_ctrlport_resp_data, reconfig_ctrlport_resp_data_osc}) + ); + + wire [19:0] spi_core_ctrlport_req_addr_filtered_osc; + wire [31:0] spi_core_ctrlport_req_data_filtered_osc; + wire spi_core_ctrlport_req_rd_filtered_osc; + wire spi_core_ctrlport_req_wr_filtered_osc; + wire spi_core_ctrlport_resp_ack_filtered_osc; + wire [31:0] spi_core_ctrlport_resp_data_filtered_osc; + wire [1:0] spi_core_ctrlport_resp_status_filtered_osc; + + wire [19:0] spi_base_ctrlport_req_addr_filtered; + wire [31:0] spi_base_ctrlport_req_data_filtered; + wire spi_base_ctrlport_req_rd_filtered; + wire spi_base_ctrlport_req_wr_filtered; + wire spi_base_ctrlport_resp_ack_filtered; + wire [31:0] spi_base_ctrlport_resp_data_filtered; + wire [1:0] spi_base_ctrlport_resp_status_filtered; + + wire [19:0] reconfig_ctrlport_req_addr_filtered_osc; + wire [31:0] reconfig_ctrlport_req_data_filtered_osc; + wire reconfig_ctrlport_req_rd_filtered_osc; + wire reconfig_ctrlport_req_wr_filtered_osc; + wire reconfig_ctrlport_resp_ack_filtered_osc; + wire [31:0] reconfig_ctrlport_resp_data_filtered_osc; + wire [1:0] reconfig_ctrlport_resp_status_filtered_osc; + + ctrlport_window #( + .BASE_ADDRESS (DB_CONTROL_WINDOW_SPI), + .WINDOW_SIZE (DB_CONTROL_WINDOW_SPI_SIZE) + ) spi_core_window_i ( + .s_ctrlport_req_wr (spi_core_ctrlport_req_wr_osc), + .s_ctrlport_req_rd (spi_core_ctrlport_req_rd_osc), + .s_ctrlport_req_addr (spi_core_ctrlport_req_addr_osc), + .s_ctrlport_req_portid (), + .s_ctrlport_req_rem_epid (), + .s_ctrlport_req_rem_portid (), + .s_ctrlport_req_data (spi_core_ctrlport_req_data_osc), + .s_ctrlport_req_byte_en (), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack (spi_core_ctrlport_resp_ack_osc), + .s_ctrlport_resp_status (spi_core_ctrlport_resp_status_osc), + .s_ctrlport_resp_data (spi_core_ctrlport_resp_data_osc), + .m_ctrlport_req_wr (spi_core_ctrlport_req_wr_filtered_osc), + .m_ctrlport_req_rd (spi_core_ctrlport_req_rd_filtered_osc), + .m_ctrlport_req_addr (spi_core_ctrlport_req_addr_filtered_osc), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (spi_core_ctrlport_req_data_filtered_osc), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (spi_core_ctrlport_resp_ack_filtered_osc), + .m_ctrlport_resp_status (spi_core_ctrlport_resp_status_filtered_osc), + .m_ctrlport_resp_data (spi_core_ctrlport_resp_data_filtered_osc) + ); + + ctrlport_window #( + .BASE_ADDRESS (BASE_WINDOW_SPI), + .WINDOW_SIZE (BASE_WINDOW_SPI_SIZE) + ) spi_base_window_i ( + .s_ctrlport_req_wr (spi_base_ctrlport_req_wr), + .s_ctrlport_req_rd (spi_base_ctrlport_req_rd), + .s_ctrlport_req_addr (spi_base_ctrlport_req_addr), + .s_ctrlport_req_portid (), + .s_ctrlport_req_rem_epid (), + .s_ctrlport_req_rem_portid (), + .s_ctrlport_req_data (spi_base_ctrlport_req_data), + .s_ctrlport_req_byte_en (), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack (spi_base_ctrlport_resp_ack), + .s_ctrlport_resp_status (spi_base_ctrlport_resp_status), + .s_ctrlport_resp_data (spi_base_ctrlport_resp_data), + .m_ctrlport_req_wr (spi_base_ctrlport_req_wr_filtered), + .m_ctrlport_req_rd (spi_base_ctrlport_req_rd_filtered), + .m_ctrlport_req_addr (spi_base_ctrlport_req_addr_filtered), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (spi_base_ctrlport_req_data_filtered), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (spi_base_ctrlport_resp_ack_filtered), + .m_ctrlport_resp_status (spi_base_ctrlport_resp_status_filtered), + .m_ctrlport_resp_data (spi_base_ctrlport_resp_data_filtered) + ); + + ctrlport_window #( + .BASE_ADDRESS (RECONFIG), + .WINDOW_SIZE (RECONFIG_SIZE) + ) spi_reconfig_window_i ( + .s_ctrlport_req_wr (reconfig_ctrlport_req_wr_osc), + .s_ctrlport_req_rd (reconfig_ctrlport_req_rd_osc), + .s_ctrlport_req_addr (reconfig_ctrlport_req_addr_osc), + .s_ctrlport_req_portid (), + .s_ctrlport_req_rem_epid (), + .s_ctrlport_req_rem_portid (), + .s_ctrlport_req_data (reconfig_ctrlport_req_data_osc), + .s_ctrlport_req_byte_en (), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack (reconfig_ctrlport_resp_ack_osc), + .s_ctrlport_resp_status (reconfig_ctrlport_resp_status_osc), + .s_ctrlport_resp_data (reconfig_ctrlport_resp_data_osc), + .m_ctrlport_req_wr (reconfig_ctrlport_req_wr_filtered_osc), + .m_ctrlport_req_rd (reconfig_ctrlport_req_rd_filtered_osc), + .m_ctrlport_req_addr (reconfig_ctrlport_req_addr_filtered_osc), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (reconfig_ctrlport_req_data_filtered_osc), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (reconfig_ctrlport_resp_ack_filtered_osc), + .m_ctrlport_resp_status (reconfig_ctrlport_resp_status_filtered_osc), + .m_ctrlport_resp_data (reconfig_ctrlport_resp_data_filtered_osc) + ); + + wire [19:0] gpio_core_ctrlport_req_addr; + wire [31:0] gpio_core_ctrlport_req_data; + wire gpio_core_ctrlport_req_rd; + wire gpio_core_ctrlport_req_wr; + wire gpio_core_ctrlport_resp_ack; + wire [31:0] gpio_core_ctrlport_resp_data; + wire [1:0] gpio_core_ctrlport_resp_status; + + wire [19:0] gpio_base_ctrlport_req_addr_prc; + wire [31:0] gpio_base_ctrlport_req_data_prc; + wire gpio_base_ctrlport_req_rd_prc; + wire gpio_base_ctrlport_req_wr_prc; + wire gpio_base_ctrlport_resp_ack_prc; + wire [31:0] gpio_base_ctrlport_resp_data_prc; + wire [1:0] gpio_base_ctrlport_resp_status_prc; + + ctrlport_splitter #( + .NUM_SLAVES(2) + ) gpio_splitter_i ( + .ctrlport_clk (pll_ref_clk), + .ctrlport_rst (ctrlport_rst_prc), + .s_ctrlport_req_wr (gpio_ctrlport_req_wr), + .s_ctrlport_req_rd (gpio_ctrlport_req_rd), + .s_ctrlport_req_addr (gpio_ctrlport_req_addr), + .s_ctrlport_req_data (gpio_ctrlport_req_data), + .s_ctrlport_req_byte_en (), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack (gpio_ctrlport_resp_ack), + .s_ctrlport_resp_status (gpio_ctrlport_resp_status), + .s_ctrlport_resp_data (gpio_ctrlport_resp_data), + .m_ctrlport_req_wr ({gpio_core_ctrlport_req_wr, gpio_base_ctrlport_req_wr_prc}), + .m_ctrlport_req_rd ({gpio_core_ctrlport_req_rd, gpio_base_ctrlport_req_rd_prc}), + .m_ctrlport_req_addr ({gpio_core_ctrlport_req_addr, gpio_base_ctrlport_req_addr_prc}), + .m_ctrlport_req_data ({gpio_core_ctrlport_req_data, gpio_base_ctrlport_req_data_prc}), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack ({gpio_core_ctrlport_resp_ack, gpio_base_ctrlport_resp_ack_prc}), + .m_ctrlport_resp_status ({gpio_core_ctrlport_resp_status, gpio_base_ctrlport_resp_status_prc}), + .m_ctrlport_resp_data ({gpio_core_ctrlport_resp_data, gpio_base_ctrlport_resp_data_prc}) + ); + + wire [19:0] gpio_core_ctrlport_req_addr_filtered; + wire [31:0] gpio_core_ctrlport_req_data_filtered; + wire gpio_core_ctrlport_req_rd_filtered; + wire gpio_core_ctrlport_req_wr_filtered; + wire gpio_core_ctrlport_resp_ack_filtered; + wire [31:0] gpio_core_ctrlport_resp_data_filtered; + wire [1:0] gpio_core_ctrlport_resp_status_filtered; + + wire [19:0] gpio_base_ctrlport_req_addr_filtered_prc; + wire [31:0] gpio_base_ctrlport_req_data_filtered_prc; + wire gpio_base_ctrlport_req_rd_filtered_prc; + wire gpio_base_ctrlport_req_wr_filtered_prc; + wire gpio_base_ctrlport_resp_ack_filtered_prc; + wire [31:0] gpio_base_ctrlport_resp_data_filtered_prc; + wire [1:0] gpio_base_ctrlport_resp_status_filtered_prc; + + ctrlport_window #( + .BASE_ADDRESS (DB_CONTROL_WINDOW_GPIO), + .WINDOW_SIZE (DB_CONTROL_WINDOW_GPIO_SIZE) + ) gpio_core_window_i ( + .s_ctrlport_req_wr (gpio_core_ctrlport_req_wr), + .s_ctrlport_req_rd (gpio_core_ctrlport_req_rd), + .s_ctrlport_req_addr (gpio_core_ctrlport_req_addr), + .s_ctrlport_req_portid (), + .s_ctrlport_req_rem_epid (), + .s_ctrlport_req_rem_portid (), + .s_ctrlport_req_data (gpio_core_ctrlport_req_data), + .s_ctrlport_req_byte_en (), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack (gpio_core_ctrlport_resp_ack), + .s_ctrlport_resp_status (gpio_core_ctrlport_resp_status), + .s_ctrlport_resp_data (gpio_core_ctrlport_resp_data), + .m_ctrlport_req_wr (gpio_core_ctrlport_req_wr_filtered), + .m_ctrlport_req_rd (gpio_core_ctrlport_req_rd_filtered), + .m_ctrlport_req_addr (gpio_core_ctrlport_req_addr_filtered), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (gpio_core_ctrlport_req_data_filtered), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (gpio_core_ctrlport_resp_ack_filtered), + .m_ctrlport_resp_status (gpio_core_ctrlport_resp_status_filtered), + .m_ctrlport_resp_data (gpio_core_ctrlport_resp_data_filtered) + ); + + ctrlport_window #( + .BASE_ADDRESS (BASE_WINDOW_GPIO), + .WINDOW_SIZE (BASE_WINDOW_GPIO_SIZE) + ) gpio_base_window_i ( + .s_ctrlport_req_wr (gpio_base_ctrlport_req_wr_prc), + .s_ctrlport_req_rd (gpio_base_ctrlport_req_rd_prc), + .s_ctrlport_req_addr (gpio_base_ctrlport_req_addr_prc), + .s_ctrlport_req_portid (), + .s_ctrlport_req_rem_epid (), + .s_ctrlport_req_rem_portid (), + .s_ctrlport_req_data (gpio_base_ctrlport_req_data_prc), + .s_ctrlport_req_byte_en (), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack (gpio_base_ctrlport_resp_ack_prc), + .s_ctrlport_resp_status (gpio_base_ctrlport_resp_status_prc), + .s_ctrlport_resp_data (gpio_base_ctrlport_resp_data_prc), + .m_ctrlport_req_wr (gpio_base_ctrlport_req_wr_filtered_prc), + .m_ctrlport_req_rd (gpio_base_ctrlport_req_rd_filtered_prc), + .m_ctrlport_req_addr (gpio_base_ctrlport_req_addr_filtered_prc), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (gpio_base_ctrlport_req_data_filtered_prc), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (gpio_base_ctrlport_resp_ack_filtered_prc), + .m_ctrlport_resp_status (gpio_base_ctrlport_resp_status_filtered_prc), + .m_ctrlport_resp_data (gpio_base_ctrlport_resp_data_filtered_prc) + ); + + wire [19:0] spi_core_ctrlport_req_addr_prc; + wire [31:0] spi_core_ctrlport_req_data_prc; + wire spi_core_ctrlport_req_rd_prc; + wire spi_core_ctrlport_req_wr_prc; + wire spi_core_ctrlport_resp_ack_prc; + wire [31:0] spi_core_ctrlport_resp_data_prc; + wire [1:0] spi_core_ctrlport_resp_status_prc; + + ctrlport_clk_cross core_clk_cross_i ( + .rst (ctrlport_rst_prc), + .s_ctrlport_clk (clk_int_osc), + .s_ctrlport_req_wr (spi_core_ctrlport_req_wr_filtered_osc), + .s_ctrlport_req_rd (spi_core_ctrlport_req_rd_filtered_osc), + .s_ctrlport_req_addr (spi_core_ctrlport_req_addr_filtered_osc), + .s_ctrlport_req_portid (), + .s_ctrlport_req_rem_epid (), + .s_ctrlport_req_rem_portid (), + .s_ctrlport_req_data (spi_core_ctrlport_req_data_filtered_osc), + .s_ctrlport_req_byte_en (), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack (spi_core_ctrlport_resp_ack_filtered_osc), + .s_ctrlport_resp_status (spi_core_ctrlport_resp_status_filtered_osc), + .s_ctrlport_resp_data (spi_core_ctrlport_resp_data_filtered_osc), + .m_ctrlport_clk (pll_ref_clk), + .m_ctrlport_req_wr (spi_core_ctrlport_req_wr_prc), + .m_ctrlport_req_rd (spi_core_ctrlport_req_rd_prc), + .m_ctrlport_req_addr (spi_core_ctrlport_req_addr_prc), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (spi_core_ctrlport_req_data_prc), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (spi_core_ctrlport_resp_ack_prc), + .m_ctrlport_resp_status (spi_core_ctrlport_resp_status_prc), + .m_ctrlport_resp_data (spi_core_ctrlport_resp_data_prc) + ); + + wire [19:0] gpio_base_ctrlport_req_addr_osc; + wire [31:0] gpio_base_ctrlport_req_data_osc; + wire gpio_base_ctrlport_req_rd_osc; + wire gpio_base_ctrlport_req_wr_osc; + wire gpio_base_ctrlport_resp_ack_osc; + wire [31:0] gpio_base_ctrlport_resp_data_osc; + wire [1:0] gpio_base_ctrlport_resp_status_osc; + + ctrlport_clk_cross base_clk_cross_i ( + .rst (ctrlport_rst_osc), + .s_ctrlport_clk (pll_ref_clk), + .s_ctrlport_req_wr (gpio_base_ctrlport_req_wr_filtered_prc), + .s_ctrlport_req_rd (gpio_base_ctrlport_req_rd_filtered_prc), + .s_ctrlport_req_addr (gpio_base_ctrlport_req_addr_filtered_prc), + .s_ctrlport_req_portid (), + .s_ctrlport_req_rem_epid (), + .s_ctrlport_req_rem_portid (), + .s_ctrlport_req_data (gpio_base_ctrlport_req_data_filtered_prc), + .s_ctrlport_req_byte_en (), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack (gpio_base_ctrlport_resp_ack_filtered_prc), + .s_ctrlport_resp_status (gpio_base_ctrlport_resp_status_filtered_prc), + .s_ctrlport_resp_data (gpio_base_ctrlport_resp_data_filtered_prc), + .m_ctrlport_clk (clk_int_osc), + .m_ctrlport_req_wr (gpio_base_ctrlport_req_wr_osc), + .m_ctrlport_req_rd (gpio_base_ctrlport_req_rd_osc), + .m_ctrlport_req_addr (gpio_base_ctrlport_req_addr_osc), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (gpio_base_ctrlport_req_data_osc), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (gpio_base_ctrlport_resp_ack_osc), + .m_ctrlport_resp_status (gpio_base_ctrlport_resp_status_osc), + .m_ctrlport_resp_data (gpio_base_ctrlport_resp_data_osc) + ); + + wire [19:0] reconfig_ctrlport_req_addr_crc; + wire [31:0] reconfig_ctrlport_req_data_crc; + wire reconfig_ctrlport_req_rd_crc; + wire reconfig_ctrlport_req_wr_crc; + wire reconfig_ctrlport_resp_ack_crc; + wire [31:0] reconfig_ctrlport_resp_data_crc; + wire [1:0] reconfig_ctrlport_resp_status_crc; + + ctrlport_clk_cross reconfig_cross_i ( + .rst (ctrlport_rst_crc), + .s_ctrlport_clk (clk_int_osc), + .s_ctrlport_req_wr (reconfig_ctrlport_req_wr_filtered_osc), + .s_ctrlport_req_rd (reconfig_ctrlport_req_rd_filtered_osc), + .s_ctrlport_req_addr (reconfig_ctrlport_req_addr_filtered_osc), + .s_ctrlport_req_portid (), + .s_ctrlport_req_rem_epid (), + .s_ctrlport_req_rem_portid (), + .s_ctrlport_req_data (reconfig_ctrlport_req_data_filtered_osc), + .s_ctrlport_req_byte_en (), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack (reconfig_ctrlport_resp_ack_filtered_osc), + .s_ctrlport_resp_status (reconfig_ctrlport_resp_status_filtered_osc), + .s_ctrlport_resp_data (reconfig_ctrlport_resp_data_filtered_osc), + .m_ctrlport_clk (CTRL_REG_CLK), + .m_ctrlport_req_wr (reconfig_ctrlport_req_wr_crc), + .m_ctrlport_req_rd (reconfig_ctrlport_req_rd_crc), + .m_ctrlport_req_addr (reconfig_ctrlport_req_addr_crc), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (reconfig_ctrlport_req_data_crc), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (reconfig_ctrlport_resp_ack_crc), + .m_ctrlport_resp_status (reconfig_ctrlport_resp_status_crc), + .m_ctrlport_resp_data (reconfig_ctrlport_resp_data_crc) + ); + + wire [19:0] core_ctrlport_req_addr; + wire [31:0] core_ctrlport_req_data; + wire core_ctrlport_req_rd; + wire core_ctrlport_req_wr; + wire core_ctrlport_resp_ack; + wire [31:0] core_ctrlport_resp_data; + wire [1:0] core_ctrlport_resp_status; + + ctrlport_combiner #( + .NUM_MASTERS (2), + .PRIORITY (1) + ) core_combiner_i ( + .ctrlport_clk (pll_ref_clk), + .ctrlport_rst (ctrlport_rst_prc), + .s_ctrlport_req_wr ({spi_core_ctrlport_req_wr_prc, gpio_core_ctrlport_req_wr_filtered}), + .s_ctrlport_req_rd ({spi_core_ctrlport_req_rd_prc, gpio_core_ctrlport_req_rd_filtered}), + .s_ctrlport_req_addr ({spi_core_ctrlport_req_addr_prc, gpio_core_ctrlport_req_addr_filtered}), + .s_ctrlport_req_portid (), + .s_ctrlport_req_rem_epid (), + .s_ctrlport_req_rem_portid (), + .s_ctrlport_req_data ({spi_core_ctrlport_req_data_prc, gpio_core_ctrlport_req_data_filtered}), + .s_ctrlport_req_byte_en (), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack ({spi_core_ctrlport_resp_ack_prc, gpio_core_ctrlport_resp_ack_filtered}), + .s_ctrlport_resp_status ({spi_core_ctrlport_resp_status_prc, gpio_core_ctrlport_resp_status_filtered}), + .s_ctrlport_resp_data ({spi_core_ctrlport_resp_data_prc, gpio_core_ctrlport_resp_data_filtered}), + .m_ctrlport_req_wr (core_ctrlport_req_wr), + .m_ctrlport_req_rd (core_ctrlport_req_rd), + .m_ctrlport_req_addr (core_ctrlport_req_addr), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (core_ctrlport_req_data), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (core_ctrlport_resp_ack), + .m_ctrlport_resp_status (core_ctrlport_resp_status), + .m_ctrlport_resp_data (core_ctrlport_resp_data) + ); + + wire [19:0] base_ctrlport_req_addr; + wire [31:0] base_ctrlport_req_data; + wire base_ctrlport_req_rd; + wire base_ctrlport_req_wr; + wire base_ctrlport_resp_ack; + wire [31:0] base_ctrlport_resp_data; + wire [1:0] base_ctrlport_resp_status; + + ctrlport_combiner #( + .NUM_MASTERS (2), + .PRIORITY (1) + ) base_combiner_i ( + .ctrlport_clk (clk_int_osc), + .ctrlport_rst (ctrlport_rst_osc), + .s_ctrlport_req_wr ({spi_base_ctrlport_req_wr_filtered, gpio_base_ctrlport_req_wr_osc}), + .s_ctrlport_req_rd ({spi_base_ctrlport_req_rd_filtered, gpio_base_ctrlport_req_rd_osc}), + .s_ctrlport_req_addr ({spi_base_ctrlport_req_addr_filtered, gpio_base_ctrlport_req_addr_osc}), + .s_ctrlport_req_portid (), + .s_ctrlport_req_rem_epid (), + .s_ctrlport_req_rem_portid (), + .s_ctrlport_req_data ({spi_base_ctrlport_req_data_filtered, gpio_base_ctrlport_req_data_osc}), + .s_ctrlport_req_byte_en (), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack ({spi_base_ctrlport_resp_ack_filtered, gpio_base_ctrlport_resp_ack_osc}), + .s_ctrlport_resp_status ({spi_base_ctrlport_resp_status_filtered, gpio_base_ctrlport_resp_status_osc}), + .s_ctrlport_resp_data ({spi_base_ctrlport_resp_data_filtered, gpio_base_ctrlport_resp_data_osc}), + .m_ctrlport_req_wr (base_ctrlport_req_wr), + .m_ctrlport_req_rd (base_ctrlport_req_rd), + .m_ctrlport_req_addr (base_ctrlport_req_addr), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (base_ctrlport_req_data), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (base_ctrlport_resp_ack), + .m_ctrlport_resp_status (base_ctrlport_resp_status), + .m_ctrlport_resp_data (base_ctrlport_resp_data) + ); + + ///////////////////////////////////////////////////////////////////////////// + // ControlPort targets + ///////////////////////////////////////////////////////////////////////////// + // ATR FPGA status input register + reg [3:0] atr_fpga_state = 4'b0; + always @(posedge pll_ref_clk) begin + atr_fpga_state <= MB_FPGA_GPIO[3:0]; + end + + // Local signals to be fanned-out to all SPI slaves. + wire lo_sclk; + wire lo_mosi; + + wire [7:0] lo_miso; + wire [7:0] lo_csb; + + // Check for same DB_CONTROL_WINDOW offset for SPI and GPIO + // assert for MAX_BITS + generate + if (DB_CONTROL_WINDOW_GPIO != DB_CONTROL_WINDOW_SPI) begin + DB_CONTROL_WINDOW_offsets_must_be_equal check_db_control_window(); + end + if (BASE_WINDOW_GPIO != BASE_WINDOW_SPI) begin + BASE_WINDOW_offsets_must_be_equal check_base_window(); + end + endgenerate + + zbx_cpld_core #( + .BASE_ADDRESS(DB_CONTROL_WINDOW_GPIO) + ) zbx_cpld_core_i ( + .s_ctrlport_req_wr (core_ctrlport_req_wr), + .s_ctrlport_req_rd (core_ctrlport_req_rd), + .s_ctrlport_req_addr (core_ctrlport_req_addr), + .s_ctrlport_req_data (core_ctrlport_req_data), + .s_ctrlport_resp_ack (core_ctrlport_resp_ack), + .s_ctrlport_resp_status (core_ctrlport_resp_status), + .s_ctrlport_resp_data (core_ctrlport_resp_data), + .ctrlport_clk (pll_ref_clk), + .ctrlport_rst (ctrlport_rst_prc), + .atr_fpga_state (atr_fpga_state), + .lo_miso (lo_miso), + .lo_csb (lo_csb), + .lo_sclk (lo_sclk), + .lo_mosi (lo_mosi), + .mb_synth_sync (MB_SYNTH_SYNC), + .tx0_lo1_sync (TX0_LO1_SYNC), + .tx0_lo2_sync (TX0_LO2_SYNC), + .tx1_lo1_sync (TX1_LO1_SYNC), + .tx1_lo2_sync (TX1_LO2_SYNC), + .rx0_lo1_sync (RX0_LO1_SYNC), + .rx0_lo2_sync (RX0_LO2_SYNC), + .rx1_lo1_sync (RX1_LO1_SYNC), + .rx1_lo2_sync (RX1_LO2_SYNC), + .tx0_sw1_sw2_ctrl (TX0_SW1_SW2_CTRL), + .tx0_sw3_a (TX0_SW3_A), + .tx0_sw3_b (TX0_SW3_B), + .tx0_sw4_a (TX0_SW4_A), + .tx0_sw4_b (TX0_SW4_B), + .tx0_sw5_a (TX0_SW5_A), + .tx0_sw5_b (TX0_SW5_B), + .tx0_sw6_a (TX0_SW6_A), + .tx0_sw6_b (TX0_SW6_B), + .tx0_sw7_a (TX0_SW7_A), + .tx0_sw7_b (TX0_SW7_B), + .tx0_sw8_v1 (TX0_SW8_V1), + .tx0_sw8_v2 (TX0_SW8_V2), + .tx0_sw8_v3 (TX0_SW8_V3), + .tx0_sw9_a (TX0_SW9_A), + .tx0_sw9_b (TX0_SW9_B), + .tx0_sw10_a (TX0_SW10_A), + .tx0_sw10_b (TX0_SW10_B), + .tx0_sw11_a (TX0_SW11_A), + .tx0_sw11_b (TX0_SW11_B), + .tx0_sw13_v1 (TX0_SW13_V1), + .tx0_sw14_v1 (TX0_SW14_V1), + .tx0_dsa1 (TX0_DSA1), + .tx0_dsa2 (TX0_DSA2), + .tx1_sw1_sw2_ctrl (TX1_SW1_SW2_CTRL), + .tx1_sw3_a (TX1_SW3_A), + .tx1_sw3_b (TX1_SW3_B), + .tx1_sw4_a (TX1_SW4_A), + .tx1_sw4_b (TX1_SW4_B), + .tx1_sw5_a (TX1_SW5_A), + .tx1_sw5_b (TX1_SW5_B), + .tx1_sw6_a (TX1_SW6_A), + .tx1_sw6_b (TX1_SW6_B), + .tx1_sw7_a (TX1_SW7_A), + .tx1_sw7_b (TX1_SW7_B), + .tx1_sw8_v1 (TX1_SW8_V1), + .tx1_sw8_v2 (TX1_SW8_V2), + .tx1_sw8_v3 (TX1_SW8_V3), + .tx1_sw9_a (TX1_SW9_A), + .tx1_sw9_b (TX1_SW9_B), + .tx1_sw10_a (TX1_SW10_A), + .tx1_sw10_b (TX1_SW10_B), + .tx1_sw11_a (TX1_SW11_A), + .tx1_sw11_b (TX1_SW11_B), + .tx1_sw13_v1 (TX1_SW13_V1), + .tx1_sw14_v1 (TX1_SW14_V1), + .tx1_dsa1 (TX1_DSA1), + .tx1_dsa2 (TX1_DSA2), + .rx0_sw1_a (RX0_SW1_A), + .rx0_sw1_b (RX0_SW1_B), + .rx0_sw2_a (RX0_SW2_A), + .rx0_sw3_v1 (RX0_SW3_V1), + .rx0_sw3_v2 (RX0_SW3_V2), + .rx0_sw3_v3 (RX0_SW3_V3), + .rx0_sw4_a (RX0_SW4_A), + .rx0_sw5_a (RX0_SW5_A), + .rx0_sw5_b (RX0_SW5_B), + .rx0_sw6_a (RX0_SW6_A), + .rx0_sw6_b (RX0_SW6_B), + .rx0_sw7_sw8_ctrl (RX0_SW7_SW8_CTRL), + .rx0_sw9_v1 (RX0_SW9_V1), + .rx0_sw10_v1 (RX0_SW10_V1), + .rx0_sw11_v3 (RX0_SW11_V3), + .rx0_sw11_v2 (RX0_SW11_V2), + .rx0_sw11_v1 (RX0_SW11_V1), + .rx0_dsa1_n (RX0_DSA1_n), + .rx0_dsa2_n (RX0_DSA2_n), + .rx0_dsa3_a_n (RX0_DSA3_A_n), + .rx0_dsa3_b_n (RX0_DSA3_B_n), + .rx1_sw1_a (RX1_SW1_A), + .rx1_sw1_b (RX1_SW1_B), + .rx1_sw2_a (RX1_SW2_A), + .rx1_sw3_v1 (RX1_SW3_V1), + .rx1_sw3_v2 (RX1_SW3_V2), + .rx1_sw3_v3 (RX1_SW3_V3), + .rx1_sw4_a (RX1_SW4_A), + .rx1_sw5_a (RX1_SW5_A), + .rx1_sw5_b (RX1_SW5_B), + .rx1_sw6_a (RX1_SW6_A), + .rx1_sw6_b (RX1_SW6_B), + .rx1_sw7_sw8_ctrl (RX1_SW7_SW8_CTRL), + .rx1_sw9_v1 (RX1_SW9_V1), + .rx1_sw10_v1 (RX1_SW10_V1), + .rx1_sw11_v3 (RX1_SW11_V3), + .rx1_sw11_v2 (RX1_SW11_V2), + .rx1_sw11_v1 (RX1_SW11_V1), + .rx1_dsa1_n (RX1_DSA1_n), + .rx1_dsa2_n (RX1_DSA2_n), + .rx1_dsa3_a_n (RX1_DSA3_A_n), + .rx1_dsa3_b_n (RX1_DSA3_B_n), + .ch0_rx2_led (CH0_RX2_LED), + .ch0_tx_led (CH0_TX_LED), + .ch0_rx_led (CH0_RX_LED), + .ch1_rx2_led (CH1_RX2_LED), + .ch1_tx_led (CH1_TX_LED), + .ch1_rx_led (CH1_RX_LED) + ); + + ///////////////////////////////////////////////////////////////////////////// + // Base registers + ///////////////////////////////////////////////////////////////////////////// + + basic_regs #( + .BASE_ADDRESS (BASE_WINDOW_SPI), + .SIZE_ADDRESS (BASE_WINDOW_SPI_SIZE) + ) basic_regs_i ( + .s_ctrlport_req_wr (base_ctrlport_req_wr), + .s_ctrlport_req_rd (base_ctrlport_req_rd), + .s_ctrlport_req_addr (base_ctrlport_req_addr), + .s_ctrlport_req_data (base_ctrlport_req_data), + .s_ctrlport_resp_ack (base_ctrlport_resp_ack), + .s_ctrlport_resp_status (base_ctrlport_resp_status), + .s_ctrlport_resp_data (base_ctrlport_resp_data), + .ctrlport_clk (clk_int_osc), + .ctrlport_rst (ctrlport_rst_osc) + ); + + ///////////////////////////////////////////////////////////////////////////// + // Power registers + ///////////////////////////////////////////////////////////////////////////// + + power_regs #( + .BASE_ADDRESS (POWER_REGS), + .SIZE_ADDRESS (POWER_REGS_SIZE) + ) power_regs_i ( + .s_ctrlport_req_wr (power_ctrlport_req_wr), + .s_ctrlport_req_rd (power_ctrlport_req_rd), + .s_ctrlport_req_addr (power_ctrlport_req_addr), + .s_ctrlport_req_data (power_ctrlport_req_data), + .s_ctrlport_resp_ack (power_ctrlport_resp_ack), + .s_ctrlport_resp_status (power_ctrlport_resp_status), + .s_ctrlport_resp_data (power_ctrlport_resp_data), + .ctrlport_clk (clk_int_osc), + .ctrlport_rst (ctrlport_rst_osc), + .enable_tx_7v0 (P7V_ENABLE_A), + .enable_rx_7v0 (P7V_ENABLE_B), + .enable_3v3 (P3D3VA_ENABLE), + .p7v_pg_b (P7V_PG_B), + .p7v_pg_a (P7V_PG_A), + .pll_ref_clk_enable (pll_ref_clk_enable_osc) + ); + + ///////////////////////////////////////////////////////////////////////////// + // Reconfiguration + ///////////////////////////////////////////////////////////////////////////// + // on chip flash interface + // (naming according to Avalon Memory-Mapped Interfaces - + // https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf) + wire csr_addr; + wire csr_read; + wire [31:0] csr_readdata; + wire csr_write; + wire [31:0] csr_writedata; + wire [16:0] data_addr; + wire data_read; + wire [31:0] data_readdata; + wire data_readdatavalid; + wire data_waitrequest; + wire data_write; + wire [31:0] data_writedata; + // reset + wire ctrlport_rst_crc_n; + + assign ctrlport_rst_crc_n = ~ctrlport_rst_crc; + + on_chip_flash flash_i ( + .clock (CTRL_REG_CLK), + .avmm_csr_addr (csr_addr), + .avmm_csr_read (csr_read), + .avmm_csr_writedata (csr_writedata), + .avmm_csr_write (csr_write), + .avmm_csr_readdata (csr_readdata), + .avmm_data_addr (data_addr), + .avmm_data_read (data_read), + .avmm_data_writedata (data_writedata), + .avmm_data_write (data_write), + .avmm_data_readdata (data_readdata), + .avmm_data_waitrequest (data_waitrequest), + .avmm_data_readdatavalid (data_readdatavalid), + .avmm_data_burstcount (4'b0001), + .reset_n (ctrlport_rst_crc_n) + ); + + reconfig_engine #( + .BASE_ADDRESS (RECONFIG), + .NUM_ADDRESSES (RECONFIG_SIZE), + .MEM_INIT (1) + ) reconfig_engine_i ( + .ctrlport_clk (CTRL_REG_CLK), + .ctrlport_rst (ctrlport_rst_crc), + .s_ctrlport_req_wr (reconfig_ctrlport_req_wr_crc), + .s_ctrlport_req_rd (reconfig_ctrlport_req_rd_crc), + .s_ctrlport_req_addr (reconfig_ctrlport_req_addr_crc), + .s_ctrlport_req_data (reconfig_ctrlport_req_data_crc), + .s_ctrlport_resp_ack (reconfig_ctrlport_resp_ack_crc), + .s_ctrlport_resp_status (reconfig_ctrlport_resp_status_crc), + .s_ctrlport_resp_data (reconfig_ctrlport_resp_data_crc), + .csr_addr (csr_addr), + .csr_read (csr_read), + .csr_writedata (csr_writedata), + .csr_write (csr_write), + .csr_readdata (csr_readdata), + .data_addr (data_addr), + .data_read (data_read), + .data_writedata (data_writedata), + .data_write (data_write), + .data_readdata (data_readdata), + .data_waitrequest (data_waitrequest), + .data_readdatavalid (data_readdatavalid) + ); + + ///////////////////////////////////////////////////////////////////////////// + // LO SPI Break-Out + ///////////////////////////////////////////////////////////////////////////// + + assign TX0_LO1_SCK = lo_sclk; + assign TX0_LO1_SDI = lo_mosi; + assign TX0_LO1_CSB = lo_csb[TX0_LO1]; + assign lo_miso[TX0_LO1] = TX0_LO1_MUXOUT; + + assign TX0_LO2_SCK = lo_sclk; + assign TX0_LO2_SDI = lo_mosi; + assign TX0_LO2_CSB = lo_csb[TX0_LO2]; + assign lo_miso[TX0_LO2] = TX0_LO2_MUXOUT; + + assign TX1_LO1_SCK = lo_sclk; + assign TX1_LO1_SDI = lo_mosi; + assign TX1_LO1_CSB = lo_csb[TX1_LO1]; + assign lo_miso[TX1_LO1] = TX1_LO1_MUXOUT; + + assign TX1_LO2_SCK = lo_sclk; + assign TX1_LO2_SDI = lo_mosi; + assign TX1_LO2_CSB = lo_csb[TX1_LO2]; + assign lo_miso[TX1_LO2] = TX1_LO2_MUXOUT; + + assign RX0_LO1_SCK = lo_sclk; + assign RX0_LO1_SDI = lo_mosi; + assign RX0_LO1_CSB = lo_csb[RX0_LO1]; + assign lo_miso[RX0_LO1] = RX0_LO1_MUXOUT; + + assign RX0_LO2_SCK = lo_sclk; + assign RX0_LO2_SDI = lo_mosi; + assign RX0_LO2_CSB = lo_csb[RX0_LO2]; + assign lo_miso[RX0_LO2] = RX0_LO2_MUXOUT; + + assign RX1_LO1_SCK = lo_sclk; + assign RX1_LO1_SDI = lo_mosi; + assign RX1_LO1_CSB = lo_csb[RX1_LO1]; + assign lo_miso[RX1_LO1] = RX1_LO1_MUXOUT; + + assign RX1_LO2_SCK = lo_sclk; + assign RX1_LO2_SDI = lo_mosi; + assign RX1_LO2_CSB = lo_csb[RX1_LO2]; + assign lo_miso[RX1_LO2] = RX1_LO2_MUXOUT; + +endmodule + +`default_nettype wire + +//XmlParse xml_on +// +// +// +// This section lists all common communication interfaces of the ZBX CPLD. +// Each input port will point to a regmap. The SPI port can reach out to +// each register. The GPIO port can access a subset of all register, where +// the use case is mainly RF configuration to enable fast changes. +// +// +// +// Controlport requests from this SPI interface are driven by the PL part +// of the RFSoC via the MB CPLD. +// +// +// +// +// Controlport requests from the FPGA GPIO lines. +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// Windows need to be without gaps to guarantee response to combiners. +// +// +// Extended original size of 0x20 to fill gap to next window. +// +// +// Extended original size of 0x400 to fill gap to next window. +// +// +// +// +// +//XmlParse xml_off -- cgit v1.2.3