From 8622a8013a429674de59cbff522b2722c8afa449 Mon Sep 17 00:00:00 2001
From: Wade Fife <wade.fife@ettus.com>
Date: Tue, 18 Aug 2020 12:02:44 -0500
Subject: fpga: e31x: Change RFNoC Ctrl clock to 40 MHz
---
fpga/usrp3/top/e31x/e31x.v | 1 +
fpga/usrp3/top/e31x/e31x_core.v | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
(limited to 'fpga')
diff --git a/fpga/usrp3/top/e31x/e31x.v b/fpga/usrp3/top/e31x/e31x.v
index 7aece6191..b303f9a91 100644
--- a/fpga/usrp3/top/e31x/e31x.v
+++ b/fpga/usrp3/top/e31x/e31x.v
@@ -849,6 +849,7 @@ module e31x (
.radio_rst(radio_rst),
.bus_clk(bus_clk),
.bus_rst(bus_rst),
+ .clk40(clk40),
// Clocking and PPS Controls/Indicators
.pps_refclk(pps),
diff --git a/fpga/usrp3/top/e31x/e31x_core.v b/fpga/usrp3/top/e31x/e31x_core.v
index 132129ae9..6e1d2ed80 100644
--- a/fpga/usrp3/top/e31x/e31x_core.v
+++ b/fpga/usrp3/top/e31x/e31x_core.v
@@ -34,6 +34,7 @@ module e31x_core #(
input wire radio_rst,
input wire bus_clk,
input wire bus_rst,
+ input wire clk40,
// Motherboard Registers: AXI lite interface
input wire s_axi_aclk,
@@ -666,7 +667,7 @@ module e31x_core #(
.PROTOVER(RFNOC_PROTOVER)
) rfnoc_image_core_i (
.chdr_aclk (bus_clk ),
- .ctrl_aclk (bus_clk ), //TODO: X310 uses bus_clk_div2. we can also reduce it here.
+ .ctrl_aclk (clk40 ),
.core_arst (bus_rst ),
.device_id (device_id ),
.radio_clk (radio_clk ),
--
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