From 82b0acb3ac8ecf495bcbbc9476968c54773f8cdc Mon Sep 17 00:00:00 2001
From: Wade Fife <wade.fife@ettus.com>
Date: Fri, 4 Jun 2021 13:54:30 -0500
Subject: fpga: ci: Add testbench pipeline

---
 fpga/.ci/hwtools/root.py     | 32 +++++++++++++++++++
 fpga/.ci/oss_testbenches.yml | 74 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 106 insertions(+)
 create mode 100644 fpga/.ci/hwtools/root.py
 create mode 100644 fpga/.ci/oss_testbenches.yml

(limited to 'fpga')

diff --git a/fpga/.ci/hwtools/root.py b/fpga/.ci/hwtools/root.py
new file mode 100644
index 000000000..082676df7
--- /dev/null
+++ b/fpga/.ci/hwtools/root.py
@@ -0,0 +1,32 @@
+#!/usr/bin/env python
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#
+#   Setup script for configuring the pipeline agent's environment to allow us
+#   to run proprietary EDA vendor tools.
+#
+
+import sys
+
+def do_setup():
+    from rootapiclass import rootapi
+
+    rootapi.set_workspace_name(name="uhddev", pretty_name="UHD FPGA")
+    rootapi.set_major_version("1")
+
+    rootapi.add_tool(name="hwtools", version="head")
+    rootapi.add_tool(name="Vivado",   version="2019.1", allowlater=False)
+    rootapi.add_tool(name="modelsim", version="2020.4", allowlater=True)
+
+def do_finish():
+    pass
+
+def do_publish():
+    pass
+
+if __name__ == "__main__":
+    sys.exit(-1)
diff --git a/fpga/.ci/oss_testbenches.yml b/fpga/.ci/oss_testbenches.yml
new file mode 100644
index 000000000..f4a01edbc
--- /dev/null
+++ b/fpga/.ci/oss_testbenches.yml
@@ -0,0 +1,74 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#
+#   This pipeline is used to run all the testbenches using ModelSim.
+#
+
+trigger:
+- none
+
+pr:
+  branches:
+    include:
+    - master
+  paths:
+    include:
+    - fpga/usrp3/lib
+    - fpga/usrp3/tools
+    - fpga/usrp3/top
+    - fpga/usrp3/sim
+    - fpga/.ci
+
+resources:
+  repositories:
+  - repository: hwtools
+    type: git
+    ref: main
+    name: DevCentral/hwtools
+
+name:
+jobs:
+- job:
+  displayName: "ModelSim Simulation"
+  timeoutInMinutes: 360
+  pool:
+    name: Hardware
+  steps:
+    - checkout: self
+      clean: true
+      persistCredentials: true
+
+    - checkout: hwtools
+      clean: true
+      path: s/hwtools/head
+      persistCredentials: true
+
+    - bash: |
+        set -e
+
+        echo "---- Set environment variables ----"
+        export path_hwtools=$(Pipeline.Workspace)/s/hwtools/head/setup
+        export PATH=$path_hwtools:$PATH
+
+        echo "---- Run hwsetup ----"
+        # This script sets the XILINX_VIVADO, MODELSIM, and LIB_BASE_PATH
+        # variables based on the agent's configuration so we can find the EDA
+        # tools.
+        pushd ../.ci/hwtools
+        source hwsetup.sh
+        popd
+
+        echo "---- Run setupenv ----"
+        export MSIM_VIV_COMPLIBDIR=$LIB_BASE_PATH/vivado/2019.1.1/modelsim_SE-64_2020
+        source ./top/x300/setupenv.sh --vivado-path $(dirname $XILINX_VIVADO) --modelsim-path $(dirname $MODELSIM)
+
+        echo "---- Run testbenches ----"
+        pushd ./tools/utils
+        python3 ./run_testbenches.py --logged --simulator modelsim --excludes=modelsim.excludes -j2 run
+        popd
+      workingDirectory: uhddev/fpga/usrp3
+      displayName: "Run Testbenches"
-- 
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