From 739b37ba40e7aba288ed781922aa8fa3b1bfc16e Mon Sep 17 00:00:00 2001
From: Humberto Jimenez <humberto.jimenez@ni.com>
Date: Wed, 17 Nov 2021 16:33:28 -0600
Subject: fpga: n3xx: rh: cpld: Refactor CPLD build process

---
 fpga/usrp3/top/n3xx/dboards/rh/cpld/.gitignore     |   7 +
 fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile       |  81 +++++-
 .../top/n3xx/dboards/rh/cpld/Makefile.cpld.inc     |  36 +++
 .../n3xx/dboards/rh/cpld/quartus/rhodium_top.qpf   |  31 +++
 .../n3xx/dboards/rh/cpld/quartus/rhodium_top.qsf   | 307 +++++++++++++++++++++
 .../usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf |  31 ---
 .../usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf | 306 --------------------
 fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v  |   4 +-
 8 files changed, 449 insertions(+), 354 deletions(-)
 create mode 100644 fpga/usrp3/top/n3xx/dboards/rh/cpld/.gitignore
 create mode 100644 fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile.cpld.inc
 create mode 100644 fpga/usrp3/top/n3xx/dboards/rh/cpld/quartus/rhodium_top.qpf
 create mode 100644 fpga/usrp3/top/n3xx/dboards/rh/cpld/quartus/rhodium_top.qsf
 delete mode 100644 fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf
 delete mode 100644 fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf

(limited to 'fpga')

diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/.gitignore b/fpga/usrp3/top/n3xx/dboards/rh/cpld/.gitignore
new file mode 100644
index 000000000..fcdcdf540
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/.gitignore
@@ -0,0 +1,7 @@
+# Ignore Quartus generated files upon project opening.
+*.qws
+db/
+incremental_db/
+output_files/
+*.sopcinfo
+build/
diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile b/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile
index ff1598894..c71d49052 100644
--- a/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile
+++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile
@@ -1,27 +1,78 @@
 #
-# Copyright 2018 Ettus Research, a National Instruments Company
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
 #
 
-.PHONY: all clean
+# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
+##-------------------
+##USRP N32x CPLD Help
+##-------------------
+##Usage:
+## make <Targets> <Options>
+##
+##Output:
+## build/usrp_n320_rh_cpld.pof:  Bitstream to use with JTAG programmer
+## build/usrp_n320_rh_cpld.svf:  Bitstream to use with PS JTAG engine
 
-SRCS=rhodium_top.qpf rhodium_top.qsf rhodium_top.sdc rhodium_top.v rhodium_gain_ctrl.v rhodium_gain_table.v rhodium_lo_gain.v
-SIM_SRCS=rh_tb.v rhodium_top.v rhodium_gain_ctrl.v rhodium_gain_table.v rhodium_lo_gain.v
-SHORT_HASH=$(addprefix GIT_HASH=,$(shell ../../../../../tools/scripts/git-hash.sh))
+# Definitions
+10M04_ID = "10M04SAU169I7G"
+
+TARGET = bin
+TOP ?= rhodium_top
+
+# quartus_build($1=Device, $2=Definitions)
+quartus_build = make -f Makefile.cpld.inc $(TARGET) NAME=$@ ARCH="MAX10" PART_ID="$1" $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
+
+# post_build($1=Artifact Name)
+ifeq ($(TARGET),bin)
+	post_build = @\
+		mkdir -p build/; \
+		echo "Exporting bitstream files..."; \
+		cp build-$@/output_files/$(TOP).pof                      build/$(1).pof; \
+		cp build-$@/output_files/$(TOP).svf                      build/$(1).svf; \
+		echo -ne "\n\n---- Make: CPLD ready!\n"; \
+		echo -ne "     Use build/$(1).pof via JTAG programmer or\n"; \
+		echo -ne "         build/$(1).svf via PS JTAG-engine\n";
+else
+	post_build = @echo "Skipping bitfile export."
+endif
+
+##
+##Supported Targets
+##-----------------
 
-all: cpld-rhodium-revb.svf
+all:              N320_CPLD_10M04 ##(Default target)
 
-output_files/rhodium_top.pof: $(SRCS)
-	quartus_map rhodium_top --verilog_macro="$(SHORT_HASH)"
-	quartus_fit rhodium_top
-	quartus_asm rhodium_top
-	quartus_sta rhodium_top
+##N320_CPLD_10M04:  N320/1 CPLD targeted to 10M04SAU169I7G.
+N320_CPLD_10M04:
+	$(call quartus_build,$(10M04_ID),$(DEFS))
+	$(call post_build,"usrp_n320_rh_cpld")
 
-cpld-rhodium-revb.svf: output_files/rhodium_top.pof
-	quartus_cpf --convert --frequency 10.0MHz --voltage 2.5 --operation p $? $@
+clean:            ##Clean up all target build outputs.
+	@echo -ne "\nCleaning targets and git repo...\n";
+	@rm -rf build-N320_CPLD*
+	@rm -rf build
+	@git clean -Xdf
 
-clean:
-	rm -rf db incremental_db output_files simulation cpld-rhodium-revb.svf
+cleanall:         ##Clean up all target and ip build outputs.
+	@echo -ne "\nCleaning targets, IP, and git repo...\n";
+	@rm -rf build-N320_CPLD*
+	@rm -rf build
+	@rm -rf build-ip
+	@git clean -Xdf
+
+help:             ##Show this help message.
+	@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
+
+
+SIM_SRCS=rh_tb.v rhodium_top.v rhodium_gain_ctrl.v rhodium_gain_table.v rhodium_lo_gain.v
 
 a.out: $(SIM_SRCS)
 	iverilog -tvvp -D$(SHORT_HASH) -s rh_tb $(SIM_SRCS)
 
+
+##
+##Supported Options
+##-----------------
+##
diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile.cpld.inc b/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile.cpld.inc
new file mode 100644
index 000000000..aa2a1c325
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile.cpld.inc
@@ -0,0 +1,36 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# Project Setup
+##################################################
+# TOP_MODULE = <Input arg>
+# NAME = <Input arg>
+# PART_ID = <Input arg>
+# ARCH = <Input arg>
+
+##################################################
+# Include other makefiles
+##################################################
+
+PROJECT_DIR = $(abspath .)
+BASE_DIR = $(abspath ../../../..)
+include $(BASE_DIR)/../tools/make/quartus_design_builder.mak
+
+# Define VERILOG_DEFS for macros definition
+VERILOG_DEFS=$(EXTRA_DEFS) $(GIT_HASH_VERILOG_DEF)
+
+bin: .prereqs
+	$(call BUILD_QUARTUS_DESIGN,$(TOP_MODULE),$(ARCH),$(PART_ID),$(PROJECT_DIR),$(BUILD_DIR),,0)
+	@\
+	pushd $(BUILD_DIR); \
+	echo "Converting bitfile to svf format..."; \
+	quartus_cpf --convert \
+		--frequency 10.0MHz \
+		--voltage 2.5       \
+		--operation p       \
+		output_files/$(TOP_MODULE).pof output_files/$(TOP_MODULE).svf; \
+	popd;
diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/quartus/rhodium_top.qpf b/fpga/usrp3/top/n3xx/dboards/rh/cpld/quartus/rhodium_top.qpf
new file mode 100644
index 000000000..5e1bf4d57
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/quartus/rhodium_top.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Intel and sold by Intel or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition
+# Date created = 08:22:34  September 13, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "17.0"
+DATE = "08:22:34  September 13, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "rhodium_top"
diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/quartus/rhodium_top.qsf b/fpga/usrp3/top/n3xx/dboards/rh/cpld/quartus/rhodium_top.qsf
new file mode 100644
index 000000000..4e4ce9e88
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/quartus/rhodium_top.qsf
@@ -0,0 +1,307 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Intel and sold by Intel or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition
+# Date created = 08:22:34  September 13, 2017
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		rhodium_top_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "MAX 10"
+set_global_assignment -name DEVICE 10M04SAU169I7G
+set_global_assignment -name TOP_LEVEL_ENTITY rhodium_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.2
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:22:34  SEPTEMBER 13, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_location_assignment PIN_D11 -to CPLD_PS_SPI_LE_25
+set_location_assignment PIN_F13 -to CPLD_PS_SPI_CLK_25
+set_location_assignment PIN_E10 -to CPLD_PS_ADDR0_25
+set_location_assignment PIN_A12 -to CPLD_PS_ADDR1_25
+set_location_assignment PIN_F12 -to CPLD_PS_SPI_SDI_25
+set_location_assignment PIN_F10 -to CPLD_PS_SPI_SDO_25
+set_location_assignment PIN_B1 -to ADC_A_Over_Range_18
+set_location_assignment PIN_D1 -to ADC_B_Over_Range_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_A_Over_Range_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_B_Over_Range_18
+set_instance_assignment -name IO_STANDARD LVDS -to LO_SYNC
+set_location_assignment PIN_G9 -to LO_SYNC
+set_location_assignment PIN_G10 -to "LO_SYNC(n)"
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_CS_L_18
+set_location_assignment PIN_C2 -to ADC_SPI_CS_L_18
+set_location_assignment PIN_C1 -to ADC_SPI_SCLK_18
+set_location_assignment PIN_E3 -to ADC_SPI_SDIO_18
+set_location_assignment PIN_M5 -to CLKDIST_SPI_CS_L
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_CS_L
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_SCLK_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_SDIO_18
+set_location_assignment PIN_L5 -to CLKDIST_SPI_SCLK
+set_location_assignment PIN_N5 -to CLKDIST_SPI_SDIO
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_SDIO
+set_location_assignment PIN_K6 -to CLKDIST_Status_LD1
+set_location_assignment PIN_J6 -to CLKDIST_Status_LD2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_Status_LD1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_Status_LD2
+set_location_assignment PIN_M1 -to CPLD_ATR_TX_18
+set_location_assignment PIN_L1 -to CPLD_ATR_RX_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_ATR_RX_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_ATR_TX_18
+set_location_assignment PIN_H6 -to CPLD_PL_SPI_ADDR0_18
+set_location_assignment PIN_K2 -to CPLD_PL_SPI_ADDR1_18
+set_location_assignment PIN_J2 -to CPLD_PL_SPI_ADDR2_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR0_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR1_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR2_18
+set_location_assignment PIN_K1 -to CPLD_PL_SPI_LE_18
+set_location_assignment PIN_H5 -to CPLD_PL_SPI_SCLK_18
+set_location_assignment PIN_L3 -to CPLD_PL_SPI_SDI_18
+set_location_assignment PIN_L2 -to CPLD_PL_SPI_SDO_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_LE_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SCLK_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SDI_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SDO_18
+set_location_assignment PIN_M2 -to DAC_Alarm_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_Alarm_18
+set_location_assignment PIN_N3 -to DAC_SPI_SDIO_18
+set_location_assignment PIN_N2 -to DAC_SPI_SCLK_18
+set_location_assignment PIN_M3 -to DAC_SPI_CS_L_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_CS_L_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_SCLK_18
+set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_SDIO_18
+set_location_assignment PIN_M7 -to LOSYNTH_RX_MUXOUT
+set_location_assignment PIN_N7 -to LOSYNTH_TX_MUXOUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LOSYNTH_RX_MUXOUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LOSYNTH_TX_MUXOUT
+set_location_assignment PIN_E6 -to LO_RX_CS_L
+set_location_assignment PIN_B2 -to LO_SPI_SCLK
+set_location_assignment PIN_M4 -to LO_SPI_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_RX_CS_L
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_SPI_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_SPI_SDI
+set_location_assignment PIN_K5 -to LO_TX_CS_L
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_TX_CS_L
+set_location_assignment PIN_B6 -to Rx_DSA1_LE
+set_location_assignment PIN_A9 -to Rx_DSA2_LE
+set_location_assignment PIN_D8 -to Rx_DSA_C1
+set_location_assignment PIN_D6 -to Rx_DSA_C2
+set_location_assignment PIN_A11 -to Rx_DSA_C4
+set_location_assignment PIN_B10 -to Rx_DSA_C8
+set_location_assignment PIN_A10 -to Rx_DSA_C16
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA1_LE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA2_LE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C4
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C8
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C16
+set_location_assignment PIN_B3 -to Rx_Demod_ADJ_1
+set_location_assignment PIN_N4 -to Rx_Demod_ADJ_2
+set_location_assignment PIN_J5 -to Rx_LO_Filter_Sw_1
+set_location_assignment PIN_J7 -to Rx_LO_Filter_Sw_2
+set_location_assignment PIN_L4 -to Rx_LO_Input_Select
+set_location_assignment PIN_A6 -to Rx_Sw1_Ctrl_1
+set_location_assignment PIN_A7 -to Rx_Sw1_Ctrl_2
+set_location_assignment PIN_A5 -to Rx_Sw2_Ctrl
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Demod_ADJ_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Demod_ADJ_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw1_Ctrl_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw1_Ctrl_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw2_Ctrl
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Filter_Sw_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Filter_Sw_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Input_Select
+set_location_assignment PIN_A4 -to Rx_Sw3_Ctrl_1
+set_location_assignment PIN_A3 -to Rx_Sw3_Ctrl_2
+set_location_assignment PIN_C10 -to Rx_Sw4_Ctrl_1
+set_location_assignment PIN_A8 -to Rx_Sw4_Ctrl_2
+set_location_assignment PIN_B9 -to Rx_Sw4_Ctrl_3
+set_location_assignment PIN_C9 -to Rx_Sw4_Ctrl_4
+set_location_assignment PIN_K13 -to Tx_DSA1_LE
+set_location_assignment PIN_K12 -to Tx_DSA2_LE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw3_Ctrl_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw3_Ctrl_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA1_LE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA2_LE
+set_location_assignment PIN_H13 -to Tx_DSA_C1
+set_location_assignment PIN_H8 -to Tx_DSA_C2
+set_location_assignment PIN_J13 -to Tx_DSA_C4
+set_location_assignment PIN_H10 -to Tx_DSA_C8
+set_location_assignment PIN_J12 -to Tx_DSA_C16
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C4
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C8
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C16
+set_location_assignment PIN_N6 -to Tx_LO_Filter_Sw_1
+set_location_assignment PIN_N12 -to Tx_LO_Filter_Sw_2
+set_location_assignment PIN_N8 -to Tx_LO_Input_Select
+set_location_assignment PIN_L10 -to Tx_Sw1_Ctrl_1
+set_location_assignment PIN_N10 -to Tx_Sw1_Ctrl_2
+set_location_assignment PIN_N11 -to Tx_Sw2_Ctrl_1
+set_location_assignment PIN_L11 -to Tx_Sw2_Ctrl_2
+set_location_assignment PIN_L12 -to Tx_Sw3_Ctrl_1
+set_location_assignment PIN_M13 -to Tx_Sw3_Ctrl_2
+set_location_assignment PIN_K11 -to Tx_Sw3_Ctrl_3
+set_location_assignment PIN_J9 -to Tx_Sw3_Ctrl_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Filter_Sw_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Filter_Sw_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Input_Select
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw1_Ctrl_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw1_Ctrl_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw2_Ctrl_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw2_Ctrl_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_4
+set_location_assignment PIN_B11 -to PHDAC_SPI_CS_L
+set_location_assignment PIN_C11 -to PHDAC_SPI_SCLK
+set_location_assignment PIN_D9 -to PHDAC_SPI_SDI
+set_location_assignment PIN_N9 -to LODIST_Bd_SPI_CS_L
+set_location_assignment PIN_J8 -to LODIST_Bd_SPI_SCLK
+set_location_assignment PIN_M9 -to LODIST_Bd_SPI_SDI
+set_location_assignment PIN_L13 -to LO_DSA_C1
+set_location_assignment PIN_K10 -to LO_DSA_C2
+set_location_assignment PIN_H9 -to LO_DSA_C4
+set_location_assignment PIN_G12 -to LO_DSA_C8
+set_location_assignment PIN_G13 -to LO_DSA_C16
+set_location_assignment PIN_J10 -to RxLO_DSA_LE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_CS_L
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C4
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C8
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C16
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RxLO_DSA_LE
+set_location_assignment PIN_B4 -to Rx_Sw6_Ctrl_1
+set_location_assignment PIN_B5 -to Rx_Sw6_Ctrl_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw6_Ctrl_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw6_Ctrl_2
+set_location_assignment PIN_M8 -to TxLO_DSA_LE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TxLO_DSA_LE
+set_location_assignment PIN_M11 -to Tx_Sw5_Ctrl_1
+set_location_assignment PIN_M12 -to Tx_Sw5_Ctrl_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw5_Ctrl_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw5_Ctrl_2
+set_location_assignment PIN_D12 -to Cal_iso_Sw_Ctrl
+set_location_assignment PIN_K8 -to LODIST_Bd_IO1
+set_location_assignment PIN_M10 -to Tx_HB_LB_Select
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_HB_LB_Select
+set_location_assignment PIN_E8 -to Rx_HB_LB_Select
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_HB_LB_Select
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_CS_L
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_SCLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_SDI
+set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_ADDR0_25
+set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_ADDR1_25
+set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_CLK_25
+set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_LE_25
+set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_SDI_25
+set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_SDO_25
+set_instance_assignment -name IO_STANDARD "2.5 V" -to Cal_iso_Sw_Ctrl
+set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to LODIST_Bd_IO1
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_location_assignment PIN_E4 -to usrp_io[0]
+set_location_assignment PIN_G5 -to usrp_io[1]
+set_location_assignment PIN_H4 -to usrp_io[2]
+set_location_assignment PIN_J1 -to usrp_io[3]
+set_location_assignment PIN_F1 -to usrp_io[4]
+set_location_assignment PIN_C12 -to usrp_io[5]
+set_location_assignment PIN_C13 -to usrp_io[6]
+set_location_assignment PIN_E12 -to usrp_io[7]
+set_location_assignment PIN_E13 -to usrp_io[8]
+set_location_assignment PIN_B13 -to usrp_io[9]
+set_location_assignment PIN_F9 -to usrp_io[10]
+set_location_assignment PIN_B12 -to usrp_io[11]
+set_location_assignment PIN_E9 -to usrp_io[12]
+set_location_assignment PIN_F8 -to usrp_io[13]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[8]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[9]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[10]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[11]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[12]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[13]
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH rh_tb -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME rh_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id rh_tb
+set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "9000 ns" -section_id rh_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME rh_tb -section_id rh_tb
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
+set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
+set_global_assignment -name VERILOG_FILE ../rhodium_top.v
+set_global_assignment -name VERILOG_FILE ../rhodium_gain_ctrl.v
+set_global_assignment -name VERILOG_FILE ../rhodium_gain_table.v
+set_global_assignment -name VERILOG_FILE ../rhodium_lo_gain.v
+set_global_assignment -name VERILOG_FILE ../rh_tb.v
+set_global_assignment -name EDA_TEST_BENCH_FILE ../rh_tb.v -section_id rh_tb
+set_global_assignment -name SDC_FILE ../rhodium_top.sdc
+
+set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
+set_global_assignment -name ENABLE_OCT_DONE OFF
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name GENERATE_SVF_FILE ON
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf
deleted file mode 100644
index 5e1bf4d57..000000000
--- a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2017  Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Intel Program License 
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel MegaCore Function License Agreement, or other 
-# applicable license agreement, including, without limitation, 
-# that your use is for the sole purpose of programming logic 
-# devices manufactured by Intel and sold by Intel or its 
-# authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition
-# Date created = 08:22:34  September 13, 2017
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "17.0"
-DATE = "08:22:34  September 13, 2017"
-
-# Revisions
-
-PROJECT_REVISION = "rhodium_top"
diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf
deleted file mode 100644
index e94f0bbc8..000000000
--- a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf
+++ /dev/null
@@ -1,306 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2017  Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Intel Program License 
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel MegaCore Function License Agreement, or other 
-# applicable license agreement, including, without limitation, 
-# that your use is for the sole purpose of programming logic 
-# devices manufactured by Intel and sold by Intel or its 
-# authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition
-# Date created = 08:22:34  September 13, 2017
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		rhodium_top_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus Prime software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "MAX 10"
-set_global_assignment -name DEVICE 10M04SAU169I7G
-set_global_assignment -name TOP_LEVEL_ENTITY rhodium_top
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.2
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:22:34  SEPTEMBER 13, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_location_assignment PIN_D11 -to CPLD_PS_SPI_LE_25
-set_location_assignment PIN_F13 -to CPLD_PS_SPI_CLK_25
-set_location_assignment PIN_E10 -to CPLD_PS_ADDR0_25
-set_location_assignment PIN_A12 -to CPLD_PS_ADDR1_25
-set_location_assignment PIN_F12 -to CPLD_PS_SPI_SDI_25
-set_location_assignment PIN_F10 -to CPLD_PS_SPI_SDO_25
-set_location_assignment PIN_B1 -to ADC_A_Over_Range_18
-set_location_assignment PIN_D1 -to ADC_B_Over_Range_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_A_Over_Range_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_B_Over_Range_18
-set_instance_assignment -name IO_STANDARD LVDS -to LO_SYNC
-set_location_assignment PIN_G9 -to LO_SYNC
-set_location_assignment PIN_G10 -to "LO_SYNC(n)"
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_CS_L_18
-set_location_assignment PIN_C2 -to ADC_SPI_CS_L_18
-set_location_assignment PIN_C1 -to ADC_SPI_SCLK_18
-set_location_assignment PIN_E3 -to ADC_SPI_SDIO_18
-set_location_assignment PIN_M5 -to CLKDIST_SPI_CS_L
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_CS_L
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_SCLK_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_SDIO_18
-set_location_assignment PIN_L5 -to CLKDIST_SPI_SCLK
-set_location_assignment PIN_N5 -to CLKDIST_SPI_SDIO
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_SCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_SDIO
-set_location_assignment PIN_K6 -to CLKDIST_Status_LD1
-set_location_assignment PIN_J6 -to CLKDIST_Status_LD2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_Status_LD1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_Status_LD2
-set_location_assignment PIN_M1 -to CPLD_ATR_TX_18
-set_location_assignment PIN_L1 -to CPLD_ATR_RX_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_ATR_RX_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_ATR_TX_18
-set_location_assignment PIN_H6 -to CPLD_PL_SPI_ADDR0_18
-set_location_assignment PIN_K2 -to CPLD_PL_SPI_ADDR1_18
-set_location_assignment PIN_J2 -to CPLD_PL_SPI_ADDR2_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR0_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR1_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR2_18
-set_location_assignment PIN_K1 -to CPLD_PL_SPI_LE_18
-set_location_assignment PIN_H5 -to CPLD_PL_SPI_SCLK_18
-set_location_assignment PIN_L3 -to CPLD_PL_SPI_SDI_18
-set_location_assignment PIN_L2 -to CPLD_PL_SPI_SDO_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_LE_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SCLK_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SDI_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SDO_18
-set_location_assignment PIN_M2 -to DAC_Alarm_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_Alarm_18
-set_location_assignment PIN_N3 -to DAC_SPI_SDIO_18
-set_location_assignment PIN_N2 -to DAC_SPI_SCLK_18
-set_location_assignment PIN_M3 -to DAC_SPI_CS_L_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_CS_L_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_SCLK_18
-set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_SDIO_18
-set_location_assignment PIN_M7 -to LOSYNTH_RX_MUXOUT
-set_location_assignment PIN_N7 -to LOSYNTH_TX_MUXOUT
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LOSYNTH_RX_MUXOUT
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LOSYNTH_TX_MUXOUT
-set_location_assignment PIN_E6 -to LO_RX_CS_L
-set_location_assignment PIN_B2 -to LO_SPI_SCLK
-set_location_assignment PIN_M4 -to LO_SPI_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_RX_CS_L
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_SPI_SCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_SPI_SDI
-set_location_assignment PIN_K5 -to LO_TX_CS_L
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_TX_CS_L
-set_location_assignment PIN_B6 -to Rx_DSA1_LE
-set_location_assignment PIN_A9 -to Rx_DSA2_LE
-set_location_assignment PIN_D8 -to Rx_DSA_C1
-set_location_assignment PIN_D6 -to Rx_DSA_C2
-set_location_assignment PIN_A11 -to Rx_DSA_C4
-set_location_assignment PIN_B10 -to Rx_DSA_C8
-set_location_assignment PIN_A10 -to Rx_DSA_C16
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA1_LE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA2_LE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C4
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C8
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C16
-set_location_assignment PIN_B3 -to Rx_Demod_ADJ_1
-set_location_assignment PIN_N4 -to Rx_Demod_ADJ_2
-set_location_assignment PIN_J5 -to Rx_LO_Filter_Sw_1
-set_location_assignment PIN_J7 -to Rx_LO_Filter_Sw_2
-set_location_assignment PIN_L4 -to Rx_LO_Input_Select
-set_location_assignment PIN_A6 -to Rx_Sw1_Ctrl_1
-set_location_assignment PIN_A7 -to Rx_Sw1_Ctrl_2
-set_location_assignment PIN_A5 -to Rx_Sw2_Ctrl
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Demod_ADJ_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Demod_ADJ_2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw1_Ctrl_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw1_Ctrl_2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw2_Ctrl
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Filter_Sw_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Filter_Sw_2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Input_Select
-set_location_assignment PIN_A4 -to Rx_Sw3_Ctrl_1
-set_location_assignment PIN_A3 -to Rx_Sw3_Ctrl_2
-set_location_assignment PIN_C10 -to Rx_Sw4_Ctrl_1
-set_location_assignment PIN_A8 -to Rx_Sw4_Ctrl_2
-set_location_assignment PIN_B9 -to Rx_Sw4_Ctrl_3
-set_location_assignment PIN_C9 -to Rx_Sw4_Ctrl_4
-set_location_assignment PIN_K13 -to Tx_DSA1_LE
-set_location_assignment PIN_K12 -to Tx_DSA2_LE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw3_Ctrl_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw3_Ctrl_2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_3
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_4
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA1_LE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA2_LE
-set_location_assignment PIN_H13 -to Tx_DSA_C1
-set_location_assignment PIN_H8 -to Tx_DSA_C2
-set_location_assignment PIN_J13 -to Tx_DSA_C4
-set_location_assignment PIN_H10 -to Tx_DSA_C8
-set_location_assignment PIN_J12 -to Tx_DSA_C16
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C4
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C8
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C16
-set_location_assignment PIN_N6 -to Tx_LO_Filter_Sw_1
-set_location_assignment PIN_N12 -to Tx_LO_Filter_Sw_2
-set_location_assignment PIN_N8 -to Tx_LO_Input_Select
-set_location_assignment PIN_L10 -to Tx_Sw1_Ctrl_1
-set_location_assignment PIN_N10 -to Tx_Sw1_Ctrl_2
-set_location_assignment PIN_N11 -to Tx_Sw2_Ctrl_1
-set_location_assignment PIN_L11 -to Tx_Sw2_Ctrl_2
-set_location_assignment PIN_L12 -to Tx_Sw3_Ctrl_1
-set_location_assignment PIN_M13 -to Tx_Sw3_Ctrl_2
-set_location_assignment PIN_K11 -to Tx_Sw3_Ctrl_3
-set_location_assignment PIN_J9 -to Tx_Sw3_Ctrl_4
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Filter_Sw_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Filter_Sw_2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Input_Select
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw1_Ctrl_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw1_Ctrl_2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw2_Ctrl_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw2_Ctrl_2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_3
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_4
-set_location_assignment PIN_B11 -to PHDAC_SPI_CS_L
-set_location_assignment PIN_C11 -to PHDAC_SPI_SCLK
-set_location_assignment PIN_D9 -to PHDAC_SPI_SDI
-set_location_assignment PIN_N9 -to LODIST_Bd_SPI_CS_L
-set_location_assignment PIN_J8 -to LODIST_Bd_SPI_SCLK
-set_location_assignment PIN_M9 -to LODIST_Bd_SPI_SDI
-set_location_assignment PIN_L13 -to LO_DSA_C1
-set_location_assignment PIN_K10 -to LO_DSA_C2
-set_location_assignment PIN_H9 -to LO_DSA_C4
-set_location_assignment PIN_G12 -to LO_DSA_C8
-set_location_assignment PIN_G13 -to LO_DSA_C16
-set_location_assignment PIN_J10 -to RxLO_DSA_LE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_CS_L
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_SCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C4
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C8
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C16
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RxLO_DSA_LE
-set_location_assignment PIN_B4 -to Rx_Sw6_Ctrl_1
-set_location_assignment PIN_B5 -to Rx_Sw6_Ctrl_2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw6_Ctrl_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw6_Ctrl_2
-set_location_assignment PIN_M8 -to TxLO_DSA_LE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TxLO_DSA_LE
-set_location_assignment PIN_M11 -to Tx_Sw5_Ctrl_1
-set_location_assignment PIN_M12 -to Tx_Sw5_Ctrl_2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw5_Ctrl_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw5_Ctrl_2
-set_location_assignment PIN_D12 -to Cal_iso_Sw_Ctrl
-set_location_assignment PIN_K8 -to LODIST_Bd_IO1
-set_location_assignment PIN_M10 -to Tx_HB_LB_Select
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_HB_LB_Select
-set_location_assignment PIN_E8 -to Rx_HB_LB_Select
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_HB_LB_Select
-set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_CS_L
-set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_SCLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_SDI
-set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_ADDR0_25
-set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_ADDR1_25
-set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_CLK_25
-set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_LE_25
-set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_SDI_25
-set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_SDO_25
-set_instance_assignment -name IO_STANDARD "2.5 V" -to Cal_iso_Sw_Ctrl
-set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to LODIST_Bd_IO1
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
-set_location_assignment PIN_E4 -to usrp_io[0]
-set_location_assignment PIN_G5 -to usrp_io[1]
-set_location_assignment PIN_H4 -to usrp_io[2]
-set_location_assignment PIN_J1 -to usrp_io[3]
-set_location_assignment PIN_F1 -to usrp_io[4]
-set_location_assignment PIN_C12 -to usrp_io[5]
-set_location_assignment PIN_C13 -to usrp_io[6]
-set_location_assignment PIN_E12 -to usrp_io[7]
-set_location_assignment PIN_E13 -to usrp_io[8]
-set_location_assignment PIN_B13 -to usrp_io[9]
-set_location_assignment PIN_F9 -to usrp_io[10]
-set_location_assignment PIN_B12 -to usrp_io[11]
-set_location_assignment PIN_E9 -to usrp_io[12]
-set_location_assignment PIN_F8 -to usrp_io[13]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[2]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[3]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[13]
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
-set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH rh_tb -section_id eda_simulation
-set_global_assignment -name EDA_TEST_BENCH_NAME rh_tb -section_id eda_simulation
-set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id rh_tb
-set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "9000 ns" -section_id rh_tb
-set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME rh_tb -section_id rh_tb
-set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
-set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
-set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
-set_global_assignment -name VERILOG_FILE rhodium_top.v
-set_global_assignment -name VERILOG_FILE rhodium_gain_ctrl.v
-set_global_assignment -name VERILOG_FILE rhodium_gain_table.v
-set_global_assignment -name VERILOG_FILE rhodium_lo_gain.v
-set_global_assignment -name VERILOG_FILE rh_tb.v
-set_global_assignment -name EDA_TEST_BENCH_FILE rh_tb.v -section_id rh_tb
-
-
-set_global_assignment -name ENABLE_OCT_DONE OFF
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name GENERATE_SVF_FILE ON
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v
index 1d0d640da..6a23f7520 100644
--- a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v
+++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v
@@ -128,9 +128,9 @@ output    Cal_iso_Sw_Ctrl
 
 /* PS SPI */
 
-localparam GIT_HASH = 36'h`GIT_HASH;
+localparam GIT_HASH = `GIT_HASH;
 localparam PROD_SIGNATURE   = 16'h0045; // Product signature (Rhodium atomic number in BCD)
-localparam REVISION_MINOR   = 16'h0002;
+localparam REVISION_MINOR   = 16'h0003;
 localparam REVISION_MAJOR   = 16'h0004;
 localparam CPLD_BUILD_LSB   = GIT_HASH[15:0]; // Build code LSB
 localparam CPLD_BUILD_MSB   = GIT_HASH[31:16]; // Build code MSB
-- 
cgit v1.2.3