From 6190eca14ec13db7456a059cbd69c93550aa45c7 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Thu, 10 Jun 2021 11:50:04 -0500 Subject: fpga: tools: Add modelsim.excludes This is a list of testbenches that don't work with ModelSim and should be excluded when running run_testbenches.py. --- fpga/usrp3/tools/utils/modelsim.excludes | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 fpga/usrp3/tools/utils/modelsim.excludes (limited to 'fpga') diff --git a/fpga/usrp3/tools/utils/modelsim.excludes b/fpga/usrp3/tools/utils/modelsim.excludes new file mode 100644 index 000000000..41df329c4 --- /dev/null +++ b/fpga/usrp3/tools/utils/modelsim.excludes @@ -0,0 +1,18 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# This file contains all testbenches to exclude from the list discovered +# by run_testbenches.py for the ModelSim simulator. +# + +top/e31x/sim/dram_test +top/n3xx/sim/arm_to_sfp_loopback +top/n3xx/sim/aurora_loopback +top/n3xx/sim/one_gig_eth_loopback +top/n3xx/sim/ten_gig_eth_loopback +top/x300/sim/x300_pcie_int + +# This TB doesn't pass in ModelSim +top/x300/sim/dram_fifo_bist -- cgit v1.2.3