From 0df4b801a34697f2058b4a7b95e08d2a0576c9db Mon Sep 17 00:00:00 2001
From: Ben Hilburn <ben.hilburn@ettus.com>
Date: Thu, 10 Oct 2013 10:17:27 -0700
Subject: Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt
 Ettus.

---
 fpga/.gitignore                                    |     8 +
 fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs          |    18 +
 fpga/usrp2/coregen/coregen_s6.cgc                  |  2352 +
 fpga/usrp2/coregen/coregen_s6.cgp                  |    22 +
 fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy          |    49 +
 fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise         |    31 +
 fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc          |     3 +
 fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v            |   173 +
 fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo          |    53 +
 fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco          |    84 +
 fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise         |   392 +
 fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_flist.txt    |    13 +
 fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_readme.txt   |    51 +
 fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl     |    72 +
 fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy          |    49 +
 fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.gise         |    31 +
 fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.ngc          |     3 +
 fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.v            |   173 +
 fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.veo          |    53 +
 fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xco          |    84 +
 fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xise         |   392 +
 fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_flist.txt    |    13 +
 fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_readme.txt   |    51 +
 fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_xmdf.tcl     |    72 +
 fpga/usrp2/coregen/fifo_s6_512x36_2clk.asy         |    49 +
 fpga/usrp2/coregen/fifo_s6_512x36_2clk.gise        |    31 +
 fpga/usrp2/coregen/fifo_s6_512x36_2clk.ngc         |     3 +
 fpga/usrp2/coregen/fifo_s6_512x36_2clk.v           |   173 +
 fpga/usrp2/coregen/fifo_s6_512x36_2clk.veo         |    53 +
 fpga/usrp2/coregen/fifo_s6_512x36_2clk.xco         |    84 +
 fpga/usrp2/coregen/fifo_s6_512x36_2clk.xise        |   392 +
 fpga/usrp2/coregen/fifo_s6_512x36_2clk_flist.txt   |    13 +
 fpga/usrp2/coregen/fifo_s6_512x36_2clk_readme.txt  |    51 +
 fpga/usrp2/coregen/fifo_s6_512x36_2clk_xmdf.tcl    |    72 +
 .../usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf |     0
 .../usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf |     0
 .../coregen/fifo_xlnx_512x36_2clk_prog_full.ncf    |     0
 fpga/usrp2/coregen/pll_100_40_75.asy               |    29 +
 fpga/usrp2/coregen/pll_100_40_75.gise              |    31 +
 fpga/usrp2/coregen/pll_100_40_75.ucf               |    71 +
 fpga/usrp2/coregen/pll_100_40_75.v                 |   158 +
 fpga/usrp2/coregen/pll_100_40_75.veo               |    82 +
 fpga/usrp2/coregen/pll_100_40_75.xco               |   266 +
 fpga/usrp2/coregen/pll_100_40_75.xdc               |    67 +
 fpga/usrp2/coregen/pll_100_40_75.xise              |    78 +
 .../coregen/pll_100_40_75/clk_wiz_v3_5_readme.txt  |   183 +
 .../coregen/pll_100_40_75/doc/clk_wiz_gsg521.pdf   |   Bin 0 -> 47768 bytes
 .../pll_100_40_75/doc/clk_wiz_v3_5_readme.txt      |   183 +
 .../pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html      |   194 +
 .../example_design/pll_100_40_75_exdes.ucf         |    72 +
 .../example_design/pll_100_40_75_exdes.v           |   160 +
 .../example_design/pll_100_40_75_exdes.xdc         |    69 +
 .../coregen/pll_100_40_75/implement/implement.bat  |    90 +
 .../coregen/pll_100_40_75/implement/implement.sh   |    91 +
 .../pll_100_40_75/implement/planAhead_ise.bat      |    58 +
 .../pll_100_40_75/implement/planAhead_ise.sh       |    59 +
 .../pll_100_40_75/implement/planAhead_ise.tcl      |    78 +
 .../pll_100_40_75/implement/planAhead_rdn.bat      |    58 +
 .../pll_100_40_75/implement/planAhead_rdn.sh       |    57 +
 .../pll_100_40_75/implement/planAhead_rdn.tcl      |    69 +
 fpga/usrp2/coregen/pll_100_40_75/implement/xst.prj |     2 +
 fpga/usrp2/coregen/pll_100_40_75/implement/xst.scr |     9 +
 .../simulation/functional/simcmds.tcl              |     8 +
 .../simulation/functional/simulate_isim.bat        |    59 +
 .../simulation/functional/simulate_isim.sh         |    61 +
 .../simulation/functional/simulate_mti.bat         |    61 +
 .../simulation/functional/simulate_mti.do          |    65 +
 .../simulation/functional/simulate_mti.sh          |    61 +
 .../simulation/functional/simulate_ncsim.sh        |    62 +
 .../simulation/functional/simulate_vcs.sh          |    72 +
 .../simulation/functional/ucli_commands.key        |     5 +
 .../simulation/functional/vcs_session.tcl          |    18 +
 .../pll_100_40_75/simulation/functional/wave.do    |    60 +
 .../pll_100_40_75/simulation/functional/wave.sv    |   119 +
 .../pll_100_40_75/simulation/pll_100_40_75_tb.v    |   143 +
 .../simulation/timing/pll_100_40_75_tb.v           |   157 +
 .../pll_100_40_75/simulation/timing/sdf_cmd_file   |     2 +
 .../pll_100_40_75/simulation/timing/simcmds.tcl    |     9 +
 .../simulation/timing/simulate_isim.sh             |    62 +
 .../simulation/timing/simulate_mti.bat             |    59 +
 .../simulation/timing/simulate_mti.do              |    65 +
 .../simulation/timing/simulate_mti.sh              |    61 +
 .../simulation/timing/simulate_ncsim.sh            |    64 +
 .../simulation/timing/simulate_vcs.sh              |    72 +
 .../simulation/timing/ucli_commands.key            |     5 +
 .../simulation/timing/vcs_session.tcl              |     1 +
 .../pll_100_40_75/simulation/timing/wave.do        |    72 +
 fpga/usrp2/coregen/pll_100_40_75_exdes.ncf         |    73 +
 fpga/usrp2/coregen/pll_100_40_75_flist.txt         |    54 +
 fpga/usrp2/coregen/pll_100_40_75_xmdf.tcl          |   144 +
 fpga/usrp2/fifo/resp_packet_padder36.v             |    88 +
 fpga/usrp2/gpif/.gitignore                         |     3 +
 fpga/usrp2/gpif/gpif.v                             |   185 +
 fpga/usrp2/gpif/gpif_rd.v                          |   111 +
 fpga/usrp2/gpif/gpif_tb.v                          |   142 +
 fpga/usrp2/gpif/gpif_wr.v                          |    95 +
 fpga/usrp2/gpif/gpif_wr_tb.v                       |   110 +
 fpga/usrp2/gpif/lint                               |     2 +
 fpga/usrp2/gpif/packet_padder36.v                  |   130 +
 fpga/usrp2/gpif/packet_splitter.v                  |   123 +
 fpga/usrp2/gpif/packet_splitter_tb.v               |   137 +
 fpga/usrp2/top/impactor.sh                         |    17 +
 fpga/usrp2/vrt/vita_packet_demux36.v               |   102 +
 fpga/usrp3/README.txt                              |     0
 fpga/usrp3/lib/control/Makefile.srcs               |    26 +
 fpga/usrp3/lib/control/README.txt                  |     0
 fpga/usrp3/lib/control/arb_qualify_master.v        |    88 +
 fpga/usrp3/lib/control/axi_crossbar.v              |   167 +
 fpga/usrp3/lib/control/axi_crossbar_tb.v           |   214 +
 fpga/usrp3/lib/control/axi_fifo_header.v           |    84 +
 fpga/usrp3/lib/control/axi_forwarding_cam.v        |   232 +
 fpga/usrp3/lib/control/axi_slave_mux.v             |   122 +
 fpga/usrp3/lib/control/axi_test_vfifo.v            |   139 +
 fpga/usrp3/lib/control/cvita_uart.v                |   164 +
 fpga/usrp3/lib/control/dram_2port.v                |    27 +
 fpga/usrp3/lib/control/gpio_atr.v                  |    64 +
 fpga/usrp3/lib/control/por_gen.v                   |    25 +
 fpga/usrp3/lib/control/radio_ctrl_proc.v           |   143 +
 fpga/usrp3/lib/control/radio_ctrl_proc_tb.v        |   104 +
 fpga/usrp3/lib/control/ram_2port.v                 |    49 +
 fpga/usrp3/lib/control/reset_sync.v                |    28 +
 fpga/usrp3/lib/control/setting_reg.v               |    35 +
 fpga/usrp3/lib/control/settings_bus_crossclock.v   |    26 +
 fpga/usrp3/lib/control/simple_i2c_core.v           |   104 +
 fpga/usrp3/lib/control/simple_spi_core.v           |   207 +
 fpga/usrp3/lib/dsp/Makefile.srcs                   |    38 +
 fpga/usrp3/lib/dsp/README.txt                      |     0
 fpga/usrp3/lib/dsp/acc.v                           |    33 +
 fpga/usrp3/lib/dsp/add2.v                          |    16 +
 fpga/usrp3/lib/dsp/add2_and_clip.v                 |    12 +
 fpga/usrp3/lib/dsp/add2_and_clip_reg.v             |    25 +
 fpga/usrp3/lib/dsp/add2_and_round.v                |    16 +
 fpga/usrp3/lib/dsp/add2_and_round_reg.v            |    21 +
 fpga/usrp3/lib/dsp/add2_reg.v                      |    22 +
 fpga/usrp3/lib/dsp/cic_dec_shifter.v               |    94 +
 fpga/usrp3/lib/dsp/cic_decim.v                     |    76 +
 fpga/usrp3/lib/dsp/cic_int_shifter.v               |    88 +
 fpga/usrp3/lib/dsp/cic_interp.v                    |    75 +
 fpga/usrp3/lib/dsp/cic_strober.v                   |    33 +
 fpga/usrp3/lib/dsp/clip.v                          |    24 +
 fpga/usrp3/lib/dsp/clip_reg.v                      |    34 +
 fpga/usrp3/lib/dsp/cordic_stage.v                  |    48 +
 fpga/usrp3/lib/dsp/cordic_z24.v                    |   112 +
 fpga/usrp3/lib/dsp/ddc_chain.v                     |   164 +
 fpga/usrp3/lib/dsp/duc_chain.v                     |   146 +
 fpga/usrp3/lib/dsp/hb_dec.v                        |   177 +
 fpga/usrp3/lib/dsp/hb_interp.v                     |   165 +
 fpga/usrp3/lib/dsp/round.v                         |    47 +
 fpga/usrp3/lib/dsp/round_reg.v                     |    32 +
 fpga/usrp3/lib/dsp/round_sd.v                      |    23 +
 fpga/usrp3/lib/dsp/rx_dcoffset.v                   |    46 +
 fpga/usrp3/lib/dsp/rx_frontend.v                   |    78 +
 fpga/usrp3/lib/dsp/rx_frontend_tb.v                |    45 +
 fpga/usrp3/lib/dsp/sign_extend.v                   |    23 +
 fpga/usrp3/lib/dsp/small_hb_dec.v                  |   124 +
 fpga/usrp3/lib/dsp/small_hb_int.v                  |    99 +
 fpga/usrp3/lib/dsp/srl.v                           |    27 +
 fpga/usrp3/lib/fifo/Makefile.srcs                  |    20 +
 fpga/usrp3/lib/fifo/axi_demux4.v                   |    77 +
 fpga/usrp3/lib/fifo/axi_demux8.v                   |    60 +
 fpga/usrp3/lib/fifo/axi_fifo.v                     |   169 +
 fpga/usrp3/lib/fifo/axi_fifo32_to_fifo64.v         |    38 +
 fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v         |    31 +
 fpga/usrp3/lib/fifo/axi_fifo_2clk.v                |    88 +
 fpga/usrp3/lib/fifo/axi_fifo_32_64_tb.v            |   114 +
 fpga/usrp3/lib/fifo/axi_fifo_short.v               |   110 +
 fpga/usrp3/lib/fifo/axi_fifo_tb.v                  |   211 +
 fpga/usrp3/lib/fifo/axi_loopback.v                 |    71 +
 fpga/usrp3/lib/fifo/axi_mux4.v                     |   112 +
 fpga/usrp3/lib/fifo/axi_mux8.v                     |    56 +
 fpga/usrp3/lib/fifo/axi_packet_gate.v              |    78 +
 fpga/usrp3/lib/fifo/axi_packet_gate_tb.v           |   106 +
 fpga/usrp3/lib/fifo/monitor_axi_fifo.v             |   123 +
 fpga/usrp3/lib/fifo/shortfifo.v                    |    92 +
 fpga/usrp3/lib/gpif2/Makefile.srcs                 |    13 +
 fpga/usrp3/lib/gpif2/fifo64_to_gpif2.v             |    64 +
 fpga/usrp3/lib/gpif2/gpif2_error_checker.v         |   126 +
 fpga/usrp3/lib/gpif2/gpif2_slave_fifo32.v          |   375 +
 fpga/usrp3/lib/gpif2/gpif2_to_fifo64.v             |   118 +
 fpga/usrp3/lib/packet_proc/.gitignore              |     3 +
 fpga/usrp3/lib/packet_proc/Makefile.srcs           |    21 +
 fpga/usrp3/lib/packet_proc/chdr_eth_framer.v       |   136 +
 .../lib/packet_proc/compressed_vita_to_vrlp.v      |    78 +
 fpga/usrp3/lib/packet_proc/cvita_chunker.v         |    91 +
 fpga/usrp3/lib/packet_proc/cvita_chunker_tb.v      |   187 +
 fpga/usrp3/lib/packet_proc/cvita_dechunker.v       |    90 +
 fpga/usrp3/lib/packet_proc/cvita_dechunker_tb.v    |   183 +
 fpga/usrp3/lib/packet_proc/cvita_dest_lookup.v     |    48 +
 fpga/usrp3/lib/packet_proc/cvita_insert_tlast.v    |    33 +
 fpga/usrp3/lib/packet_proc/cvita_insert_tlast_tb.v |    92 +
 fpga/usrp3/lib/packet_proc/eth_dispatch.v          |   573 +
 fpga/usrp3/lib/packet_proc/eth_dispatch_tb.v       |   311 +
 fpga/usrp3/lib/packet_proc/eth_interface.v         |   113 +
 fpga/usrp3/lib/packet_proc/ip_hdr_checksum.v       |    24 +
 fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v    |    38 +
 fpga/usrp3/lib/packet_proc/source_flow_control.v   |   127 +
 .../usrp3/lib/packet_proc/source_flow_control_tb.v |   249 +
 fpga/usrp3/lib/packet_proc/vita_eth_framer.v       |   137 +
 fpga/usrp3/lib/packet_proc/vrlp_eth_framer.v       |   139 +
 .../lib/packet_proc/vrlp_to_compressed_vita.v      |    90 +
 .../lib/packet_proc/vrlp_to_compressed_vita_tb.v   |   120 +
 fpga/usrp3/lib/timing/Makefile.srcs                |    11 +
 fpga/usrp3/lib/timing/time_compare.v               |    51 +
 fpga/usrp3/lib/timing/time_transfer_tb.v           |    55 +
 fpga/usrp3/lib/timing/timekeeper.v                 |    68 +
 fpga/usrp3/lib/vita/.gitignore                     |     1 +
 fpga/usrp3/lib/vita/Makefile.srcs                  |    29 +
 fpga/usrp3/lib/vita/README.txt                     |     0
 fpga/usrp3/lib/vita/binary_encoder.v               |    37 +
 fpga/usrp3/lib/vita/build_12_to_16                 |     1 +
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 fpga/usrp3/lib/vita/build_16_to_8                  |     2 +
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 fpga/usrp3/lib/vita/chdr_12sc_to_16sc.v            |   176 +
 fpga/usrp3/lib/vita/chdr_12sc_to_16sc_tb.v         |   188 +
 fpga/usrp3/lib/vita/chdr_16sc_to_12sc.v            |   221 +
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 fpga/usrp3/lib/vita/chdr_16sc_to_8sc.v             |   186 +
 fpga/usrp3/lib/vita/chdr_16sc_to_8sc_tb.v          |   146 +
 fpga/usrp3/lib/vita/chdr_16sc_to_xxxx_chain.v      |   105 +
 fpga/usrp3/lib/vita/chdr_32f_to_16sc.v             |   142 +
 fpga/usrp3/lib/vita/chdr_32f_to_16sc_tb.v          |   152 +
 fpga/usrp3/lib/vita/chdr_8sc_to_16sc.hex           |     5 +
 fpga/usrp3/lib/vita/chdr_8sc_to_16sc.v             |   115 +
 fpga/usrp3/lib/vita/chdr_8sc_to_16sc_tb.v          |   148 +
 fpga/usrp3/lib/vita/chdr_xxxx_to_16sc_chain.v      |   107 +
 fpga/usrp3/lib/vita/context_packet_gen.v           |    51 +
 fpga/usrp3/lib/vita/float_to_iq.v                  |    79 +
 fpga/usrp3/lib/vita/float_to_iq_tb.v               |    69 +
 fpga/usrp3/lib/vita/from12_to_x.hex                |    12 +
 fpga/usrp3/lib/vita/from16_to_x.hex                |     8 +
 fpga/usrp3/lib/vita/from8_to_x.hex                 |    12 +
 fpga/usrp3/lib/vita/generate_bits.cpp              |    87 +
 fpga/usrp3/lib/vita/iq_to_float.v                  |    92 +
 fpga/usrp3/lib/vita/iq_to_float_input.txt          | 65536 +++++++++++++++++++
 fpga/usrp3/lib/vita/iq_to_float_output.txt         | 65536 +++++++++++++++++++
 fpga/usrp3/lib/vita/iq_to_float_tb.v               |    61 +
 fpga/usrp3/lib/vita/new_rx_control.v               |   242 +
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 fpga/usrp3/lib/vita/new_rx_tb.v                    |   135 +
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 fpga/usrp3/lib/vita/trigger_context_pkt.v          |    50 +
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 fpga/usrp3/top/b200/coregen/.gitignore             |     3 +
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 create mode 100755 fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl
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(limited to 'fpga')

diff --git a/fpga/.gitignore b/fpga/.gitignore
new file mode 100644
index 000000000..c0c57d1e3
--- /dev/null
+++ b/fpga/.gitignore
@@ -0,0 +1,8 @@
+*~
+\#*\#
+a.out
+*.vcd
+*.lxt
+.metadata
+.project
+.settings
diff --git a/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs b/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs
new file mode 100644
index 000000000..e7bbdb9d5
--- /dev/null
+++ b/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1062" ><arg fmt="%s" index="1">Parsing Verilog file &quot;/home/jblum/src/ettus/fpga_b200/usrp2/coregen/pll_100_40_75.v&quot; into library work</arg>
+</msg>
+
+<msg type="info" file="ProjectMgmt" num="1062" ><arg fmt="%s" index="1">Parsing Verilog file &quot;/home/jblum/src/ettus/fpga_b200/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v&quot; into library work</arg>
+</msg>
+
+</messages>
+
diff --git a/fpga/usrp2/coregen/coregen_s6.cgc b/fpga/usrp2/coregen/coregen_s6.cgc
new file mode 100644
index 000000000..90b359eab
--- /dev/null
+++ b/fpga/usrp2/coregen/coregen_s6.cgc
@@ -0,0 +1,2352 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+   <spirit:vendor>xilinx.com</spirit:vendor>
+   <spirit:library>project</spirit:library>
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+               <xilinx:simulationOptions>
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+                  <xilinx:asySymbol>false</xilinx:asySymbol>
+                  <xilinx:flowVendor>Other</xilinx:flowVendor>
+                  <xilinx:addPads>false</xilinx:addPads>
+                  <xilinx:removeRPMs>false</xilinx:removeRPMs>
+                  <xilinx:createNDF>false</xilinx:createNDF>
+                  <xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
+                  <xilinx:formalVerification>false</xilinx:formalVerification>
+               </xilinx:flowOptions>
+               <xilinx:simulationOptions>
+                  <xilinx:simulationModel>Behavioral</xilinx:simulationModel>
+                  <xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
+                  <xilinx:foundationSym>false</xilinx:foundationSym>
+               </xilinx:simulationOptions>
+               <xilinx:packageInfo>
+                  <xilinx:sourceCoreCreationDate>2012-04-24+06:33</xilinx:sourceCoreCreationDate>
+               </xilinx:packageInfo>
+            </xilinx:instanceProperties>
+         </spirit:vendorExtensions>
+      </spirit:componentInstance>
+      <spirit:componentInstance>
+         <spirit:instanceName>pll_100_40_75</spirit:instanceName>
+         <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="3.5" />
+         <spirit:configurableElementValues>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">pll_100_40_75</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">40.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">250.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">true</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">3</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">CLK_IN1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">CLK_OUT1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">CLK_OUT2</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">CLK_OUT3</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">CLK_OUT4</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">CLK_OUT5</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">CLK_OUT6</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">CLK_OUT7</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">DADDR</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">DCLK</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">DRDY</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">DWE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">DIN</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">DOUT</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">DEN</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">PSCLK</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">PSEN</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">PSINCDEC</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">PSDONE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">40.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">75.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">75.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">CLK_IN2</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">CLKFB_IN</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">CLKFB_IN_P</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">CLKFB_IN_N</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">CLKFB_OUT</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">CLKFB_OUT_P</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">CLKFB_OUT_N</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">lin</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">DONE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">RESET</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">LOCKED</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">POWER_DOWN</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">CLK_IN_SEL</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">INPUT_CLK_STOPPED</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">CLKFB_STOPPED</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">4.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">4.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_DCM">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_NOTES">None</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKDV_DIVIDE">2.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKFX_DIVIDE">2</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKFX_MULTIPLY">5</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKIN_DIVIDE_BY_2">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKIN_PERIOD">25.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKOUT_PHASE_SHIFT">NONE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_DESKEW_ADJUST">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_PHASE_SHIFT">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_FEEDBACK">1X</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT1_PORT">CLKFX</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT2_PORT">CLK0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT3_PORT">CLKFX</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT4_PORT">CLKFX</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT5_PORT">CLK0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT6_PORT">CLK0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_DCM_CLKGEN">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_NOTES">None</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFX_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFX_MULTIPLY">4</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFXDV_DIVIDE">2</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFX_MD_MAX">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_STARTUP_WAIT">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_SPREAD_SPECTRUM">NONE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLK_OUT1_PORT">CLKFX</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLK_OUT2_PORT">CLKFX</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLK_OUT3_PORT">CLKFX</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">15</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">25.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">6</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">15</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">8</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">8</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_PLL_CASCADE">NONE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">AUTO</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">DCM_SP</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMPONENT_NAME">pll_100_40_75</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">lin</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">PLL_BASE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">40.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">3</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary__________40.000____________0.010</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___100.000______0.000______50.0______252.791____220.216</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2____40.000______0.000______50.0______309.264____220.216</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">CLK_OUT3____75.000______0.000______50.0______269.846____220.216</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output </spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">40.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">75.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">75.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">100.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">40.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">75.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">N/A</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">N/A</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">N/A</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">N/A</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">N/A</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">N/A</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">N/A</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">N/A</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">N/A</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">N/A</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">N/A</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">N/A</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">4.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">4.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">None</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">15</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">25.000</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">6</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">15</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">8</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">8</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
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+      <xilinx:instanceProperties>
+         <xilinx:projectOptions>
+            <xilinx:projectName>coregen_s6</xilinx:projectName>
+            <xilinx:outputDirectory>./</xilinx:outputDirectory>
+            <xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
+            <xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
+         </xilinx:projectOptions>
+         <xilinx:part>
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+            <xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
+            <xilinx:package>csg484</xilinx:package>
+            <xilinx:speedGrade>-3</xilinx:speedGrade>
+         </xilinx:part>
+         <xilinx:flowOptions>
+            <xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
+            <xilinx:designEntry>Verilog</xilinx:designEntry>
+            <xilinx:asySymbol>true</xilinx:asySymbol>
+            <xilinx:flowVendor>Other</xilinx:flowVendor>
+            <xilinx:addPads>false</xilinx:addPads>
+            <xilinx:removeRPMs>false</xilinx:removeRPMs>
+            <xilinx:createNDF>false</xilinx:createNDF>
+            <xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
+            <xilinx:formalVerification>false</xilinx:formalVerification>
+         </xilinx:flowOptions>
+         <xilinx:simulationOptions>
+            <xilinx:simulationModel>Behavioral</xilinx:simulationModel>
+            <xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
+            <xilinx:foundationSym>false</xilinx:foundationSym>
+         </xilinx:simulationOptions>
+      </xilinx:instanceProperties>
+   </spirit:vendorExtensions>
+</spirit:design>
+
diff --git a/fpga/usrp2/coregen/coregen_s6.cgp b/fpga/usrp2/coregen/coregen_s6.cgp
new file mode 100644
index 000000000..1abd1b021
--- /dev/null
+++ b/fpga/usrp2/coregen/coregen_s6.cgp
@@ -0,0 +1,22 @@
+# Date: Fri May  4 20:42:23 2012
+
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+SET workingdirectory = ./tmp/
+
+# CRC: f7d4ca66
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy
new file mode 100644
index 000000000..9664f3a57
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy
@@ -0,0 +1,49 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 fifo_s6_1Kx36_2clk
+RECTANGLE Normal 32 32 544 768
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName din[35:0]
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName wr_clk
+PINATTR Polarity IN
+LINE Normal 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName rd_clk
+PINATTR Polarity IN
+LINE Normal 144 800 144 768
+PIN 144 800 BOTTOM 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Wide 576 80 544 80
+PIN 576 80 RIGHT 36
+PINATTR PinName dout[35:0]
+PINATTR Polarity OUT
+LINE Normal 576 208 544 208
+PIN 576 208 RIGHT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Wide 576 368 544 368
+PIN 576 368 RIGHT 36
+PINATTR PinName wr_data_count[10:0]
+PINATTR Polarity OUT
+LINE Normal 576 432 544 432
+PIN 576 432 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+LINE Wide 576 592 544 592
+PIN 576 592 RIGHT 36
+PINATTR PinName rd_data_count[10:0]
+PINATTR Polarity OUT
+
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise
new file mode 100644
index 000000000..90240bfb2
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_s6_1Kx36_2clk.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_s6_1Kx36_2clk.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_s6_1Kx36_2clk.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc
new file mode 100644
index 000000000..f7e21b27e
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v
new file mode 100644
index 000000000..593d3f82c
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v
@@ -0,0 +1,173 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_s6_1Kx36_2clk.v when simulating
+// the core, fifo_s6_1Kx36_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_s6_1Kx36_2clk(
+	rst,
+	wr_clk,
+	rd_clk,
+	din,
+	wr_en,
+	rd_en,
+	dout,
+	full,
+	empty,
+	rd_data_count,
+	wr_data_count);
+
+
+input rst;
+input wr_clk;
+input rd_clk;
+input [35 : 0] din;
+input wr_en;
+input rd_en;
+output [35 : 0] dout;
+output full;
+output empty;
+output [10 : 0] rd_data_count;
+output [10 : 0] wr_data_count;
+
+// synthesis translate_off
+
+      FIFO_GENERATOR_V6_1 #(
+		.C_COMMON_CLOCK(0),
+		.C_COUNT_TYPE(0),
+		.C_DATA_COUNT_WIDTH(10),
+		.C_DEFAULT_VALUE("BlankString"),
+		.C_DIN_WIDTH(36),
+		.C_DOUT_RST_VAL("0"),
+		.C_DOUT_WIDTH(36),
+		.C_ENABLE_RLOCS(0),
+		.C_ENABLE_RST_SYNC(1),
+		.C_ERROR_INJECTION_TYPE(0),
+		.C_FAMILY("spartan6"),
+		.C_FULL_FLAGS_RST_VAL(1),
+		.C_HAS_ALMOST_EMPTY(0),
+		.C_HAS_ALMOST_FULL(0),
+		.C_HAS_BACKUP(0),
+		.C_HAS_DATA_COUNT(0),
+		.C_HAS_INT_CLK(0),
+		.C_HAS_MEMINIT_FILE(0),
+		.C_HAS_OVERFLOW(0),
+		.C_HAS_RD_DATA_COUNT(1),
+		.C_HAS_RD_RST(0),
+		.C_HAS_RST(1),
+		.C_HAS_SRST(0),
+		.C_HAS_UNDERFLOW(0),
+		.C_HAS_VALID(0),
+		.C_HAS_WR_ACK(0),
+		.C_HAS_WR_DATA_COUNT(1),
+		.C_HAS_WR_RST(0),
+		.C_IMPLEMENTATION_TYPE(2),
+		.C_INIT_WR_PNTR_VAL(0),
+		.C_MEMORY_TYPE(1),
+		.C_MIF_FILE_NAME("BlankString"),
+		.C_MSGON_VAL(1),
+		.C_OPTIMIZATION_MODE(0),
+		.C_OVERFLOW_LOW(0),
+		.C_PRELOAD_LATENCY(0),
+		.C_PRELOAD_REGS(1),
+		.C_PRIM_FIFO_TYPE("1kx36"),
+		.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+		.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+		.C_PROG_EMPTY_TYPE(0),
+		.C_PROG_FULL_THRESH_ASSERT_VAL(1023),
+		.C_PROG_FULL_THRESH_NEGATE_VAL(1022),
+		.C_PROG_FULL_TYPE(0),
+		.C_RD_DATA_COUNT_WIDTH(11),
+		.C_RD_DEPTH(1024),
+		.C_RD_FREQ(1),
+		.C_RD_PNTR_WIDTH(10),
+		.C_UNDERFLOW_LOW(0),
+		.C_USE_DOUT_RST(1),
+		.C_USE_ECC(0),
+		.C_USE_EMBEDDED_REG(0),
+		.C_USE_FIFO16_FLAGS(0),
+		.C_USE_FWFT_DATA_COUNT(1),
+		.C_VALID_LOW(0),
+		.C_WR_ACK_LOW(0),
+		.C_WR_DATA_COUNT_WIDTH(11),
+		.C_WR_DEPTH(1024),
+		.C_WR_FREQ(1),
+		.C_WR_PNTR_WIDTH(10),
+		.C_WR_RESPONSE_LATENCY(1))
+	inst (
+		.RST(rst),
+		.WR_CLK(wr_clk),
+		.RD_CLK(rd_clk),
+		.DIN(din),
+		.WR_EN(wr_en),
+		.RD_EN(rd_en),
+		.DOUT(dout),
+		.FULL(full),
+		.EMPTY(empty),
+		.RD_DATA_COUNT(rd_data_count),
+		.WR_DATA_COUNT(wr_data_count),
+		.BACKUP(),
+		.BACKUP_MARKER(),
+		.CLK(),
+		.SRST(),
+		.WR_RST(),
+		.RD_RST(),
+		.PROG_EMPTY_THRESH(),
+		.PROG_EMPTY_THRESH_ASSERT(),
+		.PROG_EMPTY_THRESH_NEGATE(),
+		.PROG_FULL_THRESH(),
+		.PROG_FULL_THRESH_ASSERT(),
+		.PROG_FULL_THRESH_NEGATE(),
+		.INT_CLK(),
+		.INJECTDBITERR(),
+		.INJECTSBITERR(),
+		.ALMOST_FULL(),
+		.WR_ACK(),
+		.OVERFLOW(),
+		.ALMOST_EMPTY(),
+		.VALID(),
+		.UNDERFLOW(),
+		.DATA_COUNT(),
+		.PROG_FULL(),
+		.PROG_EMPTY(),
+		.SBITERR(),
+		.DBITERR());
+
+
+// synthesis translate_on
+
+endmodule
+
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo
new file mode 100644
index 000000000..e348767a3
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo
@@ -0,0 +1,53 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_s6_1Kx36_2clk YourInstanceName (
+	.rst(rst),
+	.wr_clk(wr_clk),
+	.rd_clk(rd_clk),
+	.din(din), // Bus [35 : 0] 
+	.wr_en(wr_en),
+	.rd_en(rd_en),
+	.dout(dout), // Bus [35 : 0] 
+	.full(full),
+	.empty(empty),
+	.rd_data_count(rd_data_count), // Bus [10 : 0] 
+	.wr_data_count(wr_data_count)); // Bus [10 : 0] 
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_s6_1Kx36_2clk.v when simulating
+// the core, fifo_s6_1Kx36_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco
new file mode 100644
index 000000000..14ad27c2a
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco
@@ -0,0 +1,84 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.1
+# Date: Fri May  4 20:49:07 2012
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.1
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_s6_1Kx36_2clk
+CSET data_count=false
+CSET data_count_width=10
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=1023
+CSET full_threshold_negate_value=1022
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=36
+CSET input_depth=1024
+CSET output_data_width=36
+CSET output_depth=1024
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=true
+CSET read_data_count_width=11
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=true
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=true
+CSET write_data_count_width=11
+# END Parameters
+GENERATE
+# CRC: 5f5a2e48
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise
new file mode 100644
index 000000000..b6109869c
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise
@@ -0,0 +1,392 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="fifo_s6_1Kx36_2clk.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="fifo_s6_1Kx36_2clk.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="PostMapSimulation"/>
+      <association xil_pn:name="PostRouteSimulation"/>
+      <association xil_pn:name="PostTranslateSimulation"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_s6_1Kx36_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_s6_1Kx36_2clk.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_s6_1Kx36_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="fifo_s6_1Kx36_2clk" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="fifo_s6_1Kx36_2clk_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="fifo_s6_1Kx36_2clk_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="fifo_s6_1Kx36_2clk_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="fifo_s6_1Kx36_2clk_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_s6_1Kx36_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-05-04T13:49:09" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="334FF80B875B41AA9C000F6D67B92F9C" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_flist.txt
new file mode 100644
index 000000000..4f5b34b9b
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_flist.txt
@@ -0,0 +1,13 @@
+# Output products list for <fifo_s6_1Kx36_2clk>
+_xmsgs/pn_parser.xmsgs
+fifo_generator_ug175.pdf
+fifo_s6_1Kx36_2clk.asy
+fifo_s6_1Kx36_2clk.gise
+fifo_s6_1Kx36_2clk.ngc
+fifo_s6_1Kx36_2clk.v
+fifo_s6_1Kx36_2clk.veo
+fifo_s6_1Kx36_2clk.xco
+fifo_s6_1Kx36_2clk.xise
+fifo_s6_1Kx36_2clk_flist.txt
+fifo_s6_1Kx36_2clk_readme.txt
+fifo_s6_1Kx36_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_readme.txt
new file mode 100644
index 000000000..b101bd8cf
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_readme.txt
@@ -0,0 +1,51 @@
+The following files were generated for 'fifo_s6_1Kx36_2clk' in directory 
+/home/matt/fpgapriv/usrp2/coregen/
+
+fifo_generator_ug175.pdf:
+   Please see the core data sheet.
+
+fifo_s6_1Kx36_2clk.asy:
+   Graphical symbol information file. Used by the ISE tools and some
+   third party tools to create a symbol representing the core.
+
+fifo_s6_1Kx36_2clk.gise:
+   ISE Project Navigator support file. This is a generated file and should
+   not be edited directly.
+
+fifo_s6_1Kx36_2clk.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+fifo_s6_1Kx36_2clk.v:
+   Verilog wrapper file provided to support functional simulation.
+   This file contains simulation model customization data that is
+   passed to a parameterized simulation model for the core.
+
+fifo_s6_1Kx36_2clk.veo:
+   VEO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a Verilog design.
+
+fifo_s6_1Kx36_2clk.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+fifo_s6_1Kx36_2clk.xise:
+   ISE Project Navigator support file. This is a generated file and should
+   not be edited directly.
+
+fifo_s6_1Kx36_2clk_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+fifo_s6_1Kx36_2clk_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+fifo_s6_1Kx36_2clk_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl
new file mode 100644
index 000000000..f9a9ac233
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl
@@ -0,0 +1,72 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_s6_1Kx36_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_s6_1Kx36_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_s6_1Kx36_2clk_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_s6_1Kx36_2clk
+}
+# ::fifo_s6_1Kx36_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_s6_1Kx36_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_1Kx36_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_s6_1Kx36_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy
new file mode 100644
index 000000000..0b429a886
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy
@@ -0,0 +1,49 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 fifo_s6_2Kx36_2clk
+RECTANGLE Normal 32 32 544 768
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName din[35:0]
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName wr_clk
+PINATTR Polarity IN
+LINE Normal 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName rd_clk
+PINATTR Polarity IN
+LINE Normal 144 800 144 768
+PIN 144 800 BOTTOM 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Wide 576 80 544 80
+PIN 576 80 RIGHT 36
+PINATTR PinName dout[35:0]
+PINATTR Polarity OUT
+LINE Normal 576 208 544 208
+PIN 576 208 RIGHT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Wide 576 368 544 368
+PIN 576 368 RIGHT 36
+PINATTR PinName wr_data_count[11:0]
+PINATTR Polarity OUT
+LINE Normal 576 432 544 432
+PIN 576 432 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+LINE Wide 576 592 544 592
+PIN 576 592 RIGHT 36
+PINATTR PinName rd_data_count[11:0]
+PINATTR Polarity OUT
+
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.gise b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.gise
new file mode 100644
index 000000000..d90a25595
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.gise
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_s6_2Kx36_2clk.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_s6_2Kx36_2clk.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_s6_2Kx36_2clk.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.ngc b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.ngc
new file mode 100644
index 000000000..994b767ea
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.v b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.v
new file mode 100644
index 000000000..9f2cc7d4e
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.v
@@ -0,0 +1,173 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_s6_2Kx36_2clk.v when simulating
+// the core, fifo_s6_2Kx36_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_s6_2Kx36_2clk(
+	rst,
+	wr_clk,
+	rd_clk,
+	din,
+	wr_en,
+	rd_en,
+	dout,
+	full,
+	empty,
+	rd_data_count,
+	wr_data_count);
+
+
+input rst;
+input wr_clk;
+input rd_clk;
+input [35 : 0] din;
+input wr_en;
+input rd_en;
+output [35 : 0] dout;
+output full;
+output empty;
+output [11 : 0] rd_data_count;
+output [11 : 0] wr_data_count;
+
+// synthesis translate_off
+
+      FIFO_GENERATOR_V6_1 #(
+		.C_COMMON_CLOCK(0),
+		.C_COUNT_TYPE(0),
+		.C_DATA_COUNT_WIDTH(11),
+		.C_DEFAULT_VALUE("BlankString"),
+		.C_DIN_WIDTH(36),
+		.C_DOUT_RST_VAL("0"),
+		.C_DOUT_WIDTH(36),
+		.C_ENABLE_RLOCS(0),
+		.C_ENABLE_RST_SYNC(1),
+		.C_ERROR_INJECTION_TYPE(0),
+		.C_FAMILY("spartan6"),
+		.C_FULL_FLAGS_RST_VAL(1),
+		.C_HAS_ALMOST_EMPTY(0),
+		.C_HAS_ALMOST_FULL(0),
+		.C_HAS_BACKUP(0),
+		.C_HAS_DATA_COUNT(0),
+		.C_HAS_INT_CLK(0),
+		.C_HAS_MEMINIT_FILE(0),
+		.C_HAS_OVERFLOW(0),
+		.C_HAS_RD_DATA_COUNT(1),
+		.C_HAS_RD_RST(0),
+		.C_HAS_RST(1),
+		.C_HAS_SRST(0),
+		.C_HAS_UNDERFLOW(0),
+		.C_HAS_VALID(0),
+		.C_HAS_WR_ACK(0),
+		.C_HAS_WR_DATA_COUNT(1),
+		.C_HAS_WR_RST(0),
+		.C_IMPLEMENTATION_TYPE(2),
+		.C_INIT_WR_PNTR_VAL(0),
+		.C_MEMORY_TYPE(1),
+		.C_MIF_FILE_NAME("BlankString"),
+		.C_MSGON_VAL(1),
+		.C_OPTIMIZATION_MODE(0),
+		.C_OVERFLOW_LOW(0),
+		.C_PRELOAD_LATENCY(0),
+		.C_PRELOAD_REGS(1),
+		.C_PRIM_FIFO_TYPE("2kx18"),
+		.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+		.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+		.C_PROG_EMPTY_TYPE(0),
+		.C_PROG_FULL_THRESH_ASSERT_VAL(2047),
+		.C_PROG_FULL_THRESH_NEGATE_VAL(2046),
+		.C_PROG_FULL_TYPE(0),
+		.C_RD_DATA_COUNT_WIDTH(12),
+		.C_RD_DEPTH(2048),
+		.C_RD_FREQ(1),
+		.C_RD_PNTR_WIDTH(11),
+		.C_UNDERFLOW_LOW(0),
+		.C_USE_DOUT_RST(1),
+		.C_USE_ECC(0),
+		.C_USE_EMBEDDED_REG(0),
+		.C_USE_FIFO16_FLAGS(0),
+		.C_USE_FWFT_DATA_COUNT(1),
+		.C_VALID_LOW(0),
+		.C_WR_ACK_LOW(0),
+		.C_WR_DATA_COUNT_WIDTH(12),
+		.C_WR_DEPTH(2048),
+		.C_WR_FREQ(1),
+		.C_WR_PNTR_WIDTH(11),
+		.C_WR_RESPONSE_LATENCY(1))
+	inst (
+		.RST(rst),
+		.WR_CLK(wr_clk),
+		.RD_CLK(rd_clk),
+		.DIN(din),
+		.WR_EN(wr_en),
+		.RD_EN(rd_en),
+		.DOUT(dout),
+		.FULL(full),
+		.EMPTY(empty),
+		.RD_DATA_COUNT(rd_data_count),
+		.WR_DATA_COUNT(wr_data_count),
+		.BACKUP(),
+		.BACKUP_MARKER(),
+		.CLK(),
+		.SRST(),
+		.WR_RST(),
+		.RD_RST(),
+		.PROG_EMPTY_THRESH(),
+		.PROG_EMPTY_THRESH_ASSERT(),
+		.PROG_EMPTY_THRESH_NEGATE(),
+		.PROG_FULL_THRESH(),
+		.PROG_FULL_THRESH_ASSERT(),
+		.PROG_FULL_THRESH_NEGATE(),
+		.INT_CLK(),
+		.INJECTDBITERR(),
+		.INJECTSBITERR(),
+		.ALMOST_FULL(),
+		.WR_ACK(),
+		.OVERFLOW(),
+		.ALMOST_EMPTY(),
+		.VALID(),
+		.UNDERFLOW(),
+		.DATA_COUNT(),
+		.PROG_FULL(),
+		.PROG_EMPTY(),
+		.SBITERR(),
+		.DBITERR());
+
+
+// synthesis translate_on
+
+endmodule
+
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.veo b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.veo
new file mode 100644
index 000000000..7657f41bc
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.veo
@@ -0,0 +1,53 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_s6_2Kx36_2clk YourInstanceName (
+	.rst(rst),
+	.wr_clk(wr_clk),
+	.rd_clk(rd_clk),
+	.din(din), // Bus [35 : 0] 
+	.wr_en(wr_en),
+	.rd_en(rd_en),
+	.dout(dout), // Bus [35 : 0] 
+	.full(full),
+	.empty(empty),
+	.rd_data_count(rd_data_count), // Bus [11 : 0] 
+	.wr_data_count(wr_data_count)); // Bus [11 : 0] 
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_s6_2Kx36_2clk.v when simulating
+// the core, fifo_s6_2Kx36_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xco b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xco
new file mode 100644
index 000000000..659795e5f
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xco
@@ -0,0 +1,84 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.1
+# Date: Fri May  4 20:55:54 2012
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.1
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_s6_2Kx36_2clk
+CSET data_count=false
+CSET data_count_width=11
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=2047
+CSET full_threshold_negate_value=2046
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=36
+CSET input_depth=2048
+CSET output_data_width=36
+CSET output_depth=2048
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=true
+CSET read_data_count_width=12
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=true
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=true
+CSET write_data_count_width=12
+# END Parameters
+GENERATE
+# CRC: e7a1c106
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xise b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xise
new file mode 100644
index 000000000..c09cc4b35
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xise
@@ -0,0 +1,392 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="fifo_s6_2Kx36_2clk.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="fifo_s6_2Kx36_2clk.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="PostMapSimulation"/>
+      <association xil_pn:name="PostRouteSimulation"/>
+      <association xil_pn:name="PostTranslateSimulation"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_s6_2Kx36_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_s6_2Kx36_2clk.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_s6_2Kx36_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="fifo_s6_2Kx36_2clk" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="fifo_s6_2Kx36_2clk_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="fifo_s6_2Kx36_2clk_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="fifo_s6_2Kx36_2clk_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="fifo_s6_2Kx36_2clk_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_s6_2Kx36_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-05-04T13:55:55" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B3454C89F83BDEF9B4A09CDC070DE482" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_flist.txt
new file mode 100644
index 000000000..3466e5f91
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_flist.txt
@@ -0,0 +1,13 @@
+# Output products list for <fifo_s6_2Kx36_2clk>
+_xmsgs/pn_parser.xmsgs
+fifo_generator_ug175.pdf
+fifo_s6_2Kx36_2clk.asy
+fifo_s6_2Kx36_2clk.gise
+fifo_s6_2Kx36_2clk.ngc
+fifo_s6_2Kx36_2clk.v
+fifo_s6_2Kx36_2clk.veo
+fifo_s6_2Kx36_2clk.xco
+fifo_s6_2Kx36_2clk.xise
+fifo_s6_2Kx36_2clk_flist.txt
+fifo_s6_2Kx36_2clk_readme.txt
+fifo_s6_2Kx36_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_readme.txt
new file mode 100644
index 000000000..3a017fbb0
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_readme.txt
@@ -0,0 +1,51 @@
+The following files were generated for 'fifo_s6_2Kx36_2clk' in directory 
+/home/matt/fpgapriv/usrp2/coregen/
+
+fifo_generator_ug175.pdf:
+   Please see the core data sheet.
+
+fifo_s6_2Kx36_2clk.asy:
+   Graphical symbol information file. Used by the ISE tools and some
+   third party tools to create a symbol representing the core.
+
+fifo_s6_2Kx36_2clk.gise:
+   ISE Project Navigator support file. This is a generated file and should
+   not be edited directly.
+
+fifo_s6_2Kx36_2clk.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+fifo_s6_2Kx36_2clk.v:
+   Verilog wrapper file provided to support functional simulation.
+   This file contains simulation model customization data that is
+   passed to a parameterized simulation model for the core.
+
+fifo_s6_2Kx36_2clk.veo:
+   VEO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a Verilog design.
+
+fifo_s6_2Kx36_2clk.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+fifo_s6_2Kx36_2clk.xise:
+   ISE Project Navigator support file. This is a generated file and should
+   not be edited directly.
+
+fifo_s6_2Kx36_2clk_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+fifo_s6_2Kx36_2clk_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+fifo_s6_2Kx36_2clk_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_xmdf.tcl
new file mode 100644
index 000000000..63b4f2099
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_xmdf.tcl
@@ -0,0 +1,72 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_s6_2Kx36_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_s6_2Kx36_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_s6_2Kx36_2clk_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_s6_2Kx36_2clk
+}
+# ::fifo_s6_2Kx36_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_s6_2Kx36_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_2Kx36_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_s6_2Kx36_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.asy b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.asy
new file mode 100644
index 000000000..5adf4bfb4
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.asy
@@ -0,0 +1,49 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 fifo_s6_512x36_2clk
+RECTANGLE Normal 32 32 544 768
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName din[35:0]
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName wr_clk
+PINATTR Polarity IN
+LINE Normal 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName rd_clk
+PINATTR Polarity IN
+LINE Normal 144 800 144 768
+PIN 144 800 BOTTOM 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Wide 576 80 544 80
+PIN 576 80 RIGHT 36
+PINATTR PinName dout[35:0]
+PINATTR Polarity OUT
+LINE Normal 576 208 544 208
+PIN 576 208 RIGHT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Wide 576 368 544 368
+PIN 576 368 RIGHT 36
+PINATTR PinName wr_data_count[9:0]
+PINATTR Polarity OUT
+LINE Normal 576 432 544 432
+PIN 576 432 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+LINE Wide 576 592 544 592
+PIN 576 592 RIGHT 36
+PINATTR PinName rd_data_count[9:0]
+PINATTR Polarity OUT
+
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.gise b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.gise
new file mode 100644
index 000000000..2edb1c020
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.gise
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_s6_512x36_2clk.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_s6_512x36_2clk.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_s6_512x36_2clk.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.ngc b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.ngc
new file mode 100644
index 000000000..523080a69
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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1c4283>7p}:9883>7}Y=><01;=55648 1c4283=7p}:9983>7}Y=>?01;=55678 1c4283<7p}:9683>7}Y=>>01;=55668 1c428327p}:9783>7}Y=>901;=55618 1c4283j7p}:b883>7}Y=0>01;=55868 1c4283i7p}:b983>7}Y=0901;=55818 1c4283h7p}:b683>7}Y=0801;=55808 1c4283o7p}:b783>7}Y=0;01;=55838 1c4283n7p}:b483>7}Y=0:01;=55828 1c4283m7p}:b583>7}Y=1l01;=559d8 1c428k;7p}:b283>7}Y=1201;=559:8 1c428k:7p}:ac83>7}Y=>n01;=556f8 1c428k97p}:a183>7}Y=>801;=55608 1c428k?7p}:9483>7}Y=>;01;=55638 1c428k>7p}:c083>7}Y=j;01;=55b38 1c428k=7p}:bc83>7}Y=kh01;=55c`8 1c428k<7p}91`83>7}Y>9l01;=561d8 1c428k27p}91983>7}Y>9o01;=561g8 1c428ki7p}91683>7}Y>9n01;=561f8 1c428kh7p}91783>7}Y>9i01;=561a8 1c428ko7p}91483>7}Y>9h01;=561`8 1c428kn7p}91583>7}Y>9k01;=561c8 1c428km7p}91283>7}Y>9301;=561;8 1c428h;7p}91383>7}Y>9201;=561:8 1c428h:7p}91083>7}Y>9=01;=56158 1c428h97p}91183>7}Y>9<01;=56148 1c428h87p}93883>7}Y>;o01;=563g8 1c428h?7p}93683>7}Y>;n01;=563f8 1c428h=7p}93783>7}Y>;i01;=563a8 1c428h<7p}93483>7}Y>;h01;=563`8 1c428h37p}93583>7}Y>;k01;=563c8 1c428h27p}93283>7}Y>;301;=563;8 1c428hj7p}93383>7}Y>;201;=563:8 1c428hi7p}93083>7}Y>;=01;=56358 1c428hh7p}93183>7}Y>;<01;=56348 1c428ho7p}92g83>7}Y>;?01;=56378 1c428hn7psab`f94?4|@=o?7p`mad83>7}O<l>0qclnf;296~N3m=1vbol?:181M2b<2weno?50;0xL1c33tdin?4?:3yK0`2<ughi?7>52zJ7a1=zfkh?6=4={I6f0>{ijk?1<7<tH5g7?xhej?0;6?uG4d68ykde?3:1>vF;e59~jgd?2909wE:j4:mfg?=838pD9k;;|lafd<72;qC8h:4}o`af?6=:rB?i95rnc``>5<5sA>n86sabcf94?4|@=o?7p`mbd83>7}O<l>0qclmf;296~N3m=1vbom?:181M2b<2wenn?50;0xL1c33tdio?4?:3yK0`2<ughh?7>52zJ7a1=zfki?6=4={I6f0>{ijj?1<7<tH5g7?xhek?0;6?uG4d68ykdd?3:1>vF;e59~jge?2909wE:j4:mff?=838pD9k;;|lagd<72;qC8h:4}o``f?6=:rB?i95rnca`>5<5sA>n86sabbf94?4|@=o?7p`mcd83>7}O<l>0qcllf;296~N3m=1vboj?:181M2b<2weni?50;0xL1c33tdih?4?:3yK0`2<ugho?7>52zJ7a1=zfkn?6=4={I6f0>{ijm?1<7<tH5g7?xhel?0;6?uG4d68ykdc?3:1>vF;e59~jgb?2909wE:j4:mfa?=838pD9k;;|la`d<72;qC8h:4}o`gf?6=:rB?i95rncf`>5<5sA>n86sabef94?4|@=o?7p`mdd83>7}O<l>0qclkf;296~N3m=1vbok?:181M2b<2wenh?50;0xL1c33tdii?4?:3yK0`2<ughn?7>52zJ7a1=zfko?6=4={I6f0>{ijl?1<7<tH5g7?xhem?0;6?uG4d68ykdb?3:1>vF;e59~jgc?2909wE:j4:mf`?=838pD9k;;|laad<72;qC8h:4}o`ff?6=:rB?i95rncg`>5<5sA>n86sabdf94?4|@=o?7p`med83>7}O<l>0qcljf;296~N3m=1vboh?:181M2b<2wenk?50;0xL1c33tdij?4?:3yK0`2<ughm?7>52zJ7a1=zfkl?6=4={I6f0>{ijo?1<7<tH5g7?xhen?0;6?uG4d68ykda?3:1>vF;e59~jg`?2909wE:j4:mfc?=838pD9k;;|labd<72;qC8h:4}o`ef?6=:rB?i95rncd`>5<5sA>n86sabgf94?4|@=o?7p`mfd83>7}O<l>0qclif;296~N3m=1vbn>?:181M2b<2weo=?50;0xL1c33tdh<?4?:3yK0`2<ugi;?7>52zJ7a1=zfj:?6=4={I6f0>{ik9?1<7<tH5g7?xhd8?0;6?uG4d68yke7?3:1>vF;e59~jf6?2909wE:j4:mg5?=838pD9k;;|l`4d<72;qC8h:4}oa3f?6=:rB?i95rnb2`>5<5sA>n86sac1f94?4|@=o?7p`l0d83>7}O<l>0qcm?f;296~N3m=1vbl>6:182M2b<2wem9:50;3xL1c33tdj884?:0yK0`2<ugk?:7>51zJ7a1=zfh><6=4>{I6f0>{ii=21<7?tH5g7?xhf<00;6<uG4d68ykg3i3:1=vF;e59~jd2e290:wE:j4:me1e=83;pD9k;;|lb0a<728qC8h:4}oc7a?6=9rB?i95rn`6e>5<6sA>n86saa4294?7|@=o?7p`n5083>4}O<l>0qco:2;295~N3m=1vbl;<:182M2b<2wem8:50;3xL1c33tdj984?:0yK0`2<ugk>:7>51zJ7a1=zfh?<6=4>{I6f0>{ii<21<7?tH5g7?xhf=00;6<uG4d68ykg2i3:1=vF;e59~jd3e290:wE:j4:me0e=83;pD9k;;|lb1a<728qC8h:4}oc6a?6=9rB?i95rn`7e>5<6sA>n86saa7294?7|@=o?7p`n6083>4}O<l>0qco92;295~N3m=1vbl8<:182M2b<2wem;:50;3xL1c33tdj:84?:0yK0`2<ugk=:7>51zJ7a1=zfh<<6=4>{I6f0>{ii?21<7?tH5g7?xhf>00;6<uG4d68ykg1i3:1=vF;e59~jd0e290:wE:j4:me3e=83;pD9k;;|lb2a<728qC8h:4}oc5a?6=9rB?i95rn`4e>5<6sA>n86saa6294?7|@=o?7p`n7083>4}O<l>0qco82;295~N3m=1vbl9<:182M2b<2wem::50;3xL1c33tdj;84?:0yK0`2<ugk<:7>51zJ7a1=zfh=<6=4>{I6f0>{ii>21<7?tH5g7?xhf?00;6<uG4d68ykg0i3:1=vF;e59~jd1e290:wE:j4:me2e=83;pD9k;;|lb3a<728qC8h:4}oc4a?6=9rB?i95rn`5e>5<6sA>n86saa9294?7|@=o?7p`n8083>4}O<l>0qco72;295~N3m=1vbl6<:182M2b<2wem5:50;3xL1c33tdj484?:0yK0`2<ugk3:7>51zJ7a1=zfh2<6=4>{I6f0>{ii121<7?tH5g7?xhf000;6<uG4d68ykg?i3:1=vF;e59~jd>e290:wE:j4:me=e=83;pD9k;;|lb<a<728qC8h:4}oc;a?6=9rB?i95rn`:e>5<6sA>n86saa8294?7|@=o?7p`n9083>4}O<l>0qco62;295~N3m=1vbl7<:182M2b<2wem4:50;3xL1c33tdj584?:0yK0`2<ugk2:7>51zJ7a1=zfh3<6=4>{I6f0>{ii021<7?tH5g7?xhf100;6<uG4d68ykg>i3:1=vF;e59~jd?e290:wE:j4:me<e=83;pD9k;;|lb=a<728qC8h:4}oc:a?6=9rB?i95rn`;e>5<6sA>n86saa`294?7|@=o?7p`na083>4}O<l>0qcon2;295~N3m=1vblo<:182M2b<2weml:50;3xL1c33tdjm84?:0yK0`2<ugkj:7>51zJ7a1=zfhk<6=4>{I6f0>{iih21<7?tH5g7?xhfi00;6<uG4d68ykgfi3:1=vF;e59~jdge290:wE:j4:mede=83;pD9k;;|lbea<728qC8h:4}ocba?6=9rB?i95rn`ce>5<6sA>n86saac294?7|@=o?7p`nb083>4}O<l>0qcom2;295~N3m=1vbll<:182M2b<2wemo:50;3xL1c33tdjn84?:0yK0`2<ugki:7>51zJ7a1=zfhh<6=4>{I6f0>{iik21<7?tH5g7?xhfj00;6<uG4d68ykgei3:1=vF;e59~jdde290:wE:j4:mege=83;pD9k;;|lbfa<728qC8h:4}ocaa?6=9rB?i95rn``e>5<6sA>n86saab294?7|@=o?7p`nc083>4}O<l>0qcol2;295~N3m=1vblm<:182M2b<2wemn:50;3xL1c33tdjo84?:0yK0`2<ugkh:7>51zJ7a1=zfhi<6=4>{I6f0>{iij21<7?tH5g7?xhfk00;6<uG4d68ykgdi3:1=vF;e59~jdee290:wE:j4:mefe=83;pD9k;;|lbga<728qC8h:4}oc`a?6=9rB?i95rn`ae>5<6sA>n86saae294?7|@=o?7p`nd083>4}O<l>0qcok2;295~N3m=1vblj<:182M2b<2wemi:50;3xL1c33tdjh84?:0yK0`2<ugko:7>51zJ7a1=zfhn<6=4>{I6f0>{iim21<7?tH5g7?xhfl00;6<uG4d68ykgci3:1=vF;e59~jdbe290:wE:j4:meae=83;pD9k;;|lb`a<728qC8h:4}ocga?6=9rB?i95rn`fe>5<6sA>n86saad294?7|@=o?7p`ne083>4}O<l>0qcoj2;295~N3m=1vblk<:182M2b<2wemh:50;3xL1c33tdji84?:0yK0`2<ugkn:7>51zJ7a1=zfho<6=4>{I6f0>{iil21<7?tH5g7?xhfm00;6<uG4d68ykgbi3:1=vF;e59~jdce290:wE:j4:me`e=83;pD9k;;|lbaa<728qC8h:4}ocfa?6=9rB?i95rn`ge>5<6sA>n86saag294?7|@=o?7p`nf083>4}O<l>0qcoi2;295~N3m=1vblh<:182M2b<2wemk:50;3xL1c33tdjj84?:0yK0`2<ugkm:7>51zJ7a1=zfhl<6=4>{I6f0>{iio21<7?tH5g7?xhfn00;6<uG4d68ykgai3:1=vF;e59~jd`e290:wE:j4:mece=83;pD9k;;|lbba<728qC8h:4}ocea?6=9rB?i95rn`de>5<6sA>n86sab1294?7|@=o?7p`m0083>4}O<l>0qcl?2;295~N3m=1vbo><:182M2b<2wen=:50;3xL1c33tdi<84?:0yK0`2<ugh;:7>51zJ7a1=zfk:<6=4>{I6f0>{ij921<7?tH5g7?xhe800;6<uG4d68ykd7i3:1=vF;e59~jg6e290:wE:j4:mf5e=83;pD9k;;|la4a<728qC8h:4}o`3a?6=9rB?i95rnc2e>5<6sA>n86sab0294?7|@=o?7p`m1083>4}O<l>0qcl>2;295~N3m=1vbo?<:182M2b<2wen<:50;3xL1c33tdi=84?:0yK0`2<ugh::7>51zJ7a1=zfk;<6=4>{I6f0>{ij821<7?tH5g7?xhe900;6<uG4d68ykd6i3:1=vF;e59~jg7e290:wE:j4:mf4e=83;pD9k;;|la5a<728qC8h:4}o`2a?6=9rB?i95rnc3e>5<6sA>n86sab3294?7|@=o?7p`m2083>4}O<l>0qcl=2;295~N3m=1vbo<<:182M2b<2wen?:50;3xL1c33tdi>84?:0yK0`2<ugh9:7>51zJ7a1=zfk8<6=4>{I6f0>{ij;21<7?tH5g7?xhe:00;6<uG4d68ykd5i3:1=vF;e59~jg4e290:wE:j4:mf7e=83;pD9k;;|la6a<728qC8h:4}o`1a?6=9rB?i95rnc0e>5<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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.v b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.v
new file mode 100644
index 000000000..4b7a31173
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.v
@@ -0,0 +1,173 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_s6_512x36_2clk.v when simulating
+// the core, fifo_s6_512x36_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_s6_512x36_2clk(
+	rst,
+	wr_clk,
+	rd_clk,
+	din,
+	wr_en,
+	rd_en,
+	dout,
+	full,
+	empty,
+	rd_data_count,
+	wr_data_count);
+
+
+input rst;
+input wr_clk;
+input rd_clk;
+input [35 : 0] din;
+input wr_en;
+input rd_en;
+output [35 : 0] dout;
+output full;
+output empty;
+output [9 : 0] rd_data_count;
+output [9 : 0] wr_data_count;
+
+// synthesis translate_off
+
+      FIFO_GENERATOR_V6_1 #(
+		.C_COMMON_CLOCK(0),
+		.C_COUNT_TYPE(0),
+		.C_DATA_COUNT_WIDTH(9),
+		.C_DEFAULT_VALUE("BlankString"),
+		.C_DIN_WIDTH(36),
+		.C_DOUT_RST_VAL("0"),
+		.C_DOUT_WIDTH(36),
+		.C_ENABLE_RLOCS(0),
+		.C_ENABLE_RST_SYNC(1),
+		.C_ERROR_INJECTION_TYPE(0),
+		.C_FAMILY("spartan6"),
+		.C_FULL_FLAGS_RST_VAL(1),
+		.C_HAS_ALMOST_EMPTY(0),
+		.C_HAS_ALMOST_FULL(0),
+		.C_HAS_BACKUP(0),
+		.C_HAS_DATA_COUNT(0),
+		.C_HAS_INT_CLK(0),
+		.C_HAS_MEMINIT_FILE(0),
+		.C_HAS_OVERFLOW(0),
+		.C_HAS_RD_DATA_COUNT(1),
+		.C_HAS_RD_RST(0),
+		.C_HAS_RST(1),
+		.C_HAS_SRST(0),
+		.C_HAS_UNDERFLOW(0),
+		.C_HAS_VALID(0),
+		.C_HAS_WR_ACK(0),
+		.C_HAS_WR_DATA_COUNT(1),
+		.C_HAS_WR_RST(0),
+		.C_IMPLEMENTATION_TYPE(2),
+		.C_INIT_WR_PNTR_VAL(0),
+		.C_MEMORY_TYPE(1),
+		.C_MIF_FILE_NAME("BlankString"),
+		.C_MSGON_VAL(1),
+		.C_OPTIMIZATION_MODE(0),
+		.C_OVERFLOW_LOW(0),
+		.C_PRELOAD_LATENCY(0),
+		.C_PRELOAD_REGS(1),
+		.C_PRIM_FIFO_TYPE("512x36"),
+		.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+		.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+		.C_PROG_EMPTY_TYPE(0),
+		.C_PROG_FULL_THRESH_ASSERT_VAL(511),
+		.C_PROG_FULL_THRESH_NEGATE_VAL(510),
+		.C_PROG_FULL_TYPE(0),
+		.C_RD_DATA_COUNT_WIDTH(10),
+		.C_RD_DEPTH(512),
+		.C_RD_FREQ(1),
+		.C_RD_PNTR_WIDTH(9),
+		.C_UNDERFLOW_LOW(0),
+		.C_USE_DOUT_RST(1),
+		.C_USE_ECC(0),
+		.C_USE_EMBEDDED_REG(0),
+		.C_USE_FIFO16_FLAGS(0),
+		.C_USE_FWFT_DATA_COUNT(1),
+		.C_VALID_LOW(0),
+		.C_WR_ACK_LOW(0),
+		.C_WR_DATA_COUNT_WIDTH(10),
+		.C_WR_DEPTH(512),
+		.C_WR_FREQ(1),
+		.C_WR_PNTR_WIDTH(9),
+		.C_WR_RESPONSE_LATENCY(1))
+	inst (
+		.RST(rst),
+		.WR_CLK(wr_clk),
+		.RD_CLK(rd_clk),
+		.DIN(din),
+		.WR_EN(wr_en),
+		.RD_EN(rd_en),
+		.DOUT(dout),
+		.FULL(full),
+		.EMPTY(empty),
+		.RD_DATA_COUNT(rd_data_count),
+		.WR_DATA_COUNT(wr_data_count),
+		.BACKUP(),
+		.BACKUP_MARKER(),
+		.CLK(),
+		.SRST(),
+		.WR_RST(),
+		.RD_RST(),
+		.PROG_EMPTY_THRESH(),
+		.PROG_EMPTY_THRESH_ASSERT(),
+		.PROG_EMPTY_THRESH_NEGATE(),
+		.PROG_FULL_THRESH(),
+		.PROG_FULL_THRESH_ASSERT(),
+		.PROG_FULL_THRESH_NEGATE(),
+		.INT_CLK(),
+		.INJECTDBITERR(),
+		.INJECTSBITERR(),
+		.ALMOST_FULL(),
+		.WR_ACK(),
+		.OVERFLOW(),
+		.ALMOST_EMPTY(),
+		.VALID(),
+		.UNDERFLOW(),
+		.DATA_COUNT(),
+		.PROG_FULL(),
+		.PROG_EMPTY(),
+		.SBITERR(),
+		.DBITERR());
+
+
+// synthesis translate_on
+
+endmodule
+
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.veo b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.veo
new file mode 100644
index 000000000..766965d02
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.veo
@@ -0,0 +1,53 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_s6_512x36_2clk YourInstanceName (
+	.rst(rst),
+	.wr_clk(wr_clk),
+	.rd_clk(rd_clk),
+	.din(din), // Bus [35 : 0] 
+	.wr_en(wr_en),
+	.rd_en(rd_en),
+	.dout(dout), // Bus [35 : 0] 
+	.full(full),
+	.empty(empty),
+	.rd_data_count(rd_data_count), // Bus [9 : 0] 
+	.wr_data_count(wr_data_count)); // Bus [9 : 0] 
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_s6_512x36_2clk.v when simulating
+// the core, fifo_s6_512x36_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xco b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xco
new file mode 100644
index 000000000..4f40b8702
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xco
@@ -0,0 +1,84 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.1
+# Date: Fri May  4 20:46:48 2012
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.1
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_s6_512x36_2clk
+CSET data_count=false
+CSET data_count_width=9
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=511
+CSET full_threshold_negate_value=510
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=36
+CSET input_depth=512
+CSET output_data_width=36
+CSET output_depth=512
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=true
+CSET read_data_count_width=10
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=true
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=true
+CSET write_data_count_width=10
+# END Parameters
+GENERATE
+# CRC: a4cd75c3
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xise b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xise
new file mode 100644
index 000000000..9f43a161e
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xise
@@ -0,0 +1,392 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="fifo_s6_512x36_2clk.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="fifo_s6_512x36_2clk.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="PostMapSimulation"/>
+      <association xil_pn:name="PostRouteSimulation"/>
+      <association xil_pn:name="PostTranslateSimulation"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_s6_512x36_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_s6_512x36_2clk.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_s6_512x36_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="fifo_s6_512x36_2clk" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="fifo_s6_512x36_2clk_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="fifo_s6_512x36_2clk_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="fifo_s6_512x36_2clk_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="fifo_s6_512x36_2clk_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_s6_512x36_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-05-04T13:46:49" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F64CBD650BAE027D4131AE4B4B6DCBBE" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_flist.txt
new file mode 100644
index 000000000..e72108931
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_flist.txt
@@ -0,0 +1,13 @@
+# Output products list for <fifo_s6_512x36_2clk>
+_xmsgs/pn_parser.xmsgs
+fifo_generator_ug175.pdf
+fifo_s6_512x36_2clk.asy
+fifo_s6_512x36_2clk.gise
+fifo_s6_512x36_2clk.ngc
+fifo_s6_512x36_2clk.v
+fifo_s6_512x36_2clk.veo
+fifo_s6_512x36_2clk.xco
+fifo_s6_512x36_2clk.xise
+fifo_s6_512x36_2clk_flist.txt
+fifo_s6_512x36_2clk_readme.txt
+fifo_s6_512x36_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_readme.txt
new file mode 100644
index 000000000..21f058c0b
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_readme.txt
@@ -0,0 +1,51 @@
+The following files were generated for 'fifo_s6_512x36_2clk' in directory 
+/home/matt/fpgapriv/usrp2/coregen/
+
+fifo_generator_ug175.pdf:
+   Please see the core data sheet.
+
+fifo_s6_512x36_2clk.asy:
+   Graphical symbol information file. Used by the ISE tools and some
+   third party tools to create a symbol representing the core.
+
+fifo_s6_512x36_2clk.gise:
+   ISE Project Navigator support file. This is a generated file and should
+   not be edited directly.
+
+fifo_s6_512x36_2clk.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+fifo_s6_512x36_2clk.v:
+   Verilog wrapper file provided to support functional simulation.
+   This file contains simulation model customization data that is
+   passed to a parameterized simulation model for the core.
+
+fifo_s6_512x36_2clk.veo:
+   VEO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a Verilog design.
+
+fifo_s6_512x36_2clk.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+fifo_s6_512x36_2clk.xise:
+   ISE Project Navigator support file. This is a generated file and should
+   not be edited directly.
+
+fifo_s6_512x36_2clk_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+fifo_s6_512x36_2clk_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+fifo_s6_512x36_2clk_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp2/coregen/fifo_s6_512x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_xmdf.tcl
new file mode 100644
index 000000000..150807984
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_s6_512x36_2clk_xmdf.tcl
@@ -0,0 +1,72 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_s6_512x36_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_s6_512x36_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_s6_512x36_2clk_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_s6_512x36_2clk
+}
+# ::fifo_s6_512x36_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_s6_512x36_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_s6_512x36_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_s6_512x36_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ncf
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp2/coregen/pll_100_40_75.asy b/fpga/usrp2/coregen/pll_100_40_75.asy
new file mode 100644
index 000000000..9cd1ec359
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75.asy
@@ -0,0 +1,29 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 pll_100_40_75
+RECTANGLE Normal 32 32 576 1088
+LINE Normal 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName clk_in1
+PINATTR Polarity IN
+LINE Normal 0 432 32 432
+PIN 0 432 LEFT 36
+PINATTR PinName reset
+PINATTR Polarity IN
+LINE Normal 608 80 576 80
+PIN 608 80 RIGHT 36
+PINATTR PinName clk_out1
+PINATTR Polarity OUT
+LINE Normal 608 176 576 176
+PIN 608 176 RIGHT 36
+PINATTR PinName clk_out2
+PINATTR Polarity OUT
+LINE Normal 608 272 576 272
+PIN 608 272 RIGHT 36
+PINATTR PinName clk_out3
+PINATTR Polarity OUT
+LINE Normal 608 976 576 976
+PIN 608 976 RIGHT 36
+PINATTR PinName locked
+PINATTR Polarity OUT
+
diff --git a/fpga/usrp2/coregen/pll_100_40_75.gise b/fpga/usrp2/coregen/pll_100_40_75.gise
new file mode 100644
index 000000000..c94415619
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75.gise
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="pll_100_40_75.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="pll_100_40_75.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="pll_100_40_75.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp2/coregen/pll_100_40_75.ucf b/fpga/usrp2/coregen/pll_100_40_75.ucf
new file mode 100755
index 000000000..d8590fabb
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75.ucf
@@ -0,0 +1,71 @@
+# file: pll_100_40_75.ucf
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps;
+
+# Derived clock periods. These are commented out because they are 
+#   automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you 
+#   can copy them into your module level timing checks
+#-----------------------------------------------------------------
+# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
+# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 100.000 MHz;
+
+# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
+# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 40.000 MHz;
+# NET "clk_int[3]" TNM_NET = "CLK_OUT3";
+# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 75.000 MHz;
+
+# FALSE PATH constraints 
+PIN "RESET" TIG;
+
diff --git a/fpga/usrp2/coregen/pll_100_40_75.v b/fpga/usrp2/coregen/pll_100_40_75.v
new file mode 100755
index 000000000..b400ece75
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75.v
@@ -0,0 +1,158 @@
+// file: pll_100_40_75.v
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+// "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+//----------------------------------------------------------------------------
+// CLK_OUT1___100.000______0.000______50.0______252.791____220.216
+// CLK_OUT2____40.000______0.000______50.0______309.264____220.216
+// CLK_OUT3____75.000______0.000______50.0______269.846____220.216
+//
+//----------------------------------------------------------------------------
+// "Input Clock   Freq (MHz)    Input Jitter (UI)"
+//----------------------------------------------------------------------------
+// __primary__________40.000____________0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "pll_100_40_75,clk_wiz_v4_1,{component_name=pll_100_40_75,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=25.000,clkin2_period=25.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
+module pll_100_40_75
+ (// Clock in ports
+  input         CLK_IN1,
+  // Clock out ports
+  output        CLK_OUT1,
+  output        CLK_OUT2,
+  output        CLK_OUT3,
+  // Status and control signals
+  input         RESET,
+  output        LOCKED
+ );
+
+  // Input buffering
+  //------------------------------------
+  IBUFG clkin1_buf
+   (.O (clkin1),
+    .I (CLK_IN1));
+
+
+  // Clocking primitive
+  //------------------------------------
+  // Instantiation of the PLL primitive
+  //    * Unused inputs are tied off
+  //    * Unused outputs are labeled unused
+  wire [15:0] do_unused;
+  wire        drdy_unused;
+  wire        clkfbout;
+  wire        clkfbout_buf;
+  wire        clkout3_unused;
+  wire        clkout4_unused;
+  wire        clkout5_unused;
+
+  PLL_BASE
+  #(.BANDWIDTH              ("OPTIMIZED"),
+    .CLK_FEEDBACK           ("CLKFBOUT"),
+    .COMPENSATION           ("SYSTEM_SYNCHRONOUS"),
+    .DIVCLK_DIVIDE          (1),
+    .CLKFBOUT_MULT          (15),
+    .CLKFBOUT_PHASE         (0.000),
+    .CLKOUT0_DIVIDE         (6),
+    .CLKOUT0_PHASE          (0.000),
+    .CLKOUT0_DUTY_CYCLE     (0.500),
+    .CLKOUT1_DIVIDE         (15),
+    .CLKOUT1_PHASE          (0.000),
+    .CLKOUT1_DUTY_CYCLE     (0.500),
+    .CLKOUT2_DIVIDE         (8),
+    .CLKOUT2_PHASE          (0.000),
+    .CLKOUT2_DUTY_CYCLE     (0.500),
+    .CLKIN_PERIOD           (25.000),
+    .REF_JITTER             (0.010))
+  pll_base_inst
+    // Output clocks
+   (.CLKFBOUT              (clkfbout),
+    .CLKOUT0               (clkout0),
+    .CLKOUT1               (clkout1),
+    .CLKOUT2               (clkout2),
+    .CLKOUT3               (clkout3_unused),
+    .CLKOUT4               (clkout4_unused),
+    .CLKOUT5               (clkout5_unused),
+    // Status and control signals
+    .LOCKED                (LOCKED),
+    .RST                   (RESET),
+     // Input clock control
+    .CLKFBIN               (clkfbout_buf),
+    .CLKIN                 (clkin1));
+
+
+  // Output buffering
+  //-----------------------------------
+  BUFG clkf_buf
+   (.O (clkfbout_buf),
+    .I (clkfbout));
+
+  BUFG clkout1_buf
+   (.O   (CLK_OUT1),
+    .I   (clkout0));
+
+
+  BUFG clkout2_buf
+   (.O   (CLK_OUT2),
+    .I   (clkout1));
+
+  BUFG clkout3_buf
+   (.O   (CLK_OUT3),
+    .I   (clkout2));
+
+
+
+endmodule
diff --git a/fpga/usrp2/coregen/pll_100_40_75.veo b/fpga/usrp2/coregen/pll_100_40_75.veo
new file mode 100755
index 000000000..c6ebc5f5c
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75.veo
@@ -0,0 +1,82 @@
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+// "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+//----------------------------------------------------------------------------
+// CLK_OUT1___100.000______0.000______50.0______252.791____220.216
+// CLK_OUT2____40.000______0.000______50.0______309.264____220.216
+// CLK_OUT3____75.000______0.000______50.0______269.846____220.216
+//
+//----------------------------------------------------------------------------
+// "Input Clock   Freq (MHz)    Input Jitter (UI)"
+//----------------------------------------------------------------------------
+// __primary__________40.000____________0.010
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+
+  pll_100_40_75 instance_name
+   (// Clock in ports
+    .CLK_IN1(CLK_IN1),      // IN
+    // Clock out ports
+    .CLK_OUT1(CLK_OUT1),     // OUT
+    .CLK_OUT2(CLK_OUT2),     // OUT
+    .CLK_OUT3(CLK_OUT3),     // OUT
+    // Status and control signals
+    .RESET(RESET),// IN
+    .LOCKED(LOCKED));      // OUT
+// INST_TAG_END ------ End INSTANTIATION Template ---------
diff --git a/fpga/usrp2/coregen/pll_100_40_75.xco b/fpga/usrp2/coregen/pll_100_40_75.xco
new file mode 100644
index 000000000..a3a0eb4fb
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75.xco
@@ -0,0 +1,266 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.1
+# Date: Mon Jun 25 01:21:52 2012
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:clk_wiz:3.5
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.5
+# END Select
+# BEGIN Parameters
+CSET calc_done=DONE
+CSET clk_in_sel_port=CLK_IN_SEL
+CSET clk_out1_port=CLK_OUT1
+CSET clk_out1_use_fine_ps_gui=false
+CSET clk_out2_port=CLK_OUT2
+CSET clk_out2_use_fine_ps_gui=false
+CSET clk_out3_port=CLK_OUT3
+CSET clk_out3_use_fine_ps_gui=false
+CSET clk_out4_port=CLK_OUT4
+CSET clk_out4_use_fine_ps_gui=false
+CSET clk_out5_port=CLK_OUT5
+CSET clk_out5_use_fine_ps_gui=false
+CSET clk_out6_port=CLK_OUT6
+CSET clk_out6_use_fine_ps_gui=false
+CSET clk_out7_port=CLK_OUT7
+CSET clk_out7_use_fine_ps_gui=false
+CSET clk_valid_port=CLK_VALID
+CSET clkfb_in_n_port=CLKFB_IN_N
+CSET clkfb_in_p_port=CLKFB_IN_P
+CSET clkfb_in_port=CLKFB_IN
+CSET clkfb_in_signaling=SINGLE
+CSET clkfb_out_n_port=CLKFB_OUT_N
+CSET clkfb_out_p_port=CLKFB_OUT_P
+CSET clkfb_out_port=CLKFB_OUT
+CSET clkfb_stopped_port=CLKFB_STOPPED
+CSET clkin1_jitter_ps=250.0
+CSET clkin1_ui_jitter=0.010
+CSET clkin2_jitter_ps=100.0
+CSET clkin2_ui_jitter=0.010
+CSET clkout1_drives=BUFG
+CSET clkout1_requested_duty_cycle=50.0
+CSET clkout1_requested_out_freq=100.000
+CSET clkout1_requested_phase=0.000
+CSET clkout2_drives=BUFG
+CSET clkout2_requested_duty_cycle=50.0
+CSET clkout2_requested_out_freq=40.000
+CSET clkout2_requested_phase=0.000
+CSET clkout2_used=true
+CSET clkout3_drives=BUFG
+CSET clkout3_requested_duty_cycle=50.0
+CSET clkout3_requested_out_freq=75.000
+CSET clkout3_requested_phase=0.000
+CSET clkout3_used=true
+CSET clkout4_drives=BUFG
+CSET clkout4_requested_duty_cycle=50.0
+CSET clkout4_requested_out_freq=75.000
+CSET clkout4_requested_phase=0.000
+CSET clkout4_used=false
+CSET clkout5_drives=BUFG
+CSET clkout5_requested_duty_cycle=50.0
+CSET clkout5_requested_out_freq=100.000
+CSET clkout5_requested_phase=0.000
+CSET clkout5_used=false
+CSET clkout6_drives=BUFG
+CSET clkout6_requested_duty_cycle=50.0
+CSET clkout6_requested_out_freq=100.000
+CSET clkout6_requested_phase=0.000
+CSET clkout6_used=false
+CSET clkout7_drives=BUFG
+CSET clkout7_requested_duty_cycle=50.0
+CSET clkout7_requested_out_freq=100.000
+CSET clkout7_requested_phase=0.000
+CSET clkout7_used=false
+CSET clock_mgr_type=AUTO
+CSET component_name=pll_100_40_75
+CSET daddr_port=DADDR
+CSET dclk_port=DCLK
+CSET dcm_clk_feedback=1X
+CSET dcm_clk_out1_port=CLKFX
+CSET dcm_clk_out2_port=CLK0
+CSET dcm_clk_out3_port=CLKFX
+CSET dcm_clk_out4_port=CLKFX
+CSET dcm_clk_out5_port=CLK0
+CSET dcm_clk_out6_port=CLK0
+CSET dcm_clkdv_divide=2.0
+CSET dcm_clkfx_divide=2
+CSET dcm_clkfx_multiply=5
+CSET dcm_clkgen_clk_out1_port=CLKFX
+CSET dcm_clkgen_clk_out2_port=CLKFX
+CSET dcm_clkgen_clk_out3_port=CLKFX
+CSET dcm_clkgen_clkfx_divide=1
+CSET dcm_clkgen_clkfx_md_max=0.000
+CSET dcm_clkgen_clkfx_multiply=4
+CSET dcm_clkgen_clkfxdv_divide=2
+CSET dcm_clkgen_clkin_period=10.000
+CSET dcm_clkgen_notes=None
+CSET dcm_clkgen_spread_spectrum=NONE
+CSET dcm_clkgen_startup_wait=false
+CSET dcm_clkin_divide_by_2=false
+CSET dcm_clkin_period=25.000
+CSET dcm_clkout_phase_shift=NONE
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
+CSET dcm_notes=None
+CSET dcm_phase_shift=0
+CSET dcm_pll_cascade=NONE
+CSET dcm_startup_wait=false
+CSET den_port=DEN
+CSET din_port=DIN
+CSET dout_port=DOUT
+CSET drdy_port=DRDY
+CSET dwe_port=DWE
+CSET feedback_source=FDBK_AUTO
+CSET in_freq_units=Units_MHz
+CSET in_jitter_units=Units_UI
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED
+CSET jitter_options=UI
+CSET jitter_sel=No_Jitter
+CSET locked_port=LOCKED
+CSET mmcm_bandwidth=OPTIMIZED
+CSET mmcm_clkfbout_mult_f=4.000
+CSET mmcm_clkfbout_phase=0.000
+CSET mmcm_clkfbout_use_fine_ps=false
+CSET mmcm_clkin1_period=10.000
+CSET mmcm_clkin2_period=10.000
+CSET mmcm_clkout0_divide_f=4.000
+CSET mmcm_clkout0_duty_cycle=0.500
+CSET mmcm_clkout0_phase=0.000
+CSET mmcm_clkout0_use_fine_ps=false
+CSET mmcm_clkout1_divide=1
+CSET mmcm_clkout1_duty_cycle=0.500
+CSET mmcm_clkout1_phase=0.000
+CSET mmcm_clkout1_use_fine_ps=false
+CSET mmcm_clkout2_divide=1
+CSET mmcm_clkout2_duty_cycle=0.500
+CSET mmcm_clkout2_phase=0.000
+CSET mmcm_clkout2_use_fine_ps=false
+CSET mmcm_clkout3_divide=1
+CSET mmcm_clkout3_duty_cycle=0.500
+CSET mmcm_clkout3_phase=0.000
+CSET mmcm_clkout3_use_fine_ps=false
+CSET mmcm_clkout4_cascade=false
+CSET mmcm_clkout4_divide=1
+CSET mmcm_clkout4_duty_cycle=0.500
+CSET mmcm_clkout4_phase=0.000
+CSET mmcm_clkout4_use_fine_ps=false
+CSET mmcm_clkout5_divide=1
+CSET mmcm_clkout5_duty_cycle=0.500
+CSET mmcm_clkout5_phase=0.000
+CSET mmcm_clkout5_use_fine_ps=false
+CSET mmcm_clkout6_divide=1
+CSET mmcm_clkout6_duty_cycle=0.500
+CSET mmcm_clkout6_phase=0.000
+CSET mmcm_clkout6_use_fine_ps=false
+CSET mmcm_clock_hold=false
+CSET mmcm_compensation=ZHOLD
+CSET mmcm_divclk_divide=1
+CSET mmcm_notes=None
+CSET mmcm_ref_jitter1=0.010
+CSET mmcm_ref_jitter2=0.010
+CSET mmcm_startup_wait=false
+CSET num_out_clks=3
+CSET override_dcm=false
+CSET override_dcm_clkgen=false
+CSET override_mmcm=false
+CSET override_pll=false
+CSET platform=lin
+CSET pll_bandwidth=OPTIMIZED
+CSET pll_clk_feedback=CLKFBOUT
+CSET pll_clkfbout_mult=15
+CSET pll_clkfbout_phase=0.000
+CSET pll_clkin_period=25.000
+CSET pll_clkout0_divide=6
+CSET pll_clkout0_duty_cycle=0.500
+CSET pll_clkout0_phase=0.000
+CSET pll_clkout1_divide=15
+CSET pll_clkout1_duty_cycle=0.500
+CSET pll_clkout1_phase=0.000
+CSET pll_clkout2_divide=8
+CSET pll_clkout2_duty_cycle=0.500
+CSET pll_clkout2_phase=0.000
+CSET pll_clkout3_divide=8
+CSET pll_clkout3_duty_cycle=0.500
+CSET pll_clkout3_phase=0.000
+CSET pll_clkout4_divide=1
+CSET pll_clkout4_duty_cycle=0.500
+CSET pll_clkout4_phase=0.000
+CSET pll_clkout5_divide=1
+CSET pll_clkout5_duty_cycle=0.500
+CSET pll_clkout5_phase=0.000
+CSET pll_compensation=SYSTEM_SYNCHRONOUS
+CSET pll_divclk_divide=1
+CSET pll_notes=None
+CSET pll_ref_jitter=0.010
+CSET power_down_port=POWER_DOWN
+CSET prim_in_freq=40.000
+CSET prim_in_jitter=0.010
+CSET prim_source=Single_ended_clock_capable_pin
+CSET primary_port=CLK_IN1
+CSET primitive=MMCM
+CSET primtype_sel=DCM_SP
+CSET psclk_port=PSCLK
+CSET psdone_port=PSDONE
+CSET psen_port=PSEN
+CSET psincdec_port=PSINCDEC
+CSET relative_inclk=REL_PRIMARY
+CSET reset_port=RESET
+CSET secondary_in_freq=100.000
+CSET secondary_in_jitter=0.010
+CSET secondary_port=CLK_IN2
+CSET secondary_source=Single_ended_clock_capable_pin
+CSET status_port=STATUS
+CSET summary_strings=empty
+CSET use_clk_valid=false
+CSET use_clkfb_stopped=false
+CSET use_dyn_phase_shift=false
+CSET use_dyn_reconfig=false
+CSET use_freeze=false
+CSET use_freq_synth=true
+CSET use_inclk_stopped=false
+CSET use_inclk_switchover=false
+CSET use_locked=true
+CSET use_max_i_jitter=false
+CSET use_min_o_jitter=false
+CSET use_min_power=false
+CSET use_phase_alignment=true
+CSET use_power_down=false
+CSET use_reset=true
+CSET use_spread_spectrum=false
+CSET use_status=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2011-12-28T09:11:49Z
+# END Extra information
+GENERATE
+# CRC: e73fbe14
diff --git a/fpga/usrp2/coregen/pll_100_40_75.xdc b/fpga/usrp2/coregen/pll_100_40_75.xdc
new file mode 100755
index 000000000..4cf03fee7
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75.xdc
@@ -0,0 +1,67 @@
+# file: pll_100_40_75.xdc
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+create_clock -name CLK_IN1 -period 25.000 [get_ports CLK_IN1]
+set_propagated_clock CLK_IN1
+set_input_jitter CLK_IN1 0.25
+
+set_false_path -from [get_ports "RESET"]
+
+# Derived clock periods. These are commented out because they are 
+#   automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you 
+#   can copy them into your module level timing checks
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
diff --git a/fpga/usrp2/coregen/pll_100_40_75.xise b/fpga/usrp2/coregen/pll_100_40_75.xise
new file mode 100644
index 000000000..55dbd6ddb
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75.xise
@@ -0,0 +1,78 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="pll_100_40_75/example_design/pll_100_40_75_exdes.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="pll_100_40_75/example_design/pll_100_40_75_exdes.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="PostMapSimulation"/>
+      <association xil_pn:name="PostRouteSimulation"/>
+      <association xil_pn:name="PostTranslateSimulation"/>
+    </file>
+    <file xil_pn:name="pll_100_40_75.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="PostMapSimulation"/>
+      <association xil_pn:name="PostRouteSimulation"/>
+      <association xil_pn:name="PostTranslateSimulation"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|pll_100_40_75_exdes" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="pll_100_40_75/example_design/pll_100_40_75_exdes.v" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/pll_100_40_75_exdes" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="pll_100_40_75" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-06-24T18:22:22" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C844C83C3B3DDBC76B212B92126CFCA7" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp2/coregen/pll_100_40_75/clk_wiz_v3_5_readme.txt b/fpga/usrp2/coregen/pll_100_40_75/clk_wiz_v3_5_readme.txt
new file mode 100644
index 000000000..4e06648c2
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/clk_wiz_v3_5_readme.txt
@@ -0,0 +1,183 @@
+		Core name: Xilinx LogiCORE Clocking Wizard
+                Version: 3.5
+                Release: ISE 14.1
+                Release Date: April 24, 2012
+
+
+================================================================================
+
+This document contains the following sections:
+
+1. Introduction
+2. New Features
+  2.1 ISE
+3. Supported Devices
+  3.1 ISE
+4. Resolved Issues
+  4.1 ISE
+5. Known Issues
+  5.1 ISE
+6. Technical Support
+7. Core Release History
+8. Legal Disclaimer
+
+================================================================================
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.5
+solution. For the latest core updates, see the product page at:
+
+   http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. NEW FEATURES
+
+
+  2.1 ISE 
+  
+    - ISE 14.1 software support
+
+................................................................................
+
+3. SUPPORTED DEVICES
+
+
+  3.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+  - NA
+
+................................................................................
+
+5. KNOWN ISSUES 
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
diff --git a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_gsg521.pdf b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_gsg521.pdf
new file mode 100644
index 000000000..998385638
Binary files /dev/null and b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_gsg521.pdf differ
diff --git a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_readme.txt b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_readme.txt
new file mode 100644
index 000000000..4e06648c2
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_readme.txt
@@ -0,0 +1,183 @@
+		Core name: Xilinx LogiCORE Clocking Wizard
+                Version: 3.5
+                Release: ISE 14.1
+                Release Date: April 24, 2012
+
+
+================================================================================
+
+This document contains the following sections:
+
+1. Introduction
+2. New Features
+  2.1 ISE
+3. Supported Devices
+  3.1 ISE
+4. Resolved Issues
+  4.1 ISE
+5. Known Issues
+  5.1 ISE
+6. Technical Support
+7. Core Release History
+8. Legal Disclaimer
+
+================================================================================
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.5
+solution. For the latest core updates, see the product page at:
+
+   http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. NEW FEATURES
+
+
+  2.1 ISE 
+  
+    - ISE 14.1 software support
+
+................................................................................
+
+3. SUPPORTED DEVICES
+
+
+  3.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+  - NA
+
+................................................................................
+
+5. KNOWN ISSUES 
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
diff --git a/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html
new file mode 100644
index 000000000..8dc6bb6ba
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html
@@ -0,0 +1,194 @@
+<HTML>
+<HEAD>
+<TITLE>clk_wiz_v3_5_vinfo</TITLE>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
+</HEAD>
+<BODY>
+<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
+		Core name: Xilinx LogiCORE Clocking Wizard
+                Version: 3.5
+                Release: ISE 14.1
+                Release Date: April 24, 2012
+
+
+================================================================================
+
+This document contains the following sections:
+
+1. Introduction
+2. New Features
+  2.1 ISE
+3. Supported Devices
+  3.1 ISE
+4. Resolved Issues
+  4.1 ISE
+5. Known Issues
+  5.1 ISE
+6. Technical Support
+7. Core Release History
+8. Legal Disclaimer
+
+================================================================================
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
+
+For system requirements:
+
+   <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.5
+solution. For the latest core updates, see the product page at:
+
+   <A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A>
+
+................................................................................
+
+2. NEW FEATURES
+
+
+  2.1 ISE 
+  
+    - ISE 14.1 software support
+
+................................................................................
+
+3. SUPPORTED DEVICES
+
+
+  3.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+  - NA
+
+................................................................................
+
+5. KNOWN ISSUES 
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT
+
+
+To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
+</FONT>
+</PRE>
+</BODY>
+</HTML>
diff --git a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.ucf b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.ucf
new file mode 100755
index 000000000..1892548b4
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.ucf
@@ -0,0 +1,72 @@
+# file: pll_100_40_75_exdes.ucf
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps;
+
+# Derived clock periods. These are commented out because they are 
+#   automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you 
+#   can copy them into your module level timing checks
+#-----------------------------------------------------------------
+# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
+# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 100.000 MHz;
+
+# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
+# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 40.000 MHz;
+# NET "clk_int[3]" TNM_NET = "CLK_OUT3";
+# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 75.000 MHz;
+
+# FALSE PATH constraints 
+PIN "COUNTER_RESET" TIG;
+PIN "RESET" TIG;
+
diff --git a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v
new file mode 100755
index 000000000..a79d6ab10
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v
@@ -0,0 +1,160 @@
+// file: pll_100_40_75_exdes.v
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+
+//----------------------------------------------------------------------------
+// Clocking wizard example design
+//----------------------------------------------------------------------------
+// This example design instantiates the created clocking network, where each
+//   output clock drives a counter. The high bit of each counter is ported.
+//----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+module pll_100_40_75_exdes 
+ #( 
+  parameter TCQ = 100
+  )
+ (// Clock in ports
+  input         CLK_IN1,
+  // Reset that only drives logic in example design
+  input         COUNTER_RESET,
+  output [3:1]  CLK_OUT,
+  // High bits of counters driven by clocks
+  output [3:1]  COUNT,
+  // Status and control signals
+  input         RESET,
+  output        LOCKED
+ );
+
+  // Parameters for the counters
+  //-------------------------------
+  // Counter width
+  localparam    C_W       = 16;
+  // Number of counters
+  localparam    NUM_C     = 3;
+  genvar        count_gen;
+  // When the clock goes out of lock, reset the counters
+  wire          reset_int = !LOCKED || RESET || COUNTER_RESET;
+
+   reg [NUM_C:1] rst_sync;
+   reg [NUM_C:1] rst_sync_int;
+   reg [NUM_C:1] rst_sync_int1;
+   reg [NUM_C:1] rst_sync_int2;
+
+
+  // Declare the clocks and counters
+  wire [NUM_C:1] clk_int;
+  wire [NUM_C:1] clk;
+  reg [C_W-1:0]  counter [NUM_C:1];
+
+  // Instantiation of the clocking network
+  //--------------------------------------
+  pll_100_40_75 clknetwork
+   (// Clock in ports
+    .CLK_IN1            (CLK_IN1),
+    // Clock out ports
+    .CLK_OUT1           (clk_int[1]),
+    .CLK_OUT2           (clk_int[2]),
+    .CLK_OUT3           (clk_int[3]),
+    // Status and control signals
+    .RESET              (RESET),
+    .LOCKED             (LOCKED));
+
+  assign CLK_OUT =  clk_int;
+
+  // Connect the output clocks to the design
+  //-----------------------------------------
+  assign clk[1] = clk_int[1];
+  assign clk[2] = clk_int[2];
+  assign clk[3] = clk_int[3];
+
+
+  // Reset synchronizer
+  //-----------------------------------
+  generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
+    always @(posedge reset_int or posedge clk[count_gen]) begin
+       if (reset_int) begin
+            rst_sync[count_gen] <= 1'b1;
+            rst_sync_int[count_gen]<= 1'b1;
+            rst_sync_int1[count_gen]<= 1'b1;
+            rst_sync_int2[count_gen]<= 1'b1;
+       end
+       else begin
+            rst_sync[count_gen] <= 1'b0;
+            rst_sync_int[count_gen] <= rst_sync[count_gen];     
+            rst_sync_int1[count_gen] <= rst_sync_int[count_gen]; 
+            rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
+       end
+    end
+  end
+  endgenerate
+
+
+  // Output clock sampling
+  //-----------------------------------
+  generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
+
+    always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
+      if (rst_sync_int2[count_gen]) begin
+        counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
+      end else begin
+        counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
+      end
+    end
+    // alias the high bit of each counter to the corresponding
+    //   bit in the output bus
+    assign COUNT[count_gen] = counter[count_gen][C_W-1];
+  end
+  endgenerate
+
+
+
+
+
+endmodule
diff --git a/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.xdc b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.xdc
new file mode 100755
index 000000000..bd0f53e4e
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.xdc
@@ -0,0 +1,69 @@
+# file: pll_100_40_75_exdes.xdc
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+create_clock -name CLK_IN1 -period 25.000 [get_ports CLK_IN1]
+set_propagated_clock CLK_IN1
+set_input_jitter CLK_IN1 0.25
+
+# FALSE PATH constraint added on COUNTER_RESET 
+set_false_path -from [get_ports "COUNTER_RESET"]
+set_false_path -from [get_ports "RESET"]
+
+# Derived clock periods. These are commented out because they are 
+#   automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you 
+#   can copy them into your module level timing checks
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/implement.bat b/fpga/usrp2/coregen/pll_100_40_75/implement/implement.bat
new file mode 100755
index 000000000..a362117a4
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/implement/implement.bat
@@ -0,0 +1,90 @@
+REM file: implement.bat
+REM 
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM 
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM 
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM 
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM 
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM 
+
+REM -----------------------------------------------------------------------------
+REM  Script to synthesize and implement the RTL provided for the clocking wizard
+REM -----------------------------------------------------------------------------
+
+REM Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+REM Copy unisim_comp.v file to results directory
+copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
+
+REM Synthesize the Verilog Wrapper Files
+echo 'Synthesizing Clocking Wizard design with XST'
+xst -ifn xst.scr
+move pll_100_40_75_exdes.ngc results\
+
+REM  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\pll_100_40_75_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -uc pll_100_40_75_exdes.ucf pll_100_40_75_exdes
+
+echo 'Running map'
+map -timing -pr b pll_100_40_75_exdes -o mapped.ncd
+
+echo 'Running par'
+par -w mapped.ncd routed mapped.pcf
+
+echo 'Running trce'
+trce -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level model for the clocking wizard example design'
+netgen -ofmt verilog -sim -sdf_anno false -tm pll_100_40_75_exdes -w routed.ncd routed.v
+cd ..
+
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/implement.sh b/fpga/usrp2/coregen/pll_100_40_75/implement/implement.sh
new file mode 100755
index 000000000..e3ff2ce97
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/implement/implement.sh
@@ -0,0 +1,91 @@
+#!/bin/sh
+# file: implement.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the clocking wizard
+#-----------------------------------------------------------------------------
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+# Copy unisim_comp.v file to results directory
+cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
+
+# Synthesize the Verilog Wrapper Files
+echo 'Synthesizing Clocking Wizard design with XST'
+xst -ifn xst.scr
+mv pll_100_40_75_exdes.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/pll_100_40_75_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -uc pll_100_40_75_exdes.ucf pll_100_40_75_exdes
+
+echo 'Running map'
+map -timing pll_100_40_75_exdes -o mapped.ncd
+
+echo 'Running par'
+par -w mapped.ncd routed mapped.pcf
+
+echo 'Running trce'
+trce -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level model for the clocking wizard example design'
+netgen -ofmt verilog -sim -sdf_anno false -tm pll_100_40_75_exdes -w routed.ncd routed.v
+
+cd ..
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.bat b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.bat
new file mode 100755
index 000000000..8ac771810
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.bat
@@ -0,0 +1,58 @@
+REM file: planAhead_ise.bat
+REM 
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM 
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM 
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM 
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM 
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM 
+
+REM-----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the clocking wizard
+REM-----------------------------------------------------------------------------
+
+del \f results
+mkdir results
+cd results
+
+planAhead -mode batch -source ..\planAhead_ise.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.sh b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.sh
new file mode 100755
index 000000000..6c8c837d3
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.sh
@@ -0,0 +1,59 @@
+#!/bin/sh
+# file: planAhead_ise.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the clocking wizard
+#-----------------------------------------------------------------------------
+
+rm -rf results
+mkdir results
+cd results
+
+planAhead -mode batch -source ../planAhead_ise.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.tcl b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.tcl
new file mode 100755
index 000000000..f4e6c57ae
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.tcl
@@ -0,0 +1,78 @@
+# file: planAhead_ise.tcl
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+set projDir [file dirname [info script]]
+set projName pll_100_40_75
+set topName pll_100_40_75_exdes
+set device xc6slx75csg484-3
+
+create_project $projName $projDir/results/$projName -part $device
+
+set_property design_mode RTL [get_filesets sources_1]
+
+## Source files
+#set verilogSources [glob $srcDir/*.v]
+import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/pll_100_40_75_exdes.v
+import_files -fileset [get_filesets sources_1] -force -norecurse ../../../pll_100_40_75.v
+
+
+#UCF file
+import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/pll_100_40_75_exdes.ucf
+
+set_property top $topName [get_property srcset [current_run]]
+
+launch_runs -runs synth_1
+wait_on_run synth_1
+
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs -runs impl_1
+wait_on_run impl_1
+
+
+
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.bat b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.bat
new file mode 100755
index 000000000..42273f5d4
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.bat
@@ -0,0 +1,58 @@
+REM file: planAhead_rdn.sh
+REM 
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM 
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM 
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM 
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM 
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM 
+
+REM-----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the XADC wizard
+REM-----------------------------------------------------------------------------
+
+del \f results
+mkdir results
+cd results
+
+planAhead -mode batch -source ..\planAhead_rdn.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.sh b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.sh
new file mode 100755
index 000000000..f4c14729e
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.sh
@@ -0,0 +1,57 @@
+#!/bin/sh
+# file: planAhead_rdn.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the XADC wizard
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+planAhead -mode batch -source ../planAhead_rdn.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.tcl b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.tcl
new file mode 100755
index 000000000..56f9c65af
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.tcl
@@ -0,0 +1,69 @@
+# file : planAhead_rdn.tcl
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+set device xc6slx75csg484-3
+set projName pll_100_40_75
+set design pll_100_40_75
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module pll_100_40_75_exdes
+set_property top pll_100_40_75_exdes [get_property srcset [current_run]]
+add_files -norecurse {../../../pll_100_40_75.v}
+add_files -norecurse {../../example_design/pll_100_40_75_exdes.v}
+import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/pll_100_40_75_exdes.xdc}
+synth_design
+opt_design 
+place_design 
+route_design 
+write_sdf -rename_top_module pll_100_40_75_exdes -file routed.sdf 
+write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module pll_100_40_75_exdes -file routed.v
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/xst.prj b/fpga/usrp2/coregen/pll_100_40_75/implement/xst.prj
new file mode 100755
index 000000000..8409c83dd
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/implement/xst.prj
@@ -0,0 +1,2 @@
+verilog work ../../pll_100_40_75.v
+verilog work ../example_design/pll_100_40_75_exdes.v
diff --git a/fpga/usrp2/coregen/pll_100_40_75/implement/xst.scr b/fpga/usrp2/coregen/pll_100_40_75/implement/xst.scr
new file mode 100755
index 000000000..af176e2e4
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/implement/xst.scr
@@ -0,0 +1,9 @@
+run
+-ifmt MIXED
+-top pll_100_40_75_exdes
+-p xc6slx75-csg484-3
+-ifn xst.prj
+-ofn pll_100_40_75_exdes
+-keep_hierarchy soft 
+-equivalent_register_removal no 
+-max_fanout 65535
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simcmds.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simcmds.tcl
new file mode 100755
index 000000000..6692a790e
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simcmds.tcl
@@ -0,0 +1,8 @@
+# file: simcmds.tcl
+
+# create the simulation script
+vcd dumpfile isim.vcd
+vcd dumpvars -m /pll_100_40_75_tb -l 0
+wave add /
+run 50000ns
+quit
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.bat b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.bat
new file mode 100755
index 000000000..783ddc0e3
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.bat
@@ -0,0 +1,59 @@
+REM file: simulate_isim.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
+REM  of Xilinx, Inc. and is protected under U.S. and
+REM  international copyright and other intellectual property
+REM  laws.
+REM  
+REM  DISCLAIMER
+REM  This disclaimer is not a license and does not grant any
+REM  rights to the materials distributed herewith. Except as
+REM  otherwise provided in a valid license issued to you by
+REM  Xilinx, and to the maximum extent permitted by applicable
+REM  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM  (2) Xilinx shall not be liable (whether in contract or tort,
+REM  including negligence, or under any other theory of
+REM  liability) for any loss or damage of any kind or nature
+REM  related to, arising under or in connection with these
+REM  materials, including for any direct, or any indirect,
+REM  special, incidental, or consequential loss or damage
+REM  (including loss of data, profits, goodwill, or any type of
+REM  loss or damage suffered as a result of any action brought
+REM  by a third party) even if such damage or loss was
+REM  reasonably foreseeable or Xilinx had been advised of the
+REM  possibility of the same.
+REM  
+REM  CRITICAL APPLICATIONS
+REM  Xilinx products are not designed or intended to be fail-
+REM  safe, or for use in any application requiring fail-safe
+REM  performance, such as life-support or safety devices or
+REM  systems, Class III medical devices, nuclear facilities,
+REM  applications related to the deployment of airbags, or any
+REM  other applications that could lead to death, personal
+REM  injury, or severe property or environmental damage
+REM  (individually and collectively, "Critical
+REM  Applications"). Customer assumes the sole risk and
+REM  liability of any use of Xilinx products in Critical
+REM  Applications, subject only to applicable laws and
+REM  regulations governing limitations on product liability.
+REM  
+REM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM  PART OF THIS FILE AT ALL TIMES.
+REM  
+
+vlogcomp -work work %XILINX%\verilog\src\glbl.v
+vlogcomp -work work ..\..\..\pll_100_40_75.v
+vlogcomp -work work ..\..\example_design\pll_100_40_75_exdes.v
+vlogcomp -work work ..\pll_100_40_75_tb.v
+
+REM compile the project
+fuse work.pll_100_40_75_tb work.glbl -L unisims_ver -o pll_100_40_75_isim.exe
+
+REM run the simulation script
+.\pll_100_40_75_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.sh
new file mode 100755
index 000000000..cb197ed97
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.sh
@@ -0,0 +1,61 @@
+# file: simulate_isim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# lin
+# create the project
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work ../../../pll_100_40_75.v
+vlogcomp -work work ../../example_design/pll_100_40_75_exdes.v
+vlogcomp -work work ../pll_100_40_75_tb.v
+
+# compile the project
+fuse work.pll_100_40_75_tb work.glbl -L unisims_ver -o pll_100_40_75_isim.exe
+
+# run the simulation script
+./pll_100_40_75_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.bat b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.bat
new file mode 100755
index 000000000..756d94e7a
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.bat
@@ -0,0 +1,61 @@
+REM file: simulate_mti.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
+REM  of Xilinx, Inc. and is protected under U.S. and
+REM  international copyright and other intellectual property
+REM  laws.
+REM  
+REM  DISCLAIMER
+REM  This disclaimer is not a license and does not grant any
+REM  rights to the materials distributed herewith. Except as
+REM  otherwise provided in a valid license issued to you by
+REM  Xilinx, and to the maximum extent permitted by applicable
+REM  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM  (2) Xilinx shall not be liable (whether in contract or tort,
+REM  including negligence, or under any other theory of
+REM  liability) for any loss or damage of any kind or nature
+REM  related to, arising under or in connection with these
+REM  materials, including for any direct, or any indirect,
+REM  special, incidental, or consequential loss or damage
+REM  (including loss of data, profits, goodwill, or any type of
+REM  loss or damage suffered as a result of any action brought
+REM  by a third party) even if such damage or loss was
+REM  reasonably foreseeable or Xilinx had been advised of the
+REM  possibility of the same.
+REM  
+REM  CRITICAL APPLICATIONS
+REM  Xilinx products are not designed or intended to be fail-
+REM  safe, or for use in any application requiring fail-safe
+REM  performance, such as life-support or safety devices or
+REM  systems, Class III medical devices, nuclear facilities,
+REM  applications related to the deployment of airbags, or any
+REM  other applications that could lead to death, personal
+REM  injury, or severe property or environmental damage
+REM  (individually and collectively, "Critical
+REM  Applications"). Customer assumes the sole risk and
+REM  liability of any use of Xilinx products in Critical
+REM  Applications, subject only to applicable laws and
+REM  regulations governing limitations on product liability.
+REM  
+REM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM  PART OF THIS FILE AT ALL TIMES.
+REM  
+
+REM set up the working directory
+vlib work
+
+REM compile all of the files
+vlog -work work %XILINX%\verilog\src\glbl.v
+vlog -work work ..\..\..\pll_100_40_75.v
+vlog -work work ..\..\example_design\pll_100_40_75_exdes.v
+vlog -work work ..\pll_100_40_75_tb.v
+
+REM run the simulation
+vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.pll_100_40_75_tb work.glbl
+
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.do
new file mode 100755
index 000000000..c74e73aa5
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.do
@@ -0,0 +1,65 @@
+# file: simulate_mti.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $env(XILINX)/verilog/src/glbl.v
+vlog -work work ../../../pll_100_40_75.v
+vlog -work work ../../example_design/pll_100_40_75_exdes.v
+vlog -work work ../pll_100_40_75_tb.v
+
+# run the simulation
+vsim  -t ps -voptargs="+acc" -L unisims_ver work.pll_100_40_75_tb work.glbl
+do wave.do
+log pll_100_40_75_tb/dut/counter
+log -r /*
+run 50000ns
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.sh
new file mode 100755
index 000000000..a49ca05c6
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.sh
@@ -0,0 +1,61 @@
+#/bin/sh
+# file: simulate_mti.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $XILINX/verilog/src/glbl.v
+vlog -work work ../../../pll_100_40_75.v
+vlog -work work ../../example_design/pll_100_40_75_exdes.v
+vlog -work work ../pll_100_40_75_tb.v
+
+# run the simulation
+vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.pll_100_40_75_tb work.glbl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_ncsim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_ncsim.sh
new file mode 100755
index 000000000..5978c8eb7
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_ncsim.sh
@@ -0,0 +1,62 @@
+#/bin/sh
+# file: simulate_ncsim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+mkdir work
+
+# compile all of the files
+ncvlog -work work ${XILINX}/verilog/src/glbl.v
+ncvlog -work work ../../../pll_100_40_75.v
+ncvlog -work work ../../example_design/pll_100_40_75_exdes.v
+ncvlog -work work ../pll_100_40_75_tb.v
+
+# elaborate and run the simulation
+ncelab -work work -access +wc work.pll_100_40_75_tb work.glbl
+ncsim -input  "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.pll_100_40_75_tb
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_vcs.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_vcs.sh
new file mode 100755
index 000000000..bebd99d7d
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_vcs.sh
@@ -0,0 +1,72 @@
+#!/bin/sh
+# file: simulate_vcs.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# remove old files
+rm -rf simv* csrc DVEfiles AN.DB
+
+# compile all of the files
+# Note that -sverilog is not strictly required- You can
+#   remove the -sverilog if you change the type of the
+#   localparam for the periods in the testbench file to 
+#   [63:0] from time
+vlogan -sverilog \
+      ${XILINX}/verilog/src/glbl.v \
+      ../../../pll_100_40_75.v \
+      ../../example_design/pll_100_40_75_exdes.v \
+      ../pll_100_40_75_tb.v
+
+# prepare the simulation 
+vcs +vcs+lic+wait -debug pll_100_40_75_tb glbl
+
+# run the simulation
+./simv -ucli -i ucli_commands.key
+
+# launch the viewer
+dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/ucli_commands.key b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/ucli_commands.key
new file mode 100755
index 000000000..b56d68a2d
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/ucli_commands.key
@@ -0,0 +1,5 @@
+call {$vcdpluson}
+call {$vcdplusmemon(pll_100_40_75_tb.dut.counter)}
+run
+call {$vcdplusclose}
+quit
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/vcs_session.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/vcs_session.tcl
new file mode 100755
index 000000000..19b1ea0f5
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/vcs_session.tcl
@@ -0,0 +1,18 @@
+gui_open_window Wave
+gui_sg_create pll_100_40_75_group
+gui_list_add_group -id Wave.1 {pll_100_40_75_group}
+gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.test_phase}
+gui_set_radix -radix {ascii} -signals {pll_100_40_75_tb.test_phase}
+gui_sg_addsignal -group pll_100_40_75_group {{Input_clocks}} -divider
+gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.CLK_IN1}
+gui_sg_addsignal -group pll_100_40_75_group {{Output_clocks}} -divider
+gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.dut.clk}
+gui_list_expand -id Wave.1 pll_100_40_75_tb.dut.clk
+gui_sg_addsignal -group pll_100_40_75_group {{Status_control}} -divider
+gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.RESET}
+gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.LOCKED}
+gui_sg_addsignal -group pll_100_40_75_group {{Counters}} -divider
+gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.COUNT}
+gui_sg_addsignal -group pll_100_40_75_group {pll_100_40_75_tb.dut.counter}
+gui_list_expand -id Wave.1 pll_100_40_75_tb.dut.counter
+gui_zoom -window Wave.1 -full
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.do
new file mode 100755
index 000000000..4178de1c7
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.do
@@ -0,0 +1,60 @@
+# file: wave.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+add wave -noupdate -format Literal -radix ascii /pll_100_40_75_tb/test_phase
+add wave -noupdate -divider {Input clocks}
+add wave -noupdate -format Logic /pll_100_40_75_tb/CLK_IN1
+add wave -noupdate -divider {Output clocks}
+add wave -noupdate -format Literal -expand /pll_100_40_75_tb/dut/clk
+add wave -noupdate -divider Status/control
+add wave -noupdate -format Logic /pll_100_40_75_tb/RESET
+add wave -noupdate -format Logic /pll_100_40_75_tb/LOCKED
+add wave -noupdate -divider Counters
+add wave -noupdate -format Literal -radix hexadecimal /pll_100_40_75_tb/COUNT
+add wave -noupdate -format Literal -radix hexadecimal -expand /pll_100_40_75_tb/dut/counter
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.sv b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.sv
new file mode 100755
index 000000000..57e72bdec
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.sv
@@ -0,0 +1,119 @@
+# file: wave.sv
+# 
+# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# Get the windows set up
+#
+if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {
+    window geometry "Design Browser 1" 1054x819+536+322
+}
+window target "Design Browser 1" on
+browser using {Design Browser 1}
+browser set \
+    -scope nc::pll_100_40_75_tb
+browser yview see nc::pll_100_40_75_tb
+browser timecontrol set -lock 0
+
+if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
+    window geometry "Waveform 1" 1010x600+0+541
+}
+window target "Waveform 1" on
+waveform using {Waveform 1}
+waveform sidebar visibility partial
+waveform set \
+    -primarycursor TimeA \
+    -signalnames name \
+    -signalwidth 175 \
+    -units ns \
+    -valuewidth 75
+cursor set -using TimeA -time 0
+waveform baseline set -time 0
+waveform xview limits 0 20000n
+
+#
+# Define signal groups
+#
+catch {group new -name {Output clocks} -overlay 0}
+catch {group new -name {Status/control} -overlay 0}
+catch {group new -name {Counters} -overlay 0}
+
+set id [waveform add -signals [list {nc::pll_100_40_75_tb.CLK_IN1}]]
+
+group using {Output clocks}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+    {pll_100_40_75_tb.dut.clk[1]} \
+    {pll_100_40_75_tb.dut.clk[2]}  \     {pll_100_40_75_tb.dut.clk[3]} 
+group using {Counters}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+    {pll_100_40_75_tb.dut.counter[1]} \
+    {pll_100_40_75_tb.dut.counter[2]}  \     {pll_100_40_75_tb.dut.counter[3]} 
+group using {Status/control}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+   {nc::pll_100_40_75_tb.RESET}    {nc::pll_100_40_75_tb.LOCKED}
+
+
+set id [waveform add -signals [list {nc::pll_100_40_75_tb.COUNT} ]]
+
+set id [waveform add -signals [list {nc::pll_100_40_75_tb.test_phase} ]]
+waveform format $id -radix %a
+
+set groupId [waveform add -groups {{Input clocks}}]
+set groupId [waveform add -groups {{Output clocks}}]
+set groupId [waveform add -groups {{Status/control}}]
+set groupId [waveform add -groups {{Counters}}]
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/pll_100_40_75_tb.v b/fpga/usrp2/coregen/pll_100_40_75/simulation/pll_100_40_75_tb.v
new file mode 100755
index 000000000..fe800f0cc
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/pll_100_40_75_tb.v
@@ -0,0 +1,143 @@
+// file: pll_100_40_75_tb.v
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+
+//----------------------------------------------------------------------------
+// Clocking wizard demonstration testbench
+//----------------------------------------------------------------------------
+// This demonstration testbench instantiates the example design for the 
+//   clocking wizard. Input clocks are toggled, which cause the clocking
+//   network to lock and the counters to increment.
+//----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+`define wait_lock @(posedge LOCKED)
+
+module pll_100_40_75_tb ();
+
+  // Clock to Q delay of 100ps
+  localparam  TCQ              = 100;
+
+
+  // timescale is 1ps/1ps
+  localparam  ONE_NS      = 1000;
+  localparam  PHASE_ERR_MARGIN   = 100; // 100ps
+  // how many cycles to run
+  localparam  COUNT_PHASE = 1024;
+  // we'll be using the period in many locations
+  localparam time PER1    = 25.000*ONE_NS;
+  localparam time PER1_1  = PER1/2;
+  localparam time PER1_2  = PER1 - PER1/2;
+
+  // Declare the input clock signals
+  reg         CLK_IN1     = 1;
+
+  // The high bits of the sampling counters
+  wire [3:1]  COUNT;
+  // Status and control signals
+  reg         RESET      = 0;
+  wire        LOCKED;
+  reg         COUNTER_RESET = 0;
+wire [3:1] CLK_OUT;
+//Freq Check using the M & D values setting and actual Frequency generated
+
+
+  // Input clock generation
+  //------------------------------------
+  always begin
+    CLK_IN1 = #PER1_1 ~CLK_IN1;
+    CLK_IN1 = #PER1_2 ~CLK_IN1;
+  end
+
+  // Test sequence
+  reg [15*8-1:0] test_phase = "";
+  initial begin
+    // Set up any display statements using time to be readable
+    $timeformat(-12, 2, "ps", 10);
+    COUNTER_RESET = 0;
+    test_phase = "reset";
+    RESET = 1;
+    #(PER1*6);
+    RESET = 0;
+    test_phase = "wait lock";
+    `wait_lock;
+    #(PER1*6);
+    COUNTER_RESET = 1;
+    #(PER1*20)
+    COUNTER_RESET = 0;
+
+    test_phase = "counting";
+    #(PER1*COUNT_PHASE);
+
+    $display("SIMULATION PASSED");
+    $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
+    $finish;
+  end
+
+  // Instantiation of the example design containing the clock
+  //    network and sampling counters
+  //---------------------------------------------------------
+  pll_100_40_75_exdes 
+  #(
+    .TCQ (TCQ)
+   ) dut
+   (// Clock in ports
+    .CLK_IN1            (CLK_IN1),
+    // Reset for logic in example design
+    .COUNTER_RESET      (COUNTER_RESET),
+    .CLK_OUT            (CLK_OUT),
+    // High bits of the counters
+    .COUNT              (COUNT),
+    // Status and control signals
+    .RESET              (RESET),
+    .LOCKED             (LOCKED));
+
+// Freq Check 
+
+endmodule
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/pll_100_40_75_tb.v b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/pll_100_40_75_tb.v
new file mode 100755
index 000000000..0e6be6e9d
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/pll_100_40_75_tb.v
@@ -0,0 +1,157 @@
+// file: pll_100_40_75_tb.v
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+
+//----------------------------------------------------------------------------
+// Clocking wizard demonstration testbench
+//----------------------------------------------------------------------------
+// This demonstration testbench instantiates the example design for the 
+//   clocking wizard. Input clocks are toggled, which cause the clocking
+//   network to lock and the counters to increment.
+//----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+`define wait_lock @(posedge LOCKED)
+
+module pll_100_40_75_tb ();
+
+  // Clock to Q delay of 100ps
+  localparam  TCQ              = 100;
+
+
+  // timescale is 1ps/1ps
+  localparam  ONE_NS      = 1000;
+  localparam  PHASE_ERR_MARGIN   = 100; // 100ps
+  // how many cycles to run
+  localparam  COUNT_PHASE = 1024;
+  // we'll be using the period in many locations
+  localparam time PER1    = 25.000*ONE_NS;
+  localparam time PER1_1  = PER1/2;
+  localparam time PER1_2  = PER1 - PER1/2;
+
+  // Declare the input clock signals
+  reg         CLK_IN1     = 1;
+
+  // The high bits of the sampling counters
+  wire [3:1]  COUNT;
+  // Status and control signals
+  reg         RESET      = 0;
+  wire        LOCKED;
+  reg         COUNTER_RESET = 0;
+wire [3:1] CLK_OUT;
+//Freq Check using the M & D values setting and actual Frequency generated 
+
+  reg [13:0]  timeout_counter = 14'b00000000000000;
+
+  // Input clock generation
+  //------------------------------------
+  always begin
+    CLK_IN1 = #PER1_1 ~CLK_IN1;
+    CLK_IN1 = #PER1_2 ~CLK_IN1;
+  end
+
+  // Test sequence
+  reg [15*8-1:0] test_phase = "";
+  initial begin
+    // Set up any display statements using time to be readable
+    $timeformat(-12, 2, "ps", 10);
+    $display ("Timing checks are not valid");
+    COUNTER_RESET = 0;
+    test_phase = "reset";
+    RESET = 1;
+    #(PER1*6);
+    RESET = 0;
+    test_phase = "wait lock";
+    `wait_lock;
+    #(PER1*6);
+    COUNTER_RESET = 1;
+    #(PER1*19.5)
+    COUNTER_RESET = 0;
+    #(PER1*1)
+    $display ("Timing checks are valid");
+    test_phase = "counting";
+    #(PER1*COUNT_PHASE);
+
+    $display("SIMULATION PASSED");
+    $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
+    $finish;
+  end
+
+
+   always@(posedge CLK_IN1) begin
+      timeout_counter <= timeout_counter + 1'b1;
+      if (timeout_counter == 14'b10000000000000) begin
+         if (LOCKED != 1'b1) begin
+            $display("ERROR : NO LOCK signal");
+            $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
+            $finish;
+         end
+      end
+   end
+
+  // Instantiation of the example design containing the clock
+  //    network and sampling counters
+  //---------------------------------------------------------
+  pll_100_40_75_exdes 
+    dut
+   (// Clock in ports
+    .CLK_IN1            (CLK_IN1),
+    // Reset for logic in example design
+    .COUNTER_RESET      (COUNTER_RESET),
+    .CLK_OUT            (CLK_OUT),
+    // High bits of the counters
+    .COUNT              (COUNT),
+    // Status and control signals
+    .RESET              (RESET),
+    .LOCKED             (LOCKED));
+
+
+// Freq Check 
+
+endmodule
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/sdf_cmd_file b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/sdf_cmd_file
new file mode 100755
index 000000000..61dacfed8
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/sdf_cmd_file
@@ -0,0 +1,2 @@
+COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
+SCOPE = pll_100_40_75_tb.dut;
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simcmds.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simcmds.tcl
new file mode 100755
index 000000000..857329884
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simcmds.tcl
@@ -0,0 +1,9 @@
+# file: simcmds.tcl
+
+# create the simulation script
+vcd dumpfile isim.vcd
+vcd dumpvars -m /pll_100_40_75_tb -l 0
+wave add /
+run 50000ns
+quit
+
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_isim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_isim.sh
new file mode 100755
index 000000000..e3b06d7c5
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_isim.sh
@@ -0,0 +1,62 @@
+# file: simulate_isim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# create the project
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work ../../implement/results/routed.v
+vlogcomp -work work pll_100_40_75_tb.v
+
+# compile the project
+fuse work.pll_100_40_75_tb work.glbl -L secureip -L simprims_ver -o pll_100_40_75_isim.exe
+
+# run the simulation script
+./pll_100_40_75_isim.exe -tclbatch simcmds.tcl -sdfmax /pll_100_40_75_tb/dut=../../implement/results/routed.sdf
+
+# run the simulation script
+#./pll_100_40_75_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.bat b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.bat
new file mode 100755
index 000000000..7e5890086
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.bat
@@ -0,0 +1,59 @@
+REM file: simulate_mti.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
+REM  of Xilinx, Inc. and is protected under U.S. and
+REM  international copyright and other intellectual property
+REM  laws.
+REM  
+REM  DISCLAIMER
+REM  This disclaimer is not a license and does not grant any
+REM  rights to the materials distributed herewith. Except as
+REM  otherwise provided in a valid license issued to you by
+REM  Xilinx, and to the maximum extent permitted by applicable
+REM  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM  (2) Xilinx shall not be liable (whether in contract or tort,
+REM  including negligence, or under any other theory of
+REM  liability) for any loss or damage of any kind or nature
+REM  related to, arising under or in connection with these
+REM  materials, including for any direct, or any indirect,
+REM  special, incidental, or consequential loss or damage
+REM  (including loss of data, profits, goodwill, or any type of
+REM  loss or damage suffered as a result of any action brought
+REM  by a third party) even if such damage or loss was
+REM  reasonably foreseeable or Xilinx had been advised of the
+REM  possibility of the same.
+REM  
+REM  CRITICAL APPLICATIONS
+REM  Xilinx products are not designed or intended to be fail-
+REM  safe, or for use in any application requiring fail-safe
+REM  performance, such as life-support or safety devices or
+REM  systems, Class III medical devices, nuclear facilities,
+REM  applications related to the deployment of airbags, or any
+REM  other applications that could lead to death, personal
+REM  injury, or severe property or environmental damage
+REM  (individually and collectively, "Critical
+REM  Applications"). Customer assumes the sole risk and
+REM  liability of any use of Xilinx products in Critical
+REM  Applications, subject only to applicable laws and
+REM  regulations governing limitations on product liability.
+REM  
+REM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM  PART OF THIS FILE AT ALL TIMES.
+REM  
+# set up the working directory
+set work work
+vlib work
+
+REM compile all of the files
+vlog -work work %XILINX%\verilog\src\glbl.v
+vlog -work work ..\..\implement\results\routed.v
+vlog -work work pll_100_40_75_tb.v
+
+REM run the simulation
+vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax pll_100_40_75_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.pll_100_40_75_tb work.glbl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.do
new file mode 100755
index 000000000..03f8a3965
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.do
@@ -0,0 +1,65 @@
+# file: simulate_mti.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $env(XILINX)/verilog/src/glbl.v
+vlog -work work ../../implement/results/routed.v
+vlog -work work pll_100_40_75_tb.v
+
+# run the simulation
+vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax pll_100_40_75_tb/dut=../../implement/results/routed.sdf +no_notifier work.pll_100_40_75_tb work.glbl
+#do wave.do
+#log -r /*
+run 50000ns
+
+
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.sh
new file mode 100755
index 000000000..055768aa8
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.sh
@@ -0,0 +1,61 @@
+#/bin/sh
+# file: simulate_mti.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $XILINX/verilog/src/glbl.v
+vlog -work work ../../implement/results/routed.v
+vlog -work work pll_100_40_75_tb.v
+
+# run the simulation
+vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax pll_100_40_75_tb/dut=../../implement/results/routed.sdf +no_notifier work.pll_100_40_75_tb work.glbl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_ncsim.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_ncsim.sh
new file mode 100755
index 000000000..aa3a2b441
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_ncsim.sh
@@ -0,0 +1,64 @@
+#!/bin/sh
+# file: simulate_ncsim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+mkdir work
+
+# compile all of the files
+ncvlog -work work ${XILINX}/verilog/src/glbl.v
+ncvlog -work work ../../implement/results/routed.v
+ncvlog -work work pll_100_40_75_tb.v
+
+# elaborate and run the simulation
+ncsdfc ../../implement/results/routed.sdf
+
+ncelab -work work -access +wc -pulse_r 10 -nonotifier work.pll_100_40_75_tb work.glbl -sdf_cmd_file sdf_cmd_file
+ncsim -input  "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.pll_100_40_75_tb
+
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_vcs.sh b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_vcs.sh
new file mode 100755
index 000000000..3cc21dd69
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_vcs.sh
@@ -0,0 +1,72 @@
+#!/bin/sh
+# file: simulate_vcs.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# remove old files
+rm -rf simv* csrc DVEfiles AN.DB
+
+# compile all of the files
+# Note that -sverilog is not strictly required- You can
+#   remove the -sverilog if you change the type of the
+#   localparam for the periods in the testbench file to 
+#   [63:0] from time
+  vlogan -sverilog \
+           pll_100_40_75_tb.v \
+           ../../implement/results/routed.v
+
+
+# prepare the simulation
+vcs -sdf max:pll_100_40_75_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
+        +libext+.v -debug pll_100_40_75_tb.v ../../implement/results/routed.v
+
+# run the simulation
+./simv -ucli -i ucli_commands.key
+
+# launch the viewer
+#dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/ucli_commands.key b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/ucli_commands.key
new file mode 100755
index 000000000..0548d1733
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/ucli_commands.key
@@ -0,0 +1,5 @@
+
+call {$vcdpluson}
+run 50000ns
+call {$vcdplusclose}
+quit
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/vcs_session.tcl b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/vcs_session.tcl
new file mode 100755
index 000000000..1438f6bed
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/vcs_session.tcl
@@ -0,0 +1 @@
+gui_open_window Wave
diff --git a/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/wave.do b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/wave.do
new file mode 100755
index 000000000..fe9b59354
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/wave.do
@@ -0,0 +1,72 @@
+# file: wave.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /pll_100_40_75_tb/CLK_IN1
+add wave -noupdate /pll_100_40_75_tb/COUNT
+add wave -noupdate /pll_100_40_75_tb/LOCKED
+add wave -noupdate /pll_100_40_75_tb/RESET
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
+configure wave -namecolwidth 238
+configure wave -valuecolwidth 107
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {74848022 ps}
diff --git a/fpga/usrp2/coregen/pll_100_40_75_exdes.ncf b/fpga/usrp2/coregen/pll_100_40_75_exdes.ncf
new file mode 100644
index 000000000..ddff6a6e9
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75_exdes.ncf
@@ -0,0 +1,73 @@
+# file: pll_100_40_75_exdes.ucf
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps;
+
+# Derived clock periods. These are commented out because they are 
+#   automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you 
+#   can copy them into your module level timing checks
+#-----------------------------------------------------------------
+# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
+# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 100.000 MHz;
+
+# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
+# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 40.000 MHz;
+# NET "clk_int[3]" TNM_NET = "CLK_OUT3";
+# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 75.000 MHz;
+
+# FALSE PATH constraints 
+PIN "COUNTER_RESET" TIG;
+PIN "RESET" TIG;
+
+
diff --git a/fpga/usrp2/coregen/pll_100_40_75_flist.txt b/fpga/usrp2/coregen/pll_100_40_75_flist.txt
new file mode 100644
index 000000000..04c7f882d
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75_flist.txt
@@ -0,0 +1,54 @@
+# Output products list for <pll_100_40_75>
+_xmsgs/pn_parser.xmsgs
+pll_100_40_75/clk_wiz_v3_5_readme.txt
+pll_100_40_75/doc/clk_wiz_gsg521.pdf
+pll_100_40_75/doc/clk_wiz_v3_5_readme.txt
+pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html
+pll_100_40_75/example_design/pll_100_40_75_exdes.ucf
+pll_100_40_75/example_design/pll_100_40_75_exdes.v
+pll_100_40_75/example_design/pll_100_40_75_exdes.xdc
+pll_100_40_75/implement/implement.bat
+pll_100_40_75/implement/implement.sh
+pll_100_40_75/implement/planAhead_ise.bat
+pll_100_40_75/implement/planAhead_ise.sh
+pll_100_40_75/implement/planAhead_ise.tcl
+pll_100_40_75/implement/planAhead_rdn.bat
+pll_100_40_75/implement/planAhead_rdn.sh
+pll_100_40_75/implement/planAhead_rdn.tcl
+pll_100_40_75/implement/xst.prj
+pll_100_40_75/implement/xst.scr
+pll_100_40_75/simulation/functional/simcmds.tcl
+pll_100_40_75/simulation/functional/simulate_isim.bat
+pll_100_40_75/simulation/functional/simulate_isim.sh
+pll_100_40_75/simulation/functional/simulate_mti.bat
+pll_100_40_75/simulation/functional/simulate_mti.do
+pll_100_40_75/simulation/functional/simulate_mti.sh
+pll_100_40_75/simulation/functional/simulate_ncsim.sh
+pll_100_40_75/simulation/functional/simulate_vcs.sh
+pll_100_40_75/simulation/functional/ucli_commands.key
+pll_100_40_75/simulation/functional/vcs_session.tcl
+pll_100_40_75/simulation/functional/wave.do
+pll_100_40_75/simulation/functional/wave.sv
+pll_100_40_75/simulation/pll_100_40_75_tb.v
+pll_100_40_75/simulation/timing/pll_100_40_75_tb.v
+pll_100_40_75/simulation/timing/sdf_cmd_file
+pll_100_40_75/simulation/timing/simcmds.tcl
+pll_100_40_75/simulation/timing/simulate_isim.sh
+pll_100_40_75/simulation/timing/simulate_mti.bat
+pll_100_40_75/simulation/timing/simulate_mti.do
+pll_100_40_75/simulation/timing/simulate_mti.sh
+pll_100_40_75/simulation/timing/simulate_ncsim.sh
+pll_100_40_75/simulation/timing/simulate_vcs.sh
+pll_100_40_75/simulation/timing/ucli_commands.key
+pll_100_40_75/simulation/timing/vcs_session.tcl
+pll_100_40_75/simulation/timing/wave.do
+pll_100_40_75.asy
+pll_100_40_75.gise
+pll_100_40_75.ucf
+pll_100_40_75.v
+pll_100_40_75.veo
+pll_100_40_75.xco
+pll_100_40_75.xdc
+pll_100_40_75.xise
+pll_100_40_75_flist.txt
+pll_100_40_75_xmdf.tcl
diff --git a/fpga/usrp2/coregen/pll_100_40_75_xmdf.tcl b/fpga/usrp2/coregen/pll_100_40_75_xmdf.tcl
new file mode 100755
index 000000000..18eee6e1a
--- /dev/null
+++ b/fpga/usrp2/coregen/pll_100_40_75_xmdf.tcl
@@ -0,0 +1,144 @@
+# The package naming convention is <core_name>_xmdf
+package provide pll_100_40_75_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::pll_100_40_75_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::pll_100_40_75_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name pll_100_40_75
+}
+# ::pll_100_40_75_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::pll_100_40_75_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/clk_wiz_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/example_design/pll_100_40_75_exdes.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/doc/clk_wiz_ds709.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/doc/clk_wiz_gsg521.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/example_design/pll_100_40_75_exdes.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/implement.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/implement.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/xst.prj
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/implement/xst.scr
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/pll_100_40_75_tb.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simcmds.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_isim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/simulate_vcs.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/ucli_commands.key
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/vcs_session.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/wave.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75/simulation/functional/wave.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.ejp
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_100_40_75_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module pll_100_40_75
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/fifo/resp_packet_padder36.v b/fpga/usrp2/fifo/resp_packet_padder36.v
new file mode 100644
index 000000000..18fc18291
--- /dev/null
+++ b/fpga/usrp2/fifo/resp_packet_padder36.v
@@ -0,0 +1,88 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// PAD to NUM LINES
+
+module resp_packet_padder36
+#(
+    parameter NUM_LINES32 = 128
+)
+(
+    input clk, input reset,
+
+    //input interface
+    input [35:0] data_i,
+    input src_rdy_i,
+    output dst_rdy_o,
+
+    //output interface
+    output [35:0] data_o,
+    output src_rdy_o,
+    input dst_rdy_i
+);
+
+    localparam STATE_FWD = 0;
+    localparam STATE_PAD = 1;
+    reg state;
+
+    reg [15:0] counter;
+
+    always @(posedge clk) begin
+        if (reset) begin
+            counter <= 0;
+        end
+        else if (src_rdy_o && dst_rdy_i) begin
+            if (data_o[33]) counter <= 0;
+            else counter <= counter + 1;
+        end
+    end
+
+    always @(posedge clk) begin
+        if (reset) begin
+            state <= STATE_FWD;
+        end
+        else case(state)
+
+        STATE_FWD: begin
+            if (src_rdy_i && dst_rdy_o && data_i[33] && ~data_o[33]) begin
+                state <= STATE_PAD;
+            end
+        end
+
+        STATE_PAD: begin
+            if (src_rdy_o && dst_rdy_i && data_o[33]) begin
+                state <= STATE_FWD;
+            end
+        end
+
+        endcase //state
+    end
+
+    //assign data out
+    assign data_o[31:0] = (state == STATE_FWD)? data_i[31:0] : {32'b0};
+    wire eof = (counter == (NUM_LINES32-1));
+    assign data_o[35:32] = {data_i[35:34], eof, data_i[32]};
+
+    //assign ready
+    assign src_rdy_o = (state == STATE_FWD)? src_rdy_i : 1'b1;
+    assign dst_rdy_o = (state == STATE_FWD)? dst_rdy_i : 1'b0;
+
+endmodule // resp_packet_padder36
+
+
+
+
diff --git a/fpga/usrp2/gpif/.gitignore b/fpga/usrp2/gpif/.gitignore
new file mode 100644
index 000000000..421b858b6
--- /dev/null
+++ b/fpga/usrp2/gpif/.gitignore
@@ -0,0 +1,3 @@
+fuse*
+isim*
+*_tb
diff --git a/fpga/usrp2/gpif/gpif.v b/fpga/usrp2/gpif/gpif.v
new file mode 100644
index 000000000..e5b63d5a3
--- /dev/null
+++ b/fpga/usrp2/gpif/gpif.v
@@ -0,0 +1,185 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+//////////////////////////////////////////////////////////////////////////////////
+
+module gpif
+  #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11)
+   (// GPIF signals
+    input gpif_clk, input gpif_rst,
+    inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy,
+    output [2:0] gpif_misc,
+    
+    // Wishbone signals
+    input wb_clk, input wb_rst,
+    output [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
+    output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
+    input [7:0] triggers,
+    
+    // FIFO interface
+    input fifo_clk, input fifo_rst, input clear_tx, input clear_rx,
+    output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
+    input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
+    input [35:0] tx_err_data_i, input tx_err_src_rdy_i, output tx_err_dst_rdy_o,
+    
+    output tx_underrun, output rx_overrun,
+    input [7:0] frames_per_packet,
+    output [31:0] debug0, output [31:0] debug1
+    );
+
+   assign tx_underrun = 0;
+   assign rx_overrun = 0;
+   
+   wire 	  WR = gpif_ctl[0];
+   wire 	  RD = gpif_ctl[1];
+   wire 	  OE = gpif_ctl[2];
+   wire 	  EP = gpif_ctl[3];
+
+   wire 	  CF, CE, DF, DE;
+   
+   assign gpif_rdy = { CF, CE, DF, DE };
+   
+   wire [15:0] 	  gpif_d_out;
+   assign gpif_d = OE ? gpif_d_out : 16'bz;
+
+   wire [15:0] 	  gpif_d_copy = gpif_d;
+
+   wire [31:0] 	  debug_rd, debug_wr, debug_split0, debug_split1;
+   
+   // ////////////////////////////////////////////////////////////////////
+   // TX Data Path
+
+   wire [18:0] 	  tx19_data;
+   wire 	  tx19_src_rdy, tx19_dst_rdy;
+   wire [35:0] 	  tx36_data;
+   wire 	  tx36_src_rdy, tx36_dst_rdy;
+
+   wire [18:0] 	  ctrl_data;
+   wire 	  ctrl_src_rdy, ctrl_dst_rdy;
+   
+   gpif_wr gpif_wr
+     (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), 
+      .gpif_data(gpif_d), .gpif_wr(WR), .gpif_ep(EP),
+      .gpif_full_d(DF), .gpif_full_c(CF),
+      
+      .sys_clk(fifo_clk), .sys_rst(fifo_rst),
+      .data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx19_dst_rdy),
+      .ctrl_o(ctrl_data), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy),
+      .debug(debug_wr) );
+
+   // join vita packets which are longer than one frame, drop frame padding
+   wire [18:0] 	  refr_data;
+   wire 	  refr_src_rdy, refr_dst_rdy;
+   
+   packet_reframer tx_packet_reframer 
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+      .data_i(tx19_data), .src_rdy_i(tx19_src_rdy), .dst_rdy_o(tx19_dst_rdy),
+      .data_o(refr_data), .src_rdy_o(refr_src_rdy), .dst_rdy_i(refr_dst_rdy));
+
+   fifo19_to_fifo36 #(.LE(1)) f19_to_f36
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .f19_datain(refr_data), .f19_src_rdy_i(refr_src_rdy), .f19_dst_rdy_o(refr_dst_rdy),
+      .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+      .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
+      .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i));
+
+   // ////////////////////////////////////////////
+   // RX Data Path
+
+   wire [35:0] 	  rx36_data;
+   wire 	  rx36_src_rdy, rx36_dst_rdy;
+   wire [18:0] 	  rx19_data, splt_data;
+   wire 	  rx19_src_rdy, rx19_dst_rdy, splt_src_rdy, splt_dst_rdy;
+   wire [18:0] 	  resp_data, resp_int1, resp_int2;
+   wire 	  resp_src_rdy, resp_dst_rdy;
+   wire 	  resp_src_rdy_int1, resp_dst_rdy_int1, resp_src_rdy_int2, resp_dst_rdy_int2;
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
+      .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
+
+   fifo36_to_fifo19 #(.LE(1)) f36_to_f19
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
+      .f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) );
+
+   packet_splitter #(.FRAME_LEN(256)) packet_splitter
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .frames_per_packet(frames_per_packet),
+      .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy),
+      .data_o(splt_data), .src_rdy_o(splt_src_rdy), .dst_rdy_i(splt_dst_rdy),
+      .debug0(debug_split0), .debug1(debug_split1));
+     
+   gpif_rd gpif_rd
+     (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+      .gpif_data(gpif_d_out), .gpif_rd(RD), .gpif_ep(EP),
+      .gpif_empty_d(DE), .gpif_empty_c(CE), .gpif_flush(gpif_misc[0]),
+      
+      .sys_clk(fifo_clk), .sys_rst(fifo_rst),
+      .data_i(splt_data), .src_rdy_i(splt_src_rdy), .dst_rdy_o(splt_dst_rdy),
+      .resp_i(resp_data), .resp_src_rdy_i(resp_src_rdy), .resp_dst_rdy_o(resp_dst_rdy),
+      .debug(debug_rd) );
+
+   // ////////////////////////////////////////////////////////////////////
+   // FIFO to Wishbone interface
+
+   fifo_to_wb fifo_to_wb
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy),
+      .data_o(resp_int1), .src_rdy_o(resp_src_rdy_int1), .dst_rdy_i(resp_dst_rdy_int1),
+      .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), .wb_sel_o(wb_sel_o), 
+      .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i),
+      .triggers(triggers),
+      .debug0(), .debug1());
+
+   wire [18:0] 	  tx_err19_data;
+   wire 	  tx_err19_src_rdy, tx_err19_dst_rdy;
+   
+   fifo36_to_fifo19 #(.LE(1)) f36_to_f19_txerr
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .f36_datain(tx_err_data_i), .f36_src_rdy_i(tx_err_src_rdy_i), .f36_dst_rdy_o(tx_err_dst_rdy_o),
+      .f19_dataout(tx_err19_data), .f19_src_rdy_o(tx_err19_src_rdy), .f19_dst_rdy_i(tx_err19_dst_rdy) );
+
+   fifo19_mux #(.prio(0)) mux_err_stream
+     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+      .data0_i(resp_int1), .src0_rdy_i(resp_src_rdy_int1), .dst0_rdy_o(resp_dst_rdy_int1),
+      .data1_i(tx_err19_data), .src1_rdy_i(tx_err19_src_rdy), .dst1_rdy_o(tx_err19_dst_rdy),
+      .data_o(resp_int2), .src_rdy_o(resp_src_rdy_int2), .dst_rdy_i(resp_dst_rdy_int2));
+									
+   fifo19_pad #(.LENGTH(16)) fifo19_pad
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .data_i(resp_int2), .src_rdy_i(resp_src_rdy_int2), .dst_rdy_o(resp_dst_rdy_int2),
+      .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy));
+        
+   // ////////////////////////////////////////////
+   //    DEBUG
+   
+   //assign debug0 = { rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy, gpif_ctl[3:0], gpif_rdy[3:0], 
+	//	     gpif_d_copy[15:0] };
+   
+   //assign debug1 = { { debug_rd[15:8] },
+	//	     { debug_rd[7:0] },
+		//     { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy},
+		  //   { tx_src_rdy_o, tx_dst_rdy_i, tx19_src_rdy, tx19_dst_rdy, tx36_src_rdy, tx36_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy} };
+   
+   assign debug0 = { gpif_ctl[3:0], gpif_rdy[3:0], debug_split0[23:0] };
+   assign debug1 = { gpif_misc[0], debug_rd[14:0], debug_split1[15:8], debug_split1[7:0] };
+endmodule // gpif
diff --git a/fpga/usrp2/gpif/gpif_rd.v b/fpga/usrp2/gpif/gpif_rd.v
new file mode 100644
index 000000000..b05c3cfb6
--- /dev/null
+++ b/fpga/usrp2/gpif/gpif_rd.v
@@ -0,0 +1,111 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+module gpif_rd
+  (input gpif_clk, input gpif_rst,
+   output [15:0] gpif_data, input gpif_rd, input gpif_ep,
+   output reg gpif_empty_d, output reg gpif_empty_c,
+   output reg gpif_flush,
+   
+   input sys_clk, input sys_rst,
+   input [18:0] data_i, input src_rdy_i, output dst_rdy_o,
+   input [18:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o,
+   output [31:0] debug
+   );
+   
+   wire [18:0] 	 data_o; // occ bit indicates flush
+   wire [17:0] 	 resp_o; // no occ bit
+   wire 	 final_rdy_data, final_rdy_resp;
+   
+   // 33/257 Bug Fix
+   reg [8:0] 	read_count;
+   always @(negedge gpif_clk)
+     if(gpif_rst)
+       read_count <= 0;
+     else if(gpif_rd)
+       read_count <= read_count + 1;
+     else
+       read_count <= 0;
+
+   // Data Path
+   wire [18:0] 	data_int;
+   wire 	src_rdy_int, dst_rdy_int;
+   fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) rd_fifo_2clk
+     (.wclk(sys_clk), .datain(data_i[18:0]), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(),
+      .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(),
+      .arst(sys_rst));
+
+   reg [7:0] 	packet_count;
+   wire 	consume_data_line = gpif_rd & ~gpif_ep & ~read_count[8];
+   wire 	produce_eop = src_rdy_int & dst_rdy_int & data_int[17];
+   wire 	consume_sop = consume_data_line & final_rdy_data & data_o[16];
+   wire 	consume_eop = consume_data_line & final_rdy_data & data_o[17];
+   
+   fifo_cascade #(.WIDTH(19), .SIZE(10)) rd_fifo
+     (.clk(~gpif_clk), .reset(gpif_rst), .clear(0),
+      .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(),
+      .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(consume_data_line), .occupied());
+
+   always @(negedge gpif_clk)
+     if(gpif_rst)
+       packet_count <= 0;
+     else
+       if(produce_eop & ~consume_sop)
+	 packet_count <= packet_count + 1;
+       else if(consume_sop & ~produce_eop)
+	 packet_count <= packet_count - 1;
+
+   always @(negedge gpif_clk)
+     if(gpif_rst)
+       gpif_empty_d <= 1;
+     else
+       gpif_empty_d <= ~|packet_count;
+
+   // Use occ bit to signal a gpif flush
+   always @(negedge gpif_clk)
+     if(gpif_rst)
+       gpif_flush <= 0;
+     else if(consume_eop & data_o[18])
+       gpif_flush <= ~gpif_flush;
+   
+   // Response Path
+   wire [15:0] 	resp_fifolevel;
+   wire 	consume_resp_line = gpif_rd & gpif_ep & ~read_count[4];
+
+   fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk
+     (.wclk(sys_clk), .datain(resp_i[17:0]), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(),
+      .rclk(~gpif_clk), .dataout(resp_o), 
+      .src_rdy_o(final_rdy_resp), .dst_rdy_i(consume_resp_line), .occupied(resp_fifolevel),
+      .arst(sys_rst));
+
+   // FIXME -- handle short packets
+   
+   always @(negedge gpif_clk)
+     if(gpif_rst)
+       gpif_empty_c <= 1;
+     else
+       gpif_empty_c <= resp_fifolevel < 16;
+   
+   // Output Mux
+   assign gpif_data = gpif_ep ? resp_o[15:0] : data_o[15:0];
+
+   assign debug = { { 16'd0 },
+		    { data_int[17:16], data_o[17:16], packet_count[3:0] },
+		    { consume_sop, consume_eop, final_rdy_data, data_o[18], consume_data_line, consume_resp_line, src_rdy_int, dst_rdy_int} };
+   
+endmodule // gpif_rd
diff --git a/fpga/usrp2/gpif/gpif_tb.v b/fpga/usrp2/gpif/gpif_tb.v
new file mode 100644
index 000000000..686284c2b
--- /dev/null
+++ b/fpga/usrp2/gpif/gpif_tb.v
@@ -0,0 +1,142 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+module gpif_tb();
+   
+   reg sys_clk = 0;
+   reg sys_rst = 1;
+   reg gpif_clk = 0;
+   reg gpif_rst = 1;
+      
+   reg [15:0] gpif_data;
+   reg 	      WR = 0, EP = 0;
+
+   wire       CF, DF;
+   
+   wire       gpif_full_d, gpif_full_c;
+   wire [18:0] data_o, ctrl_o, data_splt;
+   wire        src_rdy, dst_rdy, src_rdy_splt, dst_rdy_splt;
+   wire        ctrl_src_rdy, ctrl_dst_rdy;
+
+   assign ctrl_dst_rdy = 1;
+   
+   initial $dumpfile("gpif_tb.vcd");
+   initial $dumpvars(0,gpif_tb);
+
+   initial #1000 gpif_rst = 0;
+   initial #1000 sys_rst = 0;
+   always #64 gpif_clk <= ~gpif_clk;
+   always #47.9 sys_clk <= ~sys_clk;
+
+   wire [18:0] data_int;
+   wire        src_rdy_int, dst_rdy_int;
+
+   assign dst_rdy_splt = 1;
+   
+   gpif_wr gpif_write
+     (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), 
+      .gpif_data(gpif_data), .gpif_wr(WR), .gpif_ep(EP),
+      .gpif_full_d(DF), .gpif_full_c(CF),
+      
+      .sys_clk(sys_clk), .sys_rst(sys_rst),
+      .data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int),
+      .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) );
+
+   packet_reframer tx_packet_reframer 
+     (.clk(sys_clk), .reset(sys_rst), .clear(0),
+      .data_i(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int),
+      .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+   packet_splitter #(.FRAME_LEN(256)) rx_packet_splitter
+     (.clk(sys_clk), .reset(sys_rst), .clear(0),
+      .frames_per_packet(2),
+      .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+      .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt));
+
+   always @(posedge sys_clk)
+     if(ctrl_src_rdy & ctrl_dst_rdy)
+       $display("CTRL: %x",ctrl_o);
+
+   always @(posedge sys_clk)
+     if(src_rdy_splt & dst_rdy_splt)
+       begin
+	  if(data_splt[16])
+	    $display("<-------- DATA SOF--------->");
+	  $display("DATA: %x",data_splt);
+	  if(data_splt[17])
+	    $display("<-------- DATA EOF--------->");
+       end
+   
+   initial
+     begin
+	#10000;
+	repeat (1)
+	  begin
+	     @(posedge gpif_clk);
+	     
+	     WR <= 1;
+	     gpif_data <= 256;  // Length
+	     @(posedge gpif_clk);
+	     gpif_data <= 16'h00;
+	     @(posedge gpif_clk);
+	     repeat(254)
+	       begin
+		  gpif_data <= gpif_data + 1;
+		  @(posedge gpif_clk);
+	       end
+	     WR <= 0;
+
+	     while(DF)
+	       @(posedge gpif_clk);
+	     repeat (16)
+	       @(posedge gpif_clk);
+	     
+	     WR <= 1;
+	     repeat(256)
+	       begin
+		  gpif_data <= gpif_data - 1;
+		  @(posedge gpif_clk);
+	       end
+	     WR <= 0;
+
+
+/*
+	     while(DF)
+	       @(posedge gpif_clk);
+	     	     
+	     repeat (20)
+	       @(posedge gpif_clk);
+	     WR <= 1;
+	     gpif_data <= 16'h5;
+	     @(posedge gpif_clk);
+	     gpif_data <= 16'h00;
+	     @(posedge gpif_clk);
+	     repeat(254)
+	       begin
+		  gpif_data <= gpif_data - 1;
+		  @(posedge gpif_clk);
+	       end
+	     WR <= 0;
+ */
+	  end
+     end // initial begin
+   
+   initial #200000 $finish;
+   
+     
+endmodule // gpif_tb
diff --git a/fpga/usrp2/gpif/gpif_wr.v b/fpga/usrp2/gpif/gpif_wr.v
new file mode 100644
index 000000000..89fae282e
--- /dev/null
+++ b/fpga/usrp2/gpif/gpif_wr.v
@@ -0,0 +1,95 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+module gpif_wr
+  (input gpif_clk, input gpif_rst,
+   input [15:0] gpif_data, input gpif_wr, input gpif_ep,
+   output reg gpif_full_d, output reg gpif_full_c,
+
+   input sys_clk, input sys_rst,
+   output [18:0] data_o, output src_rdy_o, input dst_rdy_i,
+   output [18:0] ctrl_o, output ctrl_src_rdy_o, input ctrl_dst_rdy_i,
+   output [31:0] debug );
+
+   reg 		 wr_reg, ep_reg;
+   reg [15:0] 	 gpif_data_reg;
+   
+   always @(posedge gpif_clk)
+     begin
+	ep_reg <= gpif_ep;
+	wr_reg <= gpif_wr;
+	gpif_data_reg <= gpif_data;
+     end
+
+   reg [9:0] write_count;
+   
+   always @(posedge gpif_clk)
+     if(gpif_rst)
+       write_count <= 0;
+     else if(wr_reg)
+       write_count <= write_count + 1;
+     else
+       write_count <= 0;
+
+   reg 	     sop;
+   wire      eop = (write_count == 255);
+   wire      eop_ctrl = (write_count == 15);
+   
+   always @(posedge gpif_clk)
+     sop <= gpif_wr & ~wr_reg;
+
+   // Data Path
+   wire [15:0] fifo_space;
+   always @(posedge gpif_clk)
+     if(gpif_rst)
+       gpif_full_d <= 1;
+     else
+       gpif_full_d <= fifo_space < 256;
+
+   wire [17:0] data_int;
+   wire        src_rdy_int, dst_rdy_int;
+
+   fifo_cascade #(.WIDTH(18), .SIZE(10)) wr_fifo
+     (.clk(gpif_clk), .reset(gpif_rst), .clear(0),
+      .datain({eop,sop,gpif_data_reg}), .src_rdy_i(~ep_reg & wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space),
+      .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied());
+   
+   fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) wr_fifo_2clk
+     (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(),
+      .rclk(sys_clk), .dataout(data_o[17:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(),
+      .arst(sys_rst));
+   assign data_o[18] = 1'b0;
+   
+   // Control Path
+   wire [15:0] ctrl_fifo_space;
+   always @(posedge gpif_clk)
+     if(gpif_rst)
+       gpif_full_c <= 1;
+     else
+       gpif_full_c <= ctrl_fifo_space < 16;
+   
+   fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) ctrl_fifo_2clk
+     (.wclk(gpif_clk), .datain({1'b0,eop_ctrl,sop,gpif_data_reg}), 
+      .src_rdy_i(ep_reg & wr_reg & ~write_count[4]), .dst_rdy_o(), .space(ctrl_fifo_space),
+      .rclk(sys_clk), .dataout(ctrl_o[18:0]), 
+      .src_rdy_o(ctrl_src_rdy_o), .dst_rdy_i(ctrl_dst_rdy_i), .occupied(),
+      .arst(sys_rst));
+
+   assign debug = { 16'd0, ep_reg, wr_reg, eop, sop, (~ep_reg & wr_reg & ~write_count[8]), src_rdy_int, dst_rdy_int, write_count[8:0]};
+   
+endmodule // gpif_wr
diff --git a/fpga/usrp2/gpif/gpif_wr_tb.v b/fpga/usrp2/gpif/gpif_wr_tb.v
new file mode 100644
index 000000000..171bb96a1
--- /dev/null
+++ b/fpga/usrp2/gpif/gpif_wr_tb.v
@@ -0,0 +1,110 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+module gpif_wr_tb();
+   
+   reg sys_clk = 0;
+   reg sys_rst = 1;
+   reg gpif_clk = 0;
+   reg gpif_rst = 1;
+      
+   reg [15:0] gpif_data;
+   reg 	      WR = 0, EP = 0;
+
+   wire       CF, DF;
+   
+   wire       gpif_full_d, gpif_full_c;
+   wire [18:0] data_o, ctrl_o;
+   wire        src_rdy, dst_rdy;
+   wire        ctrl_src_rdy, ctrl_dst_rdy;
+
+   assign ctrl_dst_rdy = 1;
+   assign dst_rdy = 1;
+   
+   initial $dumpfile("gpif_wr_tb.vcd");
+   initial $dumpvars(0,gpif_wr_tb);
+
+   initial #1000 gpif_rst = 0;
+   initial #1000 sys_rst = 0;
+   always #64 gpif_clk <= ~gpif_clk;
+   always #47.9 sys_clk <= ~sys_clk;
+
+   wire [18:0] data_int;
+   wire        src_rdy_int, dst_rdy_int;
+   
+   gpif_wr gpif_write
+     (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), 
+      .gpif_data(gpif_data), .gpif_wr(WR), .gpif_ep(EP),
+      .gpif_full_d(DF), .gpif_full_c(CF),
+      
+      .sys_clk(sys_clk), .sys_rst(sys_rst),
+      .data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int),
+      .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) );
+
+   packet_reframer tx_packet_reframer 
+     (.clk(sys_clk), .reset(sys_rst), .clear(0),
+      .data_i(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int),
+      .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+   always @(posedge sys_clk)
+     if(ctrl_src_rdy & ctrl_dst_rdy)
+       $display("CTRL: %x",ctrl_o);
+
+   always @(posedge sys_clk)
+     if(src_rdy & dst_rdy)
+       begin
+	  if(data_o[16])
+	    $display("<-------- DATA SOF--------->");
+	  $display("DATA: %x",data_o);
+	  if(data_o[17])
+	    $display("<-------- DATA EOF--------->");
+       end
+   
+   initial
+     begin
+	#10000;
+	repeat (1)
+	  begin
+	     WR <= 1;
+	     gpif_data <= 10;  // Length
+	     @(posedge gpif_clk);
+	     gpif_data <= 16'h00;
+	     @(posedge gpif_clk);
+	     repeat(254)
+	       begin
+		  gpif_data <= gpif_data + 1;
+		  @(posedge gpif_clk);
+	       end
+	     WR <= 0;
+	     repeat (20)
+	       @(posedge gpif_clk);
+	     WR <= 1;
+	     gpif_data <= 16'h5;
+	     @(posedge gpif_clk);
+	     repeat(254)
+	       begin
+		  gpif_data <= gpif_data - 1;
+		  @(posedge gpif_clk);
+	       end
+	  end
+     end // initial begin
+   
+   initial #100000 $finish;
+   
+     
+endmodule // gpif_wr_tb
diff --git a/fpga/usrp2/gpif/lint b/fpga/usrp2/gpif/lint
new file mode 100755
index 000000000..4316c89a9
--- /dev/null
+++ b/fpga/usrp2/gpif/lint
@@ -0,0 +1,2 @@
+iverilog -Wall -y . -y ../fifo/ -y ../control_lib/ -y ../models/ -y ../coregen/ -y ../simple_gemac/ -y ../sdr_lib/ -y ../vrt/ gpif.v 2>&1 | grep -v coregen | grep -v models
+
diff --git a/fpga/usrp2/gpif/packet_padder36.v b/fpga/usrp2/gpif/packet_padder36.v
new file mode 100644
index 000000000..c785f7ea6
--- /dev/null
+++ b/fpga/usrp2/gpif/packet_padder36.v
@@ -0,0 +1,130 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// The packet padder 36 for use with slave fifo32
+// Packet padder understands the concept of LUTs,
+// and will forward packets through the interface,
+// adding zero padding as needed to properly flush.
+// The padder will never write a packet across a LUT boundary.
+// When flushing, padder writes out zeros until the LUT boundary.
+// Requires that the input line0 be a VITA header, and SOF set.
+// Flush when the LUT is partially filled and timeout is reached,
+// or when the LUT is partially filled and the DSP is inactive.
+
+module packet_padder36
+#(
+    parameter RX_IDLE_FLUSH_CYCLES = 65536, //about 1ms at 64MHz clock
+    parameter MAX_LUT_LINES32 = 4096 //how many 32bit lines in a LUT
+)
+(
+    input clk, input reset,
+    input [35:0] data_i,
+    input src_rdy_i,
+    output dst_rdy_o,
+    output [35:0] data_o,
+    output src_rdy_o,
+    input dst_rdy_i,
+    input rx_dsp_active
+);
+
+    //state machine definitions
+    localparam STATE_READ_HDR = 0;
+    localparam STATE_WRITE_HDR = 1;
+    localparam STATE_FORWARD = 2;
+    localparam STATE_WRITE_PAD = 3;
+    reg [1:0] state;
+
+    //keep track of the outgoing lines
+    reg [15:0] line_count;
+    wire line_count_done = line_count == 1;
+    wire lut_is_empty = line_count == MAX_LUT_LINES32;
+    always @(posedge clk) begin
+        if (reset) begin
+            line_count <= MAX_LUT_LINES32;
+        end
+        else if (src_rdy_o && dst_rdy_i) begin
+            line_count <= (line_count_done)? MAX_LUT_LINES32 : line_count - 1;
+        end
+    end
+
+    //count the number of cycles since RX data so we can force a flush
+    reg [17:0] non_rx_cycles;
+    wire idle_timeout = (non_rx_cycles == RX_IDLE_FLUSH_CYCLES);
+    always @(posedge clk) begin
+        if(reset || state != STATE_READ_HDR) begin
+            non_rx_cycles <= 0;
+        end
+        else if (~idle_timeout) begin
+            non_rx_cycles <= non_rx_cycles + 1;
+        end
+    end
+
+    //flush when we have written data to a LUT and either idle or non active DSP
+    wire force_flush = ~lut_is_empty && (idle_timeout || ~rx_dsp_active);
+
+    //the padding state machine
+    reg [31:0] vita_hdr;
+    reg has_vita_hdr;
+    always @(posedge clk) begin
+        if (reset) begin
+            state <= STATE_READ_HDR;
+        end
+        else case(state)
+
+        STATE_READ_HDR: begin
+            if (src_rdy_i && dst_rdy_o && data_i[32]) begin
+                vita_hdr <= data_i[31:0];
+                has_vita_hdr <= 1;
+                state <= (data_i[15:0] > line_count)? state <= STATE_WRITE_PAD : STATE_WRITE_HDR;
+            end
+            else if (force_flush) begin
+                has_vita_hdr <= 0;
+                state <= STATE_WRITE_PAD;
+            end
+        end
+
+        STATE_WRITE_HDR: begin
+            if (src_rdy_o && dst_rdy_i) begin
+                state <= STATE_FORWARD;
+            end
+        end
+
+        STATE_FORWARD: begin
+            if (src_rdy_i && dst_rdy_o && data_i[33]) begin
+                state <= STATE_READ_HDR;
+            end
+        end
+
+        STATE_WRITE_PAD: begin
+            if (src_rdy_o && dst_rdy_i && line_count_done) begin
+                state <= (has_vita_hdr)? STATE_WRITE_HDR : STATE_READ_HDR;
+            end
+        end
+
+        endcase //state
+    end
+
+    //assign outgoing signals
+    assign dst_rdy_o = (state == STATE_READ_HDR)? 1 : ((state == STATE_FORWARD)? dst_rdy_i : 0);
+    assign src_rdy_o = (state == STATE_WRITE_HDR || state == STATE_WRITE_PAD)? 1 : ((state == STATE_FORWARD )? src_rdy_i : 0);
+    assign data_o = (state == STATE_WRITE_HDR)? {4'b0001, vita_hdr} : ((state == STATE_FORWARD)? data_i : 0);
+
+endmodule // packet_padder36
+
+
+
+
diff --git a/fpga/usrp2/gpif/packet_splitter.v b/fpga/usrp2/gpif/packet_splitter.v
new file mode 100644
index 000000000..ba4c8cded
--- /dev/null
+++ b/fpga/usrp2/gpif/packet_splitter.v
@@ -0,0 +1,123 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+// Split vita packets longer than one GPIF frame, add padding on short frames
+
+module packet_splitter
+  #(parameter FRAME_LEN=256)
+   (input clk, input reset, input clear,
+    input  [7:0] frames_per_packet,
+    input [18:0] data_i,
+    input src_rdy_i,
+    output dst_rdy_o,
+    output [18:0] data_o,
+    output src_rdy_o,
+    input dst_rdy_i,
+    output [31:0] debug0,
+    output [31:0] debug1);
+   
+   reg [1:0] state;
+   reg [15:0] length;
+   reg [15:0] frame_len;
+   reg [7:0]  frame_count;
+   
+   localparam PS_IDLE = 0;
+   localparam PS_FRAME = 1;
+   localparam PS_NEW_FRAME = 2;
+   localparam PS_PAD = 3;
+
+   wire       eof_i = data_i[17];
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  state <= PS_IDLE;
+	  frame_count <= 0;
+       end
+     else
+       case(state)
+	 PS_IDLE :
+	   if(src_rdy_i & dst_rdy_i)
+	     begin
+		length <= { data_i[14:0],1'b0};
+		frame_len <= FRAME_LEN;
+		state <= PS_FRAME;
+		frame_count <= 1;
+	     end
+	 PS_FRAME :
+	   if(src_rdy_i & dst_rdy_i)
+	     if((frame_len == 2) & ((length == 2) | eof_i))
+	       state <= PS_IDLE;
+	     else if(frame_len == 2)
+	       begin
+		  length <= length - 1;
+		  state <= PS_NEW_FRAME;
+		  frame_count <= frame_count + 1;
+	       end
+	     else if((length == 2)|eof_i)
+	       begin
+		  frame_len <= frame_len - 1;
+		  state <= PS_PAD;
+	       end
+	     else
+	       begin
+		  frame_len <= frame_len - 1;
+		  length <= length - 1;
+	       end
+	 PS_NEW_FRAME :
+	   if(src_rdy_i & dst_rdy_i)
+	     begin
+		frame_len <= FRAME_LEN;
+		if((length == 2)|eof_i)
+		  state <= PS_PAD;
+		else
+		  begin
+		     state <= PS_FRAME;
+		     length <= length - 1;
+		  end // else: !if((length == 2)|eof_i)
+	     end // if (src_rdy_i & dst_rdy_i)
+	 
+	 PS_PAD :
+	   if(dst_rdy_i)
+	     if(frame_len == 2)
+	       state <= PS_IDLE;
+	     else
+	       frame_len <= frame_len - 1;
+
+       endcase // case (state)
+
+   wire next_state_is_idle = dst_rdy_i & (frame_len==2) & 
+	( (state==PS_PAD) | ( (state==PS_FRAME) & src_rdy_i & ((length==2)|eof_i) ) );
+	  
+	 
+	
+   
+   assign dst_rdy_o = dst_rdy_i & (state != PS_PAD);
+   assign src_rdy_o = src_rdy_i | (state == PS_PAD);
+   
+   wire eof_out = (frame_len == 2) & (state != PS_IDLE) & (state != PS_NEW_FRAME);
+   wire sof_out = (state == PS_IDLE) | (state == PS_NEW_FRAME);
+   wire occ_out = eof_out & next_state_is_idle & (frames_per_packet != frame_count);
+   
+   wire [15:0] data_out = data_i[15:0];
+   assign data_o = {occ_out, eof_out, sof_out, data_out};
+   
+   assign debug0 = { 8'd0, dst_rdy_o, src_rdy_o, next_state_is_idle, eof_out, sof_out, occ_out, state[1:0], frame_count[7:0], frames_per_packet[7:0] };
+   assign debug1 = { length[15:0], frame_len[15:0] };
+   
+endmodule // packet_splitter
diff --git a/fpga/usrp2/gpif/packet_splitter_tb.v b/fpga/usrp2/gpif/packet_splitter_tb.v
new file mode 100644
index 000000000..329b58e0d
--- /dev/null
+++ b/fpga/usrp2/gpif/packet_splitter_tb.v
@@ -0,0 +1,137 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+module packet_splitter_tb();
+   
+   reg sys_clk = 0;
+   reg sys_rst = 1;
+   reg gpif_clk = 0;
+   reg gpif_rst = 1;
+      
+   reg [15:0] gpif_data;
+   reg 	      WR = 0, EP = 0;
+
+   wire       CF, DF;
+   
+   wire       gpif_full_d, gpif_full_c;
+   wire [18:0] data_o, ctrl_o, data_splt;
+   wire        src_rdy, dst_rdy, src_rdy_splt, dst_rdy_splt;
+   wire        ctrl_src_rdy, ctrl_dst_rdy;
+
+   assign ctrl_dst_rdy = 1;
+   
+   initial $dumpfile("packet_splitter_tb.vcd");
+   initial $dumpvars(0,packet_splitter_tb);
+
+   initial #1000 gpif_rst = 0;
+   initial #1000 sys_rst = 0;
+   always #64 gpif_clk <= ~gpif_clk;
+   always #47.9 sys_clk <= ~sys_clk;
+
+   wire [35:0] data_int;
+   wire        src_rdy_int, dst_rdy_int;
+
+   assign dst_rdy_splt = 1;
+
+   vita_pkt_gen vita_pkt_gen
+     (.clk(sys_clk), .reset(sys_rst) , .clear(0),
+      .len(512),.data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int));
+
+   fifo36_to_fifo19 #(.LE(1)) f36_to_f19
+     (.clk(sys_clk), .reset(sys_rst), .clear(0),
+      .f36_datain(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int),
+      .f19_dataout(data_o), .f19_src_rdy_o(src_rdy), .f19_dst_rdy_i(dst_rdy));
+   		 
+   packet_splitter #(.FRAME_LEN(13)) rx_packet_splitter
+     (.clk(sys_clk), .reset(sys_rst), .clear(0),
+      .frames_per_packet(4),
+      .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+      .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt));
+
+   always @(posedge sys_clk)
+     if(ctrl_src_rdy & ctrl_dst_rdy)
+       $display("CTRL: %x",ctrl_o);
+
+   always @(posedge sys_clk)
+     if(src_rdy_splt & dst_rdy_splt)
+       begin
+	  if(data_splt[16])
+	    $display("<-------- DATA SOF--------->");
+	  $display("DATA: %x",data_splt);
+	  if(data_splt[17])
+	    $display("<-------- DATA EOF--------->");
+       end
+   
+   initial
+     begin
+	#10000;
+	repeat (1)
+	  begin
+	     @(posedge gpif_clk);
+	     
+	     WR <= 1;
+	     gpif_data <= 256;  // Length
+	     @(posedge gpif_clk);
+	     gpif_data <= 16'h00;
+	     @(posedge gpif_clk);
+	     repeat(254)
+	       begin
+		  gpif_data <= gpif_data + 1;
+		  @(posedge gpif_clk);
+	       end
+	     WR <= 0;
+
+	     while(DF)
+	       @(posedge gpif_clk);
+	     repeat (16)
+	       @(posedge gpif_clk);
+	     
+	     WR <= 1;
+	     repeat(256)
+	       begin
+		  gpif_data <= gpif_data - 1;
+		  @(posedge gpif_clk);
+	       end
+	     WR <= 0;
+
+
+/*
+	     while(DF)
+	       @(posedge gpif_clk);
+	     	     
+	     repeat (20)
+	       @(posedge gpif_clk);
+	     WR <= 1;
+	     gpif_data <= 16'h5;
+	     @(posedge gpif_clk);
+	     gpif_data <= 16'h00;
+	     @(posedge gpif_clk);
+	     repeat(254)
+	       begin
+		  gpif_data <= gpif_data - 1;
+		  @(posedge gpif_clk);
+	       end
+	     WR <= 0;
+ */
+	  end
+     end // initial begin
+   
+   initial #200000 $finish;
+   
+     
+endmodule // packet_splitter_tb
diff --git a/fpga/usrp2/top/impactor.sh b/fpga/usrp2/top/impactor.sh
new file mode 100755
index 000000000..c6699424d
--- /dev/null
+++ b/fpga/usrp2/top/impactor.sh
@@ -0,0 +1,17 @@
+#!/bin/bash
+
+echo "loading $1 into FPGA..."
+
+CMD_PATH=/tmp/impact.cmd
+
+echo "generating ${CMD_PATH}..."
+
+echo "setmode -bscan" > ${CMD_PATH}
+echo "setcable -p auto" >> ${CMD_PATH}
+echo "addDevice -p 1 -file $1" >> ${CMD_PATH}
+echo "program -p 1" >> ${CMD_PATH}
+echo "quit" >> ${CMD_PATH}
+
+impact -batch ${CMD_PATH}
+
+echo "done!"
diff --git a/fpga/usrp2/vrt/vita_packet_demux36.v b/fpga/usrp2/vrt/vita_packet_demux36.v
new file mode 100644
index 000000000..83fb26215
--- /dev/null
+++ b/fpga/usrp2/vrt/vita_packet_demux36.v
@@ -0,0 +1,102 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+//demux an input stream based on the SID
+//output packet has SID removed from header
+
+module vita_packet_demux36
+#(
+    parameter NUMCHAN = 1,
+    parameter SID_BASE = 0
+)
+(
+    input clk, input rst,
+
+    input [35:0] in_data,
+    input in_src_rdy,
+    output in_dst_rdy,
+
+    output [35:0] out_data,
+    output [NUMCHAN-1:0] out_src_rdy,
+    input [NUMCHAN-1:0] out_dst_rdy
+);
+
+    reg [1:0] state;
+    localparam STATE_WAIT_HDR = 0;
+    localparam STATE_PROC_SID = 1;
+    localparam STATE_WRITE_HDR = 2;
+    localparam STATE_FORWARD = 3;
+
+    reg [31:0] hdr;
+    reg [NUMCHAN-1:0] sid;
+    wire has_sid = in_data[28];
+    reg has_sid_reg;
+
+    wire my_out_dst_rdy = out_dst_rdy[sid];
+    wire my_out_src_rdy = out_src_rdy[sid];
+
+    always @(posedge clk) begin
+        if (rst) begin
+            state <= STATE_WAIT_HDR;
+        end
+        else case(state)
+
+        STATE_WAIT_HDR: begin
+            if (in_src_rdy && in_dst_rdy && in_data[32]) begin
+                state <= (has_sid)? STATE_PROC_SID : STATE_WRITE_HDR;
+            end
+            sid <= 0;
+            hdr <= in_data[31:0];
+            has_sid_reg <= has_sid;
+        end
+
+        STATE_PROC_SID: begin
+            if (in_src_rdy && in_dst_rdy) begin
+                state <= STATE_WRITE_HDR;
+                sid <= in_data[31:0] - SID_BASE;
+                hdr[28] <= 1'b0; //clear has sid
+                hdr[15:0] <= hdr[15:0] - 1'b1; //subtract a line
+            end
+        end
+
+        STATE_WRITE_HDR: begin
+            if (my_out_src_rdy && my_out_dst_rdy) begin
+                state <= STATE_FORWARD;
+            end
+        end
+
+        STATE_FORWARD: begin
+            if (my_out_src_rdy && my_out_dst_rdy && out_data[33]) begin
+                state <= STATE_WAIT_HDR;
+            end
+        end
+
+        endcase //state
+    end
+
+    assign out_data = (state == STATE_WRITE_HDR)? {4'b0001, hdr} : in_data;
+    wire out_src_rdy_i = (state == STATE_WRITE_HDR)? 1'b1 : ((state == STATE_FORWARD)? in_src_rdy : 1'b0);
+    assign in_dst_rdy = (state == STATE_WAIT_HDR || state == STATE_PROC_SID)? 1'b1 : ((state == STATE_FORWARD)? my_out_dst_rdy : 1'b0);
+
+    genvar i;
+    generate
+    for(i = 0; i < NUMCHAN; i = i + 1) begin:valid_assign
+        assign out_src_rdy[i] = (i == sid)? out_src_rdy_i : 1'b0;
+    end
+    endgenerate
+
+endmodule //vita_packet_demux36
diff --git a/fpga/usrp3/README.txt b/fpga/usrp3/README.txt
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/lib/control/Makefile.srcs b/fpga/usrp3/lib/control/Makefile.srcs
new file mode 100644
index 000000000..e0ad8a942
--- /dev/null
+++ b/fpga/usrp3/lib/control/Makefile.srcs
@@ -0,0 +1,26 @@
+#
+# Copyright 2013 Ettus Research LLC
+#
+
+##################################################
+# Control Lib Sources
+##################################################
+CONTROL_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/control/, \
+reset_sync.v \
+por_gen.v \
+gpio_atr.v \
+simple_spi_core.v \
+simple_i2c_core.v \
+setting_reg.v \
+settings_bus_crossclock.v \
+radio_ctrl_proc.v \
+ram_2port.v \
+axi_crossbar.v \
+axi_slave_mux.v \
+axi_fifo_header.v \
+arb_qualify_master.v \
+axi_forwarding_cam.v \
+axi_test_vfifo.v \
+dram_2port.v \
+cvita_uart.v \
+))
diff --git a/fpga/usrp3/lib/control/README.txt b/fpga/usrp3/lib/control/README.txt
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/lib/control/arb_qualify_master.v b/fpga/usrp3/lib/control/arb_qualify_master.v
new file mode 100644
index 000000000..df17fac57
--- /dev/null
+++ b/fpga/usrp3/lib/control/arb_qualify_master.v
@@ -0,0 +1,88 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+
+
+//
+// This module forms the qualification engine for a single master as
+// part of a larger arbitration engine for a slave. It would typically
+// be instantiated from arb_select_master.v to form a complete arbitor solution.
+//
+
+module arb_qualify_master
+  #(
+    parameter WIDTH=16  // Bit width of destination field.
+    )
+    (  
+       input clk,
+       input reset,
+       input clear,     
+       // Header signals
+       input [WIDTH-1:0] header,
+       input header_valid,
+       // Slave Confg Signals
+       input [WIDTH-1:0] slave_addr,
+       input [WIDTH-1:0] slave_mask,
+       input slave_valid,
+       // Arbitration flags
+       output reg master_valid,
+       input master_ack
+       );
+
+   localparam WAIT_HEADER_VALID = 0;
+   localparam MATCH = 1;
+   localparam WAIT_HEADER_NOT_VALID = 2;
+   
+   
+   reg [1:0] state, next_state;
+
+   
+   // Does masked slave address match header field for dest from master?
+   assign    header_match = ((header & slave_mask) == (slave_addr & slave_mask)) && slave_valid;
+   
+   
+   always @(posedge clk)
+     if (reset | clear) begin
+        state <= WAIT_HEADER_VALID;
+	master_valid <= 0;
+     end else
+       begin	  
+	  case(state)
+	    //
+	    // Wait here until Masters FIFO presents a valid header word.
+	    //
+	    WAIT_HEADER_VALID: begin
+	       if (header_valid)
+		 if (header_match) begin
+		    state <= MATCH;
+		    master_valid <= 1;
+		 end else
+		   next_state <= WAIT_HEADER_NOT_VALID;
+	    end
+	    //
+	    // There should only ever be one match across various arbitors
+	    // if they are configured correctly and since the backing FIFO in the
+	    // master should not start to drain until the arbitration is won
+	    // by that master, master_ack should always preceed de-assertion of
+	    // header_valid so we don't check for the other order of deassertion.
+	    //
+	    MATCH: begin
+	       if (master_ack) begin
+		  master_valid <= 0;
+		  state <= WAIT_HEADER_NOT_VALID;
+	       end
+	    end
+	    //
+	    // Wait here until this master starts to drain this packet from his FIFO.
+	    //
+	    WAIT_HEADER_NOT_VALID: begin
+	       if (!header_valid) begin
+		  state <= WAIT_HEADER_VALID;
+	       end
+	    end
+	  endcase // case(state)
+       end // else: !if(reset | clear)
+
+endmodule // arb_qualify_master
+
+	 
\ No newline at end of file
diff --git a/fpga/usrp3/lib/control/axi_crossbar.v b/fpga/usrp3/lib/control/axi_crossbar.v
new file mode 100644
index 000000000..a408f69f0
--- /dev/null
+++ b/fpga/usrp3/lib/control/axi_crossbar.v
@@ -0,0 +1,167 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+
+
+`define LOG2(N) (\
+                 N < 2 ? 0 : \
+                 N < 4 ? 1 : \
+                 N < 8 ? 2 : \
+                 N < 16 ? 3 : \
+                 N < 32 ? 4 : \
+                 N < 64 ? 5 : \
+		 N < 128 ? 6 : \
+		 N < 256 ? 7 : \
+		 N < 512 ? 8 : \
+		 N < 1024 ? 9 : \
+                 10)
+
+module axi_crossbar
+  #(
+    parameter FIFO_WIDTH = 64,   // AXI4-STREAM data bus width
+    parameter DST_WIDTH = 16,    // Width of DST field we are routing on.
+    parameter NUM_INPUTS = 2,    // number of input AXI4-STREAM buses
+    parameter NUM_OUTPUTS = 2    // number of output AXI4-STREAM buses
+    )
+    (
+     input 				   clk,
+     input 				   reset,
+     input 				   clear,
+     input [7:0] 		 local_addr,
+     // Inputs
+     input [(FIFO_WIDTH*NUM_INPUTS)-1:0]   i_tdata,
+     input [NUM_INPUTS-1:0] 		   i_tvalid,
+     input [NUM_INPUTS-1:0] 		   i_tlast,
+     output [NUM_INPUTS-1:0] 		   i_tready,
+     input [NUM_INPUTS-1:0] 		   pkt_present,
+     // Setting Bus 
+     input 				   set_stb,
+     input [15:0] 			   set_addr,
+     input [31:0] 			   set_data,
+     // Output
+     output [(FIFO_WIDTH*NUM_OUTPUTS)-1:0] o_tdata,
+     output [NUM_OUTPUTS-1:0] 		   o_tvalid,
+     output [NUM_OUTPUTS-1:0] 		   o_tlast,
+     input [NUM_OUTPUTS-1:0] 		   o_tready,
+     // readback bus
+     input                        rb_rd_stb,
+     input [`LOG2(NUM_OUTPUTS)+`LOG2(NUM_INPUTS)-1:0] rb_addr,
+     output [31:0]                rb_data
+     );
+  
+   genvar m,n;
+   
+   wire [(NUM_INPUTS*NUM_OUTPUTS)-1:0] forward_valid_in;
+   wire [(NUM_INPUTS*NUM_OUTPUTS)-1:0] forward_ack_in;
+   wire [(NUM_INPUTS*NUM_OUTPUTS)-1:0] forward_valid_out;
+   wire [(NUM_INPUTS*NUM_OUTPUTS)-1:0] forward_ack_out;
+   
+   wire [NUM_INPUTS-1:0] i_tready_slave [0:NUM_OUTPUTS-1];
+
+   //
+   // Instantiate an axi_slave_mux for every slave/output of the Crossbar switch.
+   // Each axi_slave_mux contains logic to maux and resolve arbitration
+   // for this particular slave/output.
+   //
+   
+   generate
+      for (m = 0; m < NUM_OUTPUTS; m = m + 1) begin: instantiate_slave_mux
+
+	 wire [NUM_INPUTS-1:0] i_tready_tmp;
+	 
+	 axi_slave_mux 	
+	   #(
+	     .FIFO_WIDTH(FIFO_WIDTH),     // AXI4-STREAM data bus width
+	     .DST_WIDTH(DST_WIDTH),  // Width of DST field we are routing on.
+	     .NUM_INPUTS(NUM_INPUTS)  // number of input AXI buses
+	     ) 	axi_slave_mux_i
+	     (
+	      .clk(clk),
+	      .reset(reset),
+	      .clear(clear),
+	      // Inputs
+	      .i_tdata(i_tdata),
+	      .i_tvalid(i_tvalid),
+	      .i_tlast(i_tlast),
+	      .i_tready(i_tready_tmp),
+	      // Forwarding flags (One from each Input/Master)
+	      .forward_valid(forward_valid_in[(m+1)*NUM_INPUTS-1:m*NUM_INPUTS]),
+	      .forward_ack(forward_ack_out[(m+1)*NUM_INPUTS-1:m*NUM_INPUTS]),
+	      // Output
+	      .o_tdata(o_tdata[(m*FIFO_WIDTH)+FIFO_WIDTH-1:m*FIFO_WIDTH]),
+	      .o_tvalid(o_tvalid[m]),
+	      .o_tlast(o_tlast[m]),
+	      .o_tready(o_tready[m])
+	      );
+    
+	 if (m==0)
+	       assign i_tready_slave[0] = i_tready_tmp;
+	 else
+	      assign i_tready_slave[m] = i_tready_tmp | i_tready_slave[m-1] ;
+	 
+      end // block: instantiate_slave_mux
+   endgenerate
+
+   assign 	  i_tready = i_tready_slave[NUM_OUTPUTS-1];
+
+   //
+   // Permute the forwarding flag buses
+   //
+   
+   generate
+      for (m = 0; m < NUM_OUTPUTS; m = m + 1) begin: permute_outer
+	 for (n = 0; n < NUM_INPUTS; n = n + 1) begin: permute_inner
+	    assign forward_valid_in[n*NUM_OUTPUTS+m] = forward_valid_out[n+m*NUM_INPUTS];
+	    assign forward_ack_in[n+m*NUM_INPUTS] = forward_ack_out[n*NUM_OUTPUTS+m];
+	 end
+      end
+      
+   endgenerate
+	     
+      
+   //
+   // Instantiate an axi_forwarding_cam for every Input/Master of the Crossbar switch.
+   // Each contains a TCAM like lookup that allocates an egress port.
+   //
+
+   wire [31:0] 	   rb_data_mux[0:NUM_INPUTS-1];
+   
+   generate
+      for (m = 0; m < NUM_INPUTS; m = m + 1) begin: instantiate_cam
+	 axi_forwarding_cam 
+	   #(
+	     .BASE(0),
+	     .WIDTH(FIFO_WIDTH),  // Bit width of FIFO word.
+	     .NUM_OUTPUTS(NUM_OUTPUTS)
+	     ) axi_forwarding_cam_i
+	     (
+	      .clk(clk),
+	      .reset(reset),
+	      .clear(clear),
+	      // Monitored FIFO signals
+	      .o_tdata(i_tdata[(m*FIFO_WIDTH)+FIFO_WIDTH-1:m*FIFO_WIDTH]),
+	      .o_tvalid(i_tvalid[m]),
+	      .o_tready(i_tready[m]),
+	      .o_tlast(i_tlast[m]),
+	      .pkt_present(pkt_present[m]),
+	      // Configuration
+	      .local_addr(local_addr),
+	      // Setting Bus 
+	      .set_stb(set_stb),
+	      .set_addr(set_addr),
+	      .set_data(set_data),
+	      // Header signals
+	      .forward_valid(forward_valid_out[(m+1)*NUM_OUTPUTS-1:m*NUM_OUTPUTS]), 
+	      .forward_ack(forward_ack_in[(m+1)*NUM_OUTPUTS-1:m*NUM_OUTPUTS]),
+	      // Readback bus
+	      .rb_rd_stb(rb_rd_strobe && (rb_addr[`LOG2(NUM_OUTPUTS)+`LOG2(NUM_INPUTS)-1:`LOG2(NUM_OUTPUTS)] == m)),
+	      .rb_addr(rb_addr[`LOG2(NUM_OUTPUTS)-1:0]),
+	      .rb_data(rb_data_mux[m])
+	      );
+      end // block: instantiate_fifo_header
+   endgenerate
+
+   assign rb_data = rb_data_mux[rb_addr[`LOG2(NUM_OUTPUTS)+`LOG2(NUM_INPUTS)-1:`LOG2(NUM_OUTPUTS)]]; 
+   
+
+endmodule // axi_crossbar
diff --git a/fpga/usrp3/lib/control/axi_crossbar_tb.v b/fpga/usrp3/lib/control/axi_crossbar_tb.v
new file mode 100644
index 000000000..1994cb352
--- /dev/null
+++ b/fpga/usrp3/lib/control/axi_crossbar_tb.v
@@ -0,0 +1,214 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+
+`timescale  1 ps / 1 ps
+
+module axi_crossbar_tb;
+
+
+   localparam STREAM_WIDTH = 64;
+   
+   // Currently support simulations upto 8x8 configurations
+   localparam MAX_NUM_INPUTS = 8;
+   localparam MAX_NUM_OUTPUTS = 8;
+   
+   wire [(MAX_NUM_INPUTS*STREAM_WIDTH)-1:0] i_tdata;
+   wire [STREAM_WIDTH-1:0] 		i_tdata_array [0:MAX_NUM_INPUTS-1];   
+   wire [MAX_NUM_INPUTS-1:0] 		i_tvalid;
+   wire [MAX_NUM_INPUTS-1:0] 		i_tready;
+   wire [MAX_NUM_INPUTS-1:0] 		i_tlast;
+   wire [MAX_NUM_INPUTS-1:0] 		pkt_present;
+   
+   reg [STREAM_WIDTH-1:0] 		data_in [0:MAX_NUM_INPUTS-1];   
+   reg [MAX_NUM_INPUTS-1:0] 		valid_in;
+   wire [MAX_NUM_INPUTS-1:0] 		ready_in;
+   reg [MAX_NUM_INPUTS-1:0] 		last_in;
+   
+   wire [(MAX_NUM_OUTPUTS*STREAM_WIDTH)-1:0] o_tdata;
+   wire [STREAM_WIDTH-1:0] 		 o_tdata_array [0:MAX_NUM_OUTPUTS-1];   
+   wire [MAX_NUM_OUTPUTS-1:0] 		 o_tvalid;
+   wire [MAX_NUM_OUTPUTS-1:0] 		 o_tready;
+   wire [MAX_NUM_OUTPUTS-1:0] 		 o_tlast;
+   
+
+   wire [STREAM_WIDTH-1:0] 		 data_out [0:MAX_NUM_OUTPUTS-1];   
+   wire [MAX_NUM_OUTPUTS-1:0] 		 valid_out;
+   reg [MAX_NUM_OUTPUTS-1:0] 		 ready_out; 
+   wire [MAX_NUM_OUTPUTS-1:0] 		 last_out;
+		 
+   
+   genvar 				 m;
+
+   reg 					 clk;
+   reg 					 reset;
+   reg 					 clear;
+   reg 					 set_stb;
+   reg [15:0] 				 set_addr;
+   reg [31:0] 				 set_data;
+   
+  // reg 					 reset;
+
+   //
+   // Simulation specific testbench is included here
+   //
+`include "task_library.v"
+`include "simulation_script.v"
+
+   
+   //
+   // Define Clocks
+   //
+   initial begin
+      clk = 1'b1;
+   end
+   
+   // 125MHz clock
+   always #4000 clk = ~clk;
+
+   //
+   // Good starting state
+   //
+     initial begin
+	reset <= 0;
+	clear <= 0;
+	set_stb <= 0;
+	set_addr <= 0;
+	set_data <= 0;
+/* -----\/----- EXCLUDED -----\/-----
+	data_in[0] <= 0;
+	valid_in[0] <= 0;
+	last_in[0] <= 0;
+	
+	data_in[1] <= 0;
+	valid_in[1] <= 0;
+	last_in[1] <= 0;
+ -----/\----- EXCLUDED -----/\----- */
+	
+	
+     end
+
+  
+
+   //
+   // AXI Crossbar instance
+   //
+   localparam SR_AWIDTH = 16;
+   localparam SR_XB_LOCAL = 512;
+   
+   wire [7:0] local_addr;
+
+   setting_reg #(.my_addr(SR_XB_LOCAL), .awidth(SR_AWIDTH), .width(8)) sr_local_addr
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(local_addr),.changed());
+   
+   axi_crossbar
+     #(
+       .FIFO_WIDTH(STREAM_WIDTH),   // AXI4-STREAM data bus width
+       .DST_WIDTH(16),    // Width of DST field we are routing on.
+       .NUM_INPUTS(NUM_INPUTS),    // number of input AXI4-STREAM buses
+       .NUM_OUTPUTS(NUM_OUTPUTS)    // number of output AXI4-STREAM buses
+       ) axi_crossbar_i
+       (
+	.clk(clk),
+	.reset(reset),
+	.clear(clear),
+	.local_addr(local_addr),
+	// Inputs
+	.i_tdata(i_tdata[(NUM_INPUTS*STREAM_WIDTH)-1:0]),
+	.i_tvalid(i_tvalid[NUM_INPUTS-1:0]),
+	.i_tlast(i_tlast[NUM_INPUTS-1:0]),
+	.i_tready(i_tready[NUM_INPUTS-1:0]),
+	.pkt_present(pkt_present[NUM_INPUTS-1:0]),
+	 // Settings bus
+	.set_stb(set_stb),
+	.set_addr(set_addr),
+	.set_data(set_data),
+	// Output
+	.o_tdata(o_tdata[(NUM_OUTPUTS*STREAM_WIDTH)-1:0]),
+	.o_tvalid(o_tvalid[NUM_OUTPUTS-1:0]),
+	.o_tlast(o_tlast[NUM_OUTPUTS-1:0]),
+	.o_tready(o_tready[NUM_OUTPUTS-1:0]),
+	// Readback Bus
+	.rb_rd_stb(1'b0),
+	.rb_addr(0),
+	.rb_data()
+	);
+
+   //
+   // Input FIFOs
+   //
+   generate
+      for (m=0;m<NUM_INPUTS;m=m+1)
+	begin: input_fifos
+
+	   assign i_tdata[(STREAM_WIDTH*m)+STREAM_WIDTH-1:STREAM_WIDTH*m] = i_tdata_array[m];
+	   
+	   axi_fifo_short
+	     #(.WIDTH(STREAM_WIDTH+1)) axi_fifo_short_in
+	       (
+		.clk(clk), 
+		.reset(reset), 
+		.clear(clear),
+		.o_tdata({i_tlast[m],i_tdata_array[m]}),
+		.o_tvalid(i_tvalid[m]),
+		.o_tready(i_tready[m]),
+		.i_tdata({last_in[m],data_in[m]}),
+		.i_tvalid(valid_in[m]),
+		.i_tready(ready_in[m]),
+		.space(),
+		.occupied()
+		);
+
+	   monitor_axi_fifo
+	     #(
+	       .COUNT_BITS(8)
+	       )  monitor_axi_fifo_in
+	       (
+		.clk(clk),
+		.reset(reset),
+		.clear(clear),
+		// Monitored FIFO signals
+		.i_tvalid(valid_in[m]),
+		.i_tready(ready_in[m]),
+		.i_tlast(last_in[m]),
+		.o_tvalid(i_tvalid[m]),
+		.o_tready(i_tready[m]),
+		.o_tlast(i_tlast[m]),
+		// FIFO status output
+		.pkt_present(pkt_present[m]), // Flags any whole packets present
+		.pkt_count()
+		);
+	   
+	end
+   endgenerate
+   
+	   
+   //
+   // Output FIFO's
+   //
+   generate
+      for (m=0;m<NUM_OUTPUTS;m=m+1)
+	begin: output_fifos
+
+	   assign o_tdata_array[m] = o_tdata[(STREAM_WIDTH*m)+STREAM_WIDTH-1:STREAM_WIDTH*m];	   
+   
+	   axi_fifo_short 
+	     #(.WIDTH(STREAM_WIDTH+1)) axi_fifo_short_out
+	       (
+		.clk(clk), 
+		.reset(reset), 
+		.clear(clear),
+		.i_tdata({o_tlast[m],o_tdata_array[m]}),
+		.i_tvalid(o_tvalid[m]),
+		.i_tready(o_tready[m]),
+		.o_tdata({last_out[m],data_out[m]}),
+		.o_tvalid(valid_out[m]),
+		.o_tready(ready_out[m]),
+		.space(),
+		.occupied()
+		);
+	end
+   endgenerate // block: output_fifos
+
+endmodule // axi_crossbar_tb
diff --git a/fpga/usrp3/lib/control/axi_fifo_header.v b/fpga/usrp3/lib/control/axi_fifo_header.v
new file mode 100644
index 000000000..ceac8e324
--- /dev/null
+++ b/fpga/usrp3/lib/control/axi_fifo_header.v
@@ -0,0 +1,84 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+
+
+//
+// This module is connected to the output port of an AXI4-STREAM FIFO that is used to move packetized data.
+// It extracts and indicates the header (first word) of a packet in the FIFO. The header and flag are pipelined
+// for timing closure.
+//
+
+module axi_fifo_header
+  #(
+    parameter WIDTH=64  // Bit width of FIFO word.
+    )
+    (
+     input clk,
+     input reset,
+     input clear,
+     // Monitored FIFO signals
+     input [WIDTH-1:0] o_tdata,
+     input o_tvalid,
+     input o_tready,
+     input o_tlast,
+     input pkt_present,
+     // Header signals
+     output reg [WIDTH-1:0] header,
+     output reg header_valid
+     );
+
+   localparam WAIT_SOF = 0;
+   localparam WAIT_EOF = 1;
+   
+   reg 	    out_state;
+   
+
+    //
+    // Monitor packets leaving FIFO
+    //
+    always @(posedge clk)
+      if (reset | clear) begin
+         out_state <= WAIT_SOF;
+      end else
+	case(out_state)
+	  //
+	  // After RESET or the EOF of previous packet, the first cycle with
+	  // output valid asserted is the SOF and presents the Header word.
+	  // The cycle following the concurrent presentation of asserted output 
+	  // valid and output ready presents the word following the header.
+	  //
+          WAIT_SOF: 
+            if (o_tvalid && o_tready) begin
+               out_state <= WAIT_EOF;
+            end else begin
+               out_state <= WAIT_SOF;
+            end
+	  //
+	  // EOF is signalled by o_tlast asserted whilst output valid and ready asserted.
+	  //
+          WAIT_EOF: 
+            if (o_tlast && o_tvalid && o_tready) begin
+               out_state <= WAIT_SOF;
+            end else begin
+               out_state <= WAIT_EOF;
+            end
+	endcase // case(in_state)
+   
+   //
+   // Pipeline Header signals
+   //
+   always @(posedge clk)
+     if (reset | clear) begin
+	header <= 0;
+	header_valid <= 0;
+     end else if (o_tvalid && (out_state == WAIT_SOF) && pkt_present) begin
+	// Header will remian valid until o_tready is asserted as this will cause a state transition.
+	header <= o_tdata;
+	header_valid <= 1;
+     end else begin
+	header_valid <= 0;
+     end
+
+
+endmodule // axi_fifo_header
diff --git a/fpga/usrp3/lib/control/axi_forwarding_cam.v b/fpga/usrp3/lib/control/axi_forwarding_cam.v
new file mode 100644
index 000000000..2f28b5640
--- /dev/null
+++ b/fpga/usrp3/lib/control/axi_forwarding_cam.v
@@ -0,0 +1,232 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+//
+// This module implements a highly customized TCAM that enbales forwarding
+// decisions to be made on a 16bit field from a VITA SID field.
+// The 16bits are allocated by convention as 8 bits of Network address
+// (Addresses USRP's etc) and 8 bits of Host address (adresses endpoints in
+// a USRP). By definition if the DEST field in the SID addresses a different
+// USRP than this one then we don't care about the Host field, only the Network Field.
+// We only look at the Host Field when the Network field addresses us.
+// Thus Need TCAM of 256+256 entries with Log2(N) bits, where N is the number of
+// slave(output) ports on the crossbar switch.
+//
+//
+//
+// SID format:
+//
+// |--------|---------|--------|---------|
+// |      SOURCE      |  DEST  |  DEST   |
+// |      ADDRESS     | NETWORK|  HOST   |
+// |--------|---------|--------|---------|
+//     8         8         8        8
+//
+
+
+`define LOG2(N) (\
+                 N < 2 ? 0 : \
+                 N < 4 ? 1 : \
+                 N < 8 ? 2 : \
+                 N < 16 ? 3 : \
+                 N < 32 ? 4 : \
+                 N < 64 ? 5 : \
+		 N < 128 ? 6 : \
+		 N < 256 ? 7 : \
+		 N < 512 ? 8 : \
+		 N < 1024 ? 9 : \
+                 10)
+
+module axi_forwarding_cam
+  #(
+    parameter BASE = 0,      // BASE address for setting registers in this block. (512 addrs used)
+    parameter WIDTH=64,      // Bit width of FIFO word.
+    parameter NUM_OUTPUTS=2  // Number of outputs (destinations) in crossbar.
+    )
+    (
+     input 			  clk,
+     input 			  reset,
+     input 			  clear,
+     // Monitored FIFO signals
+     input [WIDTH-1:0] 		  o_tdata,
+     input 			  o_tvalid,
+     input 			  o_tready,
+     input 			  o_tlast,
+     input 			  pkt_present,
+     // Configuration
+     input [7:0] 		  local_addr,
+     // Setting Bus 
+     input 			  set_stb,
+     input [15:0] 		  set_addr,
+     input [31:0] 		  set_data,
+     // Forwarding Flags
+     output reg [NUM_OUTPUTS-1:0] forward_valid,
+     input [NUM_OUTPUTS-1:0] 	  forward_ack,
+     // readback bus
+     input                        rb_rd_stb,
+     input [`LOG2(NUM_OUTPUTS)-1:0] rb_addr,
+     output [31:0]                rb_data
+     );
+
+
+   localparam WAIT_SOF = 0;
+   localparam WAIT_EOF = 1;
+   reg 				  state;
+   
+   localparam IDLE = 0;
+   localparam FORWARD = 1;
+   localparam WAIT = 2;
+   
+   reg 	[1:0]			  demux_state;
+
+   reg [15:0] 			  dst;
+   reg 				  dst_valid, dst_valid_reg;
+   wire 			  local_dst;
+   wire [8:0] 			  read_addr;
+   
+   //
+   // Monitor packets leaving FIFO
+   //
+   always @(posedge clk)
+     if (reset | clear) begin
+        state <= WAIT_SOF;
+     end else
+       case(state)
+	 //
+	 // After RESET or the EOF of previous packet, the first cycle with
+	 // output valid asserted is the SOF and presents the Header word.
+	 // The cycle following the concurrent presentation of asserted output 
+	 // valid and output ready presents the word following the header.
+	 //
+         WAIT_SOF: 
+           if (o_tvalid && o_tready) begin
+              state <= WAIT_EOF;
+           end else begin
+              state <= WAIT_SOF;
+           end
+	 //
+	 // EOF is signalled by o_tlast asserted whilst output valid and ready asserted.
+	 //
+         WAIT_EOF: 
+           if (o_tlast && o_tvalid && o_tready) begin
+              state <= WAIT_SOF;
+           end else begin
+              state <= WAIT_EOF;
+           end
+       endcase // case(in_state)  
+   
+   //
+   // Extract Destination fields(s) from SID
+   //
+   always @(posedge clk)
+     if (reset | clear) begin
+	dst <= 0;
+	dst_valid <= 0;
+	dst_valid_reg <= 0;	
+     end else if (o_tvalid && (state == WAIT_SOF) && pkt_present) begin
+	// SID will remain valid until o_tready is asserted as this will cause a state transition.
+	dst <= o_tdata[15:0]; 
+	dst_valid <= 1;
+	dst_valid_reg <= dst_valid;	
+     end else begin
+	dst_valid <= 0;
+	dst_valid_reg <= dst_valid;
+     end
+
+   //
+   // Is Network field in DST our local address?
+   //
+   assign local_dst = (dst[15:8] == local_addr) && dst_valid;
+   
+
+   //
+   // Mux address to RAM so that it searches CAM for Network field or Host field.
+   // Network addresses are stored in the lower 256 locations, host addresses the upper 256.
+   //
+   assign read_addr = {local_dst,(local_dst ? dst[7:0] : dst[15:8])};
+
+   //
+   // Imply a block RAM here, 512xCeil(Log2(NUM_OUTPUTS))
+   //
+   //synthesis attribute ram_style of mem is block
+   reg [(`LOG2(NUM_OUTPUTS))-1 : 0] mem [0:511];
+   reg [8:0] 			   read_addr_reg;
+   wire 			   write;
+   wire [`LOG2(NUM_OUTPUTS)-1:0] 	   read_data;
+   
+   assign write = (set_addr[15:9] == (BASE >>9)) && set_stb; // Addr decode.
+   
+   always @(posedge clk) 
+     begin
+	read_addr_reg <= read_addr;
+
+	if (write) begin
+	   mem[set_addr[8:0]] <= set_data[`LOG2(NUM_OUTPUTS)-1:0];
+	end
+
+     end
+
+   assign read_data = mem[read_addr_reg];
+
+
+   //
+   // State machine to manage forwarding flags.
+   //
+    always @(posedge clk)
+     if (reset | clear) begin
+        demux_state <= IDLE;
+     end else
+       case(demux_state)
+	
+	 // Wait for Valid DST which indicates a new packet lookup in the CAM.
+	 IDLE: begin
+	    if (dst_valid_reg == 1) begin
+	       forward_valid <= 1 << read_data;
+	       demux_state <= FORWARD;
+	    end
+	 end
+	 // When Slave/Output thats forwarding ACK's the forward flag, clear request and wait for packet to be transfered
+	 FORWARD: begin
+	    if ((forward_ack & forward_valid) != 0) begin
+	       forward_valid <= 0;
+	       demux_state <= WAIT;
+	    end
+	 end
+	 // When packet transfered go back to idle.
+	 WAIT: begin
+	    if (forward_ack == 0)
+	      demux_state <= IDLE;
+	 end
+
+       endcase // case (demux_state)
+
+   //
+   // Compile forwarding statistics
+   // (This uses a lot of registers!)
+   //
+   genvar m;
+   reg [31:0] statistics [0:NUM_OUTPUTS-1];
+   
+   generate
+      for (m = 0; m < NUM_OUTPUTS; m = m + 1) begin: generate_stats
+	 always @(posedge clk)
+	   if (reset | clear) 
+	     statistics[m] <= 0;
+	   else if ((rb_addr == m) && rb_rd_stb)
+	     statistics[m] <= 0;
+	   else if (forward_ack[m] & forward_valid[m])
+	     statistics[m] <= statistics[m] + 1;
+         end
+      endgenerate
+   
+   assign rb_data = statistics[rb_addr];
+   	
+	  
+endmodule
+    
+	      
+	    
+   
+   
diff --git a/fpga/usrp3/lib/control/axi_slave_mux.v b/fpga/usrp3/lib/control/axi_slave_mux.v
new file mode 100644
index 000000000..1a307aba5
--- /dev/null
+++ b/fpga/usrp3/lib/control/axi_slave_mux.v
@@ -0,0 +1,122 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+
+
+   
+
+`define LOG2(N) (\
+                 N < 2 ? 0 : \
+                 N < 4 ? 1 : \
+                 N < 8 ? 2 : \
+                 N < 16 ? 3 : \
+                 N < 32 ? 4 : \
+                 N < 64 ? 5 : \
+		 N < 128 ? 6 : \
+		 N < 256 ? 7 : \
+		 N < 512 ? 8 : \
+		 N < 1024 ? 9 : \
+                 10)
+
+
+module axi_slave_mux
+  #(
+    parameter FIFO_WIDTH = 64, // AXI4-STREAM data bus width
+    parameter DST_WIDTH = 16,  // Width of DST field we are routing on.
+    parameter NUM_INPUTS = 2   // number of input AXI buses
+    )
+    (
+     input 				 clk,
+     input 				 reset,
+     input 				 clear,
+     // Inputs
+     input [(FIFO_WIDTH*NUM_INPUTS)-1:0] i_tdata,
+     input [NUM_INPUTS-1:0] 		 i_tvalid,
+     input [NUM_INPUTS-1:0] 		 i_tlast,
+     output [NUM_INPUTS-1:0] 		 i_tready,
+     // Forwarding Flags
+     input [NUM_INPUTS-1:0] 		 forward_valid,
+     output reg [NUM_INPUTS-1:0] 	 forward_ack,
+     // Output
+     output [FIFO_WIDTH-1:0] 		 o_tdata,
+     output 				 o_tvalid,
+     output 				 o_tlast,
+     input 				 o_tready
+     );
+
+   wire [FIFO_WIDTH-1:0] i_tdata_array [0:NUM_INPUTS-1];
+   
+   reg [`LOG2(NUM_INPUTS):0] select;
+   reg 			     enable;
+
+
+   reg 			     state;
+
+   localparam CHECK_THIS_INPUT = 0;
+   localparam WAIT_LAST = 1;
+   
+
+   always @(posedge clk)
+     if (reset | clear) begin
+	state <= CHECK_THIS_INPUT;
+	select <= 0;
+	enable <= 0;
+	forward_ack <= 0;	
+     end else begin
+	case(state)
+	  // Is the currently selected input addressing this slave with a ready packet?
+	  CHECK_THIS_INPUT:  begin
+	     if (forward_valid[select]) begin
+		enable <= 1;
+		forward_ack[select] <= 1;
+		state <= WAIT_LAST;
+	     end else if (select == NUM_INPUTS - 1 ) begin
+		select <= 0;
+	     end else begin
+		select <= select + 1;
+	     end
+	  end
+	  // Assert ACK immediately to forwarding logic and then wait for end of packet.
+	  WAIT_LAST: begin
+	    
+	     if (i_tlast[select] && i_tvalid[select] && o_tready) begin
+		if (select == NUM_INPUTS - 1 ) begin
+		   select <= 0;
+		end else begin
+		   select <= select + 1;
+		end
+		state <= CHECK_THIS_INPUT;
+		forward_ack <= 0;
+		enable <= 0;
+	     end else begin
+		forward_ack[select] <= 1;
+		enable <= 1;
+	     end
+	  end
+	endcase // case(state)
+     end
+	
+   //
+   // Combinatorial mux
+   //
+   genvar m;
+     
+   generate
+      for (m = 0; m < NUM_INPUTS; m = m + 1) begin: form_buses
+	 assign i_tdata_array[m] = i_tdata[(m*FIFO_WIDTH)+FIFO_WIDTH-1:m*FIFO_WIDTH];
+      end
+   endgenerate
+
+   assign 	o_tdata = i_tdata_array[select];
+   assign 	o_tvalid = enable && i_tvalid[select];
+   assign 	o_tlast = enable && i_tlast[select];
+ //  assign 	i_tready = {NUM_INPUTS{o_tready}} & (enable << select);
+
+   generate
+      for (m = 0; m < NUM_INPUTS; m = m + 1) begin: form_ready
+	 assign i_tready[m] = o_tready && enable && (select == m);
+      end
+   endgenerate
+
+    
+endmodule // axi_slave_mux
diff --git a/fpga/usrp3/lib/control/axi_test_vfifo.v b/fpga/usrp3/lib/control/axi_test_vfifo.v
new file mode 100644
index 000000000..a436e9c55
--- /dev/null
+++ b/fpga/usrp3/lib/control/axi_test_vfifo.v
@@ -0,0 +1,139 @@
+//
+// Test Virtual FIFO's by streaming modulo 2^32 counter (replicated in upper
+// and lower 32bits). Test result by tracking count on receive and using 
+// sticky flag for error indication.
+// Also provide signal from MSB of 32bit count to blink LED.
+//
+
+module axi_test_vfifo
+  #(parameter PACKET_SIZE = 128)
+   (
+    input aclk,
+    input aresetn,
+    input enable,
+    // AXI Stream Out
+    output reg out_axis_tvalid,
+    input out_axis_tready,
+    output [63 : 0] out_axis_tdata,
+    output reg [7 : 0] out_axis_tstrb,
+    output reg [7 : 0] out_axis_tkeep,
+    output reg out_axis_tlast,
+    output reg [0 : 0] out_axis_tid,
+    output reg [0 : 0] out_axis_tdest,
+    input vfifo_full,
+    // AXI Stream In
+    input in_axis_tvalid,
+    output reg in_axis_tready,
+    input [63 : 0] in_axis_tdata,
+    input [7 : 0] in_axis_tstrb,
+    input [7 : 0] in_axis_tkeep,
+    input in_axis_tlast,
+    input [0 : 0] in_axis_tid,
+    input [0 : 0] in_axis_tdest,
+    // Flags
+    output reg flag_error,
+    output heartbeat_in,
+    output heartbeat_out,
+    output [31:0] expected_count
+    );
+   
+
+   reg [31:0] 	  out_count;
+   reg [31:0] 	  in_count;
+   reg [63:0] 	  in_axis_tdata_reg;
+   reg 		  in_data_valid;
+   
+
+
+   //
+   // Output 
+   //
+   always @(posedge aclk)
+     if (!aresetn) begin
+	out_count <= 0;
+	out_axis_tvalid <= 0;
+	out_axis_tid <= 0; // Don't care.
+	out_axis_tdest <= 0; // Only use port 0 of VFIFO.
+	out_axis_tstrb <= 0;  // Unused in VFIFO
+	out_axis_tkeep <= 8'hFF; // Always use every byte of data
+	out_axis_tlast <= 1'b0;
+     end else if (enable) begin
+	if (~vfifo_full) begin
+	   // Always ready to output new count value.
+	   out_axis_tvalid <= 1;
+	   if (out_axis_tready) 
+	     out_count <= out_count + 1;
+	   // Assert TLAST every PACKET_SIZE beats.
+	   if (out_count[15:0] == PACKET_SIZE)
+	     out_axis_tlast <= 1'b1;
+	   else
+	     out_axis_tlast <= 1'b0;
+	end else begin
+	   out_axis_tvalid <= 0;
+	end
+     end else begin
+	out_axis_tlast <= 1'b0;	
+	out_axis_tvalid <= 0;
+     end
+
+   assign out_axis_tdata = {out_count,out_count};
+
+   assign heartbeat_out = out_count[28];
+   
+
+   //
+   // Input (Ignore TLAST signal)
+   //
+   always @(posedge aclk)
+     if (!aresetn) begin
+	in_axis_tready <= 0;
+	in_axis_tdata_reg <= 0;
+	in_data_valid <= 0;
+	
+     end else if (enable) begin
+	in_axis_tready <= 1;
+	in_axis_tdata_reg <= in_axis_tdata;
+	if (in_axis_tvalid) 
+	  in_data_valid <= 1;
+	else
+	  in_data_valid <= 0;
+     end else begin
+	in_data_valid <= 0;
+	in_axis_tready <= 0;
+     end // else: !if(enable)
+   
+   	  
+   assign heartbeat_in = in_count[28];
+   
+   //
+   // Input Checker
+   //
+   always @(posedge aclk)
+     if (!aresetn) begin
+	in_count <= 0;
+	flag_error <= 0;
+     end else if (enable) begin
+	if (in_data_valid) begin
+	   
+	   if ((in_axis_tdata_reg[63:32] != in_count) || (in_axis_tdata_reg[31:0] != in_count))
+	     begin
+		flag_error <= 1;
+		in_count <= in_axis_tdata_reg[63:32] + 1;
+	     end
+	   else
+	     begin
+		flag_error <= 0;
+		in_count <= in_count + 1;
+	     end
+	   
+	end
+     end
+
+   assign expected_count = in_count;
+   
+
+endmodule // axi_test_vfifo
+
+
+   
+   
diff --git a/fpga/usrp3/lib/control/cvita_uart.v b/fpga/usrp3/lib/control/cvita_uart.v
new file mode 100644
index 000000000..cbb272fc2
--- /dev/null
+++ b/fpga/usrp3/lib/control/cvita_uart.v
@@ -0,0 +1,164 @@
+
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+//create a compressed vita based uart data interface
+
+module cvita_uart
+#(
+    parameter SIZE = 0
+)
+(
+    //clocking interface
+    input clk, input rst,
+
+    //uart interface
+    input rxd, output txd,
+
+    //chdr fifo input
+    input [63:0] i_tdata,
+    input i_tlast,
+    input i_tvalid,
+    output i_tready,
+
+    //chdr fifo output
+    output [63:0] o_tdata,
+    output o_tlast,
+    output o_tvalid,
+    input o_tready
+);
+
+    reg [31:0] sid;
+
+    //baud clock divider
+    reg [15:0] clkdiv;
+
+    //hold rx in disable until a tx event
+    reg rxd_enable;
+
+    //==================================================================
+    //== RXD capture and packet generation interface
+    //==================================================================
+    wire [7:0] rx_char;
+    wire fifo_empty;
+    wire fifo_read;
+    reg [11:0] seqnum;
+    wire pgen_trigger;
+    wire pgen_done;
+
+    //rx uart capture
+    simple_uart_rx #(.SIZE(SIZE)) simple_uart_rx
+    (
+        .clk(clk), .rst(rst),
+        .fifo_out(rx_char), .fifo_read(fifo_read), .fifo_level(), .fifo_empty(fifo_empty),
+        .clkdiv(clkdiv), .rx(rxd)
+    );
+
+    //packet generation - holds rx character
+    context_packet_gen context_packet_gen
+    (
+        .clk(clk), .reset(rst), .clear(1'b0),
+        .trigger(pgen_trigger),
+        .seqnum(seqnum),
+        .sid({sid[15:0], sid[31:16]}),
+        .body({56'b0, rx_char}),
+        .vita_time(64'b0),
+
+        .done(pgen_done),
+        .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
+    );
+
+    //state machine to manage pgen and rx uart
+    reg [1:0] rxd_state;
+    localparam RXD_STATE_RECV_CHAR = 0;
+    localparam RXD_STATE_PGEN_TRIG = 1;
+    localparam RXD_STATE_WAIT_DONE = 2;
+    localparam RXD_STATE_READ_FIFO = 3;
+
+    always @(posedge clk) begin
+        if (rst) begin
+            seqnum <= 12'b0;
+            rxd_state <= RXD_STATE_RECV_CHAR;
+        end
+        else case (rxd_state)
+
+        RXD_STATE_RECV_CHAR: begin
+            if (!fifo_empty && rxd_enable) rxd_state <= RXD_STATE_PGEN_TRIG;
+        end
+
+        RXD_STATE_PGEN_TRIG: begin
+            rxd_state <= RXD_STATE_WAIT_DONE;
+        end
+
+        RXD_STATE_WAIT_DONE: begin
+            if (pgen_done) rxd_state <= RXD_STATE_READ_FIFO;
+        end
+
+        RXD_STATE_READ_FIFO: begin
+            rxd_state <= RXD_STATE_RECV_CHAR;
+            seqnum <= seqnum + 1'b1;
+        end
+
+        endcase //rxd_state
+    end
+
+    assign fifo_read = (rxd_state == RXD_STATE_READ_FIFO) || (!rxd_enable);
+    assign pgen_trigger = (rxd_state == RXD_STATE_PGEN_TRIG);
+
+    //==================================================================
+    //== TXD generation and packet control interface
+    //==================================================================
+    wire [7:0] tx_char;
+    wire fifo_write;
+    wire fifo_full;
+
+    simple_uart_tx #(.SIZE(SIZE)) simple_uart_tx
+    (
+        .clk(clk), .rst(rst),
+        .fifo_in(tx_char), .fifo_write(fifo_write), .fifo_level(), .fifo_full(fifo_full),
+        .clkdiv(clkdiv), .baudclk(), .tx(txd)
+    );
+
+    //state machine to manage control and tx uart
+    reg [1:0] txd_state;
+    localparam TXD_STATE_RECV_CHDR = 0;
+    localparam TXD_STATE_RECV_TIME = 1;
+    localparam TXD_STATE_RECV_BODY = 2;
+    localparam TXD_STATE_DROP_FIFO = 3;
+
+    always @(posedge clk) begin
+        if (rst) begin;
+            txd_state <= TXD_STATE_RECV_CHDR;
+            rxd_enable <= 1'b0;
+        end
+        if (i_tvalid && i_tready) case (txd_state)
+
+        TXD_STATE_RECV_CHDR: begin
+            txd_state <= (i_tdata[61])? TXD_STATE_RECV_TIME : TXD_STATE_RECV_BODY;
+            sid <= i_tdata[31:0];
+        end
+
+        TXD_STATE_RECV_TIME: begin
+            txd_state <= TXD_STATE_RECV_BODY;
+        end
+
+        TXD_STATE_RECV_BODY: begin
+            txd_state <= (i_tlast)? TXD_STATE_RECV_CHDR : TXD_STATE_DROP_FIFO;
+            clkdiv <= i_tdata[47:32];
+            rxd_enable <= 1'b1;
+        end
+
+        TXD_STATE_DROP_FIFO: begin
+            if (i_tlast) txd_state <= TXD_STATE_RECV_CHDR;
+        end
+
+        endcase //txd_state
+    end
+
+    assign tx_char = i_tdata[7:0];
+    assign fifo_write = (txd_state == TXD_STATE_RECV_BODY) && i_tvalid && i_tready;
+    assign i_tready = !fifo_full;
+
+endmodule // cvita_uart
diff --git a/fpga/usrp3/lib/control/dram_2port.v b/fpga/usrp3/lib/control/dram_2port.v
new file mode 100644
index 000000000..186af44e7
--- /dev/null
+++ b/fpga/usrp3/lib/control/dram_2port.v
@@ -0,0 +1,27 @@
+////////////////////////////////////////////////////////////////////////
+// Copyright Ettus Research LLC
+////////////////////////////////////////////////////////////////////////
+
+module dram_2port
+  #(parameter DWIDTH=32,
+    parameter AWIDTH=9)
+    (input clk,
+     input write,
+     input [AWIDTH-1:0] raddr,
+     input [AWIDTH-1:0] waddr,
+     input [DWIDTH-1:0] wdata,
+     output [DWIDTH-1:0] rdata);
+
+    reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
+   integer 	    i;
+   initial
+     for(i=0;i<(1<<AWIDTH);i=i+1)
+       ram[i] <= {DWIDTH{1'b0}};
+
+    assign rdata = ram[raddr];
+
+    always @(posedge clk) begin
+        if (write) ram[waddr] <= wdata;
+    end
+
+endmodule //dram_2port
diff --git a/fpga/usrp3/lib/control/gpio_atr.v b/fpga/usrp3/lib/control/gpio_atr.v
new file mode 100644
index 000000000..9c707e52a
--- /dev/null
+++ b/fpga/usrp3/lib/control/gpio_atr.v
@@ -0,0 +1,64 @@
+
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+module gpio_atr
+  #(parameter BASE = 0,
+    parameter WIDTH = 32)
+   (input clk, input reset,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input rx, input tx,
+    inout [WIDTH-1:0] gpio,
+    output reg [31:0] gpio_readback
+    );
+   
+   wire [WIDTH-1:0]   ddr, in_idle, in_tx, in_rx, in_fdx;
+   reg [WIDTH-1:0]    rgpio, igpio;
+   reg [WIDTH-1:0]    gpio_pipe;
+   
+   
+   setting_reg #(.my_addr(BASE+0), .width(WIDTH)) reg_idle
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+      .out(in_idle),.changed());
+
+   setting_reg #(.my_addr(BASE+1), .width(WIDTH)) reg_rx
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+      .out(in_rx),.changed());
+
+   setting_reg #(.my_addr(BASE+2), .width(WIDTH)) reg_tx
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+      .out(in_tx),.changed());
+
+   setting_reg #(.my_addr(BASE+3), .width(WIDTH)) reg_fdx
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+      .out(in_fdx),.changed());
+
+   setting_reg #(.my_addr(BASE+4), .width(WIDTH)) reg_ddr
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+      .out(ddr),.changed());
+
+   always @(posedge clk)
+     case({tx,rx})
+       2'b00: rgpio <= in_idle;
+       2'b01: rgpio <= in_rx;
+       2'b10: rgpio <= in_tx;
+       2'b11: rgpio <= in_fdx;
+     endcase // case ({tx,rx})
+   
+   integer 	      n;
+   always @*
+     for(n=0;n<WIDTH;n=n+1)
+       igpio[n] <= ddr[n] ? rgpio[n] : 1'bz;
+
+   assign     gpio = igpio;
+
+   // Double pipeline stage for timing, first flop is in IOB, second in core logic.
+   always @(posedge clk) begin
+      gpio_pipe <= gpio;
+      gpio_readback <= gpio_pipe;
+   end
+   
+endmodule // gpio_atr
diff --git a/fpga/usrp3/lib/control/por_gen.v b/fpga/usrp3/lib/control/por_gen.v
new file mode 100644
index 000000000..0e4fcd88a
--- /dev/null
+++ b/fpga/usrp3/lib/control/por_gen.v
@@ -0,0 +1,25 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+
+module por_gen
+  (input clk,
+   output reset_out);
+
+   reg 		por_rst;
+   reg [7:0] 	por_counter = 8'h0;
+
+   always @(posedge clk)
+     if (por_counter != 8'h55)
+       begin
+          por_counter <= por_counter + 8'h1;
+          por_rst <= 1'b1;
+       end
+     else
+       por_rst <= 1'b0;
+
+   assign reset_out = por_rst;
+
+endmodule // por_gen
diff --git a/fpga/usrp3/lib/control/radio_ctrl_proc.v b/fpga/usrp3/lib/control/radio_ctrl_proc.v
new file mode 100644
index 000000000..723ba69ff
--- /dev/null
+++ b/fpga/usrp3/lib/control/radio_ctrl_proc.v
@@ -0,0 +1,143 @@
+
+
+// Radio Control Processor
+//  Accepts compressed vita extension context packets of the following form:
+//       { VITA Compressed Header, Stream ID }
+//       { Optional 64 bit time }
+//       { 16'h0, setting bus address [15:0], setting [31:0] }
+//  
+//  If there is a timestamp, packet is held until that time comes.
+//  Goes immediately if there is no timestamp or if time has passed.
+//  Sends out setting to setting bus, and then generates a response packet
+//  with the same sequence number, the src/dest swapped streamid, and the actual time
+//  the setting was sent.
+//
+// Note -- if t0 is the requested time, the actual send time on the setting bus is t0 + 1 cycle.
+// Note 2 -- if t1 is the actual time the setting bus, t1+2 is the reported time.
+
+module radio_ctrl_proc
+  (input clk, input reset, input clear,
+   
+   input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output reg ctrl_tready,
+   output reg [63:0] resp_tdata, output reg resp_tlast, output resp_tvalid, input resp_tready,
+   
+   input [63:0] vita_time,
+
+   output set_stb, output [7:0] set_addr, output [31:0] set_data,
+   input ready,
+   
+   input [63:0] readback,
+   
+   output [31:0] debug);
+
+   localparam RC_HEAD   = 4'd0;
+   localparam RC_TIME   = 4'd1;
+   localparam RC_DATA   = 4'd2;
+   localparam RC_DUMP   = 4'd3;
+   localparam RC_RESP_HEAD = 4'd4;
+   localparam RC_RESP_TIME = 4'd5;
+   localparam RC_RESP_DATA = 4'd6;
+   
+   wire 	 IS_EC = ctrl_tdata[63];
+   wire 	 HAS_TIME = ctrl_tdata[61];
+   reg 		 HAS_TIME_reg;
+   
+   reg [3:0] 	 rc_state;
+   reg [63:0] 	 cmd_time;
+
+   wire 	 now, late, go;
+   reg [11:0] 	 seqnum;
+   reg [31:0] 	 sid;
+   
+   always @(posedge clk)
+     if(reset)
+       begin
+	  rc_state <= RC_HEAD;
+	  HAS_TIME_reg <= 1'b0;
+	  sid <= 32'd0;
+	  seqnum <= 12'd0;
+       end
+     else
+	 case(rc_state)
+	   RC_HEAD :
+	     if(ctrl_tvalid)
+	       begin
+		  sid <= ctrl_tdata[31:0];
+		  seqnum <= ctrl_tdata[59:48];
+		  HAS_TIME_reg <= HAS_TIME;
+		  if(IS_EC)
+		    if(HAS_TIME)
+		      rc_state <= RC_TIME;
+		    else
+		      rc_state <= RC_DATA;
+		  else
+		    if(~ctrl_tlast)
+		      rc_state <= RC_DUMP;
+	       end
+	   
+	   RC_TIME :
+	     if(ctrl_tvalid)
+	       if(ctrl_tlast)
+		 rc_state <= RC_RESP_HEAD;
+	       else if(go)
+		 rc_state <= RC_DATA;
+	   
+	   RC_DATA :
+	     if(ctrl_tvalid)
+	       if(ready)
+		 if(ctrl_tlast)
+		   rc_state <= RC_RESP_HEAD;
+		 else
+		   rc_state <= RC_DUMP;
+
+	   RC_DUMP :
+	     if(ctrl_tvalid)
+	       if(ctrl_tlast)
+		 rc_state <= RC_RESP_HEAD;
+
+	   RC_RESP_HEAD :
+	     if(resp_tready)
+	       rc_state <= RC_RESP_TIME;
+
+	   RC_RESP_TIME :
+	     if(resp_tready)
+	       rc_state <= RC_RESP_DATA;
+
+	   RC_RESP_DATA:
+	     if(resp_tready)
+	       rc_state <= RC_HEAD;
+	   
+	   default :
+	     rc_state <= RC_HEAD;
+	 endcase // case (rc_state)
+
+   always @*
+     case (rc_state)
+       RC_HEAD : ctrl_tready <= 1'b1;
+       RC_TIME : ctrl_tready <= ctrl_tlast | go;
+       RC_DATA : ctrl_tready <= ready;
+       RC_DUMP : ctrl_tready <= 1'b1;
+       default : ctrl_tready <= 1'b0;
+     endcase // case (rc_state)
+      
+   time_compare time_compare
+     (.clk(clk), .reset(reset), .time_now(vita_time), .trigger_time(ctrl_tdata), .now(now), .early(), .late(late), .too_early());
+
+   assign go = now | late;
+   
+   assign set_stb = (rc_state == RC_DATA) & ready & ctrl_tvalid;
+   assign set_addr = ctrl_tdata[39:32];
+   assign set_data = ctrl_tdata[31:0];
+
+   always @*
+     case (rc_state)
+       RC_RESP_HEAD : { resp_tlast, resp_tdata } <= {1'b0, 4'hA, seqnum, 16'd24, sid[15:0], sid[31:16] };
+       RC_RESP_TIME : { resp_tlast, resp_tdata } <= {1'b0, vita_time};
+       RC_RESP_DATA : { resp_tlast, resp_tdata } <= {1'b1, readback};
+       default : { resp_tlast, resp_tdata } <= 65'h0;
+     endcase // case (rc_state)
+   
+   assign resp_tvalid = (rc_state == RC_RESP_HEAD) | (rc_state == RC_RESP_TIME) | (rc_state == RC_RESP_DATA);
+   
+endmodule // radio_ctrl_proc
+
diff --git a/fpga/usrp3/lib/control/radio_ctrl_proc_tb.v b/fpga/usrp3/lib/control/radio_ctrl_proc_tb.v
new file mode 100644
index 000000000..da863f4ea
--- /dev/null
+++ b/fpga/usrp3/lib/control/radio_ctrl_proc_tb.v
@@ -0,0 +1,104 @@
+`timescale 1ns/1ps
+
+module radio_ctrl_proc_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("radio_ctrl_proc_tb.vcd");
+   initial $dumpvars(0,radio_ctrl_proc_tb);
+
+   initial
+     begin
+	#1000 reset = 0;
+	#20000;
+	$finish;
+     end
+   
+   reg [63:0] vita_time = 64'd0;
+   always @(posedge clk)
+     if(reset) vita_time <= 64'd0;
+     else vita_time <= vita_time + 64'd1;
+
+   reg [63:0]  tdata;
+   wire [63:0] tdata_int;
+   reg 	       tlast;
+   wire        tlast_int;
+   reg 	       tvalid = 1'b0;
+   wire        tvalid_int;
+   wire        tready, tready_int;
+   
+   wire [7:0]  set_addr;
+   wire [31:0] set_data;
+   wire        set_stb;
+   wire        ready = 1'b1;
+
+   task send_packet;
+      input ec;
+      input timed;
+      input [11:0] seqnum;
+      input [31:0] sid;
+      input [63:0] vtime;
+      input [15:0] addr;
+      input [31:0] data;
+      
+      begin
+	 // Send a packet
+	 @(posedge clk);
+	 tlast <= 1'b0;
+	 tdata <= { ec, 1'b0, timed, 1'b0, seqnum, timed ? 16'd6 : 16'd4, sid };
+	 tvalid <= 1;
+	 @(posedge clk);
+	 if(timed)
+	   begin
+	      tdata <= vtime;
+	      @(posedge clk);
+	   end
+	 tlast <= 1'b1;
+	 tdata <= { 16'h0, addr, data };
+	 @(posedge clk);
+	 tvalid <= 0;	 
+	 @(posedge clk);
+      end
+   endtask // send_packet
+   
+   initial
+     begin
+	tvalid <= 1'b0;
+	while(reset)
+	  @(posedge clk);
+	send_packet(1'b1,1'b0,12'h5,32'hDEAD_BEEF,64'h0,16'hB,32'hF00D_1234);
+	send_packet(1'b1,1'b1,12'h6,32'hDEAD_6789,64'h20,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h7,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	//send_packet(.ec(1), .timed(0), .seqnum(5), .sid(32'hDEAD_BEEF), .vtime(0), .addr(16'hB), .data(32'hF00D_1234));
+     end
+
+   axi_fifo_short #(.WIDTH(65)) axi_fifo_short
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({tlast,tdata}), .i_tvalid(tvalid), .i_tready(tready),
+      .o_tdata({tlast_int,tdata_int}), .o_tvalid(tvalid_int), .o_tready(tready_int));
+
+   wire [63:0] resp_tdata;
+   wire        resp_tlast, resp_tvalid, resp_tready;
+   
+   radio_ctrl_proc radio_ctrl_proc
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .ctrl_tdata(tdata_int), .ctrl_tlast(tlast_int), .ctrl_tvalid(tvalid_int), .ctrl_tready(tready_int),
+      .resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready),
+      .vita_time(vita_time), .ready(ready),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .debug()
+      );
+
+   assign resp_tready = 1'b1;
+   
+   always @(posedge clk)
+     if(resp_tvalid & resp_tready)
+       begin
+	  $display("%x",resp_tdata);
+	  if(resp_tlast)
+	    $display("TLAST");
+       end
+endmodule // radio_ctrl_proc_tb
diff --git a/fpga/usrp3/lib/control/ram_2port.v b/fpga/usrp3/lib/control/ram_2port.v
new file mode 100644
index 000000000..434af0ff3
--- /dev/null
+++ b/fpga/usrp3/lib/control/ram_2port.v
@@ -0,0 +1,49 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+
+module ram_2port
+  #(parameter DWIDTH=32,
+    parameter AWIDTH=9)
+    (input clka,
+     input ena,
+     input wea,
+     input [AWIDTH-1:0] addra,
+     input [DWIDTH-1:0] dia,
+     output reg [DWIDTH-1:0] doa,
+     
+     input clkb,
+     input enb,
+     input web,
+     input [AWIDTH-1:0] addrb,
+     input [DWIDTH-1:0] dib,
+     output reg [DWIDTH-1:0] dob);
+   
+   reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
+   /*
+   integer 	    i;
+   initial
+     for(i=0;i<(1<<AWIDTH);i=i+1)
+       ram[i] <= {DWIDTH{1'b0}};
+       */
+   
+   always @(posedge clka) begin
+      if (ena)
+        begin
+           if (wea)
+             ram[addra] <= dia;
+           doa <= ram[addra];
+        end
+   end
+   always @(posedge clkb) begin
+      if (enb)
+        begin
+           if (web)
+             ram[addrb] <= dib;
+           dob <= ram[addrb];
+        end
+   end
+endmodule // ram_2port
diff --git a/fpga/usrp3/lib/control/reset_sync.v b/fpga/usrp3/lib/control/reset_sync.v
new file mode 100644
index 000000000..da284e62e
--- /dev/null
+++ b/fpga/usrp3/lib/control/reset_sync.v
@@ -0,0 +1,28 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+
+module reset_sync
+  (input clk,
+   input reset_in,
+   output  reset_out);
+
+   reg 	   reset_int;
+
+   reg 	   reset_out_tmp;
+
+   //synthesis attribute async_reg of reset_out_tmp is "true";
+   //synthesis attribute async_reg of reset_int is "true";
+   always @(posedge clk or posedge reset_in)
+     if(reset_in)
+       {reset_out_tmp,reset_int} <= 2'b11;
+     else
+       {reset_out_tmp,reset_int} <= {reset_int,1'b0};
+
+   assign reset_out = reset_out_tmp;
+
+
+endmodule // reset_sync
diff --git a/fpga/usrp3/lib/control/setting_reg.v b/fpga/usrp3/lib/control/setting_reg.v
new file mode 100644
index 000000000..1664f54e2
--- /dev/null
+++ b/fpga/usrp3/lib/control/setting_reg.v
@@ -0,0 +1,35 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+
+
+//----------------------------------------------------------------------
+//-- A settings register is a peripheral for the settings register bus.
+//-- When the settings register sees strobe abd a matching address,
+//-- the outputs will be become registered to the given input bus.
+//----------------------------------------------------------------------
+
+module setting_reg
+  #(parameter my_addr = 0, 
+    parameter awidth = 8,
+    parameter width = 32,
+    parameter at_reset=0)
+    (input clk, input rst, input strobe, input wire [awidth-1:0] addr,
+     input wire [31:0] in, output reg [width-1:0] out, output reg changed);
+   
+   always @(posedge clk)
+     if(rst)
+       begin
+	  out <= at_reset;
+	  changed <= 1'b0;
+       end
+     else
+       if(strobe & (my_addr==addr))
+	 begin
+	    out <= in[width-1:0];
+	    changed <= 1'b1;
+	 end
+       else
+	 changed <= 1'b0;
+   
+endmodule // setting_reg
diff --git a/fpga/usrp3/lib/control/settings_bus_crossclock.v b/fpga/usrp3/lib/control/settings_bus_crossclock.v
new file mode 100644
index 000000000..2a6e7e7ef
--- /dev/null
+++ b/fpga/usrp3/lib/control/settings_bus_crossclock.v
@@ -0,0 +1,26 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+
+
+
+
+// This module takes the settings bus on one clock domain and crosses it over to another domain
+// Typically it will be used with the input settings bus on the wishbone clock, and either 
+// the system or dsp clock on the output side
+
+module settings_bus_crossclock
+  #(parameter FLOW_CTRL=0, parameter AWIDTH=8, parameter DWIDTH=32)
+  (input clk_i, input rst_i, input set_stb_i, input [AWIDTH-1:0] set_addr_i, input [DWIDTH-1:0] set_data_i,
+   input clk_o, input rst_o, output set_stb_o, output [AWIDTH-1:0] set_addr_o, output [DWIDTH-1:0] set_data_o, input blocked);
+
+   wire  nfull, nempty;
+   
+   axi_fifo_2clk #(.WIDTH(AWIDTH + DWIDTH), .SIZE(0)) settings_fifo
+     (.reset(rst_i),
+      .i_aclk(clk_i), .i_tdata({set_addr_i,set_data_i}), .i_tvalid(set_stb_i), .i_tready(nfull),
+      .o_aclk(clk_o), .o_tdata({set_addr_o,set_data_o}), .o_tready(set_stb_o), .o_tvalid(nempty));
+
+   assign set_stb_o = nempty & (~blocked | ~FLOW_CTRL);
+
+endmodule // settings_bus_crossclock
diff --git a/fpga/usrp3/lib/control/simple_i2c_core.v b/fpga/usrp3/lib/control/simple_i2c_core.v
new file mode 100644
index 000000000..47f1ac82a
--- /dev/null
+++ b/fpga/usrp3/lib/control/simple_i2c_core.v
@@ -0,0 +1,104 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+
+
+// Simple I2C core
+
+// Settings reg map:
+//
+// BASE+0 control register
+//   byte0 - control bits, data byte, or command bits, prescaler
+//   byte1 - what to do? (documented in cpp file)
+//      write prescaler lo
+//      write prescaler hi
+//      write control
+//      write data
+//      write command
+//      read data
+//      read status
+//
+
+// Readback:
+//
+// byte0 has readback value based on the last read command
+//
+
+module simple_i2c_core
+    #(
+        //settings register base address
+        parameter BASE = 0,
+
+        //i2c line level at reset
+        parameter ARST_LVL = 1
+    )
+    (
+        //clock and synchronous reset
+        input clock, input reset,
+
+        //32-bit settings bus inputs
+        input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+        //32-bit data readback
+        output reg [31:0] readback,
+
+        //read is high when i2c core can begin another transaction
+        output reg ready,
+
+        // I2C signals
+        // i2c clock line
+        input  scl_pad_i,       // SCL-line input
+        output scl_pad_o,       // SCL-line output (always 1'b0)
+        output scl_padoen_o,    // SCL-line output enable (active low)
+
+        // i2c data line
+        input  sda_pad_i,       // SDA-line input
+        output sda_pad_o,       // SDA-line output (always 1'b0)
+        output sda_padoen_o,    // SDA-line output enable (active low)
+
+        //optional debug output
+        output [31:0] debug
+    );
+
+    //declare command settings register
+    wire [7:0] sr_what, sr_data;
+    wire sr_changed;
+    setting_reg #(.my_addr(BASE+0),.width(16)) i2c_cmd_sr(
+        .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out({sr_what, sr_data}),.changed(sr_changed));
+
+    //declare wb interface signals
+    wire [2:0] wb_addr;
+    wire [7:0] wb_data_mosi;
+    wire [7:0] wb_data_miso;
+    wire wb_we, wb_stb, wb_cyc;
+    wire wb_ack;
+
+    //create wishbone-based i2c core
+    i2c_master_top #(.ARST_LVL(ARST_LVL)) i2c 
+     (.wb_clk_i(clock),.wb_rst_i(reset),.arst_i(1'b0), 
+      .wb_adr_i(wb_addr),.wb_dat_i(wb_data_mosi),.wb_dat_o(wb_data_miso),
+      .wb_we_i(wb_we),.wb_stb_i(wb_stb),.wb_cyc_i(wb_cyc),
+      .wb_ack_o(wb_ack),.wb_inta_o(),
+      .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_padoen_o),
+      .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_padoen_o) );
+
+    //not ready between setting register and wishbone ack
+    always @(posedge clock) begin
+        if (reset || wb_ack) ready <= 1;
+        else if (sr_changed) ready <= 0;
+    end
+
+    //register wishbone data on every ack
+    always @(posedge clock) begin
+        if (wb_ack) readback <= {24'b0, wb_data_miso};
+    end
+
+    //assign wishbone signals
+    assign wb_addr = sr_what[2:0];
+    assign wb_stb = sr_changed;
+    assign wb_we = wb_stb && sr_what[3];
+    assign wb_cyc = wb_stb;
+    assign wb_data_mosi = sr_data;
+
+endmodule //simple_i2c_core
diff --git a/fpga/usrp3/lib/control/simple_spi_core.v b/fpga/usrp3/lib/control/simple_spi_core.v
new file mode 100644
index 000000000..a18e00709
--- /dev/null
+++ b/fpga/usrp3/lib/control/simple_spi_core.v
@@ -0,0 +1,207 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+
+
+// Simple SPI core, the simplest, yet complete spi core I can think of
+
+// Settings register controlled.
+// 2 settings regs, control and data
+// 1 32-bit readback and status signal
+
+// Settings reg map:
+//
+// BASE+0 divider setting
+// bits [15:0] spi clock divider
+//
+// BASE+1 configuration input
+// bits [23:0] slave select, bit0 = slave0 enabled
+// bits [29:24] num bits (1 through 32)
+// bit [30] data input edge = in data bit latched on rising edge of clock
+// bit [31] data output edge = out data bit latched on rising edge of clock
+//
+// BASE+2 input data
+// Writing this register begins a spi transaction.
+// Bits are latched out from bit 0.
+// Therefore, load this register in reverse.
+//
+// Readback
+// Bits are latched into bit 0.
+// Therefore, data will be in-order.
+
+module simple_spi_core
+    #(
+        //settings register base address
+        parameter BASE = 0,
+
+        //width of serial enables (up to 24 is possible)
+        parameter WIDTH = 8,
+
+        //idle state of the spi clock
+        parameter CLK_IDLE = 0,
+
+        //idle state of the serial enables
+        parameter SEN_IDLE = 24'hffffff
+    )
+    (
+        //clock and synchronous reset
+        input clock, input reset,
+
+        //32-bit settings bus inputs
+        input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+        //32-bit data readback
+        output [31:0] readback,
+
+        //read is high when spi core can begin another transaction
+        output ready,
+
+        //spi interface, slave selects, clock, data in, data out
+        output [WIDTH-1:0] sen,
+        output sclk,
+        output mosi,
+        input miso,
+
+        //optional debug output
+        output [31:0] debug
+    );
+
+    wire [15:0] sclk_divider;
+    setting_reg #(.my_addr(BASE+0),.width(16)) divider_sr(
+        .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(sclk_divider),.changed());
+
+    wire [23:0] slave_select;
+    wire [5:0] num_bits;
+    wire datain_edge, dataout_edge;
+    setting_reg #(.my_addr(BASE+1),.width(32)) config_sr(
+        .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out({dataout_edge, datain_edge, num_bits, slave_select}),.changed());
+
+    wire [31:0] mosi_data;
+    wire trigger_spi;
+    setting_reg #(.my_addr(BASE+2),.width(32)) data_sr(
+        .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(mosi_data),.changed(trigger_spi));
+
+    localparam WAIT_TRIG = 0;
+    localparam PRE_IDLE = 1;
+    localparam CLK_REG = 2;
+    localparam CLK_INV = 3;
+    localparam POST_IDLE = 4;
+    localparam IDLE_SEN = 5;
+
+    reg [2:0] state;
+
+    reg ready_reg;
+    assign ready = ready_reg && ~trigger_spi;
+
+    //serial clock either idles or is in one of two clock states
+    reg sclk_reg;
+    assign sclk = sclk_reg;
+
+    //serial enables either idle or enabled based on state
+    wire sen_is_idle = (state == WAIT_TRIG) || (state == IDLE_SEN);
+    wire [23:0] sen24 = (sen_is_idle)? SEN_IDLE : (SEN_IDLE ^ slave_select);
+    reg [WIDTH-1:0] sen_reg;
+    always @(posedge clock) sen_reg <= sen24[WIDTH-1:0];
+    assign sen = sen_reg;
+
+    //data output shift register
+    reg [31:0] dataout_reg;
+    wire [31:0] dataout_next = {dataout_reg[30:0], 1'b0};
+    assign mosi = dataout_reg[31];
+
+    //data input shift register
+   // IJB. One pipeline stage to break critical path from register in I/O pads.
+   reg 		miso_pipe;
+   always @(posedge clock)
+     miso_pipe = miso;
+   
+    reg [31:0] datain_reg;
+    wire [31:0] datain_next = {datain_reg[30:0], miso_pipe};
+    assign readback = datain_reg;
+
+    //counter for spi clock
+    reg [15:0] sclk_counter;
+    wire sclk_counter_done = (sclk_counter == sclk_divider);
+    wire [15:0] sclk_counter_next = (sclk_counter_done)? 0 : sclk_counter + 1;
+
+    //counter for latching bits miso/mosi
+    reg [6:0] bit_counter;
+    wire [6:0] bit_counter_next = bit_counter + 1;
+    wire bit_counter_done = (bit_counter_next == num_bits);
+
+    always @(posedge clock) begin
+        if (reset) begin
+            state <= WAIT_TRIG;
+            sclk_reg <= CLK_IDLE;
+            ready_reg <= 0;
+        end
+        else begin
+            case (state)
+
+            WAIT_TRIG: begin
+                if (trigger_spi) state <= PRE_IDLE;
+                ready_reg <= ~trigger_spi;
+                dataout_reg <= mosi_data;
+                sclk_counter <= 0;
+                bit_counter <= 0;
+                sclk_reg <= CLK_IDLE;
+            end
+
+            PRE_IDLE: begin
+                if (sclk_counter_done) state <= CLK_REG;
+                sclk_counter <= sclk_counter_next;
+                sclk_reg <= CLK_IDLE;
+            end
+
+            CLK_REG: begin
+                if (sclk_counter_done) begin
+                    state <= CLK_INV;
+                    if (datain_edge  != CLK_IDLE)                     datain_reg  <= datain_next;
+                    if (dataout_edge != CLK_IDLE && bit_counter != 0) dataout_reg <= dataout_next;
+                    sclk_reg <= ~CLK_IDLE; //transition to rising when CLK_IDLE == 0
+                end
+                sclk_counter <= sclk_counter_next;
+            end
+
+            CLK_INV: begin
+                if (sclk_counter_done) begin
+                    state <= (bit_counter_done)? POST_IDLE : CLK_REG;
+                    bit_counter <= bit_counter_next;
+                    if (datain_edge  == CLK_IDLE)                      datain_reg  <= datain_next;
+                    if (dataout_edge == CLK_IDLE && ~bit_counter_done) dataout_reg <= dataout_next;
+                    sclk_reg <= CLK_IDLE; //transition to falling when CLK_IDLE == 0
+                end
+                sclk_counter <= sclk_counter_next;
+            end
+
+            POST_IDLE: begin
+                if (sclk_counter_done) state <= IDLE_SEN;
+                sclk_counter <= sclk_counter_next;
+                sclk_reg <= CLK_IDLE;
+            end
+
+            IDLE_SEN: begin
+                if (sclk_counter_done) state <= WAIT_TRIG;
+                sclk_counter <= sclk_counter_next;
+                sclk_reg <= CLK_IDLE;
+            end
+
+            default: state <= WAIT_TRIG;
+
+            endcase //state
+        end
+    end
+
+    assign debug = {
+        trigger_spi, state, //4
+        sclk, mosi, miso, ready, //4
+        //sen[7:0], //8
+        1'b0, bit_counter[6:0], //8
+        sclk_counter_done, bit_counter_done, //2
+        sclk_counter[5:0] //6
+    };
+
+endmodule //simple_spi_core
diff --git a/fpga/usrp3/lib/dsp/Makefile.srcs b/fpga/usrp3/lib/dsp/Makefile.srcs
new file mode 100644
index 000000000..3896ac5b5
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/Makefile.srcs
@@ -0,0 +1,38 @@
+#
+# Copyright 2013 Ettus Research LLC
+#
+
+##################################################
+# DSP Sources
+##################################################
+DSP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/dsp/, \
+ddc_chain.v \
+duc_chain.v \
+sign_extend.v \
+cordic_z24.v \
+clip_reg.v \
+cordic_stage.v \
+clip.v \
+cic_strober.v \
+cic_decim.v \
+cic_interp.v \
+cic_dec_shifter.v \
+cic_int_shifter.v \
+small_hb_dec.v \
+small_hb_int.v \
+hb_dec.v \
+hb_interp.v \
+round_sd.v \
+add2_and_clip_reg.v \
+add2_and_clip.v \
+add2.v \
+add2_reg.v \
+add2_and_round_reg.v \
+add2_and_round.v \
+round_reg.v \
+round.v \
+srl.v \
+acc.v \
+rx_frontend.v \
+rx_dcoffset.v \
+))
diff --git a/fpga/usrp3/lib/dsp/README.txt b/fpga/usrp3/lib/dsp/README.txt
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/lib/dsp/acc.v b/fpga/usrp3/lib/dsp/acc.v
new file mode 100644
index 000000000..86b68512f
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/acc.v
@@ -0,0 +1,33 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+module acc
+  #(parameter IWIDTH=16, OWIDTH=30)
+    (input clk,
+     input clear,
+     input acc,
+     input [IWIDTH-1:0] in,
+     output reg [OWIDTH-1:0] out);
+
+   wire [OWIDTH-1:0] in_signext;
+   sign_extend #(.bits_in(IWIDTH),.bits_out(OWIDTH)) 
+     acc_signext (.in(in),.out(in_signext));
+   
+   //  CLEAR & ~ACC  -->  clears the accumulator
+   //  CLEAR & ACC -->    loads the accumulator
+   //  ~CLEAR & ACC -->   accumulates
+   //  ~CLEAR & ~ACC -->  hold
+   
+   wire [OWIDTH-1:0] addend1 = clear ? 0 : out;
+   wire [OWIDTH-1:0] addend2 = ~acc ? 0 : in_signext;
+   wire [OWIDTH-1:0] sum_int = addend1 + addend2;
+
+   always @(posedge clk)
+     out <= sum_int;
+   
+endmodule // acc
+
+
diff --git a/fpga/usrp3/lib/dsp/add2.v b/fpga/usrp3/lib/dsp/add2.v
new file mode 100644
index 000000000..124f9d6ca
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/add2.v
@@ -0,0 +1,16 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+module add2
+  #(parameter WIDTH=16)
+    (input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output [WIDTH-1:0] sum);
+
+   wire [WIDTH:0] 	sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
+   assign 		sum = sum_int[WIDTH:1];  // Note -- will have some bias
+   
+endmodule // add2
diff --git a/fpga/usrp3/lib/dsp/add2_and_clip.v b/fpga/usrp3/lib/dsp/add2_and_clip.v
new file mode 100644
index 000000000..663f5d004
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/add2_and_clip.v
@@ -0,0 +1,12 @@
+
+module add2_and_clip
+  #(parameter WIDTH=16)
+    (input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output [WIDTH-1:0] sum);
+
+   wire [WIDTH:0] 	sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
+   clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip
+     (.in(sum_int),.out(sum));
+   
+endmodule // add2_and_clip
diff --git a/fpga/usrp3/lib/dsp/add2_and_clip_reg.v b/fpga/usrp3/lib/dsp/add2_and_clip_reg.v
new file mode 100644
index 000000000..8073b3b54
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/add2_and_clip_reg.v
@@ -0,0 +1,25 @@
+
+module add2_and_clip_reg
+  #(parameter WIDTH=16)
+    (input clk,
+     input rst,
+     input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     input strobe_in,
+     output reg [WIDTH-1:0] sum,
+     output reg strobe_out);
+
+   wire [WIDTH-1:0] sum_int;
+   
+   add2_and_clip #(.WIDTH(WIDTH)) add2_and_clip (.in1(in1),.in2(in2),.sum(sum_int));
+
+   always @(posedge clk)
+     if(rst)
+       sum <= 0;
+     else if(strobe_in)
+       sum <= sum_int;
+
+   always @(posedge clk)
+     strobe_out <= strobe_in;
+   
+endmodule // add2_and_clip_reg
diff --git a/fpga/usrp3/lib/dsp/add2_and_round.v b/fpga/usrp3/lib/dsp/add2_and_round.v
new file mode 100644
index 000000000..9d0914414
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/add2_and_round.v
@@ -0,0 +1,16 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+module add2_and_round
+  #(parameter WIDTH=16)
+    (input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output [WIDTH-1:0] sum);
+
+   wire [WIDTH:0] 	sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
+   assign 		sum = sum_int[WIDTH:1] + (sum_int[WIDTH] & sum_int[0]);
+   
+endmodule // add2_and_round
diff --git a/fpga/usrp3/lib/dsp/add2_and_round_reg.v b/fpga/usrp3/lib/dsp/add2_and_round_reg.v
new file mode 100644
index 000000000..cb20a3c1b
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/add2_and_round_reg.v
@@ -0,0 +1,21 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+module add2_and_round_reg
+  #(parameter WIDTH=16)
+    (input clk,
+     input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output reg [WIDTH-1:0] sum);
+
+   wire [WIDTH-1:0] sum_int;
+   
+   add2_and_round #(.WIDTH(WIDTH)) add2_n_rnd (.in1(in1),.in2(in2),.sum(sum_int));
+
+   always @(posedge clk)
+     sum <= sum_int;
+   
+endmodule // add2_and_round_reg
diff --git a/fpga/usrp3/lib/dsp/add2_reg.v b/fpga/usrp3/lib/dsp/add2_reg.v
new file mode 100644
index 000000000..3ac93ae2e
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/add2_reg.v
@@ -0,0 +1,22 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+module add2_reg
+  #(parameter WIDTH=16)
+    (input clk,
+     input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output reg [WIDTH-1:0] sum);
+
+   wire [WIDTH-1:0] sum_int;
+   
+   add2 #(.WIDTH(WIDTH)) add2 (.in1(in1),.in2(in2),.sum(sum_int));
+
+   always @(posedge clk)
+     sum <= sum_int;
+   
+endmodule // add2_reg
+
diff --git a/fpga/usrp3/lib/dsp/cic_dec_shifter.v b/fpga/usrp3/lib/dsp/cic_dec_shifter.v
new file mode 100644
index 000000000..efc54c106
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/cic_dec_shifter.v
@@ -0,0 +1,94 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+
+//
+
+
+// NOTE   This only works for N=4, max decim rate of 128
+// NOTE   signal "rate" is EQUAL TO the actual rate, no more -1 BS
+
+module cic_dec_shifter(rate,signal_in,signal_out);
+   parameter bw = 16;
+   parameter maxbitgain = 28;
+
+   input [7:0] rate;
+   input       wire [bw+maxbitgain-1:0] signal_in;
+   output      reg [bw-1:0] signal_out;
+
+   function [4:0] bitgain;
+      input [7:0] rate;
+      case(rate)
+	// Exact Cases -- N*log2(rate)
+	8'd1 : bitgain = 0;
+	8'd2 : bitgain = 4;
+	8'd4 : bitgain = 8;
+	8'd8 : bitgain = 12;
+	8'd16 : bitgain = 16;
+	8'd32 : bitgain = 20;
+	8'd64 : bitgain = 24;
+	8'd128 : bitgain = 28;
+	
+	// Nearest without overflow -- ceil(N*log2(rate))
+	8'd3 : bitgain = 7;
+	8'd5 : bitgain = 10;
+	8'd6 : bitgain = 11;
+	8'd7 : bitgain = 12;
+	8'd9 : bitgain = 13;
+	8'd10,8'd11 : bitgain = 14;
+	8'd12,8'd13 : bitgain = 15;
+	8'd14,8'd15 : bitgain = 16;
+	8'd17,8'd18,8'd19 : bitgain = 17;
+	8'd20,8'd21,8'd22 : bitgain = 18;
+	8'd23,8'd24,8'd25,8'd26 : bitgain = 19;
+	8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20;
+	8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21;
+	8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22;
+	8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23;
+	8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24;
+	8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25;
+	8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26;
+	8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27;
+	default : bitgain = 28;
+      endcase // case(rate)
+   endfunction // bitgain
+   
+   wire [4:0] 	  shift = bitgain(rate);
+   
+   // We should be able to do this, but can't ....
+   // assign 	  signal_out = signal_in[shift+bw-1:shift];
+   
+   always @*
+     case(shift)
+       5'd0  : signal_out = signal_in[0+bw-1:0];
+       5'd4  : signal_out = signal_in[4+bw-1:4];
+       5'd7  : signal_out = signal_in[7+bw-1:7];
+       5'd8  : signal_out = signal_in[8+bw-1:8];
+       5'd10 : signal_out = signal_in[10+bw-1:10];
+       5'd11 : signal_out = signal_in[11+bw-1:11];
+       5'd12 : signal_out = signal_in[12+bw-1:12];
+       5'd13 : signal_out = signal_in[13+bw-1:13];
+       5'd14 : signal_out = signal_in[14+bw-1:14];
+       5'd15 : signal_out = signal_in[15+bw-1:15];
+       5'd16 : signal_out = signal_in[16+bw-1:16];
+       5'd17 : signal_out = signal_in[17+bw-1:17];
+       5'd18 : signal_out = signal_in[18+bw-1:18];
+       5'd19 : signal_out = signal_in[19+bw-1:19];
+       5'd20 : signal_out = signal_in[20+bw-1:20];
+       5'd21 : signal_out = signal_in[21+bw-1:21];
+       5'd22 : signal_out = signal_in[22+bw-1:22];
+       5'd23 : signal_out = signal_in[23+bw-1:23];
+       5'd24 : signal_out = signal_in[24+bw-1:24];
+       5'd25 : signal_out = signal_in[25+bw-1:25];
+       5'd26 : signal_out = signal_in[26+bw-1:26];
+       5'd27 : signal_out = signal_in[27+bw-1:27];
+       5'd28 : signal_out = signal_in[28+bw-1:28];
+       
+       default : signal_out = signal_in[28+bw-1:28];
+     endcase // case(shift)
+
+endmodule // cic_dec_shifter
+
diff --git a/fpga/usrp3/lib/dsp/cic_decim.v b/fpga/usrp3/lib/dsp/cic_decim.v
new file mode 100644
index 000000000..feb785de8
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/cic_decim.v
@@ -0,0 +1,76 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+
+//
+
+
+module cic_decim
+  #(parameter bw = 16, parameter N = 4, parameter log2_of_max_rate = 7)
+    (input clock,
+     input reset,
+     input enable,
+     input [7:0] rate,
+     input strobe_in,
+     input strobe_out,
+     input [bw-1:0] signal_in,
+     output reg [bw-1:0] signal_out);
+
+   localparam 	     maxbitgain = N * log2_of_max_rate;
+   
+   wire [bw+maxbitgain-1:0] signal_in_ext;
+   reg [bw+maxbitgain-1:0]  integrator [0:N-1];
+   reg [bw+maxbitgain-1:0]  differentiator [0:N-1];
+   reg [bw+maxbitgain-1:0]  pipeline [0:N-1];
+   reg [bw+maxbitgain-1:0]  sampler;
+   
+   integer 		    i;
+   
+   sign_extend #(bw,bw+maxbitgain) 
+     ext_input (.in(signal_in),.out(signal_in_ext));
+   
+   always @(posedge clock)
+     if(~enable)
+       for(i=0;i<N;i=i+1)
+	 integrator[i] <= 0;
+     else if (strobe_in)
+       begin
+	  integrator[0] <= integrator[0] + signal_in_ext;
+	  for(i=1;i<N;i=i+1)
+	    integrator[i] <= integrator[i] + integrator[i-1];
+       end	
+   
+   always @(posedge clock)
+     if(~enable)
+       begin
+	  sampler <= 0;
+	  for(i=0;i<N;i=i+1)
+	    begin
+	       pipeline[i] <= 0;
+	       differentiator[i] <= 0;
+	    end
+       end
+     else if (strobe_out)
+       begin
+	  sampler <= integrator[N-1];
+	  differentiator[0] <= sampler;
+	  pipeline[0] <= sampler - differentiator[0];
+	  for(i=1;i<N;i=i+1)
+	    begin
+	       differentiator[i] <= pipeline[i-1];
+	       pipeline[i] <= pipeline[i-1] - differentiator[i];
+	    end
+       end // if (enable && strobe_out)
+   
+   wire [bw-1:0] signal_out_unreg;
+   
+   cic_dec_shifter #(bw)
+     cic_dec_shifter(rate,pipeline[N-1],signal_out_unreg);
+
+   always @(posedge clock)
+     signal_out <= signal_out_unreg;
+   
+endmodule // cic_decim
diff --git a/fpga/usrp3/lib/dsp/cic_int_shifter.v b/fpga/usrp3/lib/dsp/cic_int_shifter.v
new file mode 100644
index 000000000..ff5a30d6a
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/cic_int_shifter.v
@@ -0,0 +1,88 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+
+//
+
+
+// NOTE   This only works for N=4, max interp rate of 128
+// NOTE   signal "rate" is EQUAL TO the actual rate (no more -1 BS)
+
+module cic_int_shifter(rate,signal_in,signal_out);
+   parameter bw = 16;
+   parameter maxbitgain = 21;
+   
+   input [7:0] rate;
+   input       wire [bw+maxbitgain-1:0] signal_in;
+   output      reg [bw-1:0] signal_out;
+
+   function [4:0] bitgain;
+      input [7:0] rate;
+      case(rate)
+	// Exact Cases
+	8'd1 : bitgain = 0;
+	8'd2 : bitgain = 3;
+	8'd4 : bitgain = 6;
+	8'd8 : bitgain = 9;
+	8'd16 : bitgain = 12;
+	8'd32 : bitgain = 15;
+	8'd64 : bitgain = 18;
+	8'd128 : bitgain = 21;
+	
+	// Nearest without overflow	
+	8'd3 : bitgain = 5;
+	8'd5 : bitgain = 7;
+	8'd6 : bitgain = 8;
+	8'd7 : bitgain = 9;
+	8'd9,8'd10 : bitgain = 10;
+	8'd11,8'd12 : bitgain = 11;
+	8'd13,8'd14,8'd15 : bitgain = 12;
+	8'd17,8'd18,8'd19,8'd20 : bitgain = 13;
+	8'd21,8'd22,8'd23,8'd24,8'd25 : bitgain = 14;
+	8'd26,8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 15;
+	8'd33,8'd34,8'd35,8'd36,8'd37,8'd38,8'd39,8'd40 : bitgain = 16;
+	8'd41,8'd42,8'd43,8'd44,8'd45,8'd46,8'd47,8'd48,8'd49,8'd50 : bitgain = 17;
+	8'd51,8'd52,8'd53,8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 18;
+	8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76,8'd77,8'd78,8'd79,8'd80 : bitgain = 19;
+	8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90,8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101 : bitgain = 20;
+	
+	default : bitgain = 21;
+      endcase // case(rate)
+   endfunction // bitgain
+   
+   wire [4:0] 	  shift = bitgain(rate);
+   
+   // We should be able to do this, but can't ....
+   // assign 	  signal_out = signal_in[shift+bw-1:shift];
+   
+   always @*
+     case(shift)
+       5'd0  : signal_out = signal_in[0+bw-1:0];
+       5'd3  : signal_out = signal_in[3+bw-1:3];
+       5'd6  : signal_out = signal_in[6+bw-1:6];
+       5'd9  : signal_out = signal_in[9+bw-1:9];
+       5'd12 : signal_out = signal_in[12+bw-1:12];
+       5'd15 : signal_out = signal_in[15+bw-1:15];
+       5'd18 : signal_out = signal_in[18+bw-1:18];
+       5'd21 : signal_out = signal_in[21+bw-1:21];
+       
+       5'd5  : signal_out = signal_in[5+bw-1:5];
+       5'd7  : signal_out = signal_in[7+bw-1:7];
+       5'd8  : signal_out = signal_in[8+bw-1:8];
+       5'd10 : signal_out = signal_in[10+bw-1:10];
+       5'd11 : signal_out = signal_in[11+bw-1:11];
+       5'd13 : signal_out = signal_in[13+bw-1:13];
+       5'd14 : signal_out = signal_in[14+bw-1:14];
+       5'd16 : signal_out = signal_in[16+bw-1:16];
+       5'd17 : signal_out = signal_in[17+bw-1:17];
+       5'd19 : signal_out = signal_in[19+bw-1:19];
+       5'd20 : signal_out = signal_in[20+bw-1:20];
+       
+       default : signal_out = signal_in[21+bw-1:21];
+     endcase // case(shift)
+
+endmodule // cic_int_shifter
+
diff --git a/fpga/usrp3/lib/dsp/cic_interp.v b/fpga/usrp3/lib/dsp/cic_interp.v
new file mode 100644
index 000000000..608c2d448
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/cic_interp.v
@@ -0,0 +1,75 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+
+//
+
+
+module cic_interp
+  #(parameter bw = 16, parameter N = 4, parameter log2_of_max_rate = 7)
+    (input clock,
+     input reset,
+     input enable,
+     input [7:0] rate,
+     input strobe_in,
+     input strobe_out,
+     input [bw-1:0] signal_in,
+     output reg [bw-1:0] signal_out);
+   
+   integer 	     i;
+   localparam 	     maxbitgain = (N-1)*log2_of_max_rate;
+
+   wire [bw+maxbitgain-1:0] signal_in_ext;
+   reg [bw+maxbitgain-1:0]  integrator [0:N-1];
+   reg [bw+maxbitgain-1:0]  differentiator [0:N-1];
+   reg [bw+maxbitgain-1:0]  pipeline [0:N-1];
+   
+   sign_extend #(bw,bw+maxbitgain) 
+     ext_input (.in(signal_in),.out(signal_in_ext));
+   
+   //FIXME Note that this section has pipe and diff reversed
+   // It still works, but is confusing
+   always @(posedge clock)
+     if(reset | ~enable)
+       for(i=0;i<N;i=i+1)
+	 integrator[i] <= 0;
+     else if (enable & strobe_out)
+       begin
+	  if(strobe_in)
+	    integrator[0] <= integrator[0] + pipeline[N-1];
+	  for(i=1;i<N;i=i+1)
+	    integrator[i] <= integrator[i] + integrator[i-1];
+       end
+   
+   always @(posedge clock)
+     if(reset | ~enable)
+       begin
+	  for(i=0;i<N;i=i+1)
+	    begin
+	       differentiator[i] <= 0;
+	       pipeline[i] <= 0;
+ 	    end
+       end
+     else if (enable && strobe_in)
+       begin
+	  differentiator[0] <= signal_in_ext;
+	  pipeline[0] <= signal_in_ext - differentiator[0];
+	  for(i=1;i<N;i=i+1)
+	    begin
+	       differentiator[i] <= pipeline[i-1];
+	       pipeline[i] <= pipeline[i-1] - differentiator[i];
+	    end
+       end
+
+   wire [bw-1:0] signal_out_unreg;
+   cic_int_shifter #(bw)
+     cic_int_shifter(rate,integrator[N-1],signal_out_unreg);
+   
+   always @(posedge clock)
+     signal_out <= signal_out_unreg;
+   
+endmodule // cic_interp
+
diff --git a/fpga/usrp3/lib/dsp/cic_strober.v b/fpga/usrp3/lib/dsp/cic_strober.v
new file mode 100644
index 000000000..269b85f75
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/cic_strober.v
@@ -0,0 +1,33 @@
+//
+//  USRP2 - Universal Software Radio Peripheral Mk II
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+
+//
+
+module cic_strober
+  #(parameter WIDTH=8)
+    ( input clock,
+      input reset,
+      input enable,
+      input [WIDTH-1:0] rate, // Rate should EQUAL to your desired divide ratio, no more -1 BS
+      input strobe_fast,
+      output wire strobe_slow );
+   
+   reg [WIDTH-1:0] counter;
+   wire      now = (counter==1);
+   assign    strobe_slow = now && enable && strobe_fast;
+   
+   always @(posedge clock)
+     if(reset)
+       counter <= 0; 
+     else if (~enable)
+       counter <= rate;
+     else if(strobe_fast)
+       if(now)
+	 counter <= rate;
+       else 
+	 counter <= counter - 1;
+   
+endmodule // cic_strober
diff --git a/fpga/usrp3/lib/dsp/clip.v b/fpga/usrp3/lib/dsp/clip.v
new file mode 100644
index 000000000..294c5e8ba
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/clip.v
@@ -0,0 +1,24 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+
+//
+
+// Clipping "macro", keeps the bottom bits
+
+module clip
+  #(parameter bits_in=0,
+    parameter bits_out=0)
+    (input [bits_in-1:0] in,
+     output [bits_out-1:0] out);
+   
+   wire 		   overflow = |in[bits_in-1:bits_out-1] & ~(&in[bits_in-1:bits_out-1]);   
+   assign 		   out = overflow ? 
+			   (in[bits_in-1] ? {1'b1,{(bits_out-1){1'b0}}} : {1'b0,{(bits_out-1){1'b1}}}) :
+			   in[bits_out-1:0];
+   
+endmodule // clip
+
diff --git a/fpga/usrp3/lib/dsp/clip_reg.v b/fpga/usrp3/lib/dsp/clip_reg.v
new file mode 100644
index 000000000..ab9a5b79d
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/clip_reg.v
@@ -0,0 +1,34 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+
+//
+
+// Clipping "macro", keeps the bottom bits
+
+module clip_reg
+  #(parameter bits_in=0,
+    parameter bits_out=0,
+    parameter STROBED=1'b0)
+    (input clk,
+     input [bits_in-1:0] in,
+     output reg [bits_out-1:0] out,
+     input strobe_in,
+     output reg strobe_out);
+   
+   wire [bits_out-1:0] temp;
+
+   clip #(.bits_in(bits_in),.bits_out(bits_out)) clip (.in(in),.out(temp));
+
+   always @(posedge clk)
+     strobe_out <= strobe_in;
+   
+   always @(posedge clk)
+     if(strobe_in | ~STROBED)
+       out <= temp;
+   
+endmodule // clip_reg
+
diff --git a/fpga/usrp3/lib/dsp/cordic_stage.v b/fpga/usrp3/lib/dsp/cordic_stage.v
new file mode 100644
index 000000000..7019ead52
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/cordic_stage.v
@@ -0,0 +1,48 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+
+//
+
+module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
+   parameter bitwidth = 16;
+   parameter zwidth = 16;
+   parameter shift = 1;
+   
+   input     clock;
+   input     reset;
+   input     enable;
+   input [bitwidth-1:0] xi,yi;
+   input [zwidth-1:0] zi;
+   input [zwidth-1:0] constant;
+   output [bitwidth-1:0] xo,yo;
+   output [zwidth-1:0] zo;
+   
+   wire z_is_pos = ~zi[zwidth-1];
+
+   reg [bitwidth-1:0] 	 xo,yo;
+   reg [zwidth-1:0] zo;
+   
+   always @(posedge clock)
+     if(reset)
+       begin
+	  xo <= 0;
+	  yo <= 0;
+	  zo <= 0;
+       end
+     else //if(enable)
+       begin
+	  xo <= z_is_pos ?   
+		xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :
+		xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]};
+	  yo <= z_is_pos ?   
+		yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} :
+		yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]};
+	  zo <= z_is_pos ?   
+		zi - constant :
+		zi + constant;
+       end
+endmodule
diff --git a/fpga/usrp3/lib/dsp/cordic_z24.v b/fpga/usrp3/lib/dsp/cordic_z24.v
new file mode 100644
index 000000000..d9e983ccd
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/cordic_z24.v
@@ -0,0 +1,112 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003, 2007 Matt Ettus
+//
+
+//
+
+module cordic_z24(clock, reset, enable, xi, yi, zi, xo, yo, zo );
+   parameter bitwidth = 16;
+   parameter stages = 19;
+   localparam zwidth = 24;
+   
+   input clock;
+   input reset;
+   input enable;
+   input [bitwidth-1:0] xi, yi;
+   output [bitwidth-1:0] xo, yo;
+   input [zwidth-1:0] zi;
+   output [zwidth-1:0] zo;
+   
+   reg [bitwidth+1:0] 	 x0,y0;
+   reg [zwidth-2:0] 	 z0;
+   wire [bitwidth+1:0] 	 x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18,x19,x20;
+   wire [bitwidth+1:0] 	 y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,y14,y15,y16,y17,y18,y19,y20;
+   wire [zwidth-2:0] 	 z1,z2,z3,z4,z5,z6,z7,z8,z9,z10,z11,z12,z13,z14,z15,z16,z17,z18,z19,z20;
+   
+   wire [bitwidth+1:0] xi_ext = {{2{xi[bitwidth-1]}},xi};
+   wire [bitwidth+1:0] yi_ext = {{2{yi[bitwidth-1]}},yi};
+
+   // Compute consts.  Would be easier if vlog had atan...
+   // see gen_cordic_consts.py
+
+   // constants for 24 bit wide phase
+   localparam 	       c00 = 23'd2097152;
+   localparam 	       c01 = 23'd1238021;
+   localparam 	       c02 = 23'd654136;
+   localparam 	       c03 = 23'd332050;
+   localparam 	       c04 = 23'd166669;
+   localparam 	       c05 = 23'd83416;
+   localparam 	       c06 = 23'd41718;
+   localparam 	       c07 = 23'd20860;
+   localparam 	       c08 = 23'd10430;
+   localparam 	       c09 = 23'd5215;
+   localparam 	       c10 = 23'd2608;
+   localparam 	       c11 = 23'd1304;
+   localparam 	       c12 = 23'd652;
+   localparam 	       c13 = 23'd326;
+   localparam 	       c14 = 23'd163;
+   localparam 	       c15 = 23'd81;
+   localparam 	       c16 = 23'd41;
+   localparam 	       c17 = 23'd20;
+   localparam 	       c18 = 23'd10;
+   localparam 	       c19 = 23'd5;
+   localparam 	       c20 = 23'd3;
+   localparam 	       c21 = 23'd1;
+   localparam 	       c22 = 23'd1;
+   localparam 	       c23 = 23'd0;
+
+   always @(posedge clock)
+     if(reset)
+       begin
+	  x0   <= 0; y0   <= 0;  z0   <= 0;
+       end
+     else// if(enable)
+       begin
+	  z0 <= zi[zwidth-2:0];
+	  case (zi[zwidth-1:zwidth-2])
+	    2'b00, 2'b11 : 
+	      begin
+		 x0 <= xi_ext;
+		 y0 <= yi_ext;
+	      end
+	    2'b01, 2'b10 :
+	      begin
+		 x0 <= -xi_ext;
+		 y0 <= -yi_ext;
+	      end
+	  endcase // case(zi[zwidth-1:zwidth-2])
+       end // else: !if(reset)
+   
+   // FIXME need to handle variable number of stages
+   // This would be easier if arrays worked better in vlog...
+   
+   cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 (clock,reset,enable,x0,y0,z0,c00,x1,y1,z1);
+   cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 (clock,reset,enable,x1,y1,z1,c01,x2,y2,z2);
+   cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 (clock,reset,enable,x2,y2,z2,c02,x3,y3,z3);
+   cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 (clock,reset,enable,x3,y3,z3,c03,x4,y4,z4);
+   cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 (clock,reset,enable,x4,y4,z4,c04,x5,y5,z5);
+   cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 (clock,reset,enable,x5,y5,z5,c05,x6,y6,z6);
+   cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 (clock,reset,enable,x6,y6,z6,c06,x7,y7,z7);
+   cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 (clock,reset,enable,x7,y7,z7,c07,x8,y8,z8);
+   cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 (clock,reset,enable,x8,y8,z8,c08,x9,y9,z9);
+   cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 (clock,reset,enable,x9,y9,z9,c09,x10,y10,z10);
+   cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 (clock,reset,enable,x10,y10,z10,c10,x11,y11,z11);
+   cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 (clock,reset,enable,x11,y11,z11,c11,x12,y12,z12);
+   cordic_stage #(bitwidth+2,zwidth-1,12) cordic_stage12 (clock,reset,enable,x12,y12,z12,c12,x13,y13,z13);
+   cordic_stage #(bitwidth+2,zwidth-1,13) cordic_stage13 (clock,reset,enable,x13,y13,z13,c13,x14,y14,z14);
+   cordic_stage #(bitwidth+2,zwidth-1,14) cordic_stage14 (clock,reset,enable,x14,y14,z14,c14,x15,y15,z15);
+   cordic_stage #(bitwidth+2,zwidth-1,15) cordic_stage15 (clock,reset,enable,x15,y15,z15,c15,x16,y16,z16);
+   cordic_stage #(bitwidth+2,zwidth-1,16) cordic_stage16 (clock,reset,enable,x16,y16,z16,c16,x17,y17,z17);
+   cordic_stage #(bitwidth+2,zwidth-1,17) cordic_stage17 (clock,reset,enable,x17,y17,z17,c17,x18,y18,z18);
+   cordic_stage #(bitwidth+2,zwidth-1,18) cordic_stage18 (clock,reset,enable,x18,y18,z18,c18,x19,y19,z19);
+   cordic_stage #(bitwidth+2,zwidth-1,19) cordic_stage19 (clock,reset,enable,x19,y19,z19,c19,x20,y20,z20);
+
+   assign xo = x20[bitwidth:1];  
+   assign yo = y20[bitwidth:1];
+   assign zo = z20;		  
+
+endmodule // cordic
+
diff --git a/fpga/usrp3/lib/dsp/ddc_chain.v b/fpga/usrp3/lib/dsp/ddc_chain.v
new file mode 100644
index 000000000..365175bf1
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/ddc_chain.v
@@ -0,0 +1,164 @@
+//
+// Copyright 2011-2013 Ettus Research LLC
+//
+
+
+//! The USRP digital down-conversion chain
+
+module ddc_chain
+  #(
+    parameter BASE = 0,
+    parameter DSPNO = 0,
+    parameter WIDTH = 24
+  )
+  (input clk, input rst, input clr,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+   // From RX frontend
+   input [WIDTH-1:0] rx_fe_i,
+   input [WIDTH-1:0] rx_fe_q,
+
+   // To RX control
+   output [31:0] sample,
+   input run,
+   output strobe,
+   output [31:0] debug
+   );
+
+   localparam  cwidth = 25;
+   localparam  zwidth = 24;
+
+   wire [31:0] phase_inc;
+   reg [31:0]  phase;
+
+   wire [17:0] scale_factor;
+   wire [cwidth-1:0] i_cordic, q_cordic;
+   wire [WIDTH-1:0] i_cordic_clip, q_cordic_clip;
+   wire [WIDTH-1:0] i_cic, q_cic;
+   wire [WIDTH-1:0] i_hb1, q_hb1;
+   wire [WIDTH-1:0] i_hb2, q_hb2;
+   
+   wire        strobe_cic, strobe_hb1, strobe_hb2;
+   wire        enable_hb1, enable_hb2;
+   wire [7:0]  cic_decim_rate;
+
+   reg [WIDTH-1:0]  rx_fe_i_mux, rx_fe_q_mux;
+   wire        realmode;
+   wire        swap_iq;
+   
+   setting_reg #(.my_addr(BASE+0)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_inc),.changed());
+
+   setting_reg #(.my_addr(BASE+1), .width(18)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(scale_factor),.changed());
+
+   setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
+
+   setting_reg #(.my_addr(BASE+3), .width(2)) sr_3
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({realmode,swap_iq}),.changed());
+
+   // MUX so we can do realmode signals on either input
+   
+   always @(posedge clk)
+     if(swap_iq)
+       begin
+	  rx_fe_i_mux <= rx_fe_q;
+	  rx_fe_q_mux <= realmode ? 0 : rx_fe_i;
+       end
+     else
+       begin
+	  rx_fe_i_mux <= rx_fe_i;
+	  rx_fe_q_mux <= realmode ? 0 : rx_fe_q;
+       end
+
+   // NCO
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else if(~run)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+
+   //sign extension of cordic input
+   wire [cwidth-1:0] to_cordic_i, to_cordic_q;
+   sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_i (.in(rx_fe_i_mux), .out(to_cordic_i));
+   sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_q (.in(rx_fe_q_mux), .out(to_cordic_q));
+
+   // CORDIC  24-bit I/O
+   cordic_z24 #(.bitwidth(cwidth))
+     cordic(.clock(clk), .reset(rst), .enable(run),
+	    .xi(to_cordic_i),. yi(to_cordic_q), .zi(phase[31:32-zwidth]),
+	    .xo(i_cordic),.yo(q_cordic),.zo() );
+
+   clip_reg #(.bits_in(cwidth), .bits_out(WIDTH)) clip_i
+     (.clk(clk), .in(i_cordic), .strobe_in(1'b1), .out(i_cordic_clip));
+   clip_reg #(.bits_in(cwidth), .bits_out(WIDTH)) clip_q
+     (.clk(clk), .in(q_cordic), .strobe_in(1'b1), .out(q_cordic_clip));
+
+   // CIC decimator  24 bit I/O
+   cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate),
+			   .strobe_fast(1),.strobe_slow(strobe_cic) );
+
+   cic_decim #(.bw(WIDTH))
+     decim_i (.clock(clk),.reset(rst),.enable(run),
+	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
+	      .signal_in(i_cordic_clip),.signal_out(i_cic));
+   
+   cic_decim #(.bw(WIDTH))
+     decim_q (.clock(clk),.reset(rst),.enable(run),
+	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
+	      .signal_in(q_cordic_clip),.signal_out(q_cic));
+
+   // First (small) halfband  24 bit I/O
+   small_hb_dec #(.WIDTH(WIDTH)) small_hb_i
+     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
+      .stb_in(strobe_cic),.data_in(i_cic),.stb_out(strobe_hb1),.data_out(i_hb1));
+   
+   small_hb_dec #(.WIDTH(WIDTH)) small_hb_q
+     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
+      .stb_in(strobe_cic),.data_in(q_cic),.stb_out(),.data_out(q_hb1));
+
+   // Second (large) halfband  24 bit I/O
+   wire [8:0]  cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate};
+   hb_dec #(.WIDTH(WIDTH)) hb_i
+     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
+      .stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2));
+
+   hb_dec #(.WIDTH(WIDTH)) hb_q
+     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
+      .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
+
+   //scalar operation (gain of 6 bits)
+   wire [35:0] prod_i, prod_q;
+
+   MULT18X18S mult_i
+     (.P(prod_i), .A(i_hb2[WIDTH-1:WIDTH-18]), .B(scale_factor), .C(clk), .CE(strobe_hb2), .R(rst) );
+   MULT18X18S mult_q
+     (.P(prod_q), .A(q_hb2[WIDTH-1:WIDTH-18]), .B(scale_factor), .C(clk), .CE(strobe_hb2), .R(rst) );
+
+   //pipeline for the multiplier (gain of 10 bits)
+   reg [WIDTH-1:0] prod_reg_i, prod_reg_q;
+   reg strobe_mult;
+
+   always @(posedge clk) begin
+       strobe_mult <= strobe_hb2;
+       prod_reg_i <= prod_i[33:34-WIDTH];
+       prod_reg_q <= prod_q[33:34-WIDTH];
+   end
+
+   // Round final answer to 16 bits
+   round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(16)) round_i
+     (.clk(clk),.reset(rst), .in(prod_reg_i),.strobe_in(strobe_mult), .out(sample[31:16]), .strobe_out(strobe));
+
+   round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(16)) round_q
+     (.clk(clk),.reset(rst), .in(prod_reg_q),.strobe_in(strobe_mult), .out(sample[15:0]), .strobe_out());
+
+   assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_hb1, strobe_hb2};
+   
+endmodule // ddc_chain
diff --git a/fpga/usrp3/lib/dsp/duc_chain.v b/fpga/usrp3/lib/dsp/duc_chain.v
new file mode 100644
index 000000000..06c87bd34
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/duc_chain.v
@@ -0,0 +1,146 @@
+//
+// Copyright 2011-2013 Ettus Research LLC
+//
+
+
+//! The USRP digital up-conversion chain
+
+module duc_chain
+  #(
+    parameter BASE = 0,
+    parameter DSPNO = 0,
+    parameter WIDTH = 24
+  )
+  (input clk, input rst, input clr,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+   // To TX frontend
+   output [WIDTH-1:0] tx_fe_i,
+   output [WIDTH-1:0] tx_fe_q,
+
+   // From TX control
+   input [31:0] sample,
+   input run,
+   output strobe,
+   output [31:0] debug
+   );
+
+   wire [17:0] scale_factor;
+   wire [31:0] phase_inc;
+   reg [31:0]  phase;
+   wire [7:0]  interp_rate;
+   wire [3:0]  tx_femux_a, tx_femux_b;
+   wire        enable_hb1, enable_hb2;
+   wire        rate_change;
+   
+   setting_reg #(.my_addr(BASE+0)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_inc),.changed());
+
+   setting_reg #(.my_addr(BASE+1), .width(18)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(scale_factor),.changed());
+   
+   setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed(rate_change));
+
+   // Strobes are all now delayed by 1 cycle for timing reasons
+   wire        strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre;
+   reg 	       strobe_cic = 1;
+   reg 	       strobe_hb1 = 1;
+   reg 	       strobe_hb2 = 1;
+
+  assign strobe = strobe_hb1;
+   
+   cic_strober #(.WIDTH(8))
+     cic_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate),
+		 .strobe_fast(1),.strobe_slow(strobe_cic_pre) );
+   cic_strober #(.WIDTH(2))
+     hb2_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(enable_hb2 ? 2 : 1),
+		 .strobe_fast(strobe_cic_pre),.strobe_slow(strobe_hb2_pre) );
+   cic_strober #(.WIDTH(2))
+     hb1_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(enable_hb1 ? 2 : 1),
+		 .strobe_fast(strobe_hb2_pre),.strobe_slow(strobe_hb1_pre) );
+   
+   always @(posedge clk) strobe_hb1 <= strobe_hb1_pre;
+   always @(posedge clk) strobe_hb2 <= strobe_hb2_pre;
+   always @(posedge clk) strobe_cic <= strobe_cic_pre;
+
+   // NCO
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else if(~run)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+   
+   wire        signed [17:0] da, db;
+   wire        signed [35:0] prod_i, prod_q;
+
+   assign tx_fe_i = prod_i[33:34-WIDTH];
+   assign tx_fe_q = prod_q[33:34-WIDTH];
+
+   wire [17:0] i_interp, q_interp;
+
+   wire [17:0] hb1_i, hb1_q, hb2_i, hb2_q;
+
+   wire [7:0]  cpo = enable_hb2 ? ({interp_rate,1'b0}) : interp_rate;
+   // Note that max CIC rate is 128, which would give an overflow on cpo if enable_hb2 is true,
+   //   but the default case inside hb_interp handles this
+   
+   hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_i
+     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({sample[31:16], 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_i));
+   hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_q
+     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({sample[15:0], 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_q));
+   
+   small_hb_int #(.WIDTH(18)) small_hb_interp_i
+     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_i),
+      .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_i));
+   small_hb_int #(.WIDTH(18)) small_hb_interp_q
+     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_q),
+      .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_q));
+   
+   cic_interp  #(.bw(18),.N(4),.log2_of_max_rate(7))
+     cic_interp_i(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate),
+		  .strobe_in(strobe_cic),.strobe_out(1),
+		  .signal_in(hb2_i),.signal_out(i_interp));
+   
+   cic_interp  #(.bw(18),.N(4),.log2_of_max_rate(7))
+     cic_interp_q(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate),
+		  .strobe_in(strobe_cic),.strobe_out(1),
+		  .signal_in(hb2_q),.signal_out(q_interp));
+
+   localparam  cwidth = WIDTH;  // was 18
+   localparam  zwidth = 24;  // was 16
+
+   wire [cwidth-1:0] da_c, db_c;
+   
+   cordic_z24 #(.bitwidth(cwidth))
+     cordic(.clock(clk), .reset(rst), .enable(run),
+	    .xi({i_interp,{(cwidth-18){1'b0}}}),.yi({q_interp,{(cwidth-18){1'b0}}}),
+	    .zi(phase[31:32-zwidth]),
+	    .xo(da_c),.yo(db_c),.zo() );
+   
+   MULT18X18S MULT18X18S_inst 
+     (.P(prod_i),    // 36-bit multiplier output
+      .A(da_c[cwidth-1:cwidth-18]),    // 18-bit multiplier input
+      .B(scale_factor),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      );
+   
+   MULT18X18S MULT18X18S_inst_2 
+     (.P(prod_q),    // 36-bit multiplier output
+      .A(db_c[cwidth-1:cwidth-18]),    // 18-bit multiplier input
+      .B(scale_factor),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      );
+
+   assign      debug = {strobe_cic, strobe_hb1, strobe_hb2,run};
+
+endmodule // duc_chain
diff --git a/fpga/usrp3/lib/dsp/hb_dec.v b/fpga/usrp3/lib/dsp/hb_dec.v
new file mode 100644
index 000000000..65c771ca7
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/hb_dec.v
@@ -0,0 +1,177 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+// Final halfband decimator 
+// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A]
+// Strobe in cannot come faster than every 2nd clock cycle
+// These taps designed by halfgen4 from ldoolittle
+// myfilt = round(2^18 * halfgen4(.7/4,8))
+
+module hb_dec
+  #(parameter WIDTH=24)
+    (input clk,
+     input rst,
+     input bypass,
+     input run,
+     input [8:0] cpi,  // Clocks per input -- equal to the decimation ratio ahead of this block
+     input stb_in,
+     input [WIDTH-1:0] data_in,
+     output reg stb_out,
+     output reg [WIDTH-1:0] data_out);
+
+   localparam INTWIDTH = 17;
+   localparam ACCWIDTH = WIDTH + 3;
+   
+   // Round off inputs to 17 bits because of 18 bit multipliers
+   wire [INTWIDTH-1:0] 	     data_rnd;
+   wire 		     stb_rnd;
+   
+   round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in
+     (.clk(clk),.reset(rst),.in(data_in),.strobe_in(stb_in),.out(data_rnd),.strobe_out(stb_rnd));
+   
+   // Control
+   reg [3:0] 		addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d;
+   wire 		write_odd, write_even, do_mult;
+   reg 			odd;
+   reg [2:0] 		phase, phase_d1;
+   reg 			stb_out_int;
+   wire 		clear, do_acc;
+   assign 		do_mult = 1;
+   
+   always @(posedge clk)
+     if(rst | ~run)
+       odd <= 0;
+     else if(stb_rnd)
+       odd <= ~odd;
+
+   assign 		write_odd = stb_rnd & odd;
+   assign 		write_even = stb_rnd & ~odd;
+
+   always @(posedge clk)
+     if(rst | ~run)
+       phase <= 0;
+     else if(stb_rnd & odd)
+       phase <= 1;
+     else if(phase == 4)
+       phase <= 0;
+     else if(phase != 0)
+       phase <= phase + 1;
+
+   always @(posedge clk)
+     phase_d1 <= phase;
+   
+   reg [15:0] 		stb_out_pre;
+   always @(posedge clk)
+     if(rst)
+       stb_out_pre <= 0;
+     else
+       stb_out_pre <= {stb_out_pre[14:0],(stb_rnd & odd)};
+
+   always @*
+     case(phase)
+       1 : begin addr_odd_a = 0; addr_odd_b = 15; end
+       2 : begin addr_odd_a = 1; addr_odd_b = 14; end
+       3 : begin addr_odd_a = 2; addr_odd_b = 13; end
+       4 : begin addr_odd_a = 3; addr_odd_b = 12; end
+       default : begin addr_odd_a = 0; addr_odd_b = 15; end
+     endcase // case(phase)
+
+   always @*
+     case(phase)
+       1 : begin addr_odd_c = 4; addr_odd_d = 11; end
+       2 : begin addr_odd_c = 5; addr_odd_d = 10; end
+       3 : begin addr_odd_c = 6; addr_odd_d = 9; end
+       4 : begin addr_odd_c = 7; addr_odd_d = 8; end
+       default : begin addr_odd_c = 4; addr_odd_d = 11; end
+     endcase // case(phase)
+
+   assign do_acc = |stb_out_pre[6:3];
+   assign clear = stb_out_pre[3];
+   
+   // Data
+   wire [INTWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d;
+   reg [INTWIDTH:0]    sum1, sum2;    // these are 18-bit inputs to mult
+   reg [WIDTH:0]       final_sum;
+   wire [WIDTH-1:0]    final_sum_clip;
+   reg [17:0] 	       coeff1, coeff2;
+   wire [35:0] 	       prod1, prod2;
+
+   always @*            // Outer coeffs
+     case(phase_d1)
+       1 : coeff1 = -107;
+       2 : coeff1 = 445;
+       3 : coeff1 = -1271;
+       4 : coeff1 = 2959;
+       default : coeff1 = -107;
+     endcase // case(phase)
+   
+   always @*            //  Inner coeffs
+     case(phase_d1)
+       1 : coeff2 = -6107;
+       2 : coeff2 = 11953;
+       3 : coeff2 = -24706;
+       4 : coeff2 = 82359;
+       default : coeff2 = -6107;
+     endcase // case(phase)
+   
+   srl #(.WIDTH(INTWIDTH)) srl_odd_a
+     (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_a),.out(data_odd_a));
+   srl #(.WIDTH(INTWIDTH)) srl_odd_b
+     (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_b),.out(data_odd_b));
+   srl #(.WIDTH(INTWIDTH)) srl_odd_c
+     (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_c),.out(data_odd_c));
+   srl #(.WIDTH(INTWIDTH)) srl_odd_d
+     (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_d),.out(data_odd_d));
+
+   always @(posedge clk) sum1 <= {data_odd_a[INTWIDTH-1],data_odd_a} + {data_odd_b[INTWIDTH-1],data_odd_b};
+   always @(posedge clk) sum2 <= {data_odd_c[INTWIDTH-1],data_odd_c} + {data_odd_d[INTWIDTH-1],data_odd_d};
+   
+   wire [INTWIDTH-1:0] data_even;
+   reg [3:0] 	     addr_even;
+
+   always @(posedge clk)
+     case(cpi)
+       //  1 is an error
+       2 : addr_even <= 9;  // Maximum speed (overall decim by 4)
+       3, 4, 5, 6, 7 : addr_even <= 8;
+       default : addr_even <= 7;
+     endcase // case(cpi)
+   
+   srl #(.WIDTH(INTWIDTH)) srl_even
+     (.clk(clk),.write(write_even),.in(data_rnd),.addr(addr_even),.out(data_even));
+
+   MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) );
+   MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) );
+
+   reg [35:0] 	     sum_of_prod;
+   always @(posedge clk) sum_of_prod <= prod1 + prod2;   // Can't overflow
+   
+   wire [ACCWIDTH-1:0] 	acc_out;
+   acc #(.IWIDTH(ACCWIDTH-2),.OWIDTH(ACCWIDTH))
+     acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod[35:38-ACCWIDTH]),.out(acc_out));
+
+   wire [ACCWIDTH-1:0] 	data_even_signext;
+
+   localparam SHIFT_FACTOR = 6;
+   
+   sign_extend #(.bits_in(INTWIDTH),.bits_out(ACCWIDTH-SHIFT_FACTOR)) signext_data_even 
+     (.in(data_even),.out(data_even_signext[ACCWIDTH-1:SHIFT_FACTOR]));
+   assign 		data_even_signext[SHIFT_FACTOR-1:0] = 0;
+
+   always @(posedge clk) final_sum <= acc_out + data_even_signext;
+   
+   clip #(.bits_in(WIDTH+1), .bits_out(WIDTH)) clip (.in(final_sum), .out(final_sum_clip));
+   
+   // Output MUX to allow for bypass
+   wire 		selected_stb = bypass ? stb_in : stb_out_pre[8];
+   
+   always @(posedge clk)
+     begin
+	stb_out  <= selected_stb;
+	if(selected_stb)
+	  data_out <= bypass ? data_in : final_sum_clip;
+     end
+   
+endmodule // hb_dec
diff --git a/fpga/usrp3/lib/dsp/hb_interp.v b/fpga/usrp3/lib/dsp/hb_interp.v
new file mode 100644
index 000000000..c0914255c
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/hb_interp.v
@@ -0,0 +1,165 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+// First halfband iterpolator 
+// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A]
+// Strobe in cannot come faster than every 4th clock cycle, 
+// Strobe out cannot come faster than every 2nd clock cycle
+
+// These taps designed by halfgen4 from ldoolittle
+// myfilt = round(2^18 * halfgen4(.7/4,8))
+
+module hb_interp
+  #(parameter IWIDTH=18, OWIDTH=18, ACCWIDTH=24)
+    (input clk,
+     input rst,
+     input bypass,
+     input [7:0] cpo, //  Clocks per output, must be at least 2
+     input stb_in,
+     input [IWIDTH-1:0] data_in,
+     input stb_out,
+     output reg [OWIDTH-1:0] data_out);
+
+   localparam MWIDTH = ACCWIDTH-2;
+   localparam CWIDTH = 18;
+
+   reg [CWIDTH-1:0] coeff1, coeff2;
+   reg [3:0] 	    addr_a, addr_b, addr_c, addr_d, addr_e;
+   wire [IWIDTH-1:0] data_a, data_b, data_c, data_d, data_e, sum1, sum2;
+   wire [35:0] 	     prod1, prod2;
+
+   reg [2:0] 	     phase, phase_d1, phase_d2, phase_d3, phase_d4, phase_d5;
+
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else
+       if(stb_in)
+	 phase <= 1;
+       else if(phase==4)
+	 phase <= 0;
+       else if(phase!=0)
+	 phase <= phase + 1;
+   always @(posedge clk) phase_d1 <= phase;
+   always @(posedge clk) phase_d2 <= phase_d1;
+   always @(posedge clk) phase_d3 <= phase_d2;
+   always @(posedge clk) phase_d4 <= phase_d3;
+   always @(posedge clk) phase_d5 <= phase_d4;     
+   
+   srl #(.WIDTH(IWIDTH)) srl_a
+     (.clk(clk),.rst(rst),.write(stb_in),.in(data_in),.addr(addr_a),.out(data_a));
+   srl #(.WIDTH(IWIDTH)) srl_b
+     (.clk(clk),.rst(rst),.write(stb_in),.in(data_in),.addr(addr_b),.out(data_b));
+   srl #(.WIDTH(IWIDTH)) srl_c
+     (.clk(clk),.rst(rst),.write(stb_in),.in(data_in),.addr(addr_c),.out(data_c));
+   srl #(.WIDTH(IWIDTH)) srl_d
+     (.clk(clk),.rst(rst),.write(stb_in),.in(data_in),.addr(addr_d),.out(data_d));
+   srl #(.WIDTH(IWIDTH)) srl_e
+     (.clk(clk),.rst(rst),.write(stb_in),.in(data_in),.addr(addr_e),.out(data_e));
+
+   always @*
+     case(phase)
+       1 : begin addr_a = 0; addr_b = 15; end
+       2 : begin addr_a = 1; addr_b = 14; end
+       3 : begin addr_a = 2; addr_b = 13; end
+       4 : begin addr_a = 3; addr_b = 12; end
+       default : begin addr_a = 0; addr_b = 15; end
+     endcase // case(phase)
+
+   always @*
+     case(phase)
+       1 : begin addr_c = 4; addr_d = 11; end
+       2 : begin addr_c = 5; addr_d = 10; end
+       3 : begin addr_c = 6; addr_d = 9; end
+       4 : begin addr_c = 7; addr_d = 8; end
+       default : begin addr_c = 4; addr_d = 11; end
+     endcase // case(phase)
+
+   always @*
+     case(cpo)
+       2 : addr_e <= 9;
+       3,4,5,6,7,8 : addr_e <= 8;
+       default : addr_e <= 7;  // This case works for 256, which = 0 due to overflow outside this block
+     endcase // case(cpo)
+   
+   always @*            // Outer coeffs
+     case(phase_d1)
+       1 : coeff1 = -107;
+       2 : coeff1 = 445;
+       3 : coeff1 = -1271;
+       4 : coeff1 = 2959;
+       default : coeff1 = -107;
+     endcase // case(phase)
+   
+   always @*            //  Inner coeffs
+     case(phase_d1)
+       1 : coeff2 = -6107;
+       2 : coeff2 = 11953;
+       3 : coeff2 = -24706;
+       4 : coeff2 = 82359;
+       default : coeff2 = -6107;
+     endcase // case(phase)
+
+   add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1 (.clk(clk),.in1(data_a),.in2(data_b),.sum(sum1));
+   add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2 (.clk(clk),.in1(data_c),.in2(data_d),.sum(sum2));
+   // sum1, sum2 available on phase_d1
+
+   wire do_mult = 1;
+   MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) );
+   MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) );
+   // prod1, prod2 available on phase_d2
+   
+   wire [MWIDTH-1:0] sum_of_prod;
+   
+   add2_and_round_reg #(.WIDTH(MWIDTH)) 
+     add3 (.clk(clk),.in1(prod1[35:36-MWIDTH]),.in2(prod2[35:36-MWIDTH]),.sum(sum_of_prod));
+   // sum_of_prod available on phase_d3
+   
+   wire [ACCWIDTH-1:0] acc_out;
+ 
+   wire 	       clear = (phase_d3 == 1);
+   wire 	       do_acc = (phase_d3 != 0);
+   
+   acc #(.IWIDTH(MWIDTH),.OWIDTH(ACCWIDTH)) //IJB rst
+     acc (.clk(clk),.clear(rst|clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out));   
+   // acc_out available on phase_d4
+   
+   wire [ACCWIDTH-6:0] clipped_acc;
+   clip #(.bits_in(ACCWIDTH),.bits_out(ACCWIDTH-5)) final_clip(.in(acc_out),.out(clipped_acc));
+   
+   reg [ACCWIDTH-6:0]   clipped_reg;
+   always @(posedge clk)
+     if (rst)
+       clipped_reg <= 0;
+     else  if(phase_d4 == 4)
+       clipped_reg <= clipped_acc;
+   // clipped_reg available on phase_d5
+   
+   wire [OWIDTH-1:0]   data_out_round;
+   round #(.bits_in(ACCWIDTH-5),.bits_out(OWIDTH)) final_round (.in(clipped_reg),.out(data_out_round));
+
+   reg 		      odd;
+   always @(posedge clk)
+     if(rst)
+       odd <= 0;
+     else if(stb_in)
+       odd <= 0;
+     else if(stb_out)
+       odd <= 1;
+
+   always @(posedge clk)
+     if (rst)
+       data_out <= 0;
+     else if(bypass)
+       data_out <= data_in;
+     else if(stb_out)
+       if(odd)
+	 data_out <= data_e;
+       else
+	 data_out <= data_out_round;
+
+   // data_out available on phase_d6
+   
+endmodule // hb_interp
diff --git a/fpga/usrp3/lib/dsp/round.v b/fpga/usrp3/lib/dsp/round.v
new file mode 100644
index 000000000..7ecc10ff7
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/round.v
@@ -0,0 +1,47 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2011 Matt Ettus
+//
+
+//
+
+// Rounding "macro"
+// Keeps the topmost bits, does proper 2s comp round to zero (unbiased truncation)
+
+module round
+  #(parameter bits_in=0,
+    parameter bits_out=0,
+    parameter round_to_zero=0,       // original behavior
+    parameter round_to_nearest=1,    // lowest noise
+    parameter trunc=0)               // round to negative infinity
+    (input [bits_in-1:0] in,
+     output [bits_out-1:0] out,
+     output [bits_in-bits_out:0] err);
+
+   wire 			 round_corr,round_corr_trunc,round_corr_rtz,round_corr_nearest,round_corr_nearest_safe;
+   
+   assign 			 round_corr_trunc = 0;
+   assign 			 round_corr_rtz = (in[bits_in-1] & |in[bits_in-bits_out-1:0]);
+   assign 			 round_corr_nearest = in[bits_in-bits_out-1];
+
+   generate
+      if(bits_in-bits_out > 1)
+	assign 			 round_corr_nearest_safe = (~in[bits_in-1] & (&in[bits_in-2:bits_out])) ? 0 :
+				 round_corr_nearest;
+      else
+	assign round_corr_nearest_safe = round_corr_nearest;
+   endgenerate
+   
+      
+   assign round_corr = round_to_nearest ? round_corr_nearest_safe :
+		       trunc ? round_corr_trunc : 
+		       round_to_zero ? round_corr_rtz :
+		       0;  // default to trunc
+      
+   assign out = in[bits_in-1:bits_in-bits_out] + round_corr;
+   
+   assign err = in - {out,{(bits_in-bits_out){1'b0}}};
+   
+endmodule // round
diff --git a/fpga/usrp3/lib/dsp/round_reg.v b/fpga/usrp3/lib/dsp/round_reg.v
new file mode 100644
index 000000000..c8c77f518
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/round_reg.v
@@ -0,0 +1,32 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+
+//
+
+// Rounding "macro"
+// Keeps the topmost bits, does proper 2s comp rounding (round-to-zero)
+
+module round_reg
+  #(parameter bits_in=0,
+    parameter bits_out=0)
+    (input clk,
+     input [bits_in-1:0] in,
+     output reg [bits_out-1:0] out,
+     output reg [bits_in-bits_out:0] err);
+
+   wire [bits_out-1:0] temp;
+   wire [bits_in-bits_out:0] err_temp;
+   
+   round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp), .err(err_temp));
+   
+   always @(posedge clk)
+     out <= temp;
+
+   always @(posedge clk)
+     err <= err_temp;
+   
+endmodule // round_reg
diff --git a/fpga/usrp3/lib/dsp/round_sd.v b/fpga/usrp3/lib/dsp/round_sd.v
new file mode 100644
index 000000000..94584f6ef
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/round_sd.v
@@ -0,0 +1,23 @@
+
+
+module round_sd
+  #(parameter WIDTH_IN=18,
+    parameter WIDTH_OUT=16,
+    parameter DISABLE_SD=0)
+   (input clk, input reset,
+    input [WIDTH_IN-1:0] in, input strobe_in,
+    output [WIDTH_OUT-1:0] out, output strobe_out);
+
+   localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1;
+
+   wire [ERR_WIDTH-1:0]  err;
+   wire [WIDTH_IN-1:0] 	 err_ext, sum;
+  
+   sign_extend #(.bits_in(ERR_WIDTH),.bits_out(WIDTH_IN)) ext_err (.in(err), .out(err_ext));
+   
+   add2_and_clip_reg #(.WIDTH(WIDTH_IN)) add2_and_clip_reg
+     (.clk(clk), .rst(reset), .in1(in), .in2((DISABLE_SD == 0) ? err_ext : 0), .strobe_in(strobe_in), .sum(sum), .strobe_out(strobe_out));
+   
+   round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out), .err(err));
+   
+endmodule // round_sd
diff --git a/fpga/usrp3/lib/dsp/rx_dcoffset.v b/fpga/usrp3/lib/dsp/rx_dcoffset.v
new file mode 100644
index 000000000..f74b0f1a0
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/rx_dcoffset.v
@@ -0,0 +1,46 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+
+module rx_dcoffset 
+  #(parameter WIDTH=16,
+    parameter ADDR=8'd0,
+    parameter alpha_shift=20)
+   (input clk, input rst, 
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [WIDTH-1:0] in, output [WIDTH-1:0] out);
+   
+   wire 	      set_now = set_stb & (ADDR == set_addr);
+   
+   reg 		      fixed;  // uses fixed offset
+   wire [WIDTH-1:0]   fixed_dco;
+
+   localparam int_width = WIDTH + alpha_shift;
+   reg [int_width-1:0] integrator;
+   wire [WIDTH-1:0]    quantized;
+
+   always @(posedge clk)
+     if(rst)
+       begin
+	  fixed <= 0;
+	  integrator <= {int_width{1'b0}};
+       end
+     else if(set_now)
+       begin
+	  fixed <= set_data[31];
+	  if(set_data[30])
+	    integrator <= {set_data[29:0],{(int_width-30){1'b0}}};
+       end
+     else if(~fixed)
+       integrator <= integrator +  {{(alpha_shift){out[WIDTH-1]}},out};
+
+   round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
+     (.clk(clk), .reset(rst), .in(integrator), .strobe_in(1'b1), .out(quantized), .strobe_out());
+   
+   add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
+     (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(1'b1), .sum(out), .strobe_out());
+
+endmodule // rx_dcoffset
diff --git a/fpga/usrp3/lib/dsp/rx_frontend.v b/fpga/usrp3/lib/dsp/rx_frontend.v
new file mode 100644
index 000000000..ebe19240c
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/rx_frontend.v
@@ -0,0 +1,78 @@
+
+module rx_frontend
+  #(parameter BASE = 0,
+    parameter IQCOMP_EN = 1)
+   (input clk, input rst,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    input [15:0] adc_a, input adc_ovf_a,
+    input [15:0] adc_b, input adc_ovf_b,
+
+    output [23:0] i_out, output [23:0] q_out,
+    input run,
+    output [31:0] debug
+    );
+   
+   reg [15:0] 	  adc_i, adc_q;
+   wire [17:0] 	  adc_i_ofs, adc_q_ofs;
+   wire [35:0] 	  corr_i, corr_q; wire [17:0] 	  mag_corr,phase_corr;
+   wire 	  swap_iq;
+   
+   setting_reg #(.my_addr(BASE), .width(1)) sr_8
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(swap_iq),.changed());
+
+   always @(posedge clk)
+     if(swap_iq) // Swap
+       {adc_i,adc_q} <= {adc_b,adc_a};
+     else
+       {adc_i,adc_q} <= {adc_a,adc_b};
+       
+   setting_reg #(.my_addr(BASE+1),.width(18)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(mag_corr),.changed());
+   
+   setting_reg #(.my_addr(BASE+2),.width(18)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_corr),.changed());
+
+   generate
+      if(IQCOMP_EN == 1)
+	begin
+	   rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i
+	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+	      .in({adc_i,2'b00}),.out(adc_i_ofs));
+	   
+	   rx_dcoffset #(.WIDTH(18),.ADDR(BASE+4)) rx_dcoffset_q
+	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+	      .in({adc_q,2'b00}),.out(adc_q_ofs));
+	   
+	   MULT18X18S mult_mag_corr
+	     (.P(corr_i), .A(adc_i_ofs), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); 
+	   
+	   MULT18X18S mult_phase_corr
+	     (.P(corr_q), .A(adc_i_ofs), .B(phase_corr), .C(clk), .CE(1), .R(rst) );
+	   
+	   add2_and_clip_reg #(.WIDTH(24)) add_clip_i
+	     (.clk(clk), .rst(rst), 
+	      .in1({adc_i_ofs,6'd0}), .in2(corr_i[35:12]), .strobe_in(1'b1),
+	      .sum(i_out), .strobe_out());
+	   
+	   add2_and_clip_reg #(.WIDTH(24)) add_clip_q
+	     (.clk(clk), .rst(rst), 
+	      .in1({adc_q_ofs,6'd0}), .in2(corr_q[35:12]), .strobe_in(1'b1),
+	      .sum(q_out), .strobe_out());
+	end // if (IQCOMP_EN == 1)
+      else
+	begin
+	   rx_dcoffset #(.WIDTH(24),.ADDR(BASE+3)) rx_dcoffset_i
+	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+	      .in({adc_i,8'b00}),.out(i_out));
+	   
+	   rx_dcoffset #(.WIDTH(24),.ADDR(BASE+4)) rx_dcoffset_q
+	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+	      .in({adc_q,8'b00}),.out(q_out));
+	end // else: !if(IQCOMP_EN == 1)
+      endgenerate
+   
+endmodule // rx_frontend
diff --git a/fpga/usrp3/lib/dsp/rx_frontend_tb.v b/fpga/usrp3/lib/dsp/rx_frontend_tb.v
new file mode 100644
index 000000000..487b72687
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/rx_frontend_tb.v
@@ -0,0 +1,45 @@
+
+`timescale 1ns/1ns
+module rx_frontend_tb();
+   
+   reg clk, rst;
+
+   initial rst = 1;
+   initial #1000 rst = 0;
+   initial clk = 0;
+   always #5 clk = ~clk;
+   
+   initial $dumpfile("rx_frontend_tb.vcd");
+   initial $dumpvars(0,rx_frontend_tb);
+
+   reg [15:0] adc_in;
+   wire [17:0] adc_out;
+
+   always @(posedge clk)
+     begin
+	if(adc_in[13])
+	  $write("-%d,",-adc_in);
+	else
+	  $write("%d,",adc_in);
+	if(adc_out[13])
+	  $write("-%d\n",-adc_out);
+	else
+	  $write("%d\n",adc_out);
+     end	
+   
+   rx_frontend #(.BASE(0)) rx_frontend
+     (.clk(clk),.rst(rst),
+      .set_stb(0),.set_addr(0),.set_data(0),
+      .adc_a(adc_in), .adc_ovf_a(0),
+      .adc_b(0), .adc_ovf_b(0),
+      .i_out(adc_out),.q_out(),
+      .run(), .debug());
+
+   always @(posedge clk)
+     if(rst)
+       adc_in <= 0;
+     else
+       adc_in <= adc_in + 4;
+   //adc_in <= (($random % 473) + 23)/4;
+   
+endmodule // rx_frontend_tb
diff --git a/fpga/usrp3/lib/dsp/sign_extend.v b/fpga/usrp3/lib/dsp/sign_extend.v
new file mode 100644
index 000000000..7c85920aa
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/sign_extend.v
@@ -0,0 +1,23 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+
+//
+
+
+// Sign extension "macro"
+// bits_out should be greater than bits_in
+
+module sign_extend (in,out);
+	parameter bits_in=0;  // FIXME Quartus insists on a default
+	parameter bits_out=0;
+	
+	input [bits_in-1:0] in;
+	output [bits_out-1:0] out;
+	
+	assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
+	
+endmodule
diff --git a/fpga/usrp3/lib/dsp/small_hb_dec.v b/fpga/usrp3/lib/dsp/small_hb_dec.v
new file mode 100644
index 000000000..fc776c2d7
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/small_hb_dec.v
@@ -0,0 +1,124 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+// Short halfband decimator (intended to be followed by another stage)
+// Implements impulse responses of the form [A 0 B 0.5 B 0 A]
+//
+// These taps designed by halfgen4 from ldoolittle:
+//   2 * 131072 * halfgen4(.75/8,2)
+module small_hb_dec
+  #(parameter WIDTH=18)
+    (input clk,
+     input rst,
+     input bypass,
+     input run,
+     input stb_in,
+     input [WIDTH-1:0] data_in,
+     output reg stb_out,
+     output reg [WIDTH-1:0] data_out);
+
+   // Round off inputs to 17 bits because of 18 bit multipliers
+   localparam INTWIDTH = 17;
+   wire [INTWIDTH-1:0] 	data_rnd;
+   wire 		stb_rnd;
+   
+   round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in
+     (.clk(clk),.reset(rst),.in(data_in),.strobe_in(stb_in),.out(data_rnd),.strobe_out(stb_rnd));
+   	
+   
+   reg 			stb_rnd_d1;
+   reg [INTWIDTH-1:0] 	data_rnd_d1;
+   always @(posedge clk) stb_rnd_d1 <= stb_rnd;
+   always @(posedge clk) data_rnd_d1 <= data_rnd;
+   
+   wire 		go;
+   reg 			phase, go_d1, go_d2, go_d3, go_d4;
+   always @(posedge clk)
+     if(rst | ~run)
+       phase <= 0;
+     else if(stb_rnd_d1)
+       phase <= ~phase;
+   assign 		go = stb_rnd_d1 & phase;
+   always @(posedge clk) 
+     if(rst | ~run)
+       begin
+	  go_d1 <= 0;
+	  go_d2 <= 0;
+	  go_d3 <= 0;
+	  go_d4 <= 0;
+       end
+     else
+       begin
+	  go_d1 <= go;
+	  go_d2 <= go_d1;
+	  go_d3 <= go_d2;
+	  go_d4 <= go_d3;
+       end
+
+   wire [17:0] 		coeff_a = -10690;
+   wire [17:0] 		coeff_b = 75809;
+   
+   reg [INTWIDTH-1:0] 	d1, d2, d3, d4 , d5, d6;
+   always @(posedge clk)
+     if(stb_rnd_d1 | rst)
+       begin
+	  d1 <= data_rnd_d1;
+	  d2 <= d1;
+	  d3 <= d2;
+	  d4 <= d3;
+	  d5 <= d4;
+	  d6 <= d5;
+       end
+
+   reg [17:0] sum_a, sum_b, middle, middle_d1;
+
+   always @(posedge clk)
+     if(go)
+       begin
+	  sum_a <= {data_rnd_d1[INTWIDTH-1],data_rnd_d1} + {d6[INTWIDTH-1],d6};
+	  sum_b <= {d2[INTWIDTH-1],d2} + {d4[INTWIDTH-1],d4};
+	  //middle <= {d3[INTWIDTH-1],d3};
+	  middle <= {d3,1'b0};
+       end
+
+   always @(posedge clk)
+     if(go_d1)
+       middle_d1 <= middle;
+   
+   wire [17:0] sum = go_d1 ? sum_b : sum_a;
+   wire [17:0] coeff = go_d1 ? coeff_b : coeff_a;
+   wire [35:0] 	 prod;   
+   MULT18X18S mult(.C(clk), .CE(go_d1 | go_d2), .R(rst), .P(prod), .A(coeff), .B(sum) );
+
+   localparam ACCWIDTH = 30;
+   reg [ACCWIDTH-1:0] 	 accum;
+   
+   always @(posedge clk)
+     if(rst)
+       accum <= 0;
+     else if(go_d2)
+       accum <= {middle_d1[17],middle_d1[17],middle_d1,{(16+ACCWIDTH-36){1'b0}}} + {prod[35:36-ACCWIDTH]};
+     else if(go_d3)
+       accum <= accum + {prod[35:36-ACCWIDTH]};
+   
+   wire [WIDTH:0] 	 accum_rnd;
+   wire [WIDTH-1:0] 	 accum_rnd_clip;
+   
+   wire 	 stb_round;
+   
+   round_sd #(.WIDTH_IN(ACCWIDTH),.WIDTH_OUT(WIDTH+1)) round_acc 
+     (.clk(clk), .reset(rst), .in(accum), .strobe_in(go_d4), .out(accum_rnd), .strobe_out(stb_round));
+
+   clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip (.in(accum_rnd), .out(accum_rnd_clip));
+   
+   // Output
+   always @(posedge clk)
+     begin
+	stb_out  <= bypass ? stb_in : stb_round;
+	data_out <= bypass ? data_in : accum_rnd_clip;
+     end
+
+
+endmodule // small_hb_dec
diff --git a/fpga/usrp3/lib/dsp/small_hb_int.v b/fpga/usrp3/lib/dsp/small_hb_int.v
new file mode 100644
index 000000000..4b03b5d0c
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/small_hb_int.v
@@ -0,0 +1,99 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+// Short halfband decimator (intended to be followed by another stage)
+// Implements impulse responses of the form [A 0 B 0.5 B 0 A]
+//
+// These taps designed by halfgen4 from ldoolittle:
+//   2 * 131072 * halfgen4(.75/8,2)
+
+module small_hb_int
+  #(parameter WIDTH=18)
+    (input clk,
+     input rst,
+     input bypass,
+     input stb_in,
+     input [WIDTH-1:0] data_in,
+     input [7:0] output_rate,
+     input stb_out,
+     output reg [WIDTH-1:0] data_out);
+
+  
+   reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6;
+
+   localparam 	   MWIDTH = 36;
+   wire [MWIDTH-1:0] prod;
+
+   reg [6:0] 	     stbin_d;
+   
+   always @(posedge clk)
+     stbin_d <= {stbin_d[5:0],stb_in};
+   
+   always @(posedge clk)
+     if (rst) 
+       begin
+	  d1 <= 0;
+	  d2 <= 0;
+	  d3 <= 0;
+	  d4 <= 0;
+	  d5 <= 0;
+	  d6 <= 0;
+       end
+     else if(stb_in)
+       begin
+	  d1 <= data_in;
+	  d2 <= d1;
+	  d3 <= d2;
+	  d4 <= d3;
+	  d5 <= d4;
+	  d6 <= d5;
+       end
+
+   wire [WIDTH-1:0] sum_outer, sum_inner;
+   add2_and_round_reg #(.WIDTH(WIDTH)) add_outer (.clk(clk),.in1(d1),.in2(d4),.sum(sum_outer));
+   add2_and_round_reg #(.WIDTH(WIDTH)) add_inner (.clk(clk),.in1(d2),.in2(d3),.sum(sum_inner));
+
+   wire [17:0] 	   coeff_outer = -10690;
+   wire [17:0] 	   coeff_inner = 75809;
+
+   MULT18X18S mult(.C(clk), .CE(1), .R(rst), .P(prod), .A(stbin_d[1] ? coeff_outer : coeff_inner), 
+		   .B(stbin_d[1] ? sum_outer : sum_inner) );
+
+   wire [MWIDTH:0] accum;
+   acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1)) 
+     acc (.clk(clk),.clear(stbin_d[2]),.acc(|stbin_d[3:2]),.in(prod),.out(accum));
+   
+   wire [WIDTH+2:0] 	 accum_rnd;
+   round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH+3))
+     final_round (.clk(clk),.in(accum),.out(accum_rnd));
+
+   wire [WIDTH-1:0] 	 clipped;
+   clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH)) final_clip
+     (.clk(clk),.in(accum_rnd),.strobe_in(1'b1), .out(clipped));
+
+   reg [WIDTH-1:0] 	 saved, saved_d3;
+   always @(posedge clk)
+     if(stbin_d[6])
+       saved <= clipped;
+
+   always @(posedge clk)
+     if(stbin_d[3])
+       saved_d3 <= d3;
+	   
+   always @(posedge clk)
+     if(bypass)
+       data_out <= data_in;
+     else if(stb_in & stb_out)
+       case(output_rate)
+	 1 : data_out <= d6; 
+	 2 : data_out <= d4;
+	 3, 4, 5, 6, 7 : data_out <= d3;
+	 default : data_out <= d2;
+       endcase // case(output_rate)
+     else if(stb_out)
+       data_out <= saved;
+
+endmodule // small_hb_int
+
diff --git a/fpga/usrp3/lib/dsp/srl.v b/fpga/usrp3/lib/dsp/srl.v
new file mode 100644
index 000000000..bbd8ac1c9
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/srl.v
@@ -0,0 +1,27 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+module srl
+  #(parameter WIDTH=18)
+    (input clk,
+     input rst,
+     input write,
+     input [WIDTH-1:0] in,
+     input [3:0] addr,
+     output [WIDTH-1:0] out);
+   
+   genvar 		i;
+   generate
+      for (i=0;i<WIDTH;i=i+1)
+	begin : gen_srl
+	   SRL16E
+	     srl16e(.Q(out[i]),
+		    .A0(addr[0]),.A1(addr[1]),.A2(addr[2]),.A3(addr[3]),
+		    .CE(write|rst),.CLK(clk),.D(in[i]));
+	end
+   endgenerate
+
+endmodule // srl
diff --git a/fpga/usrp3/lib/fifo/Makefile.srcs b/fpga/usrp3/lib/fifo/Makefile.srcs
new file mode 100644
index 000000000..ffe2484f8
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/Makefile.srcs
@@ -0,0 +1,20 @@
+#
+# Copyright 2012-2013 Ettus Research LLC
+#
+
+##################################################
+# FIFO Sources
+##################################################
+FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/fifo/, \
+axi_mux4.v \
+axi_mux8.v \
+axi_demux4.v \
+axi_demux8.v \
+axi_fifo_short.v \
+axi_packet_gate.v \
+axi_fifo.v \
+axi_fifo64_to_fifo32.v \
+axi_fifo32_to_fifo64.v \
+axi_fifo_2clk.v \
+axi_loopback.v \
+))
diff --git a/fpga/usrp3/lib/fifo/axi_demux4.v b/fpga/usrp3/lib/fifo/axi_demux4.v
new file mode 100644
index 000000000..c613b064d
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_demux4.v
@@ -0,0 +1,77 @@
+
+// Copyright 2012 Ettus Research LLC
+// axi_demux -- takes one AXI stream, sends to one of 4 output channels
+//   Choice of output channel is by external logic based on first line of packet ("header" port)
+//   If compressed vita data, this line contains vita header and streamid.
+
+module axi_demux4
+  #(parameter ACTIVE_CHAN = 4'b1111,  // ACTIVE_CHAN is a map of connected outputs
+    parameter WIDTH = 64,
+    parameter BUFFER=0)
+   (input clk, input reset, input clear,
+    output [WIDTH-1:0] header, input [1:0] dest,
+    input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [WIDTH-1:0] o0_tdata, output o0_tlast, output o0_tvalid, input o0_tready,
+    output [WIDTH-1:0] o1_tdata, output o1_tlast, output o1_tvalid, input o1_tready,
+    output [WIDTH-1:0] o2_tdata, output o2_tlast, output o2_tvalid, input o2_tready,
+    output [WIDTH-1:0] o3_tdata, output o3_tlast, output o3_tvalid, input o3_tready);
+
+   wire [WIDTH-1:0]    i_tdata_int;
+   wire 	       i_tlast_int, i_tvalid_int, i_tready_int;
+
+   generate
+      if(BUFFER == 0)
+	begin
+	   assign i_tdata_int = i_tdata;
+	   assign i_tlast_int = i_tlast;
+	   assign i_tvalid_int = i_tvalid;
+	   assign i_tready = i_tready_int;
+	end
+      else
+	axi_fifo_short #(.WIDTH(WIDTH+1)) axi_fifo_short
+	  (.clk(clk), .reset(reset), .clear(clear),
+	   .i_tdata({i_tlast,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+	   .o_tdata({i_tlast_int,i_tdata_int}), .o_tvalid(i_tvalid_int), .o_tready(i_tready_int),
+	   .space(), .occupied());
+   endgenerate
+
+   reg [3:0] 	  dm_state;
+   localparam DM_IDLE = 4'b0000;
+   localparam DM_0    = 4'b0001;
+   localparam DM_1    = 4'b0010;
+   localparam DM_2    = 4'b0100;
+   localparam DM_3    = 4'b1000;
+
+   assign header = i_tdata_int;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       dm_state <= DM_IDLE;
+     else
+       case (dm_state)
+	 DM_IDLE :
+	   if(i_tvalid_int)
+	     case(dest)
+	       2'b00 : dm_state <= DM_0;
+	       2'b01 : dm_state <= DM_1;
+	       2'b10 : dm_state <= DM_2;
+	       2'b11 : dm_state <= DM_3;
+	     endcase // case (i_tdata[1:0])
+	 
+	 DM_0, DM_1, DM_2, DM_3 :
+	   if(i_tvalid_int & i_tready_int & i_tlast_int)
+	     dm_state <= DM_IDLE;
+	 
+	 default :
+	   dm_state <= DM_IDLE;
+       endcase // case (dm_state)
+
+   assign {o3_tvalid, o2_tvalid, o1_tvalid, o0_tvalid} = dm_state & {4{i_tvalid_int}};
+   assign i_tready_int = |(dm_state & ({o3_tready, o2_tready, o1_tready, o0_tready} | ~ACTIVE_CHAN));
+      
+   assign {o0_tlast, o0_tdata} = {i_tlast_int, i_tdata_int};
+   assign {o1_tlast, o1_tdata} = {i_tlast_int, i_tdata_int};
+   assign {o2_tlast, o2_tdata} = {i_tlast_int, i_tdata_int};
+   assign {o3_tlast, o3_tdata} = {i_tlast_int, i_tdata_int};
+   
+endmodule // axi_demux4
diff --git a/fpga/usrp3/lib/fifo/axi_demux8.v b/fpga/usrp3/lib/fifo/axi_demux8.v
new file mode 100644
index 000000000..9aa51674d
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_demux8.v
@@ -0,0 +1,60 @@
+
+// Copyright 2012 Ettus Research LLC
+// axi_demux -- takes one AXI stream, sends to one of 8 output channels
+//   Choice of output channel is by external logic based on first line of packet ("header" port)
+//   If compressed vita data, this line contains vita header and streamid.
+
+module axi_demux8 #(
+   parameter ACTIVE_CHAN = 8'b11111111,  // ACTIVE_CHAN is a map of connected outputs
+   parameter WIDTH = 64,
+   parameter BUFFER=0
+) (
+   input clk, input reset, input clear,
+   output [WIDTH-1:0] header, input [2:0] dest,
+   input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+   output [WIDTH-1:0] o0_tdata, output o0_tlast, output o0_tvalid, input o0_tready,
+   output [WIDTH-1:0] o1_tdata, output o1_tlast, output o1_tvalid, input o1_tready,
+   output [WIDTH-1:0] o2_tdata, output o2_tlast, output o2_tvalid, input o2_tready,
+   output [WIDTH-1:0] o3_tdata, output o3_tlast, output o3_tvalid, input o3_tready,
+   output [WIDTH-1:0] o4_tdata, output o4_tlast, output o4_tvalid, input o4_tready,
+   output [WIDTH-1:0] o5_tdata, output o5_tlast, output o5_tvalid, input o5_tready,
+   output [WIDTH-1:0] o6_tdata, output o6_tlast, output o6_tvalid, input o6_tready,
+   output [WIDTH-1:0] o7_tdata, output o7_tlast, output o7_tvalid, input o7_tready
+);
+
+   wire [WIDTH-1:0]  i_tdata_int0, i_tdata_int1;
+   wire              i_tlast_int0, i_tlast_int1;
+   wire              i_tvalid_int0, i_tvalid_int1;
+   wire              i_tready_int0, i_tready_int1;
+
+   axi_demux4 #(.ACTIVE_CHAN({2'b00, (|(ACTIVE_CHAN[7:4])), (|(ACTIVE_CHAN[3:0]))}), .WIDTH(WIDTH), .BUFFER(BUFFER)) demux2 (
+      .clk(clk), .reset(reset), .clear(clear),
+      .header(header), .dest({1'b0, dest[2]}),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o0_tdata(i_tdata_int0), .o0_tlast(i_tlast_int0), .o0_tvalid(i_tvalid_int0), .o0_tready(i_tready_int0),
+      .o1_tdata(i_tdata_int1), .o1_tlast(i_tlast_int1), .o1_tvalid(i_tvalid_int1), .o1_tready(i_tready_int1),
+      .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b0),
+      .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b0)
+   );
+
+   axi_demux4 #(.ACTIVE_CHAN(ACTIVE_CHAN[3:0]), .WIDTH(WIDTH), .BUFFER(0)) demux4_int0 (
+      .clk(clk), .reset(reset), .clear(clear),
+      .header(), .dest(dest[1:0]),
+      .i_tdata(i_tdata_int0), .i_tlast(i_tlast_int0), .i_tvalid(i_tvalid_int0), .i_tready(i_tready_int0),
+      .o0_tdata(o0_tdata), .o0_tlast(o0_tlast), .o0_tvalid(o0_tvalid), .o0_tready(o0_tready),
+      .o1_tdata(o1_tdata), .o1_tlast(o1_tlast), .o1_tvalid(o1_tvalid), .o1_tready(o1_tready),
+      .o2_tdata(o2_tdata), .o2_tlast(o2_tlast), .o2_tvalid(o2_tvalid), .o2_tready(o2_tready),
+      .o3_tdata(o3_tdata), .o3_tlast(o3_tlast), .o3_tvalid(o3_tvalid), .o3_tready(o3_tready)
+   );
+
+   axi_demux4 #(.ACTIVE_CHAN(ACTIVE_CHAN[7:4]), .WIDTH(WIDTH), .BUFFER(0)) demux4_int1 (
+      .clk(clk), .reset(reset), .clear(clear),
+      .header(), .dest(dest[1:0]),
+      .i_tdata(i_tdata_int1), .i_tlast(i_tlast_int1), .i_tvalid(i_tvalid_int1), .i_tready(i_tready_int1),
+      .o0_tdata(o4_tdata), .o0_tlast(o4_tlast), .o0_tvalid(o4_tvalid), .o0_tready(o4_tready),
+      .o1_tdata(o5_tdata), .o1_tlast(o5_tlast), .o1_tvalid(o5_tvalid), .o1_tready(o5_tready),
+      .o2_tdata(o6_tdata), .o2_tlast(o6_tlast), .o2_tvalid(o6_tvalid), .o2_tready(o6_tready),
+      .o3_tdata(o7_tdata), .o3_tlast(o7_tlast), .o3_tvalid(o7_tvalid), .o3_tready(o7_tready)
+   );
+   
+endmodule // axi_demux4
diff --git a/fpga/usrp3/lib/fifo/axi_fifo.v b/fpga/usrp3/lib/fifo/axi_fifo.v
new file mode 100644
index 000000000..2f42fc181
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo.v
@@ -0,0 +1,169 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+//
+
+
+
+// Block RAM AXI fifo
+
+// Special case SIZE <= 5 uses a short fifo
+
+module axi_fifo
+  #(parameter WIDTH=32, SIZE=9)
+   (input clk, input reset, input clear,
+    input [WIDTH-1:0] i_tdata,
+    input i_tvalid,
+    output i_tready,
+    output [WIDTH-1:0] o_tdata,
+    output o_tvalid,
+    input o_tready,
+    
+    output reg [15:0] space,
+    output reg [15:0] occupied);
+
+    generate
+    if(SIZE<=5) begin
+        wire [5:0] space_short, occupied_short;
+        axi_fifo_short #(.WIDTH(WIDTH)) fifo_short
+        (
+            .clk(clk), .reset(reset), .clear(clear),
+            .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
+            .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
+            .space(space_short), .occupied(occupied_short)
+        );
+        always @* space <= {10'b0, space_short};
+        always @* occupied <= {10'b0, occupied_short};
+    end
+    else begin
+
+   wire 	      write 	     = i_tvalid & i_tready;
+   wire 	      read 	     = o_tvalid & o_tready;
+   wire 	      full, empty;
+   
+   assign i_tready  = ~full;
+   assign o_tvalid  = ~empty;
+   
+   // Read side states
+   localparam 	  EMPTY = 0;
+   localparam 	  PRE_READ = 1;
+   localparam 	  READING = 2;
+
+   reg [SIZE-1:0] wr_addr, rd_addr;
+   reg [1:0] 	  read_state;
+
+   reg 	  empty_reg, full_reg;
+   always @(posedge clk)
+     if(reset)
+       wr_addr <= 0;
+     else if(clear)
+       wr_addr <= 0;
+     else if(write)
+       wr_addr <= wr_addr + 1;
+
+   ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
+     ram (.clka(clk),
+	  .ena(1'b1),
+	  .wea(write),
+	  .addra(wr_addr),
+	  .dia(i_tdata),
+	  .doa(),
+
+	  .clkb(clk),
+	  .enb((read_state==PRE_READ)|read),
+	  .web(1'b0),
+	  .addrb(rd_addr),
+	  .dib({WIDTH{1'b1}}),
+	  .dob(o_tdata));
+
+   always @(posedge clk)
+     if(reset)
+       begin
+	  read_state <= EMPTY;
+	  rd_addr <= 0;
+	  empty_reg <= 1;
+       end
+     else
+       if(clear)
+	 begin
+	    read_state <= EMPTY;
+	    rd_addr <= 0;
+	    empty_reg <= 1;
+	 end
+       else 
+	 case(read_state)
+	   EMPTY :
+	     if(write)
+	       begin
+		  //rd_addr <= wr_addr;
+		  read_state <= PRE_READ;
+	       end
+	   PRE_READ :
+	     begin
+		read_state <= READING;
+		empty_reg <= 0;
+		rd_addr <= rd_addr + 1;
+	     end
+	   
+	   READING :
+	     if(read)
+	       if(rd_addr == wr_addr)
+		 begin
+		    empty_reg <= 1; 
+		    if(write)
+		      read_state <= PRE_READ;
+		    else
+		      read_state <= EMPTY;
+		 end
+	       else
+		 rd_addr <= rd_addr + 1;
+	 endcase // case(read_state)
+
+   wire [SIZE-1:0] dont_write_past_me = rd_addr - 2;
+   wire 	   becoming_full = wr_addr == dont_write_past_me;
+     
+   always @(posedge clk)
+     if(reset)
+       full_reg <= 0;
+     else if(clear)
+       full_reg <= 0;
+     else if(read & ~write)
+       full_reg <= 0;
+     //else if(write & ~read & (wr_addr == (rd_addr-3)))
+     else if(write & ~read & becoming_full)
+       full_reg <= 1;
+
+   //assign empty = (read_state != READING);
+   assign empty = empty_reg;
+
+   // assign full = ((rd_addr - 1) == wr_addr);
+   assign full = full_reg;
+
+   //////////////////////////////////////////////
+   // space and occupied are for diagnostics only
+   // not guaranteed exact
+
+   localparam NUMLINES = (1<<SIZE);
+   always @(posedge clk)
+     if(reset)
+       space <= NUMLINES;
+     else if(clear)
+       space <= NUMLINES;
+     else if(read & ~write)
+       space <= space + 16'b1;
+     else if(write & ~read)
+       space <= space - 16'b1;
+   
+   always @(posedge clk)
+     if(reset)
+       occupied <= 16'b0;
+     else if(clear)
+       occupied <= 16'b0;
+     else if(read & ~write)
+       occupied <= occupied - 16'b1;
+     else if(write & ~read)
+       occupied <= occupied + 16'b1;
+
+    end
+    endgenerate
+
+endmodule // fifo_long
diff --git a/fpga/usrp3/lib/fifo/axi_fifo32_to_fifo64.v b/fpga/usrp3/lib/fifo/axi_fifo32_to_fifo64.v
new file mode 100644
index 000000000..1df69d449
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo32_to_fifo64.v
@@ -0,0 +1,38 @@
+
+module axi_fifo32_to_fifo64
+  (input clk, input reset, input clear,
+   input [31:0] i_tdata, input [1:0] i_tuser, input i_tlast, input i_tvalid, output i_tready,
+   output [63:0] o_tdata, output [2:0] o_tuser, output o_tlast, output o_tvalid, input o_tready
+   );
+
+   reg [31:0] 	 holding;
+
+   reg 		 state;
+
+   always @(posedge clk)
+     if(reset | clear)
+       state <= 0;
+     else
+       if(i_tvalid & i_tready)
+       case(state)
+	 0 : if(~i_tlast) state <= 1'b1;
+    	 1 : state <= 1'b0;
+	 default : state <= 1'b0;
+       endcase // case (state)
+
+   always @(posedge clk)
+     if(i_tvalid & i_tready)
+       holding <= i_tdata;
+   
+   assign i_tready = (state == 0 && !i_tlast)? 1'b1 : o_tready;
+   assign o_tvalid = (state == 0 && !i_tlast)? 1'b0 : i_tvalid;
+   
+   assign o_tdata = (state == 0) ? {i_tdata, 32'h0} : { holding, i_tdata };
+   assign o_tlast = i_tlast;
+
+   wire [2:0] 	 occ_in = (i_tuser == 0) ? 3'd4 : {1'b0, i_tuser};
+   wire [2:0] 	 occ_out = (state == 0) ? occ_in : (occ_in + 3'd4);
+   
+   assign o_tuser = ~o_tlast ? 3'd0 : occ_out;
+   	 
+endmodule // axi_fifo32_to_fifo64
diff --git a/fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v b/fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v
new file mode 100644
index 000000000..46b021600
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v
@@ -0,0 +1,31 @@
+
+module axi_fifo64_to_fifo32
+  (input clk, input reset, input clear,
+   input [63:0] i_tdata, input [2:0] i_tuser, input i_tlast, input i_tvalid, output i_tready,
+   output [31:0] o_tdata, output [1:0] o_tuser, output o_tlast, output o_tvalid, input o_tready
+   );
+
+   wire 	 short_last = i_tlast & ((i_tuser == 3'd1) | (i_tuser == 3'd2) | (i_tuser == 3'd3) | (i_tuser == 3'd4));
+   
+   reg 		 state;
+   always @(posedge clk)
+     if(reset | clear)
+       state <= 1'b0;
+     else
+       if(i_tvalid & o_tready)
+	 case(state)
+	   1'b0 :
+	     if(~short_last)
+	       state <= 1'b1;
+	   1'b1 :
+	     state <= 1'b0;
+	 endcase // case (state)
+   
+   assign o_tdata = (state == 0) ? i_tdata[63:32] : i_tdata[31:0];
+   assign o_tuser = o_tlast ? i_tuser[1:0] : 2'd0;
+   assign o_tlast = i_tlast & ((state == 1'b1) | short_last);
+
+   assign o_tvalid = i_tvalid;
+   assign i_tready = o_tready & ((state == 1'b1) | short_last);
+   		    
+endmodule // axi_fifo64_to_fifo32
diff --git a/fpga/usrp3/lib/fifo/axi_fifo_2clk.v b/fpga/usrp3/lib/fifo/axi_fifo_2clk.v
new file mode 100644
index 000000000..f9f7beb88
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo_2clk.v
@@ -0,0 +1,88 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+// Special case SIZE <= 5 uses a short fifo
+
+module axi_fifo_2clk
+  #(parameter WIDTH=69, SIZE=9)
+   (input reset,
+    input i_aclk,
+    input [WIDTH-1:0] i_tdata,
+    input i_tvalid,
+    output i_tready,
+    input o_aclk,
+    output [WIDTH-1:0] o_tdata,
+    output o_tvalid,
+    input o_tready);
+   
+   wire   write, read, empty, full;
+   assign i_tready = ~full;
+   assign write = i_tvalid & i_tready;
+
+   wire [71:0] tdata_int;
+   wire tvalid_int, tready_int;
+   assign tvalid_int = ~empty;
+   assign read = tvalid_int & tready_int;
+
+    wire [71:0] wr_data;
+    assign wr_data[WIDTH-1:0] = i_tdata;
+    wire [71:0] rd_data;
+    assign tdata_int = rd_data[WIDTH-1:0];
+
+    generate
+      if(WIDTH<72) begin
+        assign wr_data[71:WIDTH] = 0;
+      end
+    endgenerate
+
+   generate
+      if(SIZE<=5)
+	fifo_short_2clk fifo_short_2clk
+	      (.rst(reset),
+	       .wr_clk(i_aclk),
+	       .din(wr_data), // input [71 : 0] din
+	       .wr_en(write), // input wr_en
+	       .full(full), // output full
+	       .wr_data_count(), // output [9 : 0] wr_data_count
+	       
+	       .rd_clk(o_aclk), // input rd_clk
+	       .dout(rd_data), // output [71 : 0] dout
+	       .rd_en(read), // input rd_en
+	       .empty(empty), // output empty
+	       .rd_data_count()  // output [9 : 0] rd_data_count
+	       );
+      else
+	fifo_4k_2clk fifo_4k_2clk
+	  (.rst(reset),
+	   .wr_clk(i_aclk),
+	   .din(wr_data), // input [71 : 0] din
+	   .wr_en(write), // input wr_en
+	   .full(full), // output full
+	   .wr_data_count(), // output [9 : 0] wr_data_count
+	   
+	   .rd_clk(o_aclk), // input rd_clk
+	   .dout(rd_data), // output [71 : 0] dout
+	   .rd_en(read), // input rd_en
+	   .empty(empty), // output empty
+	   .rd_data_count()  // output [9 : 0] rd_data_count
+	   );
+   endgenerate
+   
+   generate
+      if(SIZE>9)
+	axi_fifo #(.WIDTH(WIDTH), .SIZE(SIZE)) fifo_1clk
+	  (.clk(o_aclk), .reset(reset), .clear(1'b0),
+	   .i_tdata(tdata_int), .i_tvalid(tvalid_int), .i_tready(tready_int),
+	   .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
+	   .space(), .occupied());
+      else
+	begin
+	   assign o_tdata = tdata_int;
+	   assign o_tvalid = tvalid_int;
+	   assign tready_int = o_tready;
+	end
+   endgenerate
+   
+endmodule // axi_fifo_2clk
diff --git a/fpga/usrp3/lib/fifo/axi_fifo_32_64_tb.v b/fpga/usrp3/lib/fifo/axi_fifo_32_64_tb.v
new file mode 100644
index 000000000..9b104f1d9
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo_32_64_tb.v
@@ -0,0 +1,114 @@
+`timescale 1ns/1ps
+
+module axi_fifo_32_64_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("axi_fifo_32_64_tb.vcd");
+   initial $dumpvars(0,axi_fifo_32_64_tb);
+
+   task send_packet;
+      input [63:0] data_start;
+      input [2:0]  user;
+      input [31:0] len;
+      
+      begin
+	 @(posedge clk);
+	 {i_tuser, i_tlast, i_tdata} <= { 3'd0, 1'b0, data_start };
+	 repeat(len-1)
+	   begin
+	      i_tvalid <= 1;
+	      @(posedge clk);
+	      i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
+	   end
+	 i_tuser <= user;
+	 i_tlast <= 1;
+	 @(posedge clk);
+	 i_tvalid <= 1'b0;
+	 @(posedge clk);
+      end
+   endtask // send_packet
+   
+   initial
+     begin
+	#1000 reset = 0;
+	#200000;
+	$finish;
+     end
+   
+   reg [63:0] i_tdata;
+   reg [2:0]  i_tuser;
+   reg 	      i_tlast;
+   reg 	      i_tvalid;
+   wire       i_tready;
+
+   wire [63:0] i_tdata_int;
+   wire [2:0]  i_tuser_int;
+   wire        i_tlast_int, i_tvalid_int, i_tready_int;
+
+   wire [63:0] o_tdata;
+   wire [31:0] o_tdata_int, o_tdata_int2;
+   wire [2:0]  o_tuser;
+   wire [1:0]  o_tuser_int, o_tuser_int2;
+   wire        o_tlast, o_tlast_int, o_tvalid, o_tvalid_int, o_tready, o_tready_int;
+   wire        o_tlast_int2, o_tvalid_int2, o_tready_int2;
+   
+   localparam RPT_COUNT = 16;
+   
+   initial
+     begin
+	i_tvalid <= 0;
+	
+	while(reset)
+	  @(posedge clk);
+	@(posedge clk);
+
+	send_packet(64'hA0000000_A0000001, 3'd7, 4);
+	@(posedge clk);
+     end // initial begin
+
+   axi_fifo #(.WIDTH(68), .SIZE(10)) fifo
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({i_tlast,i_tuser,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata({i_tlast_int,i_tuser_int,i_tdata_int}), .o_tvalid(i_tvalid_int), .o_tready(i_tready_int));
+
+   axi_fifo64_to_fifo32 dut
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(i_tdata_int), .i_tuser(i_tuser_int), .i_tlast(i_tlast_int), .i_tvalid(i_tvalid_int), .i_tready(i_tready_int),
+      .o_tdata(o_tdata_int), .o_tuser(o_tuser_int), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int));
+
+   /*
+   axi_fifo #(.WIDTH(35), .SIZE(10)) fifo_middle
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({o_tlast_int,o_tuser_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+      .o_tdata({o_tlast_int2,o_tuser_int2,o_tdata_int2}), .o_tvalid(o_tvalid_int2), .o_tready(o_tready_int2));
+*/
+   assign o_tdata_int2 = o_tdata_int;
+   assign o_tlast_int2 = o_tlast_int;
+   assign o_tuser_int2 = o_tuser_int;
+   assign o_tvalid_int2 = o_tvalid_int;
+   assign o_tready_int = o_tready_int2;
+   
+   axi_fifo32_to_fifo64 dut2
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(o_tdata_int2), .i_tuser(o_tuser_int2), .i_tlast(o_tlast_int2), .i_tvalid(o_tvalid_int2), .i_tready(o_tready_int2),
+      .o_tdata(o_tdata), .o_tuser(o_tuser), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+   assign o_tready = 1'b1;
+   
+   always @(posedge clk)
+     if(i_tvalid & i_tready)
+       $display("IN: TUSER %x\tTLAST %x\tTDATA %x", i_tuser, i_tlast, i_tdata);
+
+   always @(posedge clk)
+     if(o_tvalid_int & o_tready_int)
+       $display("\t\t\t\t\t\tMIDDLE: TUSER %x\tTLAST %x\tTDATA %x", o_tuser_int, o_tlast_int, o_tdata_int);
+
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       $display("\t\t\t\t\t\t\t\t\t\t\tOUT: TUSER %x\tTLAST %x\tTDATA %x", o_tuser, o_tlast, o_tdata);
+
+endmodule // axi_fifo_32_64_tb
diff --git a/fpga/usrp3/lib/fifo/axi_fifo_short.v b/fpga/usrp3/lib/fifo/axi_fifo_short.v
new file mode 100644
index 000000000..e13993199
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo_short.v
@@ -0,0 +1,110 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+
+
+//
+// 32 word FIFO with AXI4-STREAM interface.
+//
+// NOTE: This module uses the SRLC32E primitive explicitly and as such
+// can only be used with Xilinx technology of the VIRTEX-6/SPARTAN-6/SIERIES-7 or newer.
+//
+
+module axi_fifo_short
+  #(parameter WIDTH=32)
+   (
+    input clk, 
+    input reset, 
+    input clear,
+    input [WIDTH-1:0] i_tdata,
+    input i_tvalid,
+    output i_tready,
+    output [WIDTH-1:0] o_tdata,
+    output o_tvalid,
+    input o_tready,
+    
+    output reg [5:0] space,
+    output reg [5:0] occupied
+    );
+
+   reg full, empty;
+   wire write 	     = i_tvalid & i_tready;
+   wire read 	     = o_tready & o_tvalid;
+
+   assign i_tready  = ~full;
+   assign o_tvalid  = ~empty;
+   
+   reg [4:0] 	  a;
+   genvar 	  i; 
+   
+   generate
+      for (i=0;i<WIDTH;i=i+1)
+	begin : gen_srlc32e
+	   SRLC32E
+	     srlc32e(.Q(o_tdata[i]), .Q31(),
+		     .A(a), //.A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),.A4(a[4]),
+		    .CE(write),.CLK(clk),.D(i_tdata[i]));
+	end
+   endgenerate
+   
+   always @(posedge clk)
+     if(reset)
+       begin
+	  a <= 0;
+	  empty <= 1;
+	  full <= 0;
+       end
+     else if(clear)
+       begin
+	  a <= 0;
+	  empty <= 1;
+	  full<= 0;
+       end
+     else if(read & ~write)
+       begin
+	  full <= 0;
+	  if(a==0)
+	    empty <= 1;
+	  else
+	    a <= a - 1;
+       end
+     else if(write & ~read)
+       begin
+	  empty <= 0;
+	  if(~empty)
+	    a <= a + 1;
+	  if(a == 30)
+	    full <= 1;
+       end
+
+   // NOTE will fail if you write into a full fifo or read from an empty one
+
+   //////////////////////////////////////////////////////////////
+   // space and occupied are used for diagnostics, not 
+   // guaranteed correct
+   
+   //assign space = full ? 0 : empty ? 16 : 15-a;
+   //assign occupied = empty ? 0 : full ? 16 : a+1;
+
+   always @(posedge clk)
+     if(reset)
+       space <= 6'd32;
+     else if(clear)
+       space <= 6'd32;
+     else if(read & ~write)
+       space <= space + 6'd1;
+     else if(write & ~read)
+       space <= space - 6'd1;
+   
+   always @(posedge clk)
+     if(reset)
+       occupied <= 6'd0;
+     else if(clear)
+       occupied <= 6'd0;
+     else if(read & ~write)
+       occupied <= occupied - 6'd1;
+     else if(write & ~read)
+       occupied <= occupied + 6'd1;
+      
+endmodule // axi_fifo_short
+
diff --git a/fpga/usrp3/lib/fifo/axi_fifo_tb.v b/fpga/usrp3/lib/fifo/axi_fifo_tb.v
new file mode 100644
index 000000000..cb0e26ac5
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_fifo_tb.v
@@ -0,0 +1,211 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+//
+
+
+module axi_fifo_tb();
+   
+   reg clk, reset;
+   reg read_flag, write_flag;
+   
+   reg error;
+   reg [7:0] i_tdata, o_tdata_ref;
+   wire [7:0] o_tdata;
+   reg 	      i_tvalid, o_tready;
+   wire       o_tvalid, i_tready;
+   wire [15:0] space, occupied;
+
+   always
+     #100 clk = ~clk;
+
+   initial clk = 0;
+   
+ 
+   axi_fifo 
+     #(
+       .WIDTH(8),
+       .SIZE(8)
+       )
+       dut
+	 (.clk(clk),
+	  .reset(reset),
+	  .clear(1'b0),
+	  .i_tdata(i_tdata),
+	  .i_tvalid(i_tvalid),
+	  .i_tready(i_tready),
+	  .o_tdata(o_tdata),
+	  .o_tvalid(o_tvalid),
+	  .o_tready(o_tready),    
+	  .space(space),
+	  .occupied(occupied)
+	  );
+
+
+   task write;
+      begin
+	 write_flag <= 1;
+	 i_tvalid <= 1'b1;	
+	 #1; 
+	 while (i_tready != 1'b1)
+	   @(posedge clk);
+	 #1;
+	 @(posedge clk);
+	 write_flag <= 0;
+	 i_tvalid <= 1'b0;
+	 i_tdata <= i_tdata + 8'h1;
+      end
+   endtask // write
+
+   task read;
+      begin
+	 read_flag <= 1;
+	 o_tready <= 1'b1;
+	 #1;
+	 while (o_tvalid != 1'b1)
+	    @(posedge clk);
+	 #1;
+	 @(posedge clk);
+	 read_flag <= 0;
+	 o_tready <= 1'b0;
+	 if (o_tdata_ref != o_tdata) begin
+	    $display("ERROR: Expected %d, got %d, at time %d",o_tdata_ref,o_tdata,$time);
+	    error <= 1'b1;
+	 end else  
+	   error <= 1'b0;
+	 o_tdata_ref = o_tdata_ref + 8'h1;
+      end
+   endtask // read
+
+   initial
+     begin
+	reset <= 1'b0;
+	error <= 1'b0;
+	i_tdata <= 8'b00;
+	o_tdata_ref <= 8'b00;
+	i_tvalid <= 1'b0;
+	o_tready <= 1'b0;
+	read_flag <= 0;
+	write_flag <= 0;
+	
+	repeat(10) @(posedge clk);
+	reset <= 1'b1;
+   	repeat(10) @(posedge clk);
+	reset <= 1'b0;
+	@(posedge clk);
+	@(negedge clk);
+
+	// FIFO Should be empty now, check avail space
+	if (space != 16'd256)
+	  begin $display("ERROR: FIFO is empty, space should read 256 not %d at time %d",space,$time); error <= 1; end
+	if (occupied != 16'd0)
+	  begin $display("ERROR: FIFO is empty, occupied should read 0 not %d at time %d",occupied,$time); error <= 1; end
+	if (o_tvalid == 1'b1)
+	  begin $display("ERROR: FIFO is empty, o_tvalid should be 0 at time %d",$time); error <= 1; end
+	@(posedge clk);
+	// Push 1 item onto FIFO, check fullness updates accordingly
+	write();
+	@(posedge clk);
+	@(negedge clk);
+	if (space != 16'd255)
+	  begin $display("ERROR: FIFO space should read 255 not %d at time %d",space,$time); error <= 1; end
+	if (occupied != 16'd1)
+	  begin $display("ERROR: FIFO occupied should read 1 not %d at time %d",occupied,$time); error <= 1; end
+	if (o_tvalid == 1'b0)
+	  begin $display("ERROR: FIFO is not empty, o_tvalid should be 1 at time %d",$time); error <= 1; end
+	// Pop FIFO once, check it goes back empty OK.
+	@(posedge clk);	
+	read();
+	@(posedge clk);
+	@(negedge clk);
+	if (space != 16'd256)
+	  begin $display("ERROR: FIFO is empty, space should read 256 not %d at time %d",space,$time); error <= 1; end
+	if (occupied != 16'd0)
+	  begin $display("ERROR: FIFO is empty, occupied should read 0 not %d at time %d",occupied,$time); error <= 1; end
+	if (o_tvalid == 1'b1)
+	  begin $display("ERROR: FIFO is empty, o_tvalid should be 0 at time %d",$time); error <= 1; end
+	// Push FIFO 255 times and see if it goes full incorrectly
+	repeat(255) begin
+	   @(posedge clk);
+	   write();
+	end
+	@(posedge clk);
+	@(negedge clk);
+	if (space != 16'd1)
+	  begin $display("ERROR: FIFO is nearly full, space should read 1 not %d at time %d",space,$time); error <= 1; end
+	if (occupied != 16'd255)
+	  begin $display("ERROR: FIFO is nearly full, occupied should read 255 not %d at time %d",occupied,$time); error <= 1; end
+	if (o_tvalid == 1'b0)
+	  begin $display("ERROR: FIFO is nearly full, o_tvalid should be 1 at time %d",$time); error <= 1; end
+	if (i_tready == 1'b0)
+	  begin $display("ERROR: FIFO is nearly full, i_tready should be 1 at time %d",$time); error <= 1; end
+	// Push FIFO one more time, now it should be full
+	@(posedge clk);	
+	write();
+	@(posedge clk);
+	@(negedge clk);
+	if (space != 16'd0)
+	  begin $display("ERROR: FIFO is full, space should read 0 not %d at time %d",space,$time); error <= 1; end
+	if (occupied != 16'd256)
+	  begin $display("ERROR: FIFO is full, occupied should read 256 not %d at time %d",occupied,$time); error <= 1; end
+	if (o_tvalid == 1'b0)
+	  begin $display("ERROR: FIFO is full, o_tvalid should be 1 at time %d",$time); error <= 1; end
+	if (i_tready == 1'b1)
+	  begin $display("ERROR: FIFO is full, i_tready should be 0 at time %d",$time); error <= 1; end
+	// POP FIFO once, check it went nonfull.
+	@(posedge clk);	
+	read();
+	@(posedge clk);
+	@(negedge clk);
+	if (space != 16'd1)
+	  begin $display("ERROR: FIFO is nearly full, space should read 1 not %d at time %d",space,$time); error <= 1; end
+	if (occupied != 16'd255)
+	  begin $display("ERROR: FIFO is nearly full, occupied should read 255 not %d at time %d",occupied,$time); error <= 1; end
+	if (o_tvalid == 1'b0)
+	  begin $display("ERROR: FIFO is nearly full, o_tvalid should be 1 at time %d",$time); error <= 1; end
+	if (i_tready == 1'b0)
+	  begin $display("ERROR: FIFO is nearly full, i_tready should be 1 at time %d",$time); error <= 1; end
+	// Take FIFO to empty state
+	repeat(255) begin
+	   @(posedge clk);
+	   read();
+	end
+	@(posedge clk);
+	@(negedge clk);
+	if (space != 16'd256)
+	  begin $display("ERROR: FIFO is empty, space should read 256 not %d at time %d",space,$time); error <= 1; end
+	if (occupied != 16'd0)
+	  begin $display("ERROR: FIFO is empty, occupied should read 0 not %d at time %d",occupied,$time); error <= 1; end
+	if (o_tvalid == 1'b1)
+	  begin $display("ERROR: FIFO is empty, o_tvalid should be 0 at time %d",$time); error <= 1; end
+	// Push 1 item onto FIFO
+	@(posedge clk);
+	write();
+	@(posedge clk);
+	// Now write twice as fast as we read, and write 256 times, which should leave, 129 elements in FIFO.
+	fork
+	   repeat(256) begin
+	      write();
+	      @(posedge clk);
+	   end
+	   repeat(128) begin
+	      read();
+	      @(posedge clk);
+	      @(posedge clk);
+	   end
+	join
+	@(posedge clk);
+	if (space != 16'd127)
+	  begin $display("ERROR: FIFO space should read 127 not %d at time %d",space,$time); error <= 1; end
+	if (occupied != 16'd129)
+	  begin $display("ERROR: FIFO occupied should read 129 not %d at time %d",occupied,$time); error <= 1; end
+	
+
+	
+	//
+	// END
+	//
+	repeat(10) @(posedge clk);
+	$finish;
+     end // initial begin
+   
+endmodule // axi_fifo_tb
diff --git a/fpga/usrp3/lib/fifo/axi_loopback.v b/fpga/usrp3/lib/fifo/axi_loopback.v
new file mode 100644
index 000000000..aea9ae22c
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_loopback.v
@@ -0,0 +1,71 @@
+// Copyright 2012 Ettus Research LLC
+
+//
+// axi_loopback.v
+//
+// Loopback all data assuming it's in CHDR format, and swap SRC/DST in the SID in the process
+// thus reflecting it back to it's origin...in theory!
+//
+
+module axi_loopback
+  (
+   input clk,
+   input reset,
+   // Input AXIS
+   input [WIDTH-1:0] i_tdata,
+   input i_tlast,
+   input i_tvalid,
+   output i_tready,
+   // Output AXIS
+   output [WIDTH-1:0] o_tdata,
+   output o_tlast,
+   output o_tvalid,
+   input o_tready
+   );
+   
+
+   localparam WIDTH=64;
+
+   wire [WIDTH-1:0]     fifoin_tdata,fifoout_tdata,dmux_tdata;
+   wire                 fifoin_tlast,dmux_tlast;
+   wire                 fifoin_tvalid,dmux_tvalid;
+   wire                 fifoin_tready,dmux_tready;
+   
+   // Since most real endpoints go via Demux4 place one in here to look for bugs.
+   axi_demux4 #(.ACTIVE_CHAN(4'b0001), .WIDTH(WIDTH)) demux
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .header(), .dest(2'b00),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o0_tdata(dmux_tdata), .o0_tlast(dmux_tlast), .o0_tvalid(dmux_tvalid), .o0_tready(dmux_tready), 
+      .o1_tdata(), .o1_tlast(), .o1_tvalid(), .o1_tready(1'b1), 
+      .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1), 
+      .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1));
+
+   axi_fifo_short #(.WIDTH(WIDTH+1)) axi_fifo_short1
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({dmux_tlast,dmux_tdata}), .i_tvalid(dmux_tvalid), .i_tready(dmux_tready),
+      .o_tdata({fifoin_tlast,fifoin_tdata}), .o_tvalid(fifoin_tvalid), .o_tready(fifoin_tready),
+      .space(), .occupied());
+
+   reg header;
+   always @(posedge clk) begin
+     if(reset) begin
+       header <= 1'b1;
+     end else if (header) begin
+       if(fifoin_tvalid & fifoin_tready & ~fifoin_tlast) header <= 1'b0;
+     end else begin
+       if(fifoin_tvalid & fifoin_tready & fifoin_tlast) header <= 1'b1;
+     end
+   end
+
+   assign fifoout_tdata = header ? 
+			       {fifoin_tdata[63:32] ,fifoin_tdata[15:0],fifoin_tdata[31:16]} :
+			       fifoin_tdata;
+   
+   axi_fifo_short #(.WIDTH(WIDTH+1)) axi_fifo_short2
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({fifoin_tlast,fifoout_tdata}), .i_tvalid(fifoin_tvalid), .i_tready(fifoin_tready),
+      .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .space(), .occupied());
+
+endmodule // axi_loopback
diff --git a/fpga/usrp3/lib/fifo/axi_mux4.v b/fpga/usrp3/lib/fifo/axi_mux4.v
new file mode 100644
index 000000000..91bfe43a9
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_mux4.v
@@ -0,0 +1,112 @@
+
+// Copyright 2012 Ettus Research LLC
+// axi_mux -- takes 4 64-bit AXI stream, merges them to 1 output channel
+// Round-robin if PRIO=0, priority if PRIO=1 (lower number ports get priority)
+// Bubble cycles are inserted after each packet in PRIO mode, or on wraparound in Round Robin mode
+
+module axi_mux4
+  #(parameter PRIO=0,
+    parameter WIDTH=64,
+    parameter BUFFER=0)
+   (input clk, input reset, input clear,
+    input [WIDTH-1:0] i0_tdata, input i0_tlast, input i0_tvalid, output i0_tready,
+    input [WIDTH-1:0] i1_tdata, input i1_tlast, input i1_tvalid, output i1_tready,
+    input [WIDTH-1:0] i2_tdata, input i2_tlast, input i2_tvalid, output i2_tready,
+    input [WIDTH-1:0] i3_tdata, input i3_tlast, input i3_tvalid, output i3_tready,
+    output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   wire [WIDTH-1:0]    o_tdata_int;
+   wire 	       o_tlast_int, o_tvalid_int, o_tready_int;
+   
+   reg [3:0] 	  mx_state;
+   localparam MX_IDLE = 4'b0000;
+   localparam MX_0    = 4'b0001;
+   localparam MX_1    = 4'b0010;
+   localparam MX_2    = 4'b0100;
+   localparam MX_3    = 4'b1000;
+
+   always @(posedge clk)
+     if(reset | clear)
+       mx_state <= MX_IDLE;
+     else
+       case (mx_state)
+	 MX_IDLE :
+	   if(i0_tvalid)
+	     mx_state <= MX_0;
+	   else if(i1_tvalid)
+	     mx_state <= MX_1;
+	   else if(i2_tvalid)
+	     mx_state <= MX_2;
+	   else if(i3_tvalid)
+	     mx_state <= MX_3;
+
+	 MX_0 :
+	   if(o_tready_int & o_tvalid_int & o_tlast_int)
+	     if(PRIO)
+	       mx_state <= MX_IDLE;
+	     else if(i1_tvalid)
+	       mx_state <= MX_1;
+	     else if(i2_tvalid)
+	       mx_state <= MX_2;
+	     else if(i3_tvalid)
+	       mx_state <= MX_3;
+	     else
+	       mx_state <= MX_IDLE;
+	 	 
+	 MX_1 :
+	   if(o_tready_int & o_tvalid_int & o_tlast_int)
+	     if(PRIO)
+	       mx_state <= MX_IDLE;
+	     else if(i2_tvalid)
+	       mx_state <= MX_2;
+	     else if(i3_tvalid)
+	       mx_state <= MX_3;
+	     else
+	       mx_state <= MX_IDLE;
+
+	 MX_2 :
+	   if(o_tready_int & o_tvalid_int & o_tlast_int)
+	     if(PRIO)
+	       mx_state <= MX_IDLE;
+	     else if(i3_tvalid)
+	       mx_state <= MX_3;
+	     else
+	       mx_state <= MX_IDLE;
+	 	 
+	 MX_3 :
+	   if(o_tready_int & o_tvalid_int & o_tlast_int)
+	     if(PRIO)
+	       mx_state <= MX_IDLE;
+	     else
+	       mx_state <= MX_IDLE;
+	 	 
+	 default :
+	   mx_state <= MX_IDLE;
+       endcase // case (mx_state)
+
+   assign {i3_tready, i2_tready, i1_tready, i0_tready} = mx_state & {4{o_tready_int}};
+
+   assign o_tvalid_int = |(mx_state & ({i3_tvalid, i2_tvalid, i1_tvalid, i0_tvalid}));
+         
+   assign {o_tlast_int, o_tdata_int} = mx_state[3] ? {i3_tlast, i3_tdata} :
+				       mx_state[2] ? {i2_tlast, i2_tdata} :
+				       mx_state[1] ? {i1_tlast, i1_tdata} :
+				       {i0_tlast, i0_tdata};
+
+   generate
+      if(BUFFER == 0)
+	begin
+	   assign o_tdata = o_tdata_int;
+	   assign o_tlast = o_tlast_int;
+	   assign o_tvalid = o_tvalid_int;
+	   assign o_tready_int = o_tready;
+	end
+      else
+	axi_fifo_short #(.WIDTH(WIDTH+1)) axi_fifo_short
+	  (.clk(clk), .reset(reset), .clear(clear),
+	   .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+	   .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+	   .space(), .occupied());
+   endgenerate
+   
+endmodule // axi__mux4
diff --git a/fpga/usrp3/lib/fifo/axi_mux8.v b/fpga/usrp3/lib/fifo/axi_mux8.v
new file mode 100644
index 000000000..5e620d3aa
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_mux8.v
@@ -0,0 +1,56 @@
+
+// Copyright 2012 Ettus Research LLC
+// axi_mux -- takes 8 64-bit AXI stream, merges them to 1 output channel
+// Round-robin if PRIO=0, priority if PRIO=1 (lower number ports get priority)
+// Bubble cycles are inserted after each packet in PRIO mode, or on wraparound in Round Robin mode
+
+module axi_mux8 #(
+   parameter PRIO=0,
+   parameter WIDTH=64,
+   parameter BUFFER=0
+) (
+   input clk, input reset, input clear,
+   input [WIDTH-1:0] i0_tdata, input i0_tlast, input i0_tvalid, output i0_tready,
+   input [WIDTH-1:0] i1_tdata, input i1_tlast, input i1_tvalid, output i1_tready,
+   input [WIDTH-1:0] i2_tdata, input i2_tlast, input i2_tvalid, output i2_tready,
+   input [WIDTH-1:0] i3_tdata, input i3_tlast, input i3_tvalid, output i3_tready,
+   input [WIDTH-1:0] i4_tdata, input i4_tlast, input i4_tvalid, output i4_tready,
+   input [WIDTH-1:0] i5_tdata, input i5_tlast, input i5_tvalid, output i5_tready,
+   input [WIDTH-1:0] i6_tdata, input i6_tlast, input i6_tvalid, output i6_tready,
+   input [WIDTH-1:0] i7_tdata, input i7_tlast, input i7_tvalid, output i7_tready,
+   output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
+);
+
+   wire [WIDTH-1:0]  o_tdata_int0, o_tdata_int1;
+   wire              o_tlast_int0, o_tlast_int1;
+   wire              o_tvalid_int0, o_tvalid_int1;
+   wire              o_tready_int0, o_tready_int1;
+
+   axi_mux4 #(.PRIO(PRIO), .WIDTH(WIDTH), .BUFFER(0)) mux4_int0 (
+      .clk(clk), .reset(reset), .clear(clear),
+      .i0_tdata(i0_tdata), .i0_tlast(i0_tlast), .i0_tvalid(i0_tvalid), .i0_tready(i0_tready),
+      .i1_tdata(i1_tdata), .i1_tlast(i1_tlast), .i1_tvalid(i1_tvalid), .i1_tready(i1_tready),
+      .i2_tdata(i2_tdata), .i2_tlast(i2_tlast), .i2_tvalid(i2_tvalid), .i2_tready(i2_tready),
+      .i3_tdata(i3_tdata), .i3_tlast(i3_tlast), .i3_tvalid(i3_tvalid), .i3_tready(i3_tready),
+      .o_tdata(o_tdata_int0), .o_tlast(o_tlast_int0), .o_tvalid(o_tvalid_int0), .o_tready(o_tready_int0)
+   );
+
+   axi_mux4 #(.PRIO(PRIO), .WIDTH(WIDTH), .BUFFER(0)) mux4_int1 (
+      .clk(clk), .reset(reset), .clear(clear),
+      .i0_tdata(i4_tdata), .i0_tlast(i4_tlast), .i0_tvalid(i4_tvalid), .i0_tready(i4_tready),
+      .i1_tdata(i5_tdata), .i1_tlast(i5_tlast), .i1_tvalid(i5_tvalid), .i1_tready(i5_tready),
+      .i2_tdata(i6_tdata), .i2_tlast(i6_tlast), .i2_tvalid(i6_tvalid), .i2_tready(i6_tready),
+      .i3_tdata(i7_tdata), .i3_tlast(i7_tlast), .i3_tvalid(i7_tvalid), .i3_tready(i7_tready),
+      .o_tdata(o_tdata_int1), .o_tlast(o_tlast_int1), .o_tvalid(o_tvalid_int1), .o_tready(o_tready_int1)
+   );
+
+   axi_mux4 #(.PRIO(PRIO), .WIDTH(WIDTH), .BUFFER(BUFFER)) mux2 (
+      .clk(clk), .reset(reset), .clear(clear),
+      .i0_tdata(o_tdata_int0), .i0_tlast(o_tlast_int0), .i0_tvalid(o_tvalid_int0), .i0_tready(o_tready_int0),
+      .i1_tdata(o_tdata_int1), .i1_tlast(o_tlast_int1), .i1_tvalid(o_tvalid_int1), .i1_tready(o_tready_int1),
+      .i2_tdata(0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(),
+      .i3_tdata(0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
+   );
+
+endmodule // axi_mux8
diff --git a/fpga/usrp3/lib/fifo/axi_packet_gate.v b/fpga/usrp3/lib/fifo/axi_packet_gate.v
new file mode 100644
index 000000000..6d10a8cf4
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_packet_gate.v
@@ -0,0 +1,78 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+
+
+// Hold packets in fifo until they are complete.  This prevents slowly-built packets
+//  from clogging up the downstream.  This block will hold up to 255 packets.
+//  Will permanently block if a single packet is bigger than the fifo.
+//  Will also drop any packet with an error signalled on the last line.
+//  This is useful after an ethernet interface to drop packets with bad CRCs.
+
+module axi_packet_gate
+  #(parameter WIDTH=68,
+    parameter SIZE=10)
+   (input clk, 
+    input reset, 
+    input clear,
+    input [WIDTH-1:0] i_tdata,
+    input i_tlast,
+    input i_terror,
+    input i_tvalid,
+    output i_tready,
+    output [WIDTH-1:0] o_tdata,
+    output o_tlast,
+    output o_tvalid,
+    input o_tready
+    );
+
+   reg [7:0] num_packets;
+   reg 	     dump;
+   
+   wire      o_tvalid_int, o_tready_int, i_tvalid_int, i_tready_int;
+
+   assign i_tvalid_int = (~dump & (num_packets != 8'hFF)) ? i_tvalid : 1'b0;
+   assign i_tready = (~dump & (num_packets != 8'hFF)) ? i_tready_int : 1'b0;
+
+   assign o_tvalid = (num_packets != 8'h0) ? o_tvalid_int : 1'b0;
+   assign o_tready_int = (num_packets != 8'h0) ? o_tready : 1'b0;
+   
+   wire      last_in = i_tvalid_int & i_tready_int & i_tlast;
+   wire      last_out = o_tvalid_int & o_tready_int & o_tlast;
+
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  num_packets <= 8'd0;
+	  dump <= 1'b0;
+       end
+     else
+       if(dump)
+	 if(num_packets != 8'd0)
+	   if(last_out)
+	     num_packets <= num_packets - 8'd1;
+	   else
+	     ;
+	 else
+	   dump <= 1'b0;
+       else
+	 if(last_in)
+	   if(i_terror)
+	     begin
+		dump <= 1'b1;
+		if(last_out)
+		  num_packets <= num_packets - 8'd1;
+	     end
+	   else if(~last_out)
+	     num_packets <= num_packets + 8'd1;
+	   else
+	     ;
+   	 else if(last_out)
+	   num_packets <= num_packets - 8'd1;
+   
+   axi_fifo #(.SIZE(SIZE), .WIDTH(WIDTH+1)) axi_fifo
+     (.clk(clk), .reset(reset), .clear(clear | (dump & (num_packets == 8'd0))),
+      .i_tdata({i_tlast,i_tdata}), .i_tvalid(i_tvalid_int), .i_tready(i_tready_int),
+      .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int));
+      
+endmodule // axi_packet_gate
diff --git a/fpga/usrp3/lib/fifo/axi_packet_gate_tb.v b/fpga/usrp3/lib/fifo/axi_packet_gate_tb.v
new file mode 100644
index 000000000..30f8c76e4
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/axi_packet_gate_tb.v
@@ -0,0 +1,106 @@
+`timescale 1ns/1ps
+
+module axi_packet_gate_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("axi_packet_gate_tb.vcd");
+   initial $dumpvars(0,axi_packet_gate_tb);
+
+   task send_packet;
+      input [63:0] data_start;
+      input [2:0]  user;
+      input [31:0] len;
+      input 	   error;
+      
+      begin
+	 // Send a packet
+	 @(posedge clk);
+	 {i_terror, i_tuser, i_tlast, i_tdata} <= { 1'b0, user, 1'b0, data_start };
+	 repeat(len-1)
+	   begin
+	      i_tvalid <= 1;
+	      @(posedge clk);
+	      i_tdata <= i_tdata + 1;
+	   end
+	 i_tlast <= 1;
+	 i_terror <= error;
+	 i_tdata <= i_tdata + 1;
+	 @(posedge clk);
+	 i_tvalid <= 1'b0;
+	 
+	 @(posedge clk);
+      end
+   endtask // send_packet
+   
+   
+   initial
+     begin
+	#1000 reset = 0;
+	#200000;
+	$finish;
+     end
+   
+   wire [63:0]  o_tdata;
+   reg [63:0] 	i_tdata;
+   wire [2:0] 	o_tuser;
+   reg [2:0] 	i_tuser;
+   reg 		i_tlast;
+   wire 	o_tlast;
+   wire		o_tvalid, i_tready;
+   reg 		i_tvalid, o_tready;
+   reg 		i_terror;
+   
+   localparam RPT_COUNT = 16;
+   
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 0;
+	
+	while(reset)
+	  @(posedge clk);
+	@(posedge clk);
+
+	send_packet(64'hA0,3'd0, 16, 0);
+	send_packet(64'hB0,3'd0, 16, 0);
+	o_tready <= 1;
+	send_packet(64'hC0,3'd0, 16, 1);
+	send_packet(64'hD0,3'd0, 16, 0);
+	send_packet(64'hE0,3'd0, 16, 0);
+	send_packet(64'hF0,3'd0, 16, 0);
+
+	@(posedge clk);
+
+     end // initial begin
+
+   wire i_terror_int, i_tlast_int, i_tready_int, i_tvalid_int;
+   wire [2:0] i_tuser_int;
+   wire [63:0] i_tdata_int;
+   wire o_tlast_int, o_tready_int, o_tvalid_int;
+   wire [2:0] o_tuser_int;
+   wire [63:0] o_tdata_int;
+   
+   axi_fifo #(.WIDTH(69), .SIZE(10)) fifo
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({i_terror,i_tlast,i_tuser,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata({i_terror_int,i_tlast_int,i_tuser_int,i_tdata_int}), .o_tvalid(i_tvalid_int), .o_tready(i_tready_int));
+
+   axi_packet_gate #(.WIDTH(67), .SIZE(10)) dut
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({i_tuser_int,i_tdata_int}), .i_terror(i_terror_int), .i_tlast(i_tlast_int), .i_tvalid(i_tvalid_int), .i_tready(i_tready_int),
+      .o_tdata({o_tuser_int,o_tdata_int}), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int));
+
+   axi_fifo #(.WIDTH(68), .SIZE(10)) fifo_out
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({o_tlast_int,o_tuser_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+      .o_tdata({o_tlast,o_tuser,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       $display("TUSER %x\tTLAST %x\tTDATA %x",o_tuser,o_tlast, o_tdata);
+
+endmodule // axi_packet_gate_tb
diff --git a/fpga/usrp3/lib/fifo/monitor_axi_fifo.v b/fpga/usrp3/lib/fifo/monitor_axi_fifo.v
new file mode 100644
index 000000000..f5d73455f
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/monitor_axi_fifo.v
@@ -0,0 +1,123 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+
+
+//
+// This module is instantiated in parallel with a FIFO with AXI4-STREAM interfaces.
+// It tracks how many complete packets are contained within the FIFO, and also indicates
+// when the first word of a packet is presented on the FIFO outputs.
+//
+
+ 
+module monitor_axi_fifo
+  #(
+    parameter COUNT_BITS=8
+    )
+  (
+   input clk,
+   input reset,
+   input clear,
+   // Monitored FIFO signals
+   input i_tvalid,
+   input i_tready,
+   input i_tlast,
+   input o_tvalid,
+   input o_tready,
+   input o_tlast,
+   // FIFO status outputs
+   output reg [COUNT_BITS-1:0] pkt_count, // Exact whole packet count
+   output pkt_present // Flags any whole packets present
+ 
+   );
+
+   localparam WAIT_SOF = 0;
+   localparam WAIT_EOF = 1;
+    
+   
+   reg        in_state, out_state;
+   reg        pause_tx;
+                
+   //
+   // Count packets arriving into large FIFO
+   //
+   always @(posedge clk)
+     if (reset | clear) begin
+        in_state <= WAIT_SOF;
+     end else
+       case(in_state)
+	 //
+	 // After RESET or the EOF of previous packet, the first cycle with
+	 // input valid and input ready asserted is the SOF.
+	 //
+         WAIT_SOF: 
+           if (i_tvalid && i_tready) begin
+              in_state <= WAIT_EOF;
+           end else begin
+              in_state <= WAIT_SOF;
+           end
+	 //
+	 // EOF is signalled by the assertion i_tlast whilst input valid and ready are asserted.
+	 //
+         WAIT_EOF: 
+           if (i_tlast && i_tvalid && i_tready) begin
+              in_state <= WAIT_SOF;
+           end else begin
+              in_state <= WAIT_EOF;
+           end
+       endcase // case(in_state)
+   
+
+
+   //
+   // Count packets leaving large FIFO
+   //
+   always @(posedge clk)
+     if (reset | clear) begin
+        out_state <= WAIT_SOF;
+     end else
+       case(out_state)
+	 //
+	 // After RESET or the EOF of previous packet, the first cycle with
+	 // output valid and output ready asserted is the SOF.
+	 //
+         WAIT_SOF: 
+           if (o_tvalid && o_tready) begin
+              out_state <= WAIT_EOF;
+           end else begin
+              out_state <= WAIT_SOF;
+           end
+	 //
+	 // EOF is signalled by o_tlast asserted whilst output valid and ready asserted.
+	 //
+         WAIT_EOF: 
+           if (o_tlast && o_tvalid && o_tready) begin
+              out_state <= WAIT_SOF;
+           end else begin
+              out_state <= WAIT_EOF;
+           end
+       endcase // case(in_state)
+   
+
+   //
+   // Count packets in FIFO.
+   // No protection on counter wrap, 
+   // unclear how to gracefully deal with it.
+   // Perhaps generate Error IRQ so that S/W could clean up?
+   // Configure so that the pkt_count is ample for the application.
+   //
+   always @(posedge clk)
+     if (reset | clear)
+       pkt_count <= 0;
+     else if (((out_state==WAIT_EOF) && o_tlast && o_tvalid && o_tready ) &&
+	      ((in_state==WAIT_EOF) && i_tlast && i_tvalid && i_tready))
+       pkt_count <= pkt_count;
+     else if ((out_state==WAIT_EOF) && o_tlast && o_tvalid && o_tready)
+       pkt_count <= pkt_count - 1;
+     else if ((in_state==WAIT_EOF)  && i_tlast && i_tvalid && i_tready)
+       pkt_count <= pkt_count + 1;
+
+   // Non-zero packet count indicates packet(s) present.
+   assign pkt_present = |pkt_count;
+ 
+endmodule // count_tx_packets
diff --git a/fpga/usrp3/lib/fifo/shortfifo.v b/fpga/usrp3/lib/fifo/shortfifo.v
new file mode 100644
index 000000000..fbf92e2ed
--- /dev/null
+++ b/fpga/usrp3/lib/fifo/shortfifo.v
@@ -0,0 +1,92 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+module shortfifo
+  #(parameter WIDTH=32)
+    (input clk, input rst,
+     input [WIDTH-1:0] datain,
+     output [WIDTH-1:0] dataout,
+     input read,
+     input write,
+     input clear,
+     output reg full,
+     output reg empty,
+     output reg [4:0] space,
+     output reg [4:0] occupied);
+   
+   reg [3:0] 	  a;
+   genvar 	  i;
+   
+   generate
+      for (i=0;i<WIDTH;i=i+1)
+	begin : gen_srl16
+	   SRL16E
+	     srl16e(.Q(dataout[i]),
+		    .A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),
+		    .CE(write),.CLK(clk),.D(datain[i]));
+	end
+   endgenerate
+   
+   always @(posedge clk)
+     if(rst)
+       begin
+	  a <= 0;
+	  empty <= 1;
+	  full <= 0;
+       end
+     else if(clear)
+       begin
+	  a <= 0;
+	  empty <= 1;
+	  full<= 0;
+       end
+     else if(read & ~write)
+       begin
+	  full <= 0;
+	  if(a==0)
+	    empty <= 1;
+	  else
+	    a <= a - 1;
+       end
+     else if(write & ~read)
+       begin
+	  empty <= 0;
+	  if(~empty)
+	    a <= a + 1;
+	  if(a == 14)
+	    full <= 1;
+       end
+
+   // NOTE will fail if you write into a full fifo or read from an empty one
+
+   //////////////////////////////////////////////////////////////
+   // space and occupied are used for diagnostics, not 
+   // guaranteed correct
+   
+   //assign space = full ? 0 : empty ? 16 : 15-a;
+   //assign occupied = empty ? 0 : full ? 16 : a+1;
+
+   always @(posedge clk)
+     if(rst)
+       space <= 16;
+     else if(clear)
+       space <= 16;
+     else if(read & ~write)
+       space <= space + 1;
+     else if(write & ~read)
+       space <= space - 1;
+   
+   always @(posedge clk)
+     if(rst)
+       occupied <= 0;
+     else if(clear)
+       occupied <= 0;
+     else if(read & ~write)
+       occupied <= occupied - 1;
+     else if(write & ~read)
+       occupied <= occupied + 1;
+      
+endmodule // shortfifo
diff --git a/fpga/usrp3/lib/gpif2/Makefile.srcs b/fpga/usrp3/lib/gpif2/Makefile.srcs
new file mode 100644
index 000000000..1624643f6
--- /dev/null
+++ b/fpga/usrp3/lib/gpif2/Makefile.srcs
@@ -0,0 +1,13 @@
+#
+# Copyright 2010-2013 Ettus Research LLC
+#
+
+##################################################
+# SERDES Sources
+##################################################
+GPIF2_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/gpif2/, \
+gpif2_slave_fifo32.v \
+gpif2_to_fifo64.v \
+fifo64_to_gpif2.v \
+gpif2_error_checker.v \
+))
diff --git a/fpga/usrp3/lib/gpif2/fifo64_to_gpif2.v b/fpga/usrp3/lib/gpif2/fifo64_to_gpif2.v
new file mode 100644
index 000000000..cf3a221b7
--- /dev/null
+++ b/fpga/usrp3/lib/gpif2/fifo64_to_gpif2.v
@@ -0,0 +1,64 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+//
+
+
+module fifo64_to_gpif2
+#(
+    parameter FIFO_SIZE = 9
+)
+(
+    //input fifo interface
+    input fifo_clk, input fifo_rst,
+    input [63:0] i_tdata,
+    input i_tlast,
+    input i_tvalid,
+    output i_tready,
+
+    //output interface
+    input gpif_clk, input gpif_rst,
+    output [31:0] o_tdata,
+    output o_tlast,
+    output o_tvalid,
+    input o_tready
+);
+
+    wire [31:0] i32_tdata;
+    wire i32_tlast;
+    wire i32_tvalid, i32_tready;
+
+    axi_fifo64_to_fifo32 fifo64_to_fifo32
+    (
+        .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+        .i_tdata(i_tdata), .i_tuser(3'b0/*done care*/), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+        .o_tdata(i32_tdata), .o_tuser(/*ignored cuz vita has len*/), .o_tlast(i32_tlast), .o_tvalid(i32_tvalid), .o_tready(i32_tready)
+    );
+
+    wire [31:0] gate_tdata;
+    wire gate_tlast;
+    wire gate_tvalid, gate_tready;
+
+    axi_fifo_2clk #(.WIDTH(33), .SIZE(0/*SRL*/)) cross_clock_fifo
+    (
+        .reset(fifo_rst | gpif_rst),
+        .i_aclk(fifo_clk), .i_tdata({i32_tlast, i32_tdata}), .i_tvalid(i32_tvalid), .i_tready(i32_tready),
+        .o_aclk(gpif_clk), .o_tdata({gate_tlast, gate_tdata}), .o_tvalid(gate_tvalid), .o_tready(gate_tready)
+    );
+
+    wire [31:0] int0_tdata; wire int0_tlast, int0_tvalid, int0_tready;
+
+    axi_packet_gate #(.WIDTH(32), .SIZE(FIFO_SIZE)) buffer_whole_pkt
+    (
+        .clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
+        .i_tdata(gate_tdata), .i_tlast(gate_tlast), .i_terror(1'b0), .i_tvalid(gate_tvalid), .i_tready(gate_tready),
+        .o_tdata(int0_tdata), .o_tlast(int0_tlast), .o_tvalid(int0_tvalid), .o_tready(int0_tready)
+    );
+
+    axi_fifo #(.WIDTH(33), .SIZE(0)) outgress_timing_fifo
+    (
+        .clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
+        .i_tdata({int0_tlast, int0_tdata}), .i_tvalid(int0_tvalid), .i_tready(int0_tready), .space(),
+        .o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready), .occupied()
+    );
+
+endmodule //fifo_to_gpmc16
diff --git a/fpga/usrp3/lib/gpif2/gpif2_error_checker.v b/fpga/usrp3/lib/gpif2/gpif2_error_checker.v
new file mode 100644
index 000000000..0ec21a758
--- /dev/null
+++ b/fpga/usrp3/lib/gpif2/gpif2_error_checker.v
@@ -0,0 +1,126 @@
+
+// Copyright 2013 Ettus Research LLC
+
+// inspect the input for invalid conditions
+// when bad - drain input, flag error, and insert error msg packet
+//
+// Packets alignment errors are searched for in two different ways:
+// 1) Blatently illegal values in what is assumed to be the PACKET_LENGTH field
+// in the CHDR header
+// (We could probably improve this by looking at other fields of the header that 
+// have a limited range of values)
+// 2) Packet length indicating an EOF word that doesn't have TLAST set in the FIFO.
+// (Upstream can howvever legally insert TLAST in the FIFO for words that are not EOF)
+// 
+// Packet allignment recovery strategy is to wait for TLAST asserted and then decode the 
+// following data assuming it is the start of new CHDR headers.
+//
+//TODO - insert bad packet
+
+module gpif2_error_checker
+  #(parameter SIZE = 9)
+  (input clk, input reset, input clear,
+   input [31:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+   output [31:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
+   output bus_error, output [63:0] debug);
+
+    wire [31:0] gate_tdata;
+    wire gate_tlast, gate_terror;
+    wire gate_tvalid, gate_tready;
+
+    localparam STATE_HDR = 0;
+    localparam STATE_FWD = 1;
+    localparam STATE_EOF = 2;
+    localparam STATE_WAIT = 3;
+    reg [1:0] state;
+
+    reg [15:0] lines32;
+    reg [11:0] seq_id_ref;
+    reg        seq_id_bad;
+    reg        seq_id_wayoff;
+   
+
+    wire [15:0] hdr_bytes = i_tdata[15:0] + 3; //round up to multiple of 4
+    wire [15:0] hdr_lines32 = {2'b0, hdr_bytes[15:2]}; //convert to lines32 count
+    wire [11:0] seq_id_actual = i_tdata[27:16];
+   
+   
+    wire obviously_bad_hdr = (hdr_lines32 == 16'h0) || (hdr_lines32 > (1 << SIZE));
+
+    always @(posedge clk) begin
+        if (reset | clear) begin
+            state <= STATE_HDR;
+            lines32 <= 16'b0;
+	    seq_id_ref <= 12'h0;
+	    seq_id_bad <= 0;
+	    seq_id_wayoff <= 0;
+	   
+	   
+        end
+        else case (state)
+
+        STATE_HDR: begin //forward header and grab vita length
+            if (i_tvalid && i_tready) begin
+                if (obviously_bad_hdr)           state <= STATE_WAIT;
+                else if (hdr_lines32 == 16'h1)  state <= STATE_HDR;
+                else if (hdr_lines32 == 16'h2)  state <= STATE_EOF;
+                else                            state <= STATE_FWD;
+	        seq_id_bad <= (seq_id_actual != seq_id_ref);
+	        seq_id_wayoff <= (seq_id_actual != seq_id_ref) |
+				(seq_id_actual != seq_id_ref+1) |
+				(seq_id_actual != seq_id_ref+2) |
+				(seq_id_actual != seq_id_ref+3);
+	        if (seq_id_actual != seq_id_ref)
+		 seq_id_ref <= seq_id_actual + 1;
+	        else
+		 seq_id_ref <= seq_id_ref + 1;
+            end
+            lines32 <= hdr_lines32;
+	    
+        end
+
+        STATE_FWD: begin //forward the rest of vita packet
+            if (i_tvalid && i_tready) begin
+                if (lines32 == 16'h3) state <= STATE_EOF;
+                lines32 <= lines32 - 1'b1;
+            end
+        end
+
+        STATE_EOF: begin //do last line of vita frame + eof
+	   if (i_tvalid && i_tready) 
+	     if (gate_tlast) state <= STATE_HDR;
+	     else state <= STATE_WAIT; // Try somehow to get synchronized again.
+        end
+
+        STATE_WAIT: begin //drop until idle
+            if (i_tvalid && i_tready && i_tlast) state <= STATE_HDR;
+        end
+
+        endcase //state
+    end
+
+    assign bus_error = (gate_terror && gate_tvalid && gate_tready) || ((state == STATE_HDR) && i_tvalid && i_tready && obviously_bad_hdr);
+    assign gate_tlast = (state == STATE_HDR)? (hdr_lines32 == 16'h1) : (state == STATE_EOF);
+    assign gate_tdata = i_tdata;
+    assign gate_tvalid = i_tvalid && ((state == STATE_HDR)? !obviously_bad_hdr : (state != STATE_WAIT));
+    assign i_tready = gate_tready;
+
+    axi_packet_gate #(.WIDTH(32), .SIZE(SIZE)) gate_xfer
+    (
+        .clk(clk), .reset(reset), .clear(clear),
+        .i_tdata(gate_tdata), .i_tlast(gate_tlast), .i_terror(1'b0), .i_tvalid(gate_tvalid), .i_tready(gate_tready),
+        .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
+    );
+   assign  debug = {13'b0,
+		    seq_id_wayoff, //[50]      [114]
+		    gate_terror,  // [49]      [113]
+		    obviously_bad_hdr, // [48] [112]
+		    seq_id_bad,   // [47]      [111]
+		    seq_id_ref,   // [46:35]   [110:99]
+		    i_tlast,      // [34]      [98]
+		    i_tready,     // [33]      [97]
+		    i_tvalid,     // [32]      [96]
+		    i_tdata};     // [31:0]    [95:64]
+   
+
+endmodule // cvita_insert_tlast
diff --git a/fpga/usrp3/lib/gpif2/gpif2_slave_fifo32.v b/fpga/usrp3/lib/gpif2/gpif2_slave_fifo32.v
new file mode 100644
index 000000000..f332a6ab3
--- /dev/null
+++ b/fpga/usrp3/lib/gpif2/gpif2_slave_fifo32.v
@@ -0,0 +1,375 @@
+//
+// Copyright 2011-2013 Ettus Research LLC
+//
+
+
+//////////////////////////////////////////////////////////////////////////////////
+
+//this is a FIFO master interface for the FX3 in "slave fifo" mode.
+
+module gpif2_slave_fifo32
+#(
+    //sizes for fifo64 2 clock cascade fifos
+    parameter DATA_RX_FIFO_SIZE = 12, //max vita pkt size
+    parameter DATA_TX_FIFO_SIZE = 12, //max vita pkt size
+    parameter CTRL_RX_FIFO_SIZE = 5,  //small resp packets
+    parameter CTRL_TX_FIFO_SIZE = 5, //small ctrl packets
+
+    //address constants for the endpoints
+    parameter ADDR_DATA_TX = 2'b00,
+    parameter ADDR_DATA_RX = 2'b01,
+    parameter ADDR_CTRL_TX = 2'b10,
+    parameter ADDR_CTRL_RX = 2'b11,
+
+    parameter END_WITH_COMMA = 0
+)
+   (// GPIF signals
+    input gpif_clk, input gpif_rst, input gpif_enb,
+    inout [31:0] gpif_d,
+    input [3:0] gpif_ctl,
+    output reg sloe,
+    output reg slrd,
+    output reg slwr,
+    output slcs,
+    output reg pktend,
+    output reg [1:0] fifoadr,
+
+    // FIFO interfaces
+    input fifo_clk, input fifo_rst,
+
+    output [63:0] tx_tdata, output tx_tlast, output tx_tvalid, input tx_tready,
+    input [63:0] rx_tdata, input rx_tlast, input rx_tvalid, output rx_tready,
+    output [63:0] ctrl_tdata, output ctrl_tlast, output ctrl_tvalid, input ctrl_tready,
+    input [63:0] resp_tdata, input resp_tlast, input resp_tvalid, output resp_tready,
+
+    output [31:0] debug
+    );
+
+   reg 		  fifo_nearly_full;
+   wire 	  ctrl_tx_fifo_nearly_full, data_tx_fifo_nearly_full;
+   wire 	  ctrl_tx_fifo_has_space, data_tx_fifo_has_space;
+   
+
+   wire [159:0]   debug_tx_data, debug_tx_ctrl;
+   
+    assign slcs = 1'b0;
+
+    //DMA FIFO ready and watermark flags
+    reg EP_READY, EP_READY1, EP_WMARK, EP_WMARK1;
+    always @(posedge gpif_clk) EP_READY <= gpif_ctl[0];
+    always @(posedge gpif_clk) EP_WMARK <= gpif_ctl[1];
+    always @(posedge gpif_clk) EP_READY1 <= EP_READY;
+    always @(posedge gpif_clk) EP_WMARK1 <= EP_WMARK;
+
+    // GPIF output data lines, tristate
+    reg [31:0] gpif_data_in, gpif_data_out;
+    always @(posedge gpif_clk) gpif_data_in <= gpif_d;
+    assign gpif_d = sloe ? gpif_data_out[31:0] : 32'bz;
+
+   // ////////////////////////////////////////////////////////////////////
+   // GPIF bus master state machine
+
+    wire wr_fifo_xfer, wr_fifo_eof;
+    wire [31:0] wr_fifo_data;
+    reg read_ready_go, write_ready_go;
+    reg wr_one, rd_one;
+
+    reg [3:0] state; //state machine current state
+    localparam STATE_IDLE  = 0;
+    localparam STATE_THINK = 1;
+    localparam STATE_READ  = 2;
+    localparam STATE_WRITE = 3;
+    localparam STATE_WAIT = 4;
+
+    reg [2:0] idle_cycles;
+    reg [1:0] last_addr, next_addr;
+    wire local_fifo_ready;
+
+    reg slrd1, slrd2, slrd3;
+   
+   always @(posedge gpif_clk)
+     if (gpif_rst) begin
+        slrd1 <= 1;
+        slrd2 <= 1;
+        slrd3 <= 1;
+     end else begin
+        slrd1 <= slrd;
+        slrd2 <= slrd1;
+        slrd3 <= slrd2;
+     end
+   
+   wire RD_VALID = ~slrd3;
+   wire RD_LAST = slrd2;
+   wire WR_VALID = (EP_WMARK1 || !wr_one);
+
+   // //////////////////////////////////////////////////////////////
+   // FX2 slave FIFO bus master state machine
+   //
+    always @(posedge gpif_clk)
+    if(gpif_rst) begin
+        state <= STATE_IDLE;
+        sloe <= 0;
+        slrd <= 1;
+        slwr <= 1;
+        pktend <= 1;
+        gpif_data_out <= 32'b0;
+        idle_cycles <= 0;
+        fifoadr <= 0;
+        wr_one <= 1'b0;
+        rd_one <= 1'b0;
+        last_addr <= 2'b0;
+    end
+    else if (gpif_enb) begin
+        case (state)
+
+	  //
+	  // Increment fifoadr to point at next thread, set all strobes to idle,
+	  //
+        STATE_IDLE: begin
+            sloe <= 0;
+            slrd <= 1;
+            slwr <= 1;
+            pktend <= 1;
+            gpif_data_out <= 32'b0;
+            fifoadr <= next_addr;
+            state <= STATE_WAIT;
+            idle_cycles <= 0;
+        end
+
+	  //
+	  // now wait here for 8 clock cycles before transitioning to STATE_THINK.
+	  // We stay in this state if no local FIFO's can proceed at this point.
+	  //
+        STATE_WAIT: begin
+            if (local_fifo_ready) begin
+                idle_cycles <= idle_cycles + 1'b1;
+                if (idle_cycles == 3'b111) state <= STATE_THINK;
+            end
+            else begin
+                idle_cycles <= 3'b0;
+                fifoadr <= fifoadr + 2'b1;
+            end
+        end
+
+	  //
+	  // If there is a read to start, assert SLRD and SLOE and transition to STATE_READ.
+	  // If there is a write to perform, set flags that says there is the possibility to do at least
+	  // one write (wr_one) and transition to STATE_WRITE
+	  //
+        STATE_THINK: begin
+
+            if (EP_READY1 && read_ready_go) begin
+                state <= STATE_READ;
+                slrd <= 0;
+                rd_one <= 0;
+            end
+            else if (EP_READY1 && write_ready_go) begin
+                state <= STATE_WRITE;
+                sloe <= 1;
+                wr_one <= 1'b0;
+            end
+            else begin
+                state <= STATE_IDLE;
+            end
+
+            idle_cycles <= 0;
+            last_addr <= fifoadr;
+        end
+
+	  // If flag rd_one is set (armed 5 cycles after slrd goes initialy assrted) and RD_VALID has gone deasserted
+	  // (meaning that the watermark deasserted 5 clock cycles ago) transition to STATE_IDLE.
+	  // If watermark deasserted 2 cycles ago de-assert slrd ...read data is still traveling in the pipeline.
+	  // Whilst RD_VALID stays asserted keep the rd_one flag armed.
+        STATE_READ: begin
+            if (rd_one && ~RD_VALID) state <= STATE_IDLE;
+            if (~EP_WMARK1 | fifo_nearly_full) slrd <= 1;
+            if (RD_VALID) rd_one <= 1'b1;
+        end
+
+	  // If local FIFO goes empty or tlast is set then transition to STATE_IDLE
+	  // Push local FIFO data out onto GPIF data bus.
+	  // if local FIFO has valid data then assert slwr
+	  // if local FIFO assertes tlast then assert pktend
+	  // If WR_VALID asserted (because wr_one already asserted in the first cycle in this state)
+	  // now clear wr_one (watermark will keep WR_VALID asserted from now on if this is a burst).
+	  //
+        STATE_WRITE: begin
+            if (~wr_fifo_xfer || wr_fifo_eof) state <= STATE_IDLE;
+            gpif_data_out <= wr_fifo_data;
+            slwr <= ~wr_fifo_xfer;
+            pktend <= ~wr_fifo_eof;
+            if (WR_VALID) wr_one <= 1'b1;
+        end
+
+        default: state <= STATE_IDLE;
+        endcase
+    end
+
+   // ///////////////////////////////////////////////////////////////////
+   // fifo signal assignments and enables
+
+    //output from fifos - ready to xfer
+    wire data_tx_tready, ctrl_tx_tready;
+    wire ctrl_rx_tvalid, data_rx_tvalid;
+
+    //Priority encoding for the the next address to service:
+    //The next address to service is based on the readiness
+    //of the internal fifos and last serviced fairness metric.
+    always @(posedge gpif_clk) next_addr <=
+        ((ctrl_rx_tvalid && last_addr != ADDR_CTRL_RX)? ADDR_CTRL_RX :
+        ((ctrl_tx_fifo_has_space && last_addr != ADDR_CTRL_TX)? ADDR_CTRL_TX :
+        ((data_rx_tvalid && last_addr != ADDR_DATA_RX)? ADDR_DATA_RX :
+        ((data_tx_fifo_has_space && last_addr != ADDR_DATA_TX)? ADDR_DATA_TX :
+        (fifoadr + 2'b1)
+    ))));
+
+    //Help the FPGA search to only look for addrs that the FPGA is ready for
+    assign local_fifo_ready =
+        (ctrl_rx_tvalid && (fifoadr == ADDR_CTRL_RX)) ||
+        (ctrl_tx_fifo_has_space && (fifoadr == ADDR_CTRL_TX)) ||
+        (data_rx_tvalid && (fifoadr == ADDR_DATA_RX)) ||
+        (data_tx_fifo_has_space && (fifoadr == ADDR_DATA_TX));
+
+    always @(posedge gpif_clk) fifo_nearly_full <=
+        (ctrl_tx_fifo_nearly_full && (fifoadr == ADDR_CTRL_TX)) ||
+        (data_tx_fifo_nearly_full && (fifoadr == ADDR_DATA_TX));
+
+    always @(posedge gpif_clk) read_ready_go <=
+        (ctrl_tx_fifo_has_space && (fifoadr == ADDR_CTRL_TX)) ||
+        (data_tx_fifo_has_space && (fifoadr == ADDR_DATA_TX));
+
+    always @(posedge gpif_clk) write_ready_go <=
+        (ctrl_rx_tvalid && (fifoadr == ADDR_CTRL_RX)) ||
+        (data_rx_tvalid && (fifoadr == ADDR_DATA_RX));
+
+    //fifo xfer enable
+    wire data_rx_tready = (state == STATE_WRITE) && (fifoadr == ADDR_DATA_RX) && WR_VALID;
+    wire ctrl_rx_tready = (state == STATE_WRITE) && (fifoadr == ADDR_CTRL_RX) && WR_VALID;
+    wire data_tx_tvalid = (state == STATE_READ) && (fifoadr == ADDR_DATA_TX) && RD_VALID;
+    wire ctrl_tx_tvalid = (state == STATE_READ) && (fifoadr == ADDR_CTRL_TX) && RD_VALID;
+
+    //outputs from rx fifo paths
+    wire ctrl_rx_tlast, data_rx_tlast;
+    wire [31:0] ctrl_rx_tdata, data_rx_tdata;
+
+    //mux rx outputs for gpif state machine
+    assign wr_fifo_xfer = (fifoadr == ADDR_CTRL_RX)? (ctrl_rx_tvalid && ctrl_rx_tready) : (data_rx_tvalid && data_rx_tready);
+    assign wr_fifo_eof = wr_fifo_xfer && ((fifoadr == ADDR_CTRL_RX)? ctrl_rx_tlast : data_rx_tlast);
+    assign wr_fifo_data = (fifoadr == ADDR_CTRL_RX)? ctrl_rx_tdata : data_rx_tdata;
+
+    wire ctrl_bus_error, tx_bus_error;
+
+   // ////////////////////////////////////////////////////////////////////
+   // TX Data Path
+
+    gpif2_to_fifo64 #(.FIFO_SIZE(DATA_TX_FIFO_SIZE)) gpif2_to_fifo64_tx(
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .i_tdata(gpif_data_in), .i_tlast(RD_LAST), .i_tvalid(data_tx_tvalid), .i_tready(data_tx_tready),
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), 
+        .fifo_nearly_full(data_tx_fifo_nearly_full), .fifo_has_space(data_tx_fifo_has_space),
+        .o_tdata(tx_tdata), .o_tlast(tx_tlast), .o_tvalid(tx_tvalid), .o_tready(tx_tready),
+        .bus_error(tx_bus_error), .debug(debug_tx_data)
+    );
+
+   // ////////////////////////////////////////////
+   // RX Data Path
+
+    fifo64_to_gpif2 #(.FIFO_SIZE(DATA_RX_FIFO_SIZE)) fifo64_to_gpif2_rx(
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+        .i_tdata(rx_tdata), .i_tlast(rx_tlast), .i_tvalid(rx_tvalid), .i_tready(rx_tready),
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .o_tdata(data_rx_tdata), .o_tlast(data_rx_tlast), .o_tvalid(data_rx_tvalid), .o_tready(data_rx_tready)
+    );
+
+   // ////////////////////////////////////////////////////////////////////
+   // CTRL path
+
+    gpif2_to_fifo64 #(.FIFO_SIZE(CTRL_TX_FIFO_SIZE)) gpif2_to_fifo64_ctrl(
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .i_tdata(gpif_data_in), .i_tlast(RD_LAST), .i_tvalid(ctrl_tx_tvalid), .i_tready(ctrl_tx_tready),
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), 
+        .fifo_nearly_full(ctrl_tx_fifo_nearly_full), .fifo_has_space(ctrl_tx_fifo_has_space),
+        .o_tdata(ctrl_tdata), .o_tlast(ctrl_tlast), .o_tvalid(ctrl_tvalid), .o_tready(ctrl_tready),
+        .bus_error(ctrl_bus_error), .debug(debug_tx_ctrl)
+    );
+
+   // ////////////////////////////////////////////////////////////////////
+   // RESP path
+
+    fifo64_to_gpif2 #(.FIFO_SIZE(CTRL_RX_FIFO_SIZE)) fifo64_to_gpif2_resp(
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+        .i_tdata(resp_tdata), .i_tlast(resp_tlast), .i_tvalid(resp_tvalid), .i_tready(resp_tready),
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .o_tdata(ctrl_rx_tdata), .o_tlast(ctrl_rx_tlast), .o_tvalid(ctrl_rx_tvalid), .o_tready(ctrl_rx_tready)
+    );
+
+   // ////////////////////////////////////////////
+   //    DEBUG
+
+    wire [31:0] debug0 = {
+        sloe, slrd, slwr, pktend, fifoadr, EP_READY, EP_WMARK, //8
+        state, //4
+        data_tx_tvalid, data_tx_tready, data_rx_tvalid, data_rx_tready, //4
+        gpif_d[15:0] //16
+    };
+
+    reg [31:0] debug_reg0;
+    reg [31:0] debug_reg1;
+    reg [31:0] debug_reg2;
+    always @(posedge gpif_clk) debug_reg0 <= debug0;
+    always @(posedge gpif_clk) debug_reg1 <= debug_reg0;
+    always @(posedge gpif_clk) debug_reg2 <= debug_reg1;
+    assign debug = debug_reg2;
+
+   wire [37:0] debug_resp = {
+			     resp_tlast,        // 37
+			     resp_tready,       // 36
+			     resp_tvalid,       // 35
+			     ctrl_rx_tlast,     // 34
+			     ctrl_rx_tready,    // 33
+			     ctrl_rx_tvalid,    // 32
+			     ctrl_rx_tdata      // 31:0
+			     };
+   
+   
+    reg [255:0] debug1,debug2;
+   
+    always @(posedge gpif_clk) debug1 <= {debug_resp,debug_tx_ctrl,debug0};
+   always @(posedge gpif_clk) debug2 <= debug1;
+   
+   
+ 
+   wire [35:0] CONTROL0,CONTROL1;
+ /*
+   chipscope_ila_32 chipscope_ila_32(
+				   .CONTROL(CONTROL0), // INOUT BUS [35:0]
+				   .CLK(gpif_clk), // IN
+				   .TRIG0(debug2) // IN BUS [31:0]
+				   );
+   
+   chipscope_ila_128  chipscope_ila_128(
+				   .CONTROL(CONTROL1), // INOUT BUS [35:0]
+				   .CLK(fifo_clk), // IN
+				   .TRIG0({debug4,debug6}) // IN BUS [31:0]
+				   );
+   
+   
+   chipscope_ila_256 chipscope_ila_256(
+				     .CONTROL(CONTROL0), // INOUT BUS [35:0]
+				     .CLK(gpif_clk), // IN
+				     .TRIG0(debug2) // IN BUS [31:0]
+				     );
+  
+  chipscope_ila_32  chipscope_ila_32_2(
+				   .CONTROL(CONTROL1), // INOUT BUS [35:0]
+				   .CLK(gpif_clk), // IN
+				   .TRIG0(32'd0) // IN BUS [31:0]
+				   );
+   
+   chipscope_icon  chipscope_icon(
+				 .CONTROL0(CONTROL0), // INOUT BUS [35:0]
+				   .CONTROL1(CONTROL1) // INOUT BUS [35:0]
+				    );
+
+   */
+endmodule // gpif2_slave_fifo32
diff --git a/fpga/usrp3/lib/gpif2/gpif2_to_fifo64.v b/fpga/usrp3/lib/gpif2/gpif2_to_fifo64.v
new file mode 100644
index 000000000..3d60c7326
--- /dev/null
+++ b/fpga/usrp3/lib/gpif2/gpif2_to_fifo64.v
@@ -0,0 +1,118 @@
+//
+// Copyright 2012-2013 Ettus Research LLC
+//
+
+
+module gpif2_to_fifo64
+#(
+    parameter FIFO_SIZE = 9
+)
+(
+    //input interface
+    input gpif_clk, input gpif_rst,
+    input [31:0] i_tdata,
+    input i_tlast,
+    input i_tvalid,
+    output i_tready,
+    output fifo_has_space,
+    output fifo_nearly_full,
+ 
+    //output fifo interface
+    input fifo_clk, input fifo_rst,
+    output [63:0] o_tdata,
+    output o_tlast,
+    output o_tvalid,
+    input o_tready,
+
+    output bus_error,
+    output [159:0] debug
+);
+
+    wire [31:0] int_tdata;
+    wire int_tlast;
+    wire int_tvalid, int_tready;
+
+    wire [31:0] int0_tdata; wire int0_tlast, int0_tvalid, int0_tready;
+
+    //this fifo provides a space signal so we know a burst is possible
+    localparam BURST_SIZE = (FIFO_SIZE < 8)? FIFO_SIZE : 8;
+    wire [15:0] space;
+  
+   
+    assign fifo_has_space = space >= (1 << BURST_SIZE);
+    assign  fifo_nearly_full = (space < 6); // 5 spaces left.
+   
+    axi_fifo #(.WIDTH(33), .SIZE(0)) ingress_timing_fifo
+    (
+        .clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
+        .i_tdata({i_tlast, i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready), .space(),
+        .o_tdata({int0_tlast, int0_tdata}), .o_tvalid(int0_tvalid), .o_tready(int0_tready), .occupied()
+    );
+    axi_fifo #(.WIDTH(33), .SIZE(BURST_SIZE)) min_read_buff
+    (
+        .clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
+        .i_tdata({int0_tlast, int0_tdata}), .i_tvalid(int0_tvalid), .i_tready(int0_tready), .space(space),
+        .o_tdata({int_tlast, int_tdata}), .o_tvalid(int_tvalid), .o_tready(int_tready), .occupied()
+    );
+  
+ reg 	   input_write_error;
+   
+   always @(posedge gpif_clk)  input_write_error <= i_tvalid & ~i_tready;
+   
+
+    wire [31:0] chk_tdata;
+    wire chk_tlast;
+    wire chk_tvalid, chk_tready;
+
+    axi_fifo_2clk #(.WIDTH(33), .SIZE(0/*SRL*/)) cross_clock_fifo
+    (
+        .reset(fifo_rst | gpif_rst),
+        .i_aclk(gpif_clk), .i_tdata({int_tlast, int_tdata}), .i_tvalid(int_tvalid), .i_tready(int_tready),
+        .o_aclk(fifo_clk), .o_tdata({chk_tlast, chk_tdata}), .o_tvalid(chk_tvalid), .o_tready(chk_tready)
+    );
+
+    wire [31:0] o32_tdata;
+    wire o32_tlast;
+    wire o32_tvalid, o32_tready;
+
+    //reframes a tlast from the vita header - and drops bad packets
+    //*
+    gpif2_error_checker #(.SIZE(FIFO_SIZE)) checker
+    (
+        .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+        .i_tdata(chk_tdata), .i_tlast(chk_tlast), .i_tvalid(chk_tvalid), .i_tready(chk_tready),
+        .o_tdata(o32_tdata), .o_tlast(o32_tlast), .o_tvalid(o32_tvalid), .o_tready(o32_tready),
+        .bus_error(bus_error), .debug(debug[63:0])
+    );
+    //*/
+    //assign o32_tdata = chk_tdata;
+    //assign o32_tlast = chk_tlast;
+    //assign o32_tvalid = chk_tvalid;
+    //assign chk_tready = o32_tready;
+
+    axi_fifo32_to_fifo64 fifo32_to_fifo64
+    (
+        .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+        .i_tdata(o32_tdata), .i_tuser(2'b0/*always 32 bits*/), .i_tlast(o32_tlast), .i_tvalid(o32_tvalid), .i_tready(o32_tready),
+        .o_tdata(o_tdata), .o_tuser(/*ignored cuz vita has len*/), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
+    );
+
+  assign debug[159:64] = {
+			  fifo_nearly_full, // 146
+			  space[9:0],      // 145:136
+			  input_write_error, // 135
+			  int_tlast,       // 134
+			  int_tready,      // 133
+			  int_tvalid,      // 132
+			  i_tlast,         // 131
+			  i_tready,    // 130
+			  fifo_has_space,        // 129
+			  i_tvalid,        // 128
+			  int_tdata[31:0], // 127:96
+			  i_tdata[31:0]    // 95:64
+			  };
+
+   
+   
+
+endmodule //fifo_to_gpif2
diff --git a/fpga/usrp3/lib/packet_proc/.gitignore b/fpga/usrp3/lib/packet_proc/.gitignore
new file mode 100644
index 000000000..ca543057c
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/.gitignore
@@ -0,0 +1,3 @@
+vita.txt
+xo.txt
+zpu.txt
diff --git a/fpga/usrp3/lib/packet_proc/Makefile.srcs b/fpga/usrp3/lib/packet_proc/Makefile.srcs
new file mode 100644
index 000000000..078609514
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/Makefile.srcs
@@ -0,0 +1,21 @@
+#
+# Copyright 2013 Ettus Research LLC
+#
+
+##################################################
+# Packet Processing Sources
+##################################################
+PACKET_PROC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/packet_proc/, \
+eth_dispatch.v \
+ip_hdr_checksum.v \
+vrlp_eth_framer.v \
+chdr_eth_framer.v \
+eth_interface.v \
+vrlp_to_compressed_vita.v \
+compressed_vita_to_vrlp.v \
+source_flow_control.v \
+cvita_insert_tlast.v \
+cvita_dest_lookup.v \
+cvita_chunker.v \
+cvita_dechunker.v \
+))
diff --git a/fpga/usrp3/lib/packet_proc/chdr_eth_framer.v b/fpga/usrp3/lib/packet_proc/chdr_eth_framer.v
new file mode 100644
index 000000000..ac56a7a32
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/chdr_eth_framer.v
@@ -0,0 +1,136 @@
+
+// chdr_eth_framer
+//  Takes a CHDR stream in and adds udp, ip, and ethernet framing
+//  Uses 8 setting reg addresses.  First 4 are simple registers:
+//    BASE+0 : Upper 16 bits of ethernet src mac
+//    BASE+1 : Lower 32 bits of ethernet src mac
+//    BASE+2 : IP src address
+//    BASE+3 : UDP src port
+//
+//  Next 4 control write ports on a RAM indexed by destination field of stream ID
+//    BASE+4 : Dest SID for next 3 regs
+//    BASE+5 : Dest IP
+//    BASE+6 : Dest UDP port, upper 16 bits of dest mac
+//    BASE+7 : Lower 32 bits of dest mac
+//
+
+module chdr_eth_framer
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [63:0] in_tdata, input in_tlast, input in_tvalid, output in_tready,
+    output [63:0] out_tdata, output [3:0] out_tuser, output out_tlast, output out_tvalid, input out_tready,
+    output [31:0] debug );
+
+   localparam SR_AWIDTH = 8;
+   
+   reg [7:0] 	  sid;
+   reg [15:0] 	  chdr_len;
+   
+   reg [2:0] 	  vef_state;
+   localparam VEF_IDLE    = 3'd0;
+   localparam VEF_PAYLOAD = 3'd7;
+   
+   reg [63:0] 	  tdata;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  vef_state <= VEF_IDLE;
+	  sid <= 8'd0;
+	  chdr_len <= 16'd0;
+       end
+     else
+       case(vef_state)
+	 VEF_IDLE :
+	   if(in_tvalid)
+	     begin
+		vef_state <= 1;
+		sid <= in_tdata[7:0];
+		chdr_len <= in_tdata[47:32];
+	     end
+	 VEF_PAYLOAD :
+	   if(in_tvalid & out_tready)
+	     if(in_tlast)
+	       vef_state <= VEF_IDLE;
+	 default :
+	   if(out_tready)
+	     vef_state <= vef_state + 3'd1;
+       endcase // case (vef_state)
+
+   assign in_tready = (vef_state == VEF_PAYLOAD) ? out_tready : 1'b0;
+   assign out_tvalid = (vef_state == VEF_PAYLOAD) ? in_tvalid : (vef_state == VEF_IDLE) ? 1'b0 : 1'b1;
+   assign out_tlast = (vef_state == VEF_PAYLOAD) ? in_tlast : 1'b0;
+   assign out_tuser = ((vef_state == VEF_PAYLOAD) & in_tlast) ? {1'b0,chdr_len[2:0]} : 4'b0000;
+   assign out_tdata = tdata;
+
+   wire [47:0] pad = 48'h0;
+   wire [47:0] mac_src, mac_dst;
+   wire [15:0] eth_type = 16'h0800;
+   wire [15:0] misc_ip = { 4'd4 /* IPv4 */, 4'd5 /* IP HDR Len */, 8'h00 /* DSCP and ECN */};
+   wire [15:0] ip_len = (16'd28 + chdr_len);  // 20 for IP, 8 for UDP
+   wire [15:0] ident = 16'h0;
+   wire [15:0] flag_frag = { 3'b010 /* don't fragment */, 13'h0 };
+   wire [15:0] ttl_prot = { 8'h10 /* TTL */, 8'h11 /* UDP */ };
+   wire [15:0] iphdr_checksum;
+   wire [31:0] ip_src, ip_dst;
+   wire [15:0] udp_src, udp_dst;
+   wire [15:0] udp_len = (16'd8 + chdr_len);
+   wire [15:0] udp_checksum = 16'h0;
+
+   setting_reg #(.my_addr(BASE), .awidth(SR_AWIDTH), .width(16)) set_mac_upper
+     (.clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(mac_src[47:32]), .changed());
+   
+   setting_reg #(.my_addr(BASE+1), .awidth(SR_AWIDTH), .width(32)) set_mac_lower
+     (.clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(mac_src[31:0]), .changed());
+   
+   setting_reg #(.my_addr(BASE+2), .awidth(SR_AWIDTH), .width(32)) set_ip
+     (.clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(ip_src), .changed());
+
+   setting_reg #(.my_addr(BASE+3), .awidth(SR_AWIDTH), .width(16)) set_udp
+     (.clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(udp_src), .changed());
+
+   // Tables of MAC/IP/UDP addresses
+   wire [7:0]  ram_addr;  // FIXME we could skip this part if we had wider SR addresses
+   
+   setting_reg #(.my_addr(BASE+4), .awidth(SR_AWIDTH), .width(8)) set_ram_addr
+     (.clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(ram_addr), .changed());
+
+   ram_2port #(.DWIDTH(32), .AWIDTH(8)) ram_ip
+     (.clka(clk), .ena(1'b1), .wea(set_stb & (set_addr == BASE+5)), .addra(ram_addr), .dia(set_data), .doa(),
+      .clkb(clk), .enb(1'b1), .web(1'b0), .addrb(sid[7:0]), .dib(32'hFFFF_FFFF), .dob(ip_dst));
+   
+   ram_2port #(.DWIDTH(32), .AWIDTH(8)) ram_udpmac
+     (.clka(clk), .ena(1'b1), .wea(set_stb & (set_addr == BASE+6)), .addra(ram_addr), .dia(set_data), .doa(),
+      .clkb(clk), .enb(1'b1), .web(1'b0), .addrb(sid[7:0]), .dib(32'hFFFF_FFFF), .dob({udp_dst,mac_dst[47:32]}));
+   
+   ram_2port #(.DWIDTH(32), .AWIDTH(8)) ram_maclower
+     (.clka(clk), .ena(1'b1), .wea(set_stb & (set_addr == BASE+7)), .addra(ram_addr), .dia(set_data), .doa(),
+      .clkb(clk), .enb(1'b1), .web(1'b0), .addrb(sid[7:0]), .dib(32'hFFFF_FFFF), .dob(mac_dst[31:0]));
+   
+   ip_hdr_checksum ip_hdr_checksum
+     (.clk(clk), .in({misc_ip,ip_len,ident,flag_frag,ttl_prot,16'd0,ip_src,ip_dst}),
+      .out(iphdr_checksum));
+
+   always @*
+     case(vef_state)
+       1 : tdata <= { pad[47:0], mac_dst[47:32]};
+       2 : tdata <= { mac_dst[31:0], mac_src[47:16]};
+       3 : tdata <= { mac_src[15:0], eth_type[15:0], misc_ip[15:0], ip_len[15:0] };
+       4 : tdata <= { ident[15:0], flag_frag[15:0], ttl_prot[15:0], iphdr_checksum[15:0]};
+       5 : tdata <= { ip_src, ip_dst};
+       6 : tdata <= { udp_src, udp_dst, udp_len, udp_checksum};
+       default : tdata <= in_tdata;
+     endcase // case (vef_state)
+      
+endmodule // chdr_eth_framer
diff --git a/fpga/usrp3/lib/packet_proc/compressed_vita_to_vrlp.v b/fpga/usrp3/lib/packet_proc/compressed_vita_to_vrlp.v
new file mode 100644
index 000000000..11595f200
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/compressed_vita_to_vrlp.v
@@ -0,0 +1,78 @@
+
+module compressed_vita_to_vrlp
+  (input clk, input reset, input clear,
+   input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+   output [63:0] o_tdata, output [15:0] o_tuser, output o_tlast, output o_tvalid, input o_tready
+   );
+
+   wire [19:0] 	 vrlp_size = 20'd3 + {4'b0000,i_tdata[47:32]};
+   reg 		 odd_len;
+   reg [2:0] 	 cv2v_state;
+
+   reg [63:0] 	 o_tdata_int;
+   wire 	 o_tlast_int, o_tvalid_int, o_tready_int;
+   
+   localparam CV2V_VRLP      = 3'd0; // VRLP header
+   localparam CV2V_VRT_ECH   = 3'd1; // Extension context header
+   localparam CV2V_VRT_IFH   = 3'd2; // IF Data header
+   localparam CV2V_BODY      = 3'd3;
+   localparam CV2V_VEND_ODD  = 3'd4;
+   localparam CV2V_VEND_EVEN = 3'd4;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  cv2v_state <= CV2V_VRLP;
+	  odd_len <= 1'b0;
+       end
+     else
+       case(cv2v_state)
+	 CV2V_VRLP :
+	   if(i_tvalid & o_tready_int)
+	     begin
+		odd_len <= i_tdata[32];
+		if(i_tdata[63])
+		  cv2v_state <= CV2V_VRT_ECH;
+		else
+		  cv2v_state <= CV2V_VRT_IFH;
+	     end
+
+	 CV2V_VRT_ECH, CV2V_VRT_IFH :
+	   if(i_tvalid & o_tready_int)
+	     cv2v_state <= CV2V_BODY;
+
+	 CV2V_BODY :
+	   if(i_tlast & i_tvalid & o_tready_int)
+	     if(odd_len)
+	       cv2v_state <= CV2V_VRLP;
+	     else
+	       cv2v_state <= CV2V_VEND_EVEN;
+	 
+	 CV2V_VEND_EVEN :
+	   if(o_tready_int)
+	     cv2v_state <= CV2V_VRLP;
+       endcase // case (cv2v_state)
+   
+   assign i_tready = o_tready_int & (cv2v_state != CV2V_VRLP) & (cv2v_state != CV2V_VEND_EVEN);
+   assign o_tvalid_int = i_tvalid | (cv2v_state == CV2V_VEND_EVEN);
+
+   always @*
+     case(cv2v_state)
+       CV2V_VRLP      : o_tdata_int <= { 32'h5652_4c50 /*VRLP*/, i_tdata[59:48] /*seqnum*/, vrlp_size[19:0] };
+       CV2V_VRT_ECH   : o_tdata_int <= { 4'h5 /*type*/, 4'h0, 3'b00, i_tdata[61] /*time*/, i_tdata[51:48] /*seqnum*/, i_tdata[47:32] /*len*/, i_tdata[31:0] /*sid*/ };
+       CV2V_VRT_IFH   : o_tdata_int <= { 4'h1 /*type*/, 1'b0, i_tdata[62] /*TRL*/, 1'b0, i_tdata[60] /*eob*/, 3'b00, i_tdata[61] /*time*/, i_tdata[51:48] /*seqnum*/, i_tdata[47:32] /*len*/, i_tdata[31:0] /*sid*/ };
+       CV2V_BODY      : o_tdata_int <= (i_tlast & odd_len) ? { i_tdata[63:32], 32'h5645_4E44 /*VEND*/ } : i_tdata;
+       CV2V_VEND_EVEN : o_tdata_int <= { 32'h5645_4E44 /*VEND*/, 32'h0};
+       default : o_tdata_int <= i_tdata;
+     endcase // case (cv2v_state)
+   
+   assign o_tlast_int = (cv2v_state == CV2V_VEND_EVEN) | ((cv2v_state == CV2V_BODY) & i_tlast & odd_len);
+
+   // Short FIFO before output
+   axi_fifo_short #(.WIDTH(81)) axi_fifo_short
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({o_tlast_int, i_tdata[15:0], o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+      .o_tdata({o_tlast, o_tuser, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .space(), .occupied());
+   
+endmodule // compressed_vita_to_vrlp
diff --git a/fpga/usrp3/lib/packet_proc/cvita_chunker.v b/fpga/usrp3/lib/packet_proc/cvita_chunker.v
new file mode 100644
index 000000000..cbc34d00a
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/cvita_chunker.v
@@ -0,0 +1,91 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+// Quantize cvita packets to a configurable quantum value. o_tlast and 
+// i_tready will be held off until the entire quantized packet is xferred. 
+// If quantum is changed, it is the responsibility of the client to clear
+// this module. error is asserted if a packet is larger than the quantum
+// error can be reset by asserting reset or clear.
+
+module cvita_chunker # (
+   parameter PAD_VALUE = 64'hFFFFFFFF_FFFFFFFF
+) (
+   input          clk,
+   input          reset,
+   input          clear,
+   input [15:0]   frame_size,
+
+   input [63:0]   i_tdata,
+   input          i_tlast,
+   input          i_tvalid,
+   output         i_tready,
+   
+   output [63:0]  o_tdata,
+   output         o_tlast,
+   output         o_tvalid,
+   input          o_tready,
+   
+   output         error
+);
+
+   localparam ST_HEADER  = 2'd0;
+   localparam ST_DATA    = 2'd1;
+   localparam ST_PADDING = 2'd2;
+   localparam ST_ERROR   = 2'd3;
+
+   reg [1:0]   state;
+   reg [15:0]  frame_rem;
+
+   wire [15:0] cvita_len_ceil = i_tdata[47:32] + 7;
+   wire [15:0] axi_len = {3'b000, cvita_len_ceil[15:3]};
+
+   always @(posedge clk) begin
+      if (reset | clear) begin
+         state <= ST_HEADER;
+         frame_rem <= 16'd0;
+      end else if (o_tvalid & o_tready) begin
+         case (state)
+            ST_HEADER: begin
+               if (axi_len > frame_size)
+                  state <= ST_ERROR;
+               else if (i_tlast)
+                  state <= ST_PADDING;
+               else
+                  state <= ST_DATA;
+                  
+               frame_rem <= frame_size - 16'd1;
+            end
+
+            ST_DATA: begin
+               if (i_tlast) begin
+                  state   <= o_tlast ? ST_HEADER : ST_PADDING;
+                  frame_rem <= o_tlast ? 16'd0 : (frame_rem - 16'd1);
+               end else begin
+                  state <= ST_DATA;
+                  frame_rem <= frame_rem - 16'd1;
+               end
+            end
+
+            ST_PADDING: begin
+               if (o_tlast) begin
+                  state   <= ST_HEADER;
+                  frame_rem <= 16'd0;
+               end else begin
+                  state   <= ST_PADDING;
+                  frame_rem <= frame_rem - 16'd1;
+               end
+            end
+         endcase
+      end
+   end
+
+   assign i_tready = o_tready & (state != ST_PADDING);
+   
+   assign o_tvalid = i_tvalid | (state == ST_PADDING);
+   assign o_tlast = (frame_rem != 0) ? (frame_rem == 16'd1) : (axi_len == 16'd1);
+   assign o_tdata = (state == ST_PADDING) ? PAD_VALUE : i_tdata;
+
+   assign error = (state == ST_ERROR);
+
+endmodule // cvita_chunker
diff --git a/fpga/usrp3/lib/packet_proc/cvita_chunker_tb.v b/fpga/usrp3/lib/packet_proc/cvita_chunker_tb.v
new file mode 100644
index 000000000..08f46d72a
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/cvita_chunker_tb.v
@@ -0,0 +1,187 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+`timescale 500ps/1ps
+
+module cvita_chunker_tb();
+
+   // TB stimulus
+   reg clk    = 0;
+   reg reset  = 1;
+   reg clear  = 0;
+   reg [15:0] quantum;
+
+   // Check vars
+   reg [31:0] o_xfer_count = 0, i_xfer_count = 0;
+   reg [63:0] o_last_tdata = 0;
+
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("cvita_chunker_tb.vcd");
+   initial $dumpvars(0,cvita_chunker_tb);
+
+   function check_result;
+      input [31:0]   o_xfer_count_arg;
+      input [31:0]   i_xfer_count_arg;
+      input [63:0]   o_last_tdata_arg;
+      input          error_arg;
+      begin
+         //Check vars
+         check_result = 1;
+         check_result = check_result & ((o_xfer_count_arg == o_xfer_count) !== 0);
+         check_result = check_result & ((i_xfer_count_arg == i_xfer_count) !== 0);
+         check_result = check_result & ((o_last_tdata_arg == o_last_tdata) !== 0);
+         check_result = check_result & ((error_arg == error) != 0);
+         
+         if (check_result) begin
+            $display ("... Passed");
+         end else begin
+            $display ("... FAILED!!!");
+            $display ("o_xfer_count = %d (Expected %d)",o_xfer_count,o_xfer_count_arg);
+            $display ("i_xfer_count = %d (Expected %d)",i_xfer_count,i_xfer_count_arg);
+            $display ("o_last_tdata = %h (Expected %h)",o_last_tdata,o_last_tdata_arg);
+            $display ("error = %d  (Expected %d)",error,error_arg);
+         end
+
+         //Reset vars
+         o_xfer_count = 0;
+         i_xfer_count = 0;
+         o_last_tdata = 64'h0;
+      end
+   endfunction
+
+   task send_packet;
+      input [63:0] data_start;
+      input [31:0] len;
+      
+      begin
+         if(len < 9) begin
+            {i_tlast, i_tdata} <= { 1'b1, data_start[63:48],len[15:0], data_start[31:0] };
+            i_tvalid <= 1;
+            @(posedge clk);
+            i_tvalid <= 0;
+         end else begin
+            {i_tlast, i_tdata} <= { 1'b0, data_start[63:48],len[15:0], data_start[31:0] };
+            i_tvalid <= 1;
+            @(posedge clk);
+            repeat(((len-1)/8)-1) begin
+               i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
+               @(posedge clk);
+            end
+            i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
+            i_tlast <= 1;
+            @(posedge clk);
+            i_tvalid <= 0;
+        end // else: !if(len < 3)
+      end
+   endtask // send_packet
+
+   task reset_quantum_atomic;
+      input [15:0] quant;
+      begin
+         quantum <= quant;
+         clear <= 1;
+         @(posedge clk);
+         clear <= 0;
+         @(posedge clk);
+      end
+   endtask // reset_quantum_atomic
+
+
+   initial begin
+      #100 reset = 0;
+      #200000;
+      $finish;
+   end
+   
+   reg [63:0]  i_tdata;
+   reg         i_tlast;
+   reg         i_tvalid;
+   wire        i_tready;
+
+   wire [63:0] o_tdata;
+   wire        o_tlast, o_tvalid, o_tready;
+   wire        error;
+   
+   initial begin
+      quantum <= 256;
+      i_tvalid <= 0;
+      while(reset) @(posedge clk);
+
+      $write ("Running test case: First packet after reset");
+      send_packet(64'h00000001_00000000, 128);
+      while(o_tvalid) @(posedge clk);
+      check_result(256,16,64'hFFFFFFFF_FFFFFFFF,0);
+
+      reset_quantum_atomic(8);
+
+      $write ("Running test case: sizeof(packet) < quantum");
+      send_packet(64'h00000001_00000000, 40);
+      while(o_tvalid) @(posedge clk);
+      check_result(8,5,64'hFFFFFFFF_FFFFFFFF,0);
+
+      reset_quantum_atomic(5);
+
+      $write ("Running test case: sizeof(packet) == quantum");
+      send_packet(64'h00000001_00000000, 40);
+      while(o_tvalid) @(posedge clk);
+      check_result(5,5,64'h00000030_00000008,0);
+      
+      $write ("Running test case: sizeof(packet) == quantum - 64bits");
+      send_packet(64'h00000001_00000000, 32);
+      while(o_tvalid) @(posedge clk);
+      check_result(5,4,64'hFFFFFFFF_FFFFFFFF,0);
+
+      $write ("Running test case: sizeof(packet) == quantum + 64bits");
+      send_packet(64'h00000001_00000000, 48);
+      while(o_tvalid) @(posedge clk);
+      check_result(32'hxxxxxxxx,32'hxxxxxxxx,64'hxxxxxxxx_xxxxxxxx,1);
+
+      $write ("Running test case: Error reset");
+      reset_quantum_atomic(8);
+      check_result(32'hxxxxxxxx,32'hxxxxxxxx,64'hxxxxxxxx_xxxxxxxx,0);
+      
+      $write ("Running test case: sizeof(packet) > quantum");
+      send_packet(64'h00000001_00000000, 80);
+      while(o_tvalid) @(posedge clk);
+      check_result(32'hxxxxxxxx,32'hxxxxxxxx,64'hxxxxxxxx_xxxxxxxx,1);
+
+      reset_quantum_atomic(8);
+
+      $write ("Running test case: sizeof(packet) == 2");
+      send_packet(64'h00000001_00000000, 8);
+      while(o_tvalid) @(posedge clk);
+      check_result(8,1,64'hFFFFFFFF_FFFFFFFF,0);
+
+      $write ("Running test case: Multiple packets back-to-back");
+      send_packet(64'h00000001_00000000, 40);
+      while(o_tvalid) @(posedge clk);
+      send_packet(64'h00000001_00000000, 16);
+      while(o_tvalid) @(posedge clk);
+      send_packet(64'h00000001_00000000, 64);
+      while(o_tvalid) @(posedge clk);
+      check_result(24,15,64'h0000004e0000000e,0);
+
+   end // initial begin
+
+
+   cvita_chunker dut (
+      .clk(clk), .reset(reset), .clear(clear), .frame_size(quantum),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .error(error));
+      
+   assign o_tready = 1;
+  
+   always @(posedge clk) begin
+      if (o_tvalid & o_tready) begin
+         o_xfer_count <= o_xfer_count + 1;
+         o_last_tdata <= o_tdata;
+      end
+      if (i_tvalid & i_tready) i_xfer_count <= i_xfer_count + 1;
+   end
+
+endmodule // cvita_chunker_tb
diff --git a/fpga/usrp3/lib/packet_proc/cvita_dechunker.v b/fpga/usrp3/lib/packet_proc/cvita_dechunker.v
new file mode 100644
index 000000000..2ad873305
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/cvita_dechunker.v
@@ -0,0 +1,90 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+module cvita_dechunker # (
+   parameter PAD_VALUE = 64'hFFFFFFFF_FFFFFFFF
+) (
+   input          clk,
+   input          reset,
+   input          clear,
+   input [15:0]   frame_size,
+
+   input [63:0]   i_tdata,
+   input          i_tvalid,
+   output         i_tready,
+   
+   output [63:0]  o_tdata,
+   output         o_tlast,
+   output         o_tvalid,
+   input          o_tready,
+
+   output         error
+);
+
+   localparam ST_HEADER  = 2'd0;
+   localparam ST_DATA    = 2'd1;
+   localparam ST_PADDING = 2'd2;
+   localparam ST_ERROR   = 2'd3;
+
+   reg [1:0]   state;
+   reg [15:0]  frame_rem, pkt_rem;
+   wire        i_tlast;
+
+   wire [15:0] cvita_len_ceil = i_tdata[47:32] + 7;
+   wire [15:0] axi_len = {3'b000, cvita_len_ceil[15:3]};
+
+   always @(posedge clk) begin
+      if (reset | clear) begin
+         state <= ST_HEADER;
+         frame_rem <= 16'd0;
+         pkt_rem   <= 16'd0;
+      end else if (i_tvalid & i_tready) begin
+         case (state)
+            ST_HEADER: begin
+               if (axi_len > frame_size)
+                  state <= ST_ERROR;
+               else if (~o_tlast)
+                  state <= ST_DATA;
+               else
+                  state <= ST_PADDING;
+                  
+               frame_rem <= frame_size - 16'd1;
+               pkt_rem   <= axi_len - 16'd1;
+            end
+         
+            ST_DATA: begin
+               if (o_tlast) begin
+                  state   <= i_tlast ? ST_HEADER : ST_PADDING;
+                  pkt_rem <= 16'd0;
+               end else begin
+                  state   <= ST_DATA;
+                  pkt_rem <= pkt_rem - 16'd1;
+               end
+               frame_rem <= frame_rem - 16'd1;
+            end
+
+            ST_PADDING: begin
+               if (i_tlast) begin
+                  state   <= ST_HEADER;
+                  frame_rem <= 16'd0;
+               end else begin
+                  state   <= ST_PADDING;
+                  frame_rem <= frame_rem - 16'd1;
+               end
+            end
+         endcase   
+      end   
+   end
+   
+   assign i_tready = o_tready | (state == ST_PADDING);
+   assign i_tlast = (frame_rem == 16'd1); //Temp signal
+   
+   assign o_tvalid = i_tvalid & (state != ST_PADDING);
+   assign o_tlast = (pkt_rem != 0) ? (pkt_rem == 16'd1) : (axi_len == 16'd1);
+   assign o_tdata  = i_tdata;
+   
+   assign error = (state == ST_ERROR);
+
+endmodule // cvita_dechunker
diff --git a/fpga/usrp3/lib/packet_proc/cvita_dechunker_tb.v b/fpga/usrp3/lib/packet_proc/cvita_dechunker_tb.v
new file mode 100644
index 000000000..198eb4c40
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/cvita_dechunker_tb.v
@@ -0,0 +1,183 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+`timescale 500ps/1ps
+
+module cvita_dechunker_tb();
+
+   // TB stimulus
+   reg clk    = 0;
+   reg reset  = 1;
+   reg clear  = 0;
+   reg [15:0] quantum;
+   wire error;
+
+   // Check vars
+   reg [31:0] o_xfer_count = 0, i_xfer_count = 0;
+   reg [63:0] o_last_tdata = 0;
+
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("cvita_dechunker_tb.vcd");
+   initial $dumpvars(0,cvita_dechunker_tb);
+
+   function check_result;
+      input [31:0]   o_xfer_count_arg;
+      input [31:0]   i_xfer_count_arg;
+      input [63:0]   o_last_tdata_arg;
+      input          error_arg;
+      begin
+         //Check vars
+         check_result = 1;
+         check_result = check_result & ((o_xfer_count_arg == o_xfer_count) !== 0);
+         check_result = check_result & ((i_xfer_count_arg == i_xfer_count) !== 0);
+         check_result = check_result & ((o_last_tdata_arg == o_last_tdata) !== 0);
+         check_result = check_result & ((error_arg == error) != 0);
+         
+         if (check_result) begin
+            $display ("... Passed");
+         end else begin
+            $display ("... FAILED!!!");
+            $display ("o_xfer_count = %d (Expected %d)",o_xfer_count,o_xfer_count_arg);
+            $display ("i_xfer_count = %d (Expected %d)",i_xfer_count,i_xfer_count_arg);
+            $display ("o_last_tdata = %h (Expected %h)",o_last_tdata,o_last_tdata_arg);
+            $display ("error = %d  (Expected %d)",error,error_arg);
+         end
+
+         //Reset vars
+         o_xfer_count = 0;
+         i_xfer_count = 0;
+         o_last_tdata = 64'h0;
+      end
+   endfunction
+
+   task send_packet;
+      input [63:0] data_start;
+      input [31:0] len;
+      input [31:0] quant;
+      
+      begin
+         if(quant < 2) begin
+            {i_tlast, i_tdata} <= { 1'b1, data_start[63:48],len[15:0], data_start[31:0] };
+            i_tvalid <= 1;
+            @(posedge clk);
+            i_tvalid <= 0;
+         end else begin
+            {i_tlast, i_tdata} <= { 1'b0, data_start[63:48],len[15:0], data_start[31:0] };
+            i_tvalid <= 1;
+            @(posedge clk);
+            repeat(quant - 2) begin
+               i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
+               @(posedge clk);
+            end
+            i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
+            i_tlast <= 1;
+            @(posedge clk);
+            i_tvalid <= 1'b0;
+         end // else: !if(len < 3)
+      end
+   endtask // send_packet
+
+   task reset_quantum_atomic;
+      input [15:0] quant;
+      begin
+         quantum <= quant;
+         clear <= 1;
+         @(posedge clk);
+         clear <= 0;
+         @(posedge clk);
+      end
+   endtask // reset_quantum_atomic
+
+
+   initial begin
+      #100 reset = 0;
+      #200000;
+      $finish;
+   end
+   
+   reg [63:0]  i_tdata;
+   reg         i_tlast;
+   reg         i_tvalid;
+   wire        i_tready;
+
+   wire [63:0] o_tdata;
+   wire        o_tlast, o_tvalid, o_tready;
+   
+   initial begin
+      quantum <= 8;
+      i_tvalid <= 0;
+      while(reset) @(posedge clk);
+
+      $write ("Running test case: First packet after reset");
+      send_packet(64'h00000001_00000000, 32, 8);
+      @(posedge clk);
+      check_result(4,8,64'hxxxxxxxx_xxxxxx06, 0);
+
+      reset_quantum_atomic(10);
+
+      $write ("Running test case: sizeof(packet) < quantum");
+      send_packet(64'h00000001_00000000, 64, 10);
+      @(posedge clk);
+      check_result(8,10,64'hxxxxxxxx_xxxxxx0e, 0);
+
+      $write ("Running test case: sizeof(packet) == quantum");
+      send_packet(64'h00000001_00000000, 80, 10);
+      @(posedge clk);
+      check_result(10,10,64'hxxxxxxxx_xxxxxx12, 0);
+      
+      $write ("Running test case: sizeof(packet) == quantum - 64bits");
+      send_packet(64'h00000001_00000000, 72, 10);
+      @(posedge clk);
+      check_result(9,10,64'hxxxxxxxx_xxxxxx10, 0);
+
+      $write ("Running test case: sizeof(packet) == quantum + 64bits");
+      send_packet(64'h00000001_00000000, 88, 10);
+      @(posedge clk);
+      check_result(32'hxxxxxxxx,10,64'hxxxxxxxx_xxxxxxxx, 1);
+
+      reset_quantum_atomic(10);
+
+      $write ("Running test case: sizeof(packet) > quantum");
+      send_packet(64'h00000001_00000000, 88, 10);
+      @(posedge clk);
+      check_result(32'hxxxxxxxx,10,64'hxxxxxxxx_xxxxxxxx, 1);
+
+      reset_quantum_atomic(8);
+
+      $write ("Running test case: sizeof(packet) == 2");
+      send_packet(64'h00000001_00000000, 8, 8);
+      @(posedge clk);
+      check_result(1,8,64'hxxxxxxxx_xxxxxx00, 0);
+
+      $write ("Running test case: Multiple packets");
+      send_packet(64'h00000001_00000000, 8, 8);
+      send_packet(64'h00000001_00000000, 16, 8);
+      send_packet(64'h00000001_00000000, 24, 8);
+      send_packet(64'h00000001_00000000, 32, 8);
+      @(posedge clk);
+      check_result(10,32,64'hxxxxxxxx_xxxxxx06, 0);
+
+   end // initial begin
+
+
+   cvita_dechunker dut (
+      .clk(clk), .reset(reset), .clear(clear), .frame_size(quantum),
+      .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .error(error));
+      
+   assign o_tready = 1;
+  
+   always @(posedge clk) begin
+      if (o_tvalid & o_tready) begin
+         o_xfer_count <= o_xfer_count + 1;
+         o_last_tdata <= o_tdata;
+      end
+      if (i_tvalid & i_tready) i_xfer_count <= i_xfer_count + 1;
+   end
+
+endmodule // cvita_dechunker_tb
diff --git a/fpga/usrp3/lib/packet_proc/cvita_dest_lookup.v b/fpga/usrp3/lib/packet_proc/cvita_dest_lookup.v
new file mode 100644
index 000000000..5951b127a
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/cvita_dest_lookup.v
@@ -0,0 +1,48 @@
+
+// Map the endpoint dest part of the SID in the CVITA header to a destination
+// This destination (o_tdest) signal will be valid with o_tdata
+// This only works with VALID CVITA frames
+
+module cvita_dest_lookup
+#(
+    parameter DEST_WIDTH = 4
+)
+(
+    input clk, input rst,
+    input set_stb, input [7:0] set_addr, input [DEST_WIDTH-1:0] set_data,
+    input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+    output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
+    output [DEST_WIDTH-1:0] o_tdest
+);
+
+    reg [7:0] endpoint;
+    ram_2port #(.DWIDTH(DEST_WIDTH), .AWIDTH(8)) dest_lut
+    (
+        .clka(clk), .ena(1'b1), .wea(set_stb), .addra(set_addr), .dia(set_data), .doa(),
+        .clkb(clk), .enb(1'b1), .web(1'b0), .addrb(endpoint), .dib(8'hff), .dob(o_tdest)
+    );
+
+    reg forward;
+    reg [1:0] count;
+    always @(posedge clk) begin
+        if (rst) begin
+            forward <= 1'b0;
+            count <= 2'b0;
+        end
+        else if (forward == 1'b0 && i_tvalid) begin
+            if (count == 2'b11) forward <= 1'b1;
+            endpoint <= i_tdata[23:16];
+            count <= count + 1'b1;
+        end
+        else if (forward == 1'b1 && i_tvalid && i_tready && i_tlast) begin
+            forward <= 1'b0;
+            count <= 2'b0;
+        end
+    end
+
+    assign o_tdata = i_tdata;
+    assign o_tlast = i_tlast;
+    assign o_tvalid = i_tvalid && forward;
+    assign i_tready = o_tready && forward;
+
+endmodule // cvita_dest_lookup
diff --git a/fpga/usrp3/lib/packet_proc/cvita_insert_tlast.v b/fpga/usrp3/lib/packet_proc/cvita_insert_tlast.v
new file mode 100644
index 000000000..8d5c4f981
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/cvita_insert_tlast.v
@@ -0,0 +1,33 @@
+
+// Insert tlast bit for fifos that don't support it.  This only works with VALID CVITA frames
+//  A single partial or invalid frame will make this wrong FOREVER
+
+module cvita_insert_tlast
+  (input clk, input reset, input clear,
+   input [63:0] i_tdata, input i_tvalid, output i_tready,
+   output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   assign o_tdata = i_tdata;
+   assign o_tvalid = i_tvalid;
+   assign i_tready = o_tready;
+
+   wire [15:0] cvita_len_ceil = i_tdata[47:32] + 7;
+   wire [15:0] axi_len = {3'b000, cvita_len_ceil[15:3]};
+   
+   reg [15:0] 	 count;
+
+   assign o_tlast = (count != 0) ? (count == 16'd1) : (axi_len == 16'd1);
+
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  count <= 16'd0;
+       end
+     else
+       if(i_tready & i_tvalid)
+	 if(count != 16'd0)
+	   count <= count - 16'd1;
+	 else
+	   count <= axi_len - 16'd1;
+   
+endmodule // cvita_insert_tlast
diff --git a/fpga/usrp3/lib/packet_proc/cvita_insert_tlast_tb.v b/fpga/usrp3/lib/packet_proc/cvita_insert_tlast_tb.v
new file mode 100644
index 000000000..6398c40a4
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/cvita_insert_tlast_tb.v
@@ -0,0 +1,92 @@
+`timescale 1ns/1ps
+
+module cvita_insert_tlast_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("cvita_insert_tlast_tb.vcd");
+   initial $dumpvars(0,cvita_insert_tlast_tb);
+
+   task send_packet;
+      input [63:0] data_start;
+      input [31:0] len;
+      
+      begin
+	 if(len < 9)
+	   begin
+	      {i_tlast, i_tdata} <= { 1'b1, data_start[63:48],len[15:0], data_start[31:0] };
+	      i_tvalid <= 1;
+	      @(posedge clk);
+	      i_tvalid <= 0;
+	   end
+	 else
+	   begin
+	      {i_tlast, i_tdata} <= { 1'b0, data_start[63:48],len[15:0], data_start[31:0] };
+	      i_tvalid <= 1;
+	      @(posedge clk);
+	      repeat(((len-2)/2)-1+len[0])
+		begin
+		   i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
+		   @(posedge clk);
+		end
+	      i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
+	      i_tlast <= 1;
+	      @(posedge clk);
+	      i_tvalid <= 1'b0;
+	   end // else: !if(len < 3)
+      end
+   endtask // send_packet
+   
+   initial
+     begin
+	#1000 reset = 0;
+	#200000;
+	$finish;
+     end
+   
+   reg [63:0] i_tdata;
+   reg 	      i_tlast;
+   reg 	      i_tvalid;
+   wire       i_tready;
+
+   wire [63:0] o_tdata;
+   wire        o_tlast, o_tvalid, o_tready, o_tlast_regen;
+   
+   initial
+     begin
+	i_tvalid <= 0;
+	
+	while(reset)
+	  @(posedge clk);
+	@(posedge clk);
+
+	send_packet(64'hA0000000_A0000001, 24);
+	send_packet(64'hA0000000_A0000001, 20);
+	send_packet(64'hA0000000_A0000001, 16);
+	send_packet(64'hA0000000_A0000001, 12);
+	send_packet(64'hA0000000_A0000001, 8);
+	send_packet(64'hA0000000_A0000001, 4);
+	send_packet(64'hA0000000_A0000001, 4);
+	send_packet(64'hA0000000_A0000001, 8);
+	send_packet(64'hA0000000_A0000001, 12);
+     end // initial begin
+
+   cvita_insert_tlast dut
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast_regen), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+   assign o_tready = 1;
+   
+
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       begin
+	  $display ("TLAST %x\t TLAST_REGEN %x",i_tlast, o_tlast_regen);
+	  if(i_tlast != o_tlast_regen)
+	    $display("ERROR!!!!!!");
+       end
+endmodule // cvita_insert_tlast_tb
diff --git a/fpga/usrp3/lib/packet_proc/eth_dispatch.v b/fpga/usrp3/lib/packet_proc/eth_dispatch.v
new file mode 100644
index 000000000..b600a1533
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/eth_dispatch.v
@@ -0,0 +1,573 @@
+
+// Ethernet dispatcher
+//  Incoming ethernet packets are examined and sent to the correct destination
+//  There are 3 destinations, ZPU, other ethernet port (out), and vita router
+//  Packets going to the vita router will have the ethernet/ip/udp headers stripped off.
+//
+//  To make things simpler, we start out by sending all packets to zpu and out port.
+//  By the end of the eth/ip/udp headers, we can determine where the correct destination is.
+//  If the correct destination is vita, we send an error indication on the zpu and out ports,
+//  which will cause the axi_packet_gate to drop those packets, and send the vita frame to
+//  the vita port.
+//
+//  If at the end of the headers we determine the packet should go to zpu, then we send an
+//  error indication on the out port, the rest of the packet to zpu and nothing on vita.  
+//  If it should go to out, we send the error indication to zpu, the rest of the packet to out,
+//  and nothing on vita.
+//
+//  Downstream we should have adequate fifo space, otherwise we could get backed up here.
+//
+//  No tuser bits sent to vita, as vita assumes there are no errors and that occupancy is
+//  indicated by the length field of the vita header.
+
+//
+// Rules for forwarding:
+//
+// Ethernet Broadcast (Dst MAC = ff:ff:ff:ff:ff:ff). Forward to both ZPU and XO MAC.
+// ? Ethernet Multicast (Dst MAC = USRP_NEXT_HOP). Forward only to ZPU.
+// ? Ethernet Multicast (Dst MAC = Unknown). Forward only to XO.
+// Ethernet Unicast (Dst MAC = Unknown). Forward only to XO.
+// Ethernet Unicast (Dst MAC = local). Look deeper......
+// IP Broadcast. Forward to both ZPU and XO MAC. (Should be coverd by Eth broadcast)
+// IP Multicast. ? Unknow Action.
+// IP Unicast (Dst IP = local). Look deeper....
+// UDP (Port = Listed) and its a VRLP packet. Forward only to VITA Radio Core.
+// UDP (Port = Unknown). Forward only to ZPU.
+//
+//
+
+module eth_dispatch
+  #(parameter BASE=0)
+   (
+    // Clocking and reset interface
+    input clk, 
+    input reset, 
+    input clear, 
+    // Setting register interface
+    input set_stb, 
+    input [15:0] set_addr, 
+    input [31:0] set_data,
+    // Input 68bit AXI-Stream interface (from MAC)
+    input [63:0] in_tdata, 
+    input [3:0] in_tuser, 
+    input in_tlast, 
+    input in_tvalid, 
+    output in_tready,
+    // Output AXI-STream interface to VITA Radio Core
+    output [63:0] vita_tdata,
+    output [3:0] vita_tuser, 
+    output vita_tlast, 
+    output vita_tvalid, 
+    input vita_tready,
+    // Output AXI-Stream interface to ZPU
+    output [63:0] zpu_tdata, 
+    output [3:0] zpu_tuser, 
+    output zpu_tlast, 
+    output zpu_tvalid, 
+    input zpu_tready,
+    // Output AXI-Stream interface to cross-over MAC
+    output [63:0] xo_tdata, 
+    output [3:0] xo_tuser, 
+    output xo_tlast, 
+    output xo_tvalid, 
+    input xo_tready,
+    // Debug
+    output [31:0] debug
+    );
+
+   //
+   // State machine declarations
+   //
+   reg [2:0] 	  state;
+   
+   localparam WAIT_PACKET = 0;
+   localparam READ_HEADER = 1;
+   localparam FORWARD_ZPU = 2;
+   localparam FORWARD_ZPU_AND_XO = 3;
+   localparam FORWARD_XO = 4;
+   localparam FORWARD_RADIO_CORE = 5;
+   localparam DROP_PACKET = 6;
+   localparam CLASSIFY_PACKET = 7;
+   
+      
+   //
+   // Small RAM stores packet header during parsing.
+   //
+   localparam HEADER_RAM_SIZE = 9;
+   (*ram_style="distributed"*)
+   reg [68:0] 	  header_ram [HEADER_RAM_SIZE-1:0];
+   reg [3:0] 	  header_ram_addr;
+   reg 		  drop_this_packet;
+
+   wire 	  header_done = (header_ram_addr == HEADER_RAM_SIZE-1);
+   reg fwd_input;
+
+   //
+   reg [63:0] 	  in_tdata_reg;
+   
+   //
+   wire 	  out_tvalid;
+   wire 	  out_tready;
+   wire 	  out_tlast;
+   wire [3:0] 	  out_tuser;
+   wire [63:0] 	  out_tdata;
+   
+   
+   
+   //
+   // Output AXI-STream interface to VITA Radio Core
+   wire [63:0] 	  vita_pre_tdata;
+   wire [3:0] 	  vita_pre_tuser; 
+   wire 	  vita_pre_tlast; 
+   wire 	  vita_pre_tvalid; 
+   wire 	  vita_pre_tready;
+   // Output AXI-Stream interface to ZPU
+   wire [63:0] 	  zpu_pre_tdata; 
+   wire [3:0] 	  zpu_pre_tuser; 
+   wire 	  zpu_pre_tlast; 
+   wire 	  zpu_pre_tvalid; 
+   wire 	  zpu_pre_tready;
+   // Output AXI-Stream interface to cross-over MAC
+   wire [63:0] 	  xo_pre_tdata; 
+   wire [3:0] 	  xo_pre_tuser; 
+   wire 	  xo_pre_tlast; 
+   wire 	  xo_pre_tvalid; 
+   wire 	  xo_pre_tready;
+
+   //
+   // Packet Parse Flags
+   //
+   reg 		  is_eth_dst_addr;
+   reg 		  is_eth_broadcast;
+   reg 		  is_eth_type_ipv4;
+   reg 		  is_ipv4_dst_addr;
+   reg 		  is_ipv4_proto_udp;
+   reg 		  is_ipv4_proto_icmp;
+   reg [1:0] 	  is_udp_dst_ports;
+   reg		  is_icmp_no_fwd;
+   reg 		  is_chdr;
+   
+
+   
+   
+
+   //
+   // Settings regs
+   //
+   
+   wire [47:0] 	  my_mac;
+   
+   setting_reg #(.my_addr(BASE), .awidth(16), .width(32)) sr_my_mac_lsb
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(my_mac[31:0]),.changed());
+
+   setting_reg #(.my_addr(BASE+1), .awidth(16), .width(16)) sr_my_mac_msb
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(my_mac[47:32]),.changed());
+
+   wire [31:0] 	  my_ip;
+   
+   setting_reg #(.my_addr(BASE+2), .awidth(16), .width(32)) sr_my_ip
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(my_ip[31:0]),.changed());
+   
+   wire [15:0] 	  my_port0, my_port1;
+   
+   setting_reg #(.my_addr(BASE+3), .awidth(16), .width(32)) sr_udp_port
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({my_port1[15:0],my_port0[15:0]}),.changed());
+
+   wire forward_ndest, forward_bcast;
+   setting_reg #(.my_addr(BASE+4), .awidth(16), .width(2)) sr_forward_ctrl
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({forward_ndest, forward_bcast}),.changed());
+
+   wire [7:0] my_icmp_type, my_icmp_code;
+   setting_reg #(.my_addr(BASE+5), .awidth(16), .width(16)) sr_icmp_ctrl
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({my_icmp_type, my_icmp_code}),.changed());
+
+    assign debug =
+    {
+    	1'b0, state, //4
+        1'b0, in_tvalid, in_tready, in_tlast, //4
+        1'b0, is_eth_dst_addr, is_eth_broadcast, is_eth_type_ipv4,
+        is_ipv4_dst_addr, is_ipv4_proto_udp, is_udp_dst_ports, //8
+        header_ram_addr[3:0], //4
+        4'b0, 8'b0
+    };
+
+
+   //
+   // Packet Forwarding State machine.
+   //
+   
+   always @(posedge clk) 
+     if (reset || clear) begin
+        state <= WAIT_PACKET;
+        header_ram_addr <= 0;
+	drop_this_packet <= 0;	 
+	fwd_input <= 0;
+     end else begin
+	// Defaults.
+	drop_this_packet <= 0;
+	
+	case(state)
+	  //
+	  // Wait for start of a packet
+	  // IJB: Add protection for a premature EOF here
+	  //
+	  WAIT_PACKET: begin 
+	     if (in_tvalid && in_tready) begin
+                header_ram[header_ram_addr] <= {in_tlast,in_tuser,in_tdata};
+                header_ram_addr <= header_ram_addr + 1;
+		state <= READ_HEADER;
+	     end
+	     fwd_input <= 0;
+          end
+	  //
+	  // Continue to read full packet header into RAM.
+	  //
+	  READ_HEADER: begin
+	     if (in_tvalid && in_tready) begin
+		header_ram[header_ram_addr] <= {in_tlast,in_tuser,in_tdata};
+		// Have we reached end of fields we parse in header or got a short packet?
+		if (header_done || in_tlast) begin
+		   // Make decision about where this packet is forwarded to.
+		   state <= CLASSIFY_PACKET;
+		end // if (header_done || in_tlast)
+		else begin
+		   header_ram_addr <= header_ram_addr + 1;
+		   state <= READ_HEADER;
+		end // else: !if(header_done || in_tlast)
+	     end // if (in_tvalid && in_tready)
+	  end // case: READ_HEADER
+
+	  //
+	  // Classify Packet 
+	  //
+	  CLASSIFY_PACKET: begin
+	     // Make decision about where this packet is forwarded to.
+	     if (is_eth_type_ipv4 && is_ipv4_proto_icmp && is_icmp_no_fwd) begin
+	        header_ram_addr <= 0;
+		state <= FORWARD_ZPU;
+	     end else if (is_eth_broadcast) begin
+		header_ram_addr <= 0;
+		state <= forward_bcast? FORWARD_ZPU_AND_XO : FORWARD_ZPU;
+	     end else if (!is_eth_dst_addr) begin
+		header_ram_addr <= 0;
+		state <= forward_ndest? FORWARD_XO : DROP_PACKET;
+	     end else if ((is_udp_dst_ports != 0) && is_chdr) begin
+		header_ram_addr <= 6;  // Jump to CHDR
+		state <= FORWARD_RADIO_CORE;
+	     end else if (drop_this_packet) begin
+		header_ram_addr <= HEADER_RAM_SIZE-1;
+		state  <= DROP_PACKET;
+	     end else begin
+		header_ram_addr <= 0;
+		state <= FORWARD_ZPU;
+	     end
+	  end // case: CLASSIFY_PACKET
+	  	  
+	  //
+	  // Forward this packet only to local ZPU
+	  //
+	  FORWARD_ZPU: begin
+	     if (out_tvalid && out_tready) begin
+		if (out_tlast) begin
+		   state <= WAIT_PACKET;
+		end
+		if (header_done) fwd_input <= 1;
+		header_ram_addr <= out_tlast? 4'b0 : header_ram_addr + 1;
+	     end
+	  end
+	  //
+	  // Forward this packet to both local ZPU and XO 
+	  //
+	  FORWARD_ZPU_AND_XO: begin
+	     if (out_tvalid && out_tready) begin
+		if (out_tlast) begin
+		   state <= WAIT_PACKET;
+		end
+		if (header_done) fwd_input <= 1;
+		header_ram_addr <= out_tlast? 4'b0 : header_ram_addr + 1;
+	     end
+	  end
+	  //
+	  // Forward this packet to XO only
+	  //
+	  FORWARD_XO: begin
+	     if (out_tvalid && out_tready) begin
+		if (out_tlast) begin
+		   state <= WAIT_PACKET;
+		end
+		if (header_done) fwd_input <= 1;
+		header_ram_addr <= out_tlast? 4'b0 : header_ram_addr + 1;
+	     end
+	  end
+	  //
+	  // Forward this packet to the Radio Core only
+	  //
+	  FORWARD_RADIO_CORE: begin
+	     if (out_tvalid && out_tready) begin
+		if (out_tlast) begin
+		   state <= WAIT_PACKET;
+		end
+		if (header_done) fwd_input <= 1;
+		header_ram_addr <= out_tlast? 4'b0 : header_ram_addr + 1;
+	     end
+	  end
+	  //
+	  // Drop this packet on the ground
+	  //
+	  DROP_PACKET: begin
+	     if (out_tvalid && out_tready) begin
+		if (out_tlast) begin
+		   state <= WAIT_PACKET;
+		end
+		if (header_done) fwd_input <= 1;
+		header_ram_addr <= out_tlast? 4'b0 : header_ram_addr + 1;
+	     end
+	  end
+	endcase // case (state)
+     end // else: !if(reset || clear)
+   
+   //
+   // Classifier State machine.
+   // Deep packet inspection during header ingress.
+   //
+   always @(posedge clk)
+     if (reset || clear) begin
+	is_eth_dst_addr <= 1'b0;
+	is_eth_broadcast <= 1'b0;
+	is_eth_type_ipv4 <= 1'b0;
+	is_ipv4_dst_addr <= 1'b0;
+	is_ipv4_proto_udp <=  1'b0;
+	is_ipv4_proto_icmp <=  1'b0;
+	is_udp_dst_ports <= 0;
+	is_icmp_no_fwd <= 0;
+	is_chdr <= 1'b0;
+	
+	//	   space_in_fifo <= 0;
+	//	   is_there_fifo_space <= 1;
+	//	   packet_length <= 0;
+     end else if (in_tvalid && in_tready) begin // if (reset || clear)
+	in_tdata_reg <= in_tdata;
+	
+	case (header_ram_addr)
+	  // Pipelined, so nothing to look at first cycle.
+	  // Reset all the flags here.
+	  0: begin
+	     is_eth_dst_addr <= 1'b0;
+	     is_eth_broadcast <= 1'b0;
+	     is_eth_type_ipv4 <= 1'b0;
+	     is_ipv4_dst_addr <= 1'b0;
+	     is_ipv4_proto_udp <=  1'b0;
+	     is_ipv4_proto_icmp <=  1'b0;
+	     is_udp_dst_ports <= 0;
+	     is_icmp_no_fwd <= 0;
+	     is_chdr <= 1'b0;
+	  end
+	  1: begin
+	     // Look at upper 16bits of MAC Dst Addr.
+	     if (in_tdata_reg[15:0] == 16'hFFFF)
+	       is_eth_broadcast <= 1'b1;
+	     if (in_tdata_reg[15:0] == my_mac[47:32])
+	       is_eth_dst_addr <= 1'b1;
+	  end
+	  2: begin	
+	     // Look at lower 32bits of MAC Dst Addr.
+	     if (is_eth_broadcast && (in_tdata_reg[63:32] == 32'hFFFFFFFF))
+	       is_eth_broadcast <= 1'b1;
+	     else
+	       is_eth_broadcast <= 1'b0;
+	     if (is_eth_dst_addr && (in_tdata_reg[63:32] == my_mac[31:0]))
+		  is_eth_dst_addr <= 1'b1;
+		else
+		  is_eth_dst_addr <= 1'b0;
+	     end // case: 2
+	     3: begin
+		// Look at Ethertype
+		if (in_tdata_reg[47:32] == 16'h0800)
+		  is_eth_type_ipv4 <= 1'b1;
+		// Extract Packet Length
+		// ADD THIS HERE.
+	     end
+	     4: begin
+		// Look at protocol enapsulated by IPv4
+		if ((in_tdata_reg[23:16] == 8'h11) && is_eth_type_ipv4)
+		  is_ipv4_proto_udp <= 1'b1;
+		if ((in_tdata_reg[23:16] == 8'h01) && is_eth_type_ipv4)
+		  is_ipv4_proto_icmp <= 1'b1;
+	     end
+	     5: begin
+		// Look at IP DST Address.
+		if ((in_tdata_reg[31:0] == my_ip[31:0]) && is_eth_type_ipv4)
+		  is_ipv4_dst_addr <= 1'b1;
+	     end
+	     6: begin
+		// Look at UDP dest port
+		if ((in_tdata_reg[47:32] == my_port0[15:0]) && is_ipv4_proto_udp)
+		  is_udp_dst_ports[0] <= 1'b1;
+		if ((in_tdata_reg[47:32] == my_port1[15:0]) && is_ipv4_proto_udp)
+		  is_udp_dst_ports[1] <= 1'b1;
+		// Look at ICMP type and code
+		if (in_tdata_reg[63:48] == {my_icmp_type, my_icmp_code} && is_ipv4_proto_icmp)
+		  is_icmp_no_fwd <= 1'b1;
+	     end
+	     7: begin
+		// Look for a possible CHDR header string
+		if (in_tdata_reg[63:32] != 32'h0)
+		  is_chdr <= 1'b1;
+	     end
+	     8: begin
+		// Check VRT Stream ID
+		// ADD THIS HERE.
+	     end
+	   endcase // case (header_ram_addr)
+	end // if (in_tvalid && in_tready)
+   
+   
+   //
+   // Output (Egress) Interface muxing
+   //
+   assign out_tready = 
+		       (state == DROP_PACKET) ||
+		       ((state == FORWARD_RADIO_CORE) && vita_pre_tready) ||
+		       ((state == FORWARD_XO) && xo_pre_tready) ||
+	   	       ((state == FORWARD_ZPU) && zpu_pre_tready) ||
+		       ((state == FORWARD_ZPU_AND_XO) && zpu_pre_tready && xo_pre_tready);
+
+   assign out_tvalid = ((state == FORWARD_RADIO_CORE) ||
+			(state == FORWARD_XO) ||
+			(state == FORWARD_ZPU) ||
+			(state == FORWARD_ZPU_AND_XO) ||
+			(state == DROP_PACKET)) && (!fwd_input || in_tvalid);
+
+   assign {out_tlast,out_tuser,out_tdata} = fwd_input ?  {in_tlast,in_tuser,in_tdata} : header_ram[header_ram_addr];
+   
+   assign in_tready = (state == WAIT_PACKET) || 
+		      (state == READ_HEADER) ||
+		      (state == DROP_PACKET) ||
+		      (out_tready && fwd_input);
+   
+
+   // Because we can forward to both the ZPU and XO FIFO's concurrently
+   // we have to make sure both can accept data in the same cycle.
+   // This makes it possible for either destination to block the other.
+   assign xo_pre_tvalid = out_tvalid && 
+			  ((state == FORWARD_XO) || 
+			  ((state == FORWARD_ZPU_AND_XO) && zpu_pre_tready));
+   assign zpu_pre_tvalid = out_tvalid && 
+			   ((state == FORWARD_ZPU) ||
+			   ((state == FORWARD_ZPU_AND_XO) && xo_pre_tready));
+   assign vita_pre_tvalid = out_tvalid && (state == FORWARD_RADIO_CORE);
+   
+   assign {zpu_pre_tuser,zpu_pre_tdata} = ((state == FORWARD_ZPU_AND_XO) || (state == FORWARD_ZPU)) ?
+					  {out_tuser,out_tdata} : 0;
+
+   assign {xo_pre_tuser,xo_pre_tdata} = ((state == FORWARD_ZPU_AND_XO) || (state == FORWARD_XO)) ?
+					{out_tuser,out_tdata} : 0;
+
+   assign {vita_pre_tuser,vita_pre_tdata} = (state == FORWARD_RADIO_CORE) ? {out_tuser,out_tdata} : 0;
+
+   assign zpu_pre_tlast = out_tlast && ((state == FORWARD_ZPU) || (state == FORWARD_ZPU_AND_XO));
+   
+   assign xo_pre_tlast =  out_tlast && ((state == FORWARD_XO) || (state == FORWARD_ZPU_AND_XO));
+   
+   assign vita_pre_tlast = out_tlast && (state == FORWARD_RADIO_CORE);
+   
+   //
+   // Egress FIFO's (Large)
+   //
+   axi_fifo #(.WIDTH(69),.SIZE(10)) 
+   axi_fifo_zpu (
+     .clk(clk),
+     .reset(reset),
+     .clear(clear),
+     .i_tdata({zpu_pre_tlast,zpu_pre_tuser,zpu_pre_tdata}),
+     .i_tvalid(zpu_pre_tvalid),
+     .i_tready(zpu_pre_tready),
+     .o_tdata({zpu_tlast,zpu_tuser,zpu_tdata}),
+     .o_tvalid(zpu_tvalid),
+     .o_tready(zpu_tready),
+     .space(),
+     .occupied()
+     );
+   
+   axi_fifo #(.WIDTH(69),.SIZE(10)) 
+   axi_fifo_xo (
+     .clk(clk),
+     .reset(reset),
+     .clear(clear),
+     .i_tdata({xo_pre_tlast,xo_pre_tuser,xo_pre_tdata}),
+     .i_tvalid(xo_pre_tvalid),
+     .i_tready(xo_pre_tready),
+     .o_tdata({xo_tlast,xo_tuser,xo_tdata}),
+     .o_tvalid(xo_tvalid),
+     .o_tready(xo_tready),
+     .space(),
+     .occupied()
+     );
+   
+   axi_fifo #(.WIDTH(69),.SIZE(10)) 
+   axi_fifo_vita (     
+     .clk(clk),
+     .reset(reset),
+     .clear(clear),
+     .i_tdata({vita_pre_tlast,vita_pre_tuser,vita_pre_tdata}),
+     .i_tvalid(vita_pre_tvalid),
+     .i_tready(vita_pre_tready),
+     .o_tdata({vita_tlast,vita_tuser,vita_tdata}),
+     .o_tvalid(vita_tvalid),
+     .o_tready(vita_tready),
+     .space(),
+     .occupied()
+     );
+ 
+     
+/* -----\/----- EXCLUDED -----\/-----
+   
+   wire 	  vready, zready, oready;
+   wire 	  vvalid, zvalid, ovalid;
+   
+   reg [2:0] 	  ed_state;
+   localparam ED_IDLE     = 3'd0;
+   localparam ED_IN_HDR   = 3'd1;
+   localparam ED_VITA     = 3'd2;
+   localparam ED_ZPU      = 3'd3;
+   localparam ED_OUT      = 3'd4;
+   localparam ED_DROP     = 3'd5;
+ -----/\----- EXCLUDED -----/\----- */
+
+   // for now, send everything to zpu
+   /*
+   always @(posedge clk)
+     if(reset | clear)
+       ed_state <= ED_IDLE;
+     else
+       case(ed_state)
+	 ED_IDLE:
+	   if(vready & zready & oready & in_tvalid)
+	     ;
+       endcase // case (ed_state)
+   */
+   
+/* -----\/----- EXCLUDED -----\/-----
+   axi_packet_gate #(.WIDTH(64), .SIZE(10)) vita_gate
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(in_tdata), .i_tlast(), .i_terror(), .i_tvalid(1'b0), .i_tready(vready),
+      .o_tdata(vita_tdata), .o_tlast(vita_tlast), .o_tvalid(vita_tvalid), .o_tready(vita_tready));
+   
+   axi_packet_gate #(.WIDTH(68), .SIZE(10)) zpu_gate
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({in_tuser,in_tdata}), .i_tlast(in_tlast), .i_terror(in_tuser[3]), .i_tvalid(in_tvalid), .i_tready(in_tready),
+      .o_tdata({zpu_tuser,zpu_tdata}), .o_tlast(zpu_tlast), .o_tvalid(zpu_tvalid), .o_tready(zpu_tready));
+   
+   axi_packet_gate #(.WIDTH(68), .SIZE(10)) out_gate
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({in_tuser,in_tdata}), .i_tlast(), .i_terror(), .i_tvalid(1'b0), .i_tready(oready),
+      .o_tdata({out_tuser,out_tdata}), .o_tlast(out_tlast), .o_tvalid(out_tvalid), .o_tready(out_tready));
+ -----/\----- EXCLUDED -----/\----- */
+   
+endmodule // eth_dispatch
diff --git a/fpga/usrp3/lib/packet_proc/eth_dispatch_tb.v b/fpga/usrp3/lib/packet_proc/eth_dispatch_tb.v
new file mode 100644
index 000000000..ecc7d1025
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/eth_dispatch_tb.v
@@ -0,0 +1,311 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+
+`timescale  1 ps / 1 ps
+
+module eth_dispatch_tb();
+
+ 
+   // Clocking and reset interface
+   reg clk; 
+   reg reset; 
+   reg clear; 
+   // Setting register interface
+   reg set_stb; 
+   reg [15:0] set_addr; 
+   reg [31:0] set_data;
+   // Input 68bit AXI-Stream interface (from MAC)
+   wire [63:0] in_tdata; 
+   wire [3:0]  in_tuser; 
+   wire        in_tlast; 
+   wire        in_tvalid; 
+   wire        in_tready;
+   // Output AXI-Stream interface to VITA Radio Core
+   wire [63:0] vita_tdata;
+   wire [3:0]  vita_tuser; 
+   wire        vita_tlast; 
+   wire        vita_tvalid; 
+   wire        vita_tready;
+   // Output AXI-Stream interface to ZPU
+   wire [63:0] zpu_tdata; 
+   wire [3:0]  zpu_tuser; 
+   wire        zpu_tlast; 
+   wire        zpu_tvalid; 
+   wire        zpu_tready;
+   // Output AXI-Stream interface to cross-over MAC
+   wire [63:0] xo_tdata; 
+   wire [3:0]  xo_tuser; 
+   wire        xo_tlast; 
+   wire        xo_tvalid; 
+   wire        xo_tready;
+   
+   reg [63:0] data_in;
+   reg [3:0]  user_in;
+   reg 	      valid_in;
+   wire       ready_in;
+   reg 	      last_in;
+   
+   eth_dispatch
+     #(.BASE(0))
+   eth_dispatch_i
+     (
+      // Clocking and reset interface
+      .clk(clk), 
+      .reset(reset), 
+      .clear(clear), 
+      // Setting register interface
+      .set_stb(set_stb), 
+      .set_addr(set_addr), 
+      .set_data(set_data),
+      // Input 68bit AXI-Stream interface (from MAC)
+      .in_tdata(in_tdata), 
+      .in_tuser(in_tuser), 
+      .in_tlast(in_tlast), 
+      .in_tvalid(in_tvalid), 
+      .in_tready(in_tready),
+      // Output AXI-STream interface to VITA Radio Core
+      .vita_tdata(vita_tdata),
+      .vita_tuser(vita_tuser),
+      .vita_tlast(vita_tlast), 
+      .vita_tvalid(vita_tvalid), 
+      .vita_tready(vita_tready),
+      // Output AXI-Stream interface to ZPU
+      .zpu_tdata(zpu_tdata), 
+      .zpu_tuser(zpu_tuser), 
+      .zpu_tlast(zpu_tlast), 
+      .zpu_tvalid(zpu_tvalid), 
+      .zpu_tready(zpu_tready),
+      // Output AXI-Stream interface to cross-over MAC
+      .xo_tdata(xo_tdata), 
+      .xo_tuser(xo_tuser), 
+      .xo_tlast(xo_tlast), 
+      .xo_tvalid(xo_tvalid), 
+      .xo_tready(xo_tready)
+      );
+    
+   //
+   // Define Clocks
+   //
+   initial begin
+      clk = 1'b1;
+   end
+   
+   // 125MHz clock
+   always #4000 clk = ~clk;
+
+   //
+   // Good starting state
+   //
+     initial begin
+	reset <= 0;
+	clear <= 0;
+	set_stb <= 0;
+	set_addr <= 0;
+	set_data <= 0;
+	data_in <= 0;
+	user_in <= 0;
+	valid_in <= 0;
+	last_in <= 0;
+	
+     end
+
+   
+
+   //
+   // Task Libaray
+   //
+  task write_setting_bus;
+      input [15:0] address;
+      input [31:0] data;
+
+     begin
+
+	@(negedge clk);
+	set_stb = 1'b0;
+	set_addr = 16'h0;
+	set_data = 32'h0;
+	@(negedge clk);
+	set_stb = 1'b1;
+	set_addr = address;
+	set_data = data;
+	@(negedge clk);
+	set_stb = 1'b0;
+	set_addr = 16'h0;
+	set_data = 32'h0;
+
+      end
+   endtask // write_setting_bus
+ 
+   
+   task  enqueue_line;
+      input last;
+      input [2:0] keep;
+      input [63:0] data;
+      begin
+         data_in <= {keep, data};
+	 last_in <= last;
+         valid_in <= 1;
+         while (~ready_in) begin
+            @(negedge clk);
+         end
+         @(negedge clk);
+         data_in <= 0;
+	 last_in <= 0;	 
+         valid_in <= 0;
+      end
+   endtask // enqueue_line
+
+   task enqueue_arp_req;
+      input [47:0] src_mac;
+      input [31:0] src_ip;
+      input [47:0] dst_mac;
+      input [31:0] dst_ip;
+
+      begin
+	 @(negedge clk);
+	 // Line 0
+	 enqueue_line( 0, 3'b0, {48'h0,16'hffff});
+	 // Line 1 - Eth
+	 enqueue_line( 0, 3'b0, {32'hffffffff,src_mac[47:16]});
+	 // Line 2 - Eth+ARP (HTYPE = 1, PTYPE = 0x0800)
+	 enqueue_line( 0, 3'b0, {src_mac[15:0],16'h0806,16'h0001,16'h0800});
+	 // Line 3 -  HLEN=6, PLEN=4 OPER=1
+	 enqueue_line( 0, 3'b0, {8'h06,8'h04,16'h0001,src_mac[47:16]});
+	 // Line 4 - ARP
+	 enqueue_line( 0, 3'b0, {src_mac[15:0],src_ip[31:0],dst_mac[47:32]});
+	 // Line 5 - ARP
+	 enqueue_line( 1, 3'b0, {dst_mac[31:0],dst_ip[31:0]});
+      end
+   endtask // enqueue_arp_req
+   
+
+   
+   reg [11:0] frame_count =12'h0;
+    
+   task  enqueue_vita_pkt;
+      // We assume that we always have SID and TSF fields.
+      input [47:0] mac;
+      input [31:0] ip;
+      input [15:0] udp;
+      input [15:0] vita_size;
+      input [63:0] vita_tsf;
+      input [31:0] vita_sid;
+     
+      
+      integer i;
+      reg [15:0] j;
+      reg [19:0] vrl_size;
+      reg [15:0] udp_size;
+      reg [15:0] ip_size;
+
+      
+      begin
+	 vrl_size = vita_size + 3;
+	 udp_size = vrl_size*4 + 8;
+	 ip_size = udp_size + 20;
+	 @(negedge clk);
+	 // Line 0
+	 enqueue_line( 0, 3'b0, {48'h0,mac[47:32]});
+	 // Line 1 - Eth
+	 enqueue_line( 0, 3'b0, {mac[31:0],32'h11223344});
+	 // Line 2 - Eth+IP
+	 enqueue_line( 0, 3'b0, {16'h5566,16'h0800,16'h0000,ip_size});
+	 // Line 3 - IP
+	 enqueue_line( 0, 3'b0, 'h11<<16);
+	 // Line 4 - IP
+	 enqueue_line( 0, 3'b0, {32'h09080706, ip});
+	 // Line 5 - UDP
+	 enqueue_line( 0, 3'b0, {16'h1234, udp, udp_size, 16'h0});
+         // Line 6 - VRL
+	 enqueue_line( 0, 3'b0, {"VRLP",frame_count,vrl_size});	 
+	 // Line 7 - VRT
+	 enqueue_line( 0, 3'b0, {16'b0001000000010000, vita_size,vita_sid}); //vita hdr + SID
+	 enqueue_line( 0, 3'b0, vita_tsf);
+	 j = 0;
+	 
+	 for (i = 6; i < vita_size; i = i + 2) begin
+	    enqueue_line( 0 , 3'b0, {j,j+16'h1,j+16'h2,j+16'h3});
+	    j = j + 4;	    
+         end
+	 
+	 if (i-vita_size==0) // 2x32words to finish VITA packet.
+	   enqueue_line( 1, 3'b0, {j,j+16'h1,j+16'h2,j+16'h3});
+	 else // 1x32bit word to finish VITA packet
+	   enqueue_line( 1, 3'h4, {j,j+16'h1,j+16'h2,j+16'h3});
+      end	 
+  
+   endtask // enqueue_packet
+   
+
+   //
+   // Simulation specific testbench is included here
+   //
+`include "simulation_script.v"
+
+
+   //
+   // Input FIFO
+   //
+   axi_fifo_short
+     #(.WIDTH(69)) axi_fifo_short_in
+       (
+	.clk(clk), 
+	.reset(reset), 
+	.clear(clear),
+	.o_tdata({in_tlast,in_tuser,in_tdata}),
+	.o_tvalid(in_tvalid),
+	.o_tready(in_tready),
+	.i_tdata({last_in,user_in,data_in}),
+	.i_tvalid(valid_in),
+	.i_tready(ready_in),
+	.space(),
+	.occupied()
+	);  
+
+   //
+   // Output Sinks
+   //
+   axi_probe_tb 
+     #(.FILENAME("zpu.txt"),.VITA_PORT0(60000),.VITA_PORT1(60001)) axi_probe_tb_zpu 
+       (
+	.clk(clk),
+	.reset(reset),
+	.clear(clear),
+	.tdata(zpu_tdata),
+	.tvalid(zpu_tvalid),
+	.tready(zpu_tready),
+	.tlast(zpu_tlast)
+	);
+
+   assign zpu_tready = 1'b1;
+
+   axi_probe_tb 
+     #(.FILENAME("xo.txt"),.VITA_PORT0(60000),.VITA_PORT1(60001)) axi_probe_tb_xo 
+       (
+	.clk(clk),
+	.reset(reset),
+	.clear(clear),
+	.tdata(xo_tdata),
+	.tvalid(xo_tvalid),
+	.tready(xo_tready),
+	.tlast(xo_tlast)
+	);
+
+   assign xo_tready = 1'b1;
+   		     
+   axi_probe_tb 
+     #(.FILENAME("vita.txt"),.VITA_PORT0(60000),.VITA_PORT1(60001),.START_AT_VRL(1)) axi_probe_tb_vita 
+       (
+	.clk(clk),
+	.reset(reset),
+	.clear(clear),
+	.tdata(vita_tdata),
+	.tvalid(vita_tvalid),
+	.tready(vita_tready),
+	.tlast(vita_tlast)
+	);
+
+   assign vita_tready = 1'b1;
+
+endmodule // eth_dispatch_tb
diff --git a/fpga/usrp3/lib/packet_proc/eth_interface.v b/fpga/usrp3/lib/packet_proc/eth_interface.v
new file mode 100644
index 000000000..083badfea
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/eth_interface.v
@@ -0,0 +1,113 @@
+
+// Adapts from internal VITA to ethernet packets.  Also handles ZPU and ethernet crossover interfaces.
+
+module eth_interface
+  #(parameter BASE=0,
+    parameter XO_FIFOSIZE=10,
+    parameter ZPU_FIFOSIZE=10,
+    parameter VITA_FIFOSIZE=10,
+    parameter ETHOUT_FIFOSIZE=10)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    // Eth ports
+    output [63:0] eth_tx_tdata, output [3:0] eth_tx_tuser, output eth_tx_tlast, output eth_tx_tvalid, input eth_tx_tready,
+    input [63:0] eth_rx_tdata, input [3:0] eth_rx_tuser, input eth_rx_tlast, input eth_rx_tvalid, output eth_rx_tready,
+    // Vita router interface
+    output [63:0] e2v_tdata, output e2v_tlast, output e2v_tvalid, input e2v_tready,
+    input [63:0] v2e_tdata, input v2e_tlast, input v2e_tvalid, output v2e_tready,
+    // Ethernet crossover
+    output [63:0] xo_tdata, output [3:0] xo_tuser, output xo_tlast, output xo_tvalid, input xo_tready,
+    input [63:0] xi_tdata, input [3:0] xi_tuser, input xi_tlast, input xi_tvalid, output xi_tready,
+    // ZPU
+    output [63:0] e2z_tdata, output [3:0] e2z_tuser, output e2z_tlast, output e2z_tvalid, input e2z_tready,
+    input [63:0] z2e_tdata, input [3:0] z2e_tuser, input z2e_tlast, input z2e_tvalid, output z2e_tready,
+    
+    output [31:0] debug
+    );
+
+   wire [63:0] 	  v2ef_tdata;
+   wire [3:0] 	  v2ef_tuser;
+   wire 	  v2ef_tlast, v2ef_tvalid, v2ef_tready;
+
+   // //////////////////////////////////////////////////////////////
+   // Incoming Ethernet path
+   //  Includes FIFO on the output going to ZPU
+
+   wire [63:0] 	  epg_tdata_int;
+   wire [3:0] 	  epg_tuser_int;
+   wire 	  epg_tlast_int, epg_tvalid_int, epg_tready_int;
+
+   axi_packet_gate #(.WIDTH(68), .SIZE(10)) packet_gater //holds 8K pkts
+     (.clk(clk), .reset(reset), .clear(clear),
+
+      .i_tdata({eth_rx_tuser, eth_rx_tdata}), .i_tlast(eth_rx_tlast),
+      .i_terror(eth_rx_tuser[3]), //top bit of user bus is error
+      .i_tvalid(eth_rx_tvalid), .i_tready(eth_rx_tready),
+
+      .o_tdata({epg_tuser_int, epg_tdata_int}), .o_tlast(epg_tlast_int),
+      .o_tvalid(epg_tvalid_int), .o_tready(epg_tready_int));
+
+   wire [63:0] 	  e2z_tdata_int;
+   wire [3:0] 	  e2z_tuser_int;
+   wire 	  e2z_tlast_int, e2z_tvalid_int, e2z_tready_int;
+
+   eth_dispatch #(.BASE(BASE+8)) eth_dispatch
+     (.clk(clk), .reset(reset), .clear(clear),
+      .set_stb(set_stb), .set_addr(set_addr) , .set_data(set_data),
+      .in_tdata(epg_tdata_int), .in_tuser(epg_tuser_int), .in_tlast(epg_tlast_int), .in_tvalid(epg_tvalid_int), .in_tready(epg_tready_int),
+      .vita_tdata(e2v_tdata), .vita_tlast(e2v_tlast), .vita_tvalid(e2v_tvalid), .vita_tready(e2v_tready),
+      .zpu_tdata(e2z_tdata_int), .zpu_tuser(e2z_tuser_int), .zpu_tlast(e2z_tlast_int), .zpu_tvalid(e2z_tvalid_int), .zpu_tready(e2z_tready_int),
+      .xo_tdata(xo_tdata), .xo_tuser(xo_tuser), .xo_tlast(xo_tlast), .xo_tvalid(xo_tvalid), .xo_tready(xo_tready), // to other eth port
+      .debug(debug));
+
+   axi_fifo #(.WIDTH(69),.SIZE(ZPU_FIFOSIZE)) zpu_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({e2z_tlast_int,e2z_tuser_int,e2z_tdata_int}), .i_tvalid(e2z_tvalid_int), .i_tready(e2z_tready_int),
+      .o_tdata({e2z_tlast,e2z_tuser,e2z_tdata}), .o_tvalid(e2z_tvalid), .o_tready(e2z_tready));
+
+   // //////////////////////////////////////////////////////////////
+   // Outgoing Ethernet path
+   //  Includes FIFOs on path from VITA router, from ethernet crossover, and on the overall output
+
+   wire [63:0] 	  eth_tx_tdata_int;
+   wire [3:0] 	  eth_tx_tuser_int;
+   wire 	  eth_tx_tlast_int, eth_tx_tvalid_int, eth_tx_tready_int;
+
+   wire [63:0] 	  xi_tdata_int;
+   wire [3:0] 	  xi_tuser_int;
+   wire 	  xi_tlast_int, xi_tvalid_int, xi_tready_int;
+
+   wire [63:0] 	  v2e_tdata_int;
+   wire 	  v2e_tlast_int, v2e_tvalid_int, v2e_tready_int;
+   
+   axi_fifo #(.WIDTH(65),.SIZE(VITA_FIFOSIZE)) vitaout_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({v2e_tlast,v2e_tdata}), .i_tvalid(v2e_tvalid), .i_tready(v2e_tready),
+      .o_tdata({v2e_tlast_int,v2e_tdata_int}), .o_tvalid(v2e_tvalid_int), .o_tready(v2e_tready_int));
+
+   chdr_eth_framer #(.BASE(BASE)) my_eth_framer
+     (.clk(clk), .reset(reset), .clear(clear),
+      .set_stb(set_stb), .set_addr(set_addr) , .set_data(set_data),
+      .in_tdata(v2e_tdata_int), .in_tlast(v2e_tlast_int), .in_tvalid(v2e_tvalid_int), .in_tready(v2e_tready_int),
+      .out_tdata(v2ef_tdata), .out_tuser(v2ef_tuser), .out_tlast(v2ef_tlast), .out_tvalid(v2ef_tvalid), .out_tready(v2ef_tready),
+      .debug());
+
+   axi_fifo #(.WIDTH(69),.SIZE(XO_FIFOSIZE)) xo_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({xi_tlast,xi_tuser,xi_tdata}), .i_tvalid(xi_tvalid), .i_tready(xi_tready),
+      .o_tdata({xi_tlast_int,xi_tuser_int,xi_tdata_int}), .o_tvalid(xi_tvalid_int), .o_tready(xi_tready_int));
+
+   axi_mux4 #(.PRIO(0), .WIDTH(68)) eth_mux
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i0_tdata({z2e_tuser,z2e_tdata}), .i0_tlast(z2e_tlast), .i0_tvalid(z2e_tvalid), .i0_tready(z2e_tready),
+      .i1_tdata({v2ef_tuser,v2ef_tdata}), .i1_tlast(v2ef_tlast), .i1_tvalid(v2ef_tvalid), .i1_tready(v2ef_tready),
+      .i2_tdata({xi_tuser_int,xi_tdata_int}), .i2_tlast(xi_tlast_int), .i2_tvalid(xi_tvalid_int), .i2_tready(xi_tready_int),
+      .i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(),
+      .o_tdata({eth_tx_tuser_int,eth_tx_tdata_int}), .o_tlast(eth_tx_tlast_int), .o_tvalid(eth_tx_tvalid_int), .o_tready(eth_tx_tready_int));
+
+   axi_fifo #(.WIDTH(69),.SIZE(ETHOUT_FIFOSIZE)) ethout_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({eth_tx_tlast_int,eth_tx_tuser_int,eth_tx_tdata_int}), .i_tvalid(eth_tx_tvalid_int), .i_tready(eth_tx_tready_int),
+      .o_tdata({eth_tx_tlast,eth_tx_tuser,eth_tx_tdata}), .o_tvalid(eth_tx_tvalid), .o_tready(eth_tx_tready));
+
+endmodule // eth_interface
diff --git a/fpga/usrp3/lib/packet_proc/ip_hdr_checksum.v b/fpga/usrp3/lib/packet_proc/ip_hdr_checksum.v
new file mode 100644
index 000000000..869378aba
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/ip_hdr_checksum.v
@@ -0,0 +1,24 @@
+
+// Compute IP header checksum.  2 cycles of latency.
+module ip_hdr_checksum
+  (input clk, input [159:0] in, output reg [15:0] out);
+
+   wire [18:0] padded [0:9];
+   reg [18:0]  sum_a, sum_b;
+   
+   genvar     i;
+   generate
+      for(i=0 ; i<10 ; i=i+1)
+	assign padded[i] = {3'b000,in[i*16+15:i*16]};
+   endgenerate
+
+   always @(posedge clk)  sum_a = padded[0] + padded[1] + padded[2] + padded[3] + padded[4];
+   always @(posedge clk)  sum_b = padded[5] + padded[6] + padded[7] + padded[8] + padded[9];
+
+   wire [18:0] sum = sum_a + sum_b;
+
+   always @(posedge clk)
+     out <= ~(sum[15:0] + {13'd0,sum[18:16]});
+   
+   
+endmodule // ip_hdr_checksum
diff --git a/fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v b/fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v
new file mode 100644
index 000000000..8d9ccf948
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v
@@ -0,0 +1,38 @@
+
+module ip_hdr_checksum_tb();
+   
+   initial $dumpfile("ip_hdr_checksum_tb.vcd");
+   initial $dumpvars(0,ip_hdr_checksum_tb);
+
+   reg clk;
+   
+   wire [159:0] in = {
+		      16'h4500,
+		      16'h0030,
+		      16'h4422,
+		      16'h4000,
+		      16'h8006,
+		      16'h0000,
+		      16'h8c7c,
+		      16'h19ac,
+		      16'hae24,
+		      16'h1e2b
+		      };
+   
+   wire [15:0] 	out;
+   ip_hdr_checksum ip_hdr_checksum
+     (.clk(clk), 
+      .in(in),
+      .out(out));
+
+   initial
+     begin
+	clk <= 0;
+	#100 clk <= 1;
+	#100 clk <= 0;
+	#100 clk <= 1;
+	#100 $display("Computed 0x%x, should be 0x442e", out);
+	#100 $finish;
+     end
+   
+endmodule // ip_hdr_checksum_tb
diff --git a/fpga/usrp3/lib/packet_proc/source_flow_control.v b/fpga/usrp3/lib/packet_proc/source_flow_control.v
new file mode 100644
index 000000000..d26b848c9
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/source_flow_control.v
@@ -0,0 +1,127 @@
+
+// source_flow_control.v
+//
+//  This block passes the in_* AXI port to the out_* AXI port only when it has
+//   enough flow control credits.  Data is held when there are not enough credits.
+//  Credits are replenished with extension context packets which update the 
+//   last_consumed packet register.  Max credits are controlled by settings regs.
+//  The 2nd line of the packet contains the sequence number in the low 12 bits.
+//  These packets should not have a time value, but if they do it will be ignored.
+
+module source_flow_control
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [63:0] fc_tdata, input fc_tlast, input fc_tvalid, output fc_tready,
+    input [63:0] in_tdata, input in_tlast, input in_tvalid, output in_tready,
+    output [63:0] out_tdata, output out_tlast, output out_tvalid, input out_tready);
+   
+   reg [31:0] 	  last_seqnum_consumed;
+   wire [31:0] 	  window_size;
+   wire [31:0] 	  go_until_seqnum = last_seqnum_consumed + window_size + 1;
+   reg [31:0] 	  current_seqnum;
+   wire 	  window_reset;
+   wire 	  window_enable;
+   wire 	  setting_changed;
+   
+   setting_reg #(.my_addr(BASE)) sr_window_size
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+      .out(window_size),.changed(setting_changed));
+
+   setting_reg #(.my_addr(BASE+1), .width(1)) sr_window_enable
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+      .out(window_enable),.changed(window_reset));
+
+   reg 		  go;
+   reg [1:0] 	  sfc_state;
+  
+   
+   localparam SFC_HEAD = 2'd0;
+   localparam SFC_TIME = 2'd1;
+   localparam SFC_BODY = 2'd2;
+   localparam SFC_DUMP = 2'd3;
+
+   always @(posedge clk)
+     if(reset | clear | window_reset)
+       begin
+	  last_seqnum_consumed <= 32'hFFFFFFFF;
+	  sfc_state <= SFC_HEAD;
+       end
+     else
+       if(fc_tvalid & fc_tready)
+	 case(sfc_state)
+	   SFC_HEAD :
+	     if(fc_tlast)
+	       sfc_state <= SFC_HEAD; // Error. CHDR packet with only a header is an error.
+	     else if(~fc_tdata[63])   // Is this NOT an extension context packet?
+	       sfc_state <= SFC_DUMP; // Error. Only extension context packets should come in on this interface.
+	     else if(fc_tdata[61])    // Does this packet have time?
+	       sfc_state <= SFC_TIME;
+	     else
+	       sfc_state <= SFC_BODY;
+	   
+	   SFC_TIME :
+	     if(fc_tlast)
+	       sfc_state <= SFC_HEAD; // Error, CHDR packet with only header and time is an error.
+	     else
+	       sfc_state <= SFC_BODY;
+	   
+	   SFC_BODY :
+	     begin
+		last_seqnum_consumed <= fc_tdata[31:0]; // Sequence number is in lower 32bits.
+		if(fc_tlast)
+		  sfc_state <= SFC_HEAD;
+		else
+		  sfc_state <= SFC_DUMP; // Error. Not expecting any more data in a CHDR packet.
+	     end
+
+	   SFC_DUMP :   // shouldn't ever need to be here, this is an error condition
+	     if(fc_tlast)
+	       sfc_state <= SFC_HEAD;
+	 endcase // case (sfc_state)
+      
+   assign fc_tready = 1'b1;  // Always consume FC -- FIXME Even if we are getting reset?
+   assign out_tdata = in_tdata; // CHDR data flows through combinatorially.
+   assign out_tlast = in_tlast;
+   assign in_tready = go ? out_tready : 1'b0;
+   assign out_tvalid = go ? in_tvalid : 1'b0;
+
+   //
+   // Each time we recieve the end of an IF data packet increment the current_seqnum.
+   // We bravely assume that no packets go missing...or at least that they will be detected elsewhere
+   // and then handled appropriately.
+   // The SEQNUM needs to be initialized every time we start a new stream. In new_rx_framer this is done
+   // as a side effect of writing a new SID value to the setting reg.
+   //
+   // By incrementing current_seqnum on the last signal we get the nice effect that packet flow is 
+   // always suspended between packets rather than within a packet.
+   //
+   always @(posedge clk)
+     if(reset | clear | window_reset)
+       current_seqnum <= 0;
+     else if (in_tvalid && in_tready && in_tlast)
+       current_seqnum <= current_seqnum + 1;
+
+   always @(posedge clk)
+     if(reset | clear)
+       go <= 1'b0;
+     else
+       if(~window_enable)
+	 go <= 1'b1;
+       else 
+	 case(go)
+	   1'b0 :
+	     // This test assumes the host is well behaved in sending good numbers for packets consumed
+	     // and that current_seqnum increments always by 1 only.
+	     // This way wraps are dealt with without a large logic penalty.
+	     if (in_tvalid & (go_until_seqnum - current_seqnum != 0))
+	     // 	     if(in_tvalid & (go_until_seqnum > current_seqnum))  // FIXME will need to handle wrap of 32-bit seqnum
+	       go <= 1'b1;
+	   
+	   1'b1 :
+	     if(in_tvalid & in_tready & in_tlast)
+	       go <= 1'b0;
+	 endcase // case (go)
+
+   
+endmodule // source_flow_control
diff --git a/fpga/usrp3/lib/packet_proc/source_flow_control_tb.v b/fpga/usrp3/lib/packet_proc/source_flow_control_tb.v
new file mode 100644
index 000000000..f51d17f97
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/source_flow_control_tb.v
@@ -0,0 +1,249 @@
+`timescale 1ns/1ps
+
+module source_flow_control_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("source_flow_control_tb.vcd");
+   initial $dumpvars(0,source_flow_control_tb);
+
+   initial
+     begin
+	#1000 reset = 0;
+	#20000;
+	$finish;
+     end
+   
+   reg [63:0]  tdata;
+   wire [63:0] tdata_int;
+   reg 	       tlast;
+   wire        tlast_int;
+   reg 	       tvalid = 1'b0;
+   wire        tvalid_int;
+   wire        tready, tready_int;
+   
+   reg [63:0]  fc_tdata;
+   reg 	       fc_tlast, fc_tvalid;
+   wire        fc_tready;
+
+   wire [63:0] out_tdata;
+   wire        out_tlast, out_tready, out_tvalid;
+
+   wire [15:0] occ_in, occ_out;
+   reg 	       set_stb = 0;
+   reg [7:0]   set_addr;
+   reg [31:0]  set_data;
+   
+   
+   task send_fc_packet;
+      input [31:0] seqnum;
+      input [31:0] sid;
+      input always_go;
+      
+      begin
+	 @(posedge clk);
+	 fc_tlast <= 1'b0;
+	 fc_tdata <= { 1'b1, 1'b0, 1'b0, 1'b0, 12'hABC, 16'd4, sid };
+	 fc_tvalid <= 1;
+	 @(posedge clk);
+	 fc_tlast <= 1'b1;
+	 //fc_tdata <= { 52'h0,seqnum };
+	 fc_tdata <= { 31'h0,always_go, seqnum };
+	 @(posedge clk);
+	 fc_tvalid <= 0;	 
+	 @(posedge clk);
+      end
+   endtask // send_packet
+
+   task send_packet;
+      input ec;
+      input timed;
+      input [11:0] seqnum;
+      input [31:0] sid;
+      input [63:0] vtime;
+      input [15:0] addr;
+      input [31:0] data;
+      
+      begin
+	 // Send a packet
+	 @(posedge clk);
+	 tlast <= 1'b0;
+	 tdata <= { ec, 1'b0, timed, 1'b0, seqnum, timed ? 16'd6 : 16'd4, sid };
+	 tvalid <= 1;
+	 @(posedge clk);
+	 if(timed)
+	   begin
+	      tdata <= vtime;
+	      @(posedge clk);
+	   end
+	 tlast <= 1'b1;
+	 tdata <= { 16'h0, addr, data };
+	 @(posedge clk);
+	 tlast <= 1'b0;
+	 tvalid <= 0;	 
+	 @(posedge clk);
+      end
+   endtask // send_packet
+   
+   initial
+     begin
+	tvalid <= 1'b0;
+	while(reset)
+	  @(posedge clk);
+	@(posedge clk);
+	// Set flow control window to be 2
+	set_stb <= 1;
+	set_addr <= 0;
+	set_data <= 2;
+	@(posedge clk);
+	set_stb <= 0;
+	// ExtContext. Time. Seq=0, SID=DEAD_6789, Time=10
+	send_packet(1'b1,1'b1,12'h0,32'hDEAD_6789,64'h10,16'hB,32'hF00D_1234);
+	send_packet(1'b1,1'b1,12'h1,32'hDEAD_6789,64'h20,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h2,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h3,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h4,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h5,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h6,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h7,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h8,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	#500;
+	// Consumed 2 packets
+	send_fc_packet(32'd1,32'h3,1'b0);
+	#300;
+	// Consumed 1 packet
+	send_fc_packet(32'd2,32'h3,1'b0);
+	#500;	
+	// Consumed 2 packets
+	send_fc_packet(32'd4,32'h3,1'b0);
+	#400;	
+	// Send same SEQ ID again to test it causes no changes.
+	send_fc_packet(32'd4,32'h3,1'b0);
+	#300;
+	// Consumed 1 packet
+	send_fc_packet(32'd5,32'h3,1'b0);
+	#500;	
+	// Consumed 2 packets
+	send_fc_packet(32'd7,32'h3,1'b0);
+	#500;	
+	send_packet(1'b1,1'b1,12'h9,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'hA,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
+	#300;
+	// Consumed 1 packet
+	send_fc_packet(32'd8,32'h3,1'b0);
+	//
+	// Now force internal sequence count to close to wrap value to test corner case
+	//
+	#100;
+	source_flow_control.current_seqnum <= 32'hFFFF_FFFC;
+	#100;
+	send_fc_packet(32'hFFFF_FFFA,32'h3,1'b0);
+	#100;
+	send_packet(1'b1,1'b1,12'hFFC,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	#200;
+	send_packet(1'b1,1'b1,12'hFFD,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'hFFE,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'hFFF,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h000,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h001,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h002,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	#200;
+	// Consumed 2 packets
+	send_fc_packet(32'hFFFF_FFFC,32'h3,1'b0);
+	#200;
+	// Consumed 2 packets
+	send_fc_packet(32'hFFFF_FFFE,32'h3,1'b0);
+	send_packet(1'b1,1'b1,12'h003,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h004,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	#200;
+	// Consumed 2 packets
+	send_fc_packet(32'h0,32'h3,1'b0);
+	#200;
+	// Consumed 2 packets
+	send_fc_packet(32'h2,32'h3,1'b0);
+	#500;
+	//
+	// Again force internal sequence count to close to wrap value to test new corner case
+	//
+	#100;
+	source_flow_control.current_seqnum <= 32'hFFFF_FFFC;
+	#100;
+	send_fc_packet(32'hFFFF_FFFA,32'h3,1'b0);
+	#100;
+	send_packet(1'b1,1'b1,12'hFFC,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	#200;
+	send_packet(1'b1,1'b1,12'hFFD,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'hFFE,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'hFFF,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h000,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h001,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h002,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	#200;
+	// Consumed 1 packets
+	send_fc_packet(32'hFFFF_FFFB,32'h3,1'b0);
+	#200;
+	// Consumed 1 packets
+	send_fc_packet(32'hFFFF_FFFC,32'h3,1'b0);
+	send_packet(1'b1,1'b1,12'h003,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	send_packet(1'b1,1'b1,12'h004,32'hDEAD_6789,64'h40,16'hC,32'hABCD_4321);
+	#200;
+	// Consumed 1 packets
+	send_fc_packet(32'hFFFF_FFFD,32'h3,1'b0);
+	#200;
+	// Consumed 1 packets
+	send_fc_packet(32'hFFFF_FFFE,32'h3,1'b0);
+	#200;
+	// Consumed 1 packets
+	send_fc_packet(32'hFFFF_FFFF,32'h3,1'b0);
+	#200;	
+	// Consumed 1 packets
+	send_fc_packet(32'h0,32'h3,1'b0);
+	#200;	
+	// Consumed 1 packets
+	send_fc_packet(32'h1,32'h3,1'b0);
+	#200;	
+	// Consumed 1 packets
+	send_fc_packet(32'h2,32'h3,1'b0);
+	#500;
+	
+
+
+	
+     end
+
+   axi_fifo #(.WIDTH(65), .SIZE(10)) fifo_in
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({tlast,tdata}), .i_tvalid(tvalid), .i_tready(tready),
+      .o_tdata({tlast_int,tdata_int}), .o_tvalid(tvalid_int), .o_tready(tready_int),
+      .occupied(occ_in));
+
+   source_flow_control source_flow_control
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .fc_tdata(fc_tdata), .fc_tlast(fc_tlast), .fc_tvalid(fc_tvalid), .fc_tready(fc_tready),
+      .in_tdata(tdata_int), .in_tlast(tlast_int), .in_tvalid(tvalid_int), .in_tready(tready_int),
+      .out_tdata(out_tdata), .out_tlast(out_tlast), .out_tvalid(out_tvalid), .out_tready(out_tready)
+      );
+
+   wire [63:0] dump_tdata;
+   wire        dump_tlast, dump_tvalid, dump_tready;
+   
+   axi_fifo #(.WIDTH(65), .SIZE(10)) fifo_out
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({out_tlast,out_tdata}), .i_tvalid(out_tvalid), .i_tready(out_tready),
+      .o_tdata({dump_tlast,dump_tdata}), .o_tvalid(dump_tvalid), .o_tready(dump_tready),
+      .occupied(occ_out));
+
+   assign dump_tready = 0;
+   
+   always @(posedge clk)
+     if(out_tvalid & out_tready)
+       begin
+	  $display("%x",out_tdata);
+	  if(out_tlast)
+	    $display("TLAST");
+       end
+endmodule // source_flow_control_tb
diff --git a/fpga/usrp3/lib/packet_proc/vita_eth_framer.v b/fpga/usrp3/lib/packet_proc/vita_eth_framer.v
new file mode 100644
index 000000000..a5e02e899
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/vita_eth_framer.v
@@ -0,0 +1,137 @@
+
+// vita_eth_framer
+//  Takes a vita stream in and adds udp, ip, and ethernet framing
+//  Uses 8 setting reg addresses.  First 4 are simple registers:
+//    BASE+0 : Upper 16 bits of ethernet src mac
+//    BASE+1 : Lower 32 bits of ethernet src mac
+//    BASE+2 : IP src address
+//    BASE+3 : UDP src port
+//
+//  Next 4 control write ports on a RAM indexed by destination field of stream ID
+//    BASE+4 : Dest SID for next 3 regs
+//    BASE+5 : Dest IP
+//    BASE+6 : Dest UDP port, upper 16 bits of dest mac
+//    BASE+7 : Lower 32 bits of dest mac
+
+module vita_eth_framer
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [63:0] in_tdata, input in_tlast, input in_tvalid, output in_tready,
+    output [63:0] out_tdata, output [3:0] out_tuser, output out_tlast, output out_tvalid, input out_tready,
+    output [31:0] debug );
+
+   localparam SR_AWIDTH = 8;
+   
+   reg [31:0] 	  sid;
+   reg [15:0] 	  vita_len;
+   
+   reg [2:0] 	  vef_state;
+   localparam VEF_IDLE    = 3'd0;
+   localparam VEF_PAYLOAD = 3'd7;
+   
+   reg [63:0] 	  tdata;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  vef_state <= VEF_IDLE;
+	  sid <= 32'd0;
+	  vita_len <= 16'd0;
+       end
+     else
+       case(vef_state)
+	 VEF_IDLE :
+	   if(in_tvalid)
+	     begin
+		vef_state <= 1;
+		sid <= in_tdata[31:0];
+		vita_len <= in_tdata[47:32];
+	     end
+	 VEF_PAYLOAD :
+	   if(in_tvalid & out_tready)
+	     if(in_tlast)
+	       vef_state <= VEF_IDLE;
+	 default :
+	   if(out_tready)
+	     vef_state <= vef_state + 3'd1;
+       endcase // case (vef_state)
+   
+   assign in_tready = (vef_state == VEF_PAYLOAD) ? out_tready : 1'b0;
+   assign out_tvalid = (vef_state == VEF_PAYLOAD) ? in_tvalid : (vef_state == VEF_IDLE) ? 1'b0 : 1'b1;
+   assign out_tlast = (vef_state == VEF_PAYLOAD) ? in_tlast : 1'b0;
+   assign out_tuser = ((vef_state == VEF_PAYLOAD) & in_tlast) ? {1'b0,vita_len[0],2'b00} : 4'b0000;
+   assign out_tdata = tdata;
+
+   wire [15:0] vita_len_in_bytes = {vita_len[13:0],2'b00};  // Vita length is in 32-bit words
+
+   wire [47:0] pad = 48'h0;
+   wire [47:0] mac_src, mac_dst;
+   wire [15:0] eth_type = 16'h0800;
+   wire [15:0] misc_ip = { 4'd4 /* IPv4 */, 4'd5 /* IP HDR Len */, 8'h00 /* DSCP and ECN */};
+   wire [15:0] ip_len = (16'd28 + vita_len_in_bytes);  // 20 for IP, 8 for UDP
+   wire [15:0] ident = 16'h0;
+   wire [15:0] flag_frag = { 3'b010 /* don't fragment */, 13'h0 };
+   wire [15:0] ttl_prot = { 8'h10 /* TTL */, 8'h11 /* UDP */ };
+   wire [15:0] iphdr_checksum;
+   wire [31:0] ip_src, ip_dst;
+   wire [15:0] udp_src, udp_dst;
+   wire [15:0] udp_len = (16'd8 + vita_len_in_bytes);
+   wire [15:0] udp_checksum = 16'h0;
+
+   setting_reg #(.my_addr(BASE), .awidth(SR_AWIDTH), .width(16)) set_mac_upper
+     (.clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(mac_src[47:32]), .changed());
+   
+   setting_reg #(.my_addr(BASE+1), .awidth(SR_AWIDTH), .width(32)) set_mac_lower
+     (.clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(mac_src[31:0]), .changed());
+   
+   setting_reg #(.my_addr(BASE+2), .awidth(SR_AWIDTH), .width(32)) set_ip
+     (.clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(ip_src), .changed());
+
+   setting_reg #(.my_addr(BASE+3), .awidth(SR_AWIDTH), .width(16)) set_udp
+     (.clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(udp_src), .changed());
+
+   // Tables of MAC/IP/UDP addresses
+   wire [8:0]  ram_addr;  // FIXME we could skip this part if we had wider SR addresses
+   
+   setting_reg #(.my_addr(BASE+4), .awidth(SR_AWIDTH), .width(9)) set_ram_addr
+     (.clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(ram_addr), .changed());
+
+   ram_2port #(.DWIDTH(32), .AWIDTH(9)) ram_ip
+     (.clka(clk), .ena(1'b1), .wea(set_stb & (set_addr == BASE+5)), .addra(ram_addr), .dia(set_data), .doa(),
+      .clkb(clk), .enb(1'b1), .web(1'b0), .addrb(sid[8:0]), .dib(32'hFFFF_FFFF), .dob(ip_dst));
+   
+   ram_2port #(.DWIDTH(32), .AWIDTH(9)) ram_udpmac
+     (.clka(clk), .ena(1'b1), .wea(set_stb & (set_addr == BASE+6)), .addra(ram_addr), .dia(set_data), .doa(),
+      .clkb(clk), .enb(1'b1), .web(1'b0), .addrb(sid[8:0]), .dib(32'hFFFF_FFFF), .dob({udp_dst,mac_dst[47:32]}));
+   
+   ram_2port #(.DWIDTH(32), .AWIDTH(9)) ram_maclower
+     (.clka(clk), .ena(1'b1), .wea(set_stb & (set_addr == BASE+7)), .addra(ram_addr), .dia(set_data), .doa(),
+      .clkb(clk), .enb(1'b1), .web(1'b0), .addrb(sid[8:0]), .dib(32'hFFFF_FFFF), .dob(mac_dst[31:0]));
+   
+   ip_hdr_checksum ip_hdr_checksum
+     (.clk(clk), .in({misc_ip,ip_len,ident,flag_frag,ttl_prot,16'd0,ip_src,ip_dst}),
+      .out(iphdr_checksum));
+
+   always @*
+     case(vef_state)
+       1 : tdata <= { pad[47:0], mac_dst[47:32]};
+       2 : tdata <= { mac_dst[31:0], mac_src[47:16]};
+       3 : tdata <= { mac_src[15:0], eth_type[15:0], misc_ip[15:0], ip_len[15:0] };
+       4 : tdata <= { ident[15:0], flag_frag[15:0], ttl_prot[15:0], iphdr_checksum[15:0]};
+       5 : tdata <= { ip_src, ip_dst};
+       6 : tdata <= { udp_src, udp_dst, udp_len, udp_checksum};
+       default : tdata <= in_tdata;
+     endcase // case (vef_state)
+      
+endmodule // vita_eth_framer
diff --git a/fpga/usrp3/lib/packet_proc/vrlp_eth_framer.v b/fpga/usrp3/lib/packet_proc/vrlp_eth_framer.v
new file mode 100644
index 000000000..5962b9ba1
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/vrlp_eth_framer.v
@@ -0,0 +1,139 @@
+
+// vrlp_eth_framer
+//  Takes a vrlp stream in and adds udp, ip, and ethernet framing
+//  Uses 8 setting reg addresses.  First 4 are simple registers:
+//    BASE+0 : Upper 16 bits of ethernet src mac
+//    BASE+1 : Lower 32 bits of ethernet src mac
+//    BASE+2 : IP src address
+//    BASE+3 : UDP src port
+//
+//  Next 4 control write ports on a RAM indexed by destination field of stream ID
+//    BASE+4 : Dest SID for next 3 regs
+//    BASE+5 : Dest IP
+//    BASE+6 : Dest UDP port, upper 16 bits of dest mac
+//    BASE+7 : Lower 32 bits of dest mac
+//
+// in_tuser holds streamid
+
+module vrlp_eth_framer
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [63:0] in_tdata, input [15:0] in_tuser, input in_tlast, input in_tvalid, output in_tready,
+    output [63:0] out_tdata, output [3:0] out_tuser, output out_tlast, output out_tvalid, input out_tready,
+    output [31:0] debug );
+
+   localparam SR_AWIDTH = 8;
+   
+   reg [15:0] 	  sid;
+   reg [15:0] 	  vrlp_len;
+   
+   reg [2:0] 	  vef_state;
+   localparam VEF_IDLE    = 3'd0;
+   localparam VEF_PAYLOAD = 3'd7;
+   
+   reg [63:0] 	  tdata;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  vef_state <= VEF_IDLE;
+	  sid <= 16'd0;
+	  vrlp_len <= 16'd0;
+       end
+     else
+       case(vef_state)
+	 VEF_IDLE :
+	   if(in_tvalid)
+	     begin
+		vef_state <= 1;
+		sid <= in_tuser[15:0];
+		vrlp_len <= in_tdata[15:0]; // modified for VRLP header
+	     end
+	 VEF_PAYLOAD :
+	   if(in_tvalid & out_tready)
+	     if(in_tlast)
+	       vef_state <= VEF_IDLE;
+	 default :
+	   if(out_tready)
+	     vef_state <= vef_state + 3'd1;
+       endcase // case (vef_state)
+   
+   wire [15:0] vrlp_len_in_bytes = {vrlp_len[13:0],2'b00};  // Vrlp length is in 32-bit words
+
+   assign in_tready = (vef_state == VEF_PAYLOAD) ? out_tready : 1'b0;
+   assign out_tvalid = (vef_state == VEF_PAYLOAD) ? in_tvalid : (vef_state == VEF_IDLE) ? 1'b0 : 1'b1;
+   assign out_tlast = (vef_state == VEF_PAYLOAD) ? in_tlast : 1'b0;
+   assign out_tuser = ((vef_state == VEF_PAYLOAD) & in_tlast) ? {1'b0,vrlp_len_in_bytes[2:0]} : 4'b0000;
+   assign out_tdata = tdata;
+
+   wire [47:0] pad = 48'h0;
+   wire [47:0] mac_src, mac_dst;
+   wire [15:0] eth_type = 16'h0800;
+   wire [15:0] misc_ip = { 4'd4 /* IPv4 */, 4'd5 /* IP HDR Len */, 8'h00 /* DSCP and ECN */};
+   wire [15:0] ip_len = (16'd28 + vrlp_len_in_bytes);  // 20 for IP, 8 for UDP
+   wire [15:0] ident = 16'h0;
+   wire [15:0] flag_frag = { 3'b010 /* don't fragment */, 13'h0 };
+   wire [15:0] ttl_prot = { 8'h10 /* TTL */, 8'h11 /* UDP */ };
+   wire [15:0] iphdr_checksum;
+   wire [31:0] ip_src, ip_dst;
+   wire [15:0] udp_src, udp_dst;
+   wire [15:0] udp_len = (16'd8 + vrlp_len_in_bytes);
+   wire [15:0] udp_checksum = 16'h0;
+
+   setting_reg #(.my_addr(BASE), .awidth(SR_AWIDTH), .width(16)) set_mac_upper
+     (.clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(mac_src[47:32]), .changed());
+   
+   setting_reg #(.my_addr(BASE+1), .awidth(SR_AWIDTH), .width(32)) set_mac_lower
+     (.clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(mac_src[31:0]), .changed());
+   
+   setting_reg #(.my_addr(BASE+2), .awidth(SR_AWIDTH), .width(32)) set_ip
+     (.clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(ip_src), .changed());
+
+   setting_reg #(.my_addr(BASE+3), .awidth(SR_AWIDTH), .width(16)) set_udp
+     (.clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(udp_src), .changed());
+
+   // Tables of MAC/IP/UDP addresses
+   wire [8:0]  ram_addr;  // FIXME we could skip this part if we had wider SR addresses
+   
+   setting_reg #(.my_addr(BASE+4), .awidth(SR_AWIDTH), .width(9)) set_ram_addr
+     (.clk(clk), .rst(reset),
+      .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(ram_addr), .changed());
+
+   ram_2port #(.DWIDTH(32), .AWIDTH(9)) ram_ip
+     (.clka(clk), .ena(1'b1), .wea(set_stb & (set_addr == BASE+5)), .addra(ram_addr), .dia(set_data), .doa(),
+      .clkb(clk), .enb(1'b1), .web(1'b0), .addrb(sid[8:0]), .dib(32'hFFFF_FFFF), .dob(ip_dst));
+   
+   ram_2port #(.DWIDTH(32), .AWIDTH(9)) ram_udpmac
+     (.clka(clk), .ena(1'b1), .wea(set_stb & (set_addr == BASE+6)), .addra(ram_addr), .dia(set_data), .doa(),
+      .clkb(clk), .enb(1'b1), .web(1'b0), .addrb(sid[8:0]), .dib(32'hFFFF_FFFF), .dob({udp_dst,mac_dst[47:32]}));
+   
+   ram_2port #(.DWIDTH(32), .AWIDTH(9)) ram_maclower
+     (.clka(clk), .ena(1'b1), .wea(set_stb & (set_addr == BASE+7)), .addra(ram_addr), .dia(set_data), .doa(),
+      .clkb(clk), .enb(1'b1), .web(1'b0), .addrb(sid[8:0]), .dib(32'hFFFF_FFFF), .dob(mac_dst[31:0]));
+   
+   ip_hdr_checksum ip_hdr_checksum
+     (.clk(clk), .in({misc_ip,ip_len,ident,flag_frag,ttl_prot,16'd0,ip_src,ip_dst}),
+      .out(iphdr_checksum));
+
+   always @*
+     case(vef_state)
+       1 : tdata <= { pad[47:0], mac_dst[47:32]};
+       2 : tdata <= { mac_dst[31:0], mac_src[47:16]};
+       3 : tdata <= { mac_src[15:0], eth_type[15:0], misc_ip[15:0], ip_len[15:0] };
+       4 : tdata <= { ident[15:0], flag_frag[15:0], ttl_prot[15:0], iphdr_checksum[15:0]};
+       5 : tdata <= { ip_src, ip_dst};
+       6 : tdata <= { udp_src, udp_dst, udp_len, udp_checksum};
+       default : tdata <= in_tdata;
+     endcase // case (vef_state)
+      
+endmodule // vrlp_eth_framer
diff --git a/fpga/usrp3/lib/packet_proc/vrlp_to_compressed_vita.v b/fpga/usrp3/lib/packet_proc/vrlp_to_compressed_vita.v
new file mode 100644
index 000000000..04da73616
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/vrlp_to_compressed_vita.v
@@ -0,0 +1,90 @@
+
+module vrlp_to_compressed_vita
+  (input clk, input reset, input clear,
+   input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+   output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   wire [63:0] 	 o_tdata_int;
+   wire 	 o_tlast_int, o_tvalid_int, o_tready_int;
+
+   reg [1:0] 	 v2cv_state;
+   reg [11:0] 	 seqnum;
+   reg 		 trim_line;
+		 
+   localparam V2CV_VRLP = 2'd0;
+   localparam V2CV_VRTH = 2'd1;
+   localparam V2CV_BODY = 2'd2;
+   localparam V2CV_DUMP = 2'd3;
+
+   wire 	 is_ec = i_tdata[63:60] == 4'h5;
+   wire 	 has_trailer = i_tdata[58] & ~is_ec;
+   wire 	 has_time = |i_tdata[53:52];
+   wire 	 eob = i_tdata[56] & ~is_ec;
+   wire [15:0] 	 len = i_tdata[47:32];
+   wire [31:0] 	 sid = i_tdata[31:0];
+   
+   wire [63:0] 	 compressed_hdr = { is_ec, has_trailer, has_time, eob, seqnum, len, sid };
+   wire 	 bad_vita = |i_tdata[55:54]  /* has secs */ | i_tdata[59] /* has class */ | ( {i_tdata[63],i_tdata[61:60]} != 3'b001 );
+   reg [15:0] 	 len_reg;
+   wire [16:0] vita_words32 = i_tdata[16:0]-17'd4;
+   assign trim_now = 0;
+
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  v2cv_state <= V2CV_VRLP;
+	  seqnum <= 12'd0;
+	  trim_line <= 1'b0;
+	  len_reg <= 16'd0;
+       end
+     else
+       case(v2cv_state)
+	 V2CV_VRLP :
+	   if(i_tvalid)
+	     begin
+		seqnum <= i_tdata[31:20];
+		trim_line <= i_tdata[0];
+		len_reg <= vita_words32[16:1];
+		if(~i_tlast)
+		  v2cv_state <= V2CV_VRTH;
+	     end
+
+	 V2CV_VRTH :
+	   if(i_tvalid & o_tready_int)
+	     begin
+	     len_reg <= len_reg - 16'd1;
+	     if(i_tlast)
+	       v2cv_state <= V2CV_VRLP;
+	     else if(bad_vita)
+	       v2cv_state <= V2CV_DUMP;
+	     else
+	       v2cv_state <= V2CV_BODY;
+	     end
+
+	 V2CV_BODY :
+	   if(i_tvalid & o_tready_int)
+	     begin
+		len_reg <= len_reg - 16'd1;
+		if(i_tlast)
+		  v2cv_state <= V2CV_VRLP;
+		else if(len_reg == 16'd0)
+		  v2cv_state <= V2CV_DUMP;
+	     end
+	 V2CV_DUMP :
+	   if(i_tvalid)
+	     if(i_tlast)
+	       v2cv_state <= V2CV_VRLP;
+       endcase // case (v2cv_state)
+
+   assign o_tdata_int = (v2cv_state == V2CV_VRTH) ? compressed_hdr : i_tdata;
+   assign o_tlast_int = i_tlast | (len_reg == 16'd0);
+   assign o_tvalid_int = i_tvalid && (((v2cv_state == V2CV_VRTH) && !bad_vita) || (v2cv_state == V2CV_BODY));
+   assign i_tready = o_tready_int | (v2cv_state == V2CV_VRLP) | (v2cv_state == V2CV_DUMP);
+
+   axi_fifo_short #(.WIDTH(65)) short_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+      .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .space(), .occupied());
+
+endmodule // vrlp_to_compressed_vita
diff --git a/fpga/usrp3/lib/packet_proc/vrlp_to_compressed_vita_tb.v b/fpga/usrp3/lib/packet_proc/vrlp_to_compressed_vita_tb.v
new file mode 100644
index 000000000..167c0b014
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/vrlp_to_compressed_vita_tb.v
@@ -0,0 +1,120 @@
+`timescale 1ns/1ps
+
+module vrlp_to_compressed_vita_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("vrlp_to_compressed_vita_tb.vcd");
+   initial $dumpvars(0,vrlp_to_compressed_vita_tb);
+
+   task send_packet;
+      input [63:0] data_start;
+      input [31:0] len;
+      
+      begin
+	 // Send a packet
+	 @(posedge clk);
+	 {i_tlast, i_tdata} <= { 1'b0, data_start };
+	 i_tvalid <= 1;
+	 @(posedge clk);
+	 i_tdata <= 64'hAAAA_BBBB_CCCC_0000;
+	 
+	 repeat(len-2)
+	   begin
+	      i_tvalid <= 1;
+	      @(posedge clk);
+	      i_tdata <= i_tdata + 1;
+	   end
+	 i_tlast <= 1;
+	 i_tdata <= i_tdata + 1;
+	 @(posedge clk);
+	 i_tvalid <= 1'b0;
+	 
+	 @(posedge clk);
+      end
+   endtask // send_packet
+   
+   
+   initial
+     begin
+	#1000 reset = 0;
+	#200000;
+	$finish;
+     end
+   
+   wire [63:0]  o_tdata;
+   reg [63:0] 	i_tdata;
+   wire [2:0] 	o_tuser;
+   reg [2:0] 	i_tuser;
+   reg 		i_tlast;
+   wire 	o_tlast;
+   wire		o_tvalid, i_tready;
+   reg 		i_tvalid, o_tready;
+   reg 		i_terror;
+   
+   localparam RPT_COUNT = 16;
+   
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 0;
+	
+	while(reset)
+	  @(posedge clk);
+	@(posedge clk);
+
+	//send_packet(64'hA0,3'd0, 16, 0);
+	send_packet(64'hAABC_0008_DEAD_BEEF, 4);
+	send_packet(64'h7DEF_0008_8765_4321, 4);
+	send_packet(64'hAABC_0007_F00D_1234, 4);
+	send_packet(64'h7DEF_0007_ABCD_4321, 4);
+	o_tready <= 1;
+	//send_packet(64'hC0,3'd0, 16, 1);
+	//send_packet(64'hD0,3'd0, 16, 0);
+	//send_packet(64'hE0,3'd0, 16, 0);
+	//send_packet(64'hF0,3'd0, 16, 0);
+
+	@(posedge clk);
+
+     end // initial begin
+
+   wire i_terror_int, i_tlast_int, i_tready_int, i_tvalid_int;
+   wire [2:0] i_tuser_int;
+   wire [63:0] i_tdata_int;
+   wire o_tlast_int, o_tready_int, o_tvalid_int;
+   wire [2:0] o_tuser_int;
+   wire [63:0] o_tdata_int;
+   wire [63:0] vrlp_tdata;
+   wire        vrlp_tlast, vrlp_tvalid, vrlp_tready;
+   
+   axi_fifo #(.WIDTH(65), .SIZE(10)) fifo
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({i_tlast,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata({i_tlast_int,i_tdata_int}), .o_tvalid(i_tvalid_int), .o_tready(i_tready_int));
+
+   compressed_vita_to_vrlp dut0
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(i_tdata_int), .i_tlast(i_tlast_int), .i_tvalid(i_tvalid_int), .i_tready(i_tready_int),
+      .o_tdata(vrlp_tdata), .o_tlast(vrlp_tlast), .o_tvalid(vrlp_tvalid), .o_tready(vrlp_tready));
+
+   vrlp_to_compressed_vita dut1
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(vrlp_tdata), .i_tlast(vrlp_tlast), .i_tvalid(vrlp_tvalid), .i_tready(vrlp_tready),
+      .o_tdata(o_tdata_int), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int));
+
+   axi_fifo #(.WIDTH(65), .SIZE(10)) fifo_out
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+      .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready));
+
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       begin
+	  $display("%x",o_tdata);
+	  if(o_tlast)
+	    $display("======EOF========");
+       end
+endmodule // vrlp_to_compressed_vita_tb
diff --git a/fpga/usrp3/lib/timing/Makefile.srcs b/fpga/usrp3/lib/timing/Makefile.srcs
new file mode 100644
index 000000000..ff4ca17d2
--- /dev/null
+++ b/fpga/usrp3/lib/timing/Makefile.srcs
@@ -0,0 +1,11 @@
+#
+# Copyright 2013 Ettus Research LLC
+#
+
+##################################################
+# Timing Sources
+##################################################
+TIMING_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/timing/, \
+time_compare.v \
+timekeeper.v \
+))
diff --git a/fpga/usrp3/lib/timing/time_compare.v b/fpga/usrp3/lib/timing/time_compare.v
new file mode 100644
index 000000000..272c41b65
--- /dev/null
+++ b/fpga/usrp3/lib/timing/time_compare.v
@@ -0,0 +1,51 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+
+
+
+// 64 bits worth of ticks
+//
+// Not concerned with clock wrapping, human race will likely have extermintated it's self by this time.
+//
+
+module time_compare
+  (
+   input clk,
+   input reset,
+   input [63:0] time_now,
+   input [63:0] trigger_time,
+   output now,
+   output early,
+   output late,
+   output too_early);
+
+/*
+   reg [63:0] time_diff;
+
+   always @(posedge clk) begin
+        if (reset) begin
+            time_diff <= 64'b0;
+            now <= 1'b0;
+            late <= 1'b0;
+            early <= 1'b0;
+        end
+        else begin
+          time_diff <= trigger_time - time_now;
+          now <= ~(|time_diff);
+          late <= time_diff[63];
+          early <= ~now & ~late;
+       end
+   end
+   //assign now = ~(|time_diff);
+   //assign late = time_diff[63];
+   //assign early = ~now & ~late;
+   assign too_early = 0; //not implemented
+*/
+
+    assign now = time_now == trigger_time;
+    assign late = time_now > trigger_time;
+    assign early = ~now & ~late;
+    assign too_early = 0; //not implemented
+
+endmodule // time_compare
diff --git a/fpga/usrp3/lib/timing/time_transfer_tb.v b/fpga/usrp3/lib/timing/time_transfer_tb.v
new file mode 100644
index 000000000..af1207605
--- /dev/null
+++ b/fpga/usrp3/lib/timing/time_transfer_tb.v
@@ -0,0 +1,55 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+`timescale 1ns / 1ps
+
+module time_transfer_tb();
+
+   reg clk = 0, rst = 1;
+   always #5 clk = ~clk;
+   
+   initial 
+     begin
+	@(negedge clk);
+	@(negedge clk);
+	rst <= 0;
+     end
+
+   initial $dumpfile("time_transfer_tb.vcd");
+   initial $dumpvars(0,time_transfer_tb);
+   
+   initial #100000000 $finish;
+
+   wire exp_time, pps, pps_rcv;
+   wire [63:0] vita_time_rcv;
+   reg [63:0]  vita_time = 0;
+   reg [63:0]  counter = 0;
+
+   localparam  PPS_PERIOD = 439; // PPS_PERIOD % 10 must = 9
+   always @(posedge clk)
+     if(counter == PPS_PERIOD)
+       counter <= 0;
+     else
+       counter <= counter + 1;
+   assign      pps = (counter == (PPS_PERIOD-1));
+   
+   always @(posedge clk)
+     vita_time <= vita_time + 1;
+   
+   time_sender time_sender
+     (.clk(clk),.rst(rst),
+      .vita_time(vita_time),
+      .send_sync(pps),
+      .exp_time_out(exp_time) );
+
+   time_receiver time_receiver
+     (.clk(clk),.rst(rst),
+      .vita_time(vita_time_rcv),
+      .sync_rcvd(pps_rcv),
+      .exp_time_in(exp_time) );
+
+   wire [31:0] delta = vita_time - vita_time_rcv;
+endmodule // time_transfer_tb
diff --git a/fpga/usrp3/lib/timing/timekeeper.v b/fpga/usrp3/lib/timing/timekeeper.v
new file mode 100644
index 000000000..627472094
--- /dev/null
+++ b/fpga/usrp3/lib/timing/timekeeper.v
@@ -0,0 +1,68 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+module timekeeper
+  #(parameter BASE = 0)
+   (input clk, input reset, input pps,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    output reg [63:0] vita_time, output reg [63:0] vita_time_lastpps);
+
+   //////////////////////////////////////////////////////////////////////////
+   // timer settings for this module
+   //////////////////////////////////////////////////////////////////////////
+   wire [63:0] time_at_next_event;
+   wire set_time_pps, set_time_now;
+   wire cmd_trigger;
+
+   setting_reg #(.my_addr(BASE), .width()) sr_time_hi
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(time_at_next_event[63:32]), .changed());
+   
+   setting_reg #(.my_addr(BASE+1), .width()) sr_time_lo
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(time_at_next_event[31:0]), .changed());
+   
+   setting_reg #(.my_addr(BASE+2), .width(2)) sr_ctrl
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out({set_time_pps, set_time_now}), .changed(cmd_trigger));
+
+   //////////////////////////////////////////////////////////////////////////
+   // PPS edge detection logic
+   //////////////////////////////////////////////////////////////////////////
+   reg pps_del, pps_del2;
+   always @(posedge clk)
+     {pps_del2,pps_del} <= {pps_del, pps};
+
+   wire pps_edge = !pps_del2 & pps_del;
+
+   //////////////////////////////////////////////////////////////////////////
+   // track the time at last pps so host can detect the pps
+   //////////////////////////////////////////////////////////////////////////
+   always @(posedge clk)
+     if(pps_edge) vita_time_lastpps <= vita_time;
+
+   //////////////////////////////////////////////////////////////////////////
+   // arm the trigger to latch a new time when the ctrl register is written
+   //////////////////////////////////////////////////////////////////////////
+   reg armed;
+   wire time_event = armed && ((set_time_now) || (set_time_pps && pps_edge));
+   always @(posedge clk) begin
+     if (reset) armed <= 1'b0;
+     else if (cmd_trigger) armed <= 1'b1;
+     else if (time_event) armed <= 1'b0;
+   end
+
+   //////////////////////////////////////////////////////////////////////////
+   // vita time tracker - update every tick or when we get an "event"
+   //////////////////////////////////////////////////////////////////////////
+   always @(posedge clk)
+     if(reset)
+       vita_time <= 64'h0;
+     else if (time_event)
+       vita_time <= time_at_next_event;
+     else
+       vita_time <= vita_time + 64'h1;
+
+endmodule // timekeeper
diff --git a/fpga/usrp3/lib/vita/.gitignore b/fpga/usrp3/lib/vita/.gitignore
new file mode 100644
index 000000000..4ab6ae4ba
--- /dev/null
+++ b/fpga/usrp3/lib/vita/.gitignore
@@ -0,0 +1 @@
+*tb
diff --git a/fpga/usrp3/lib/vita/Makefile.srcs b/fpga/usrp3/lib/vita/Makefile.srcs
new file mode 100644
index 000000000..e4a8df26e
--- /dev/null
+++ b/fpga/usrp3/lib/vita/Makefile.srcs
@@ -0,0 +1,29 @@
+#
+# Copyright 2013 Ettus Research LLC
+#
+
+##################################################
+# VITA Sources
+##################################################
+VITA_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/vita/, \
+new_tx_control.v \
+new_tx_deframer.v \
+tx_responder.v \
+trigger_context_pkt.v \
+context_packet_gen.v \
+new_rx_control.v \
+new_rx_framer.v \
+chdr_16sc_to_xxxx_chain.v \
+chdr_xxxx_to_16sc_chain.v \
+chdr_16sc_to_12sc.v \
+chdr_12sc_to_16sc.v \
+chdr_16sc_to_8sc.v \
+chdr_8sc_to_16sc.v \
+chdr_16sc_to_32f.v \
+chdr_32f_to_16sc.v \
+chdr_16sc_to_32f.v \
+chdr_32f_to_16sc.v \
+float_to_iq.v \
+iq_to_float.v \
+binary_encoder.v \
+))
diff --git a/fpga/usrp3/lib/vita/README.txt b/fpga/usrp3/lib/vita/README.txt
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/lib/vita/binary_encoder.v b/fpga/usrp3/lib/vita/binary_encoder.v
new file mode 100644
index 000000000..95d4b55e7
--- /dev/null
+++ b/fpga/usrp3/lib/vita/binary_encoder.v
@@ -0,0 +1,37 @@
+`define log2(N) (\
+                 N < 2 ? 0 : \
+                 N < 4 ? 1 : \
+                 N < 8 ? 2 : \
+                 N < 16 ? 3 : \
+                 N < 32 ? 4 : \
+                 N < 64 ? 5 : \
+                 N < 128 ? 6 : \
+                 N < 256 ? 7 : \
+                 N < 512 ? 8 : \
+                 N < 1024 ? 9 : \
+                 10)
+
+  module binary_encoder
+    #(
+      parameter SIZE = 16
+      )
+      (
+       input [SIZE-1:0] in,
+       output [`log2(SIZE)-1:0] out
+       );
+
+  genvar m,n;
+
+   generate
+      // Loop enough times to represent the total number of input bits as an encoded value
+      for (m = 0; m <= `log2(SIZE-1); m = m + 1)  begin: expand_or_tree
+         wire [SIZE-1:0] encoding;
+         // Build enable mask by iterating through every input bit.
+         for (n = 0; n < SIZE ; n = n + 1) begin: encode_this_bit
+            assign encoding[n] = n[m];
+         end
+         // OR tree for this output bit with appropraite bits enabled.
+         assign    out[m] = |(encoding & in);
+      end
+   endgenerate
+endmodule // binary_encoder
diff --git a/fpga/usrp3/lib/vita/build_12_to_16 b/fpga/usrp3/lib/vita/build_12_to_16
new file mode 100755
index 000000000..a897a966e
--- /dev/null
+++ b/fpga/usrp3/lib/vita/build_12_to_16
@@ -0,0 +1 @@
+iverilog -y . -y ../dsp/ -y ../control/ -Wall chdr_12sc_to_16sc_tb.v -o chdr_12sc_to_16sc_tb
diff --git a/fpga/usrp3/lib/vita/build_16_to_12 b/fpga/usrp3/lib/vita/build_16_to_12
new file mode 100755
index 000000000..45e354e9e
--- /dev/null
+++ b/fpga/usrp3/lib/vita/build_16_to_12
@@ -0,0 +1 @@
+iverilog -y . -y ../dsp/ -y ../control/ -Wall chdr_16sc_to_12sc_tb.v -o chdr_16sc_to_12sc_tb
diff --git a/fpga/usrp3/lib/vita/build_16_to_8 b/fpga/usrp3/lib/vita/build_16_to_8
new file mode 100755
index 000000000..9c32aa7cd
--- /dev/null
+++ b/fpga/usrp3/lib/vita/build_16_to_8
@@ -0,0 +1,2 @@
+iverilog -y . -y ../dsp/ -y ../control/ -Wall chdr_16sc_to_8sc_tb.v -o chdr_16sc_to_8sc_tb
+
diff --git a/fpga/usrp3/lib/vita/build_8_to_16 b/fpga/usrp3/lib/vita/build_8_to_16
new file mode 100755
index 000000000..17116b481
--- /dev/null
+++ b/fpga/usrp3/lib/vita/build_8_to_16
@@ -0,0 +1,2 @@
+iverilog -y . -y ../dsp/ -y ../control/ -Wall chdr_8sc_to_16sc_tb.v -o chdr_8sc_to_16sc_tb
+
diff --git a/fpga/usrp3/lib/vita/chdr_12sc_to_16sc.v b/fpga/usrp3/lib/vita/chdr_12sc_to_16sc.v
new file mode 100644
index 000000000..2ae61a32d
--- /dev/null
+++ b/fpga/usrp3/lib/vita/chdr_12sc_to_16sc.v
@@ -0,0 +1,176 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+
+
+
+
+module chdr_12sc_to_16sc
+  #(parameter BASE = 0)
+   ( input set_stb, input [7:0] set_addr, input [31:0] set_data,
+     //input side of device
+     input 	       clk, input reset,
+     input [63:0]      i_tdata,
+     input 	       i_tlast,
+     input 	       i_tvalid,
+     output 	       i_tready,
+     //output side of device
+     output reg [63:0] o_tdata,
+     output 	       o_tlast,
+     output 	       o_tvalid,
+     input 	       o_tready,
+
+     output [31:0]     debug
+     );
+   
+
+   
+   
+   
+   wire 	       chdr_has_hdr = 1'b1;
+   wire 	       chdr_has_time = i_tdata[61];
+   wire 	       chdr_has_tlr = 1'b0;
+
+   wire [15:0] 	       chdr_header_lines = chdr_has_time? 16 : 8;  
+   wire [15:0] 	       just_samples_in = i_tdata[47:32] - chdr_header_lines;
+
+   //calculating output length based on input ( 4/3*input = output)
+
+   wire [30:0] 	       calc_output_len = ({just_samples_in,14'h0} + {just_samples_in,12'h0} + {just_samples_in,10'h0} + {just_samples_in,8'h0} + {just_samples_in,6'h0} + {just_samples_in,4'h0} + {just_samples_in,2'h0}+{just_samples_in} +'b0001000000000000)<<2;
+
+   wire [15:0] 	       samples = calc_output_len[30:16];
+   wire [15:0] 	       chdr_payload_lines = samples + chdr_header_lines;
+   
+
+   reg 		       has_exline;
+   reg 		       in_exline;
+   
+   
+   
+   wire 	       set_sid;
+   wire [15:0] 	       my_newhome;
+   
+
+   setting_reg #(.my_addr(BASE), .width(17)) new_destination
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out({set_sid, my_newhome[15:0]}));
+
+   localparam HEADER = 3'd0; // IDLE
+   localparam TIME     = 3'd1;
+   localparam ODD_LINE_ZERO = 3'd2;
+   localparam EVEN_LINE_ONE = 3'd3;
+   localparam ODD_LINE_TWO = 3'd4;
+   localparam EVEN_LINE_THREE = 3'd5;
+   
+   reg [2:0] 	       state;
+
+   
+
+   always @(posedge clk) begin
+      
+      if (reset) begin
+         state <= HEADER;	 
+      end
+      
+      else if (o_tvalid && o_tready) case(state)
+
+
+				       HEADER: begin
+					  has_exline <= ( (samples[4:2] == 5) || (samples[4:2] == 7) || (samples[4:2] == 0));
+					  state <= (chdr_has_time)? TIME : ODD_LINE_ZERO;
+				       end
+				       
+				       TIME: begin
+					  state <= (i_tlast)? HEADER: ODD_LINE_ZERO; 
+				       end
+
+				       ODD_LINE_ZERO: begin
+					  if ((i_tlast & !has_exline) || in_exline) begin
+					     state <= HEADER;
+					     in_exline <= 0;
+					  end
+					  else if (i_tlast & has_exline) begin
+					     in_exline <= 1;
+					     state <= EVEN_LINE_ONE;
+					  end
+					  else
+					    state <= EVEN_LINE_ONE;
+				       end
+
+				       EVEN_LINE_ONE: begin
+					  if ((i_tlast & !has_exline) || in_exline) begin
+					     state <= HEADER;
+					     in_exline <= 0;
+					  end
+					  else if (i_tlast & has_exline) begin
+					     in_exline <= 1;
+					     state <= ODD_LINE_TWO;
+					  end
+					  else
+					    state <= ODD_LINE_TWO;
+				       end
+				       
+				       ODD_LINE_TWO: begin
+					  if ((i_tlast & !has_exline) || in_exline) begin
+					     state <= HEADER;
+					     in_exline <= 0;
+					  end
+					  else if (i_tlast & has_exline) begin
+					     in_exline <= 1;
+					     state <= EVEN_LINE_THREE;
+					  end
+					  else
+					    state <= EVEN_LINE_THREE;
+				       end 
+				       
+				       EVEN_LINE_THREE: begin
+					  if (in_exline) begin
+					     state <= HEADER;
+					     in_exline <= 0;
+					  end
+					  else
+					    state <= ODD_LINE_ZERO;
+				       end 
+				       
+				       default: state <= HEADER;
+				       
+				     endcase
+   end
+
+
+   //hold data after each input xfer
+   reg [63:0] 	       hold_tdata;
+   always @(posedge clk) begin
+      if (i_tvalid && i_tready) hold_tdata <= i_tdata;
+   end
+
+   //main mux
+   
+   always @(*)
+     case(state)
+
+       HEADER: o_tdata <= {i_tdata[63:48],chdr_payload_lines,
+			   set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
+       
+       TIME: o_tdata <= i_tdata;
+       
+       ODD_LINE_ZERO: o_tdata <= {i_tdata[63:52], 4'h0, i_tdata[51:40], 4'h0, i_tdata[39:28],4'h0, i_tdata[27:16], 4'h0};
+       
+       EVEN_LINE_ONE: o_tdata <= {hold_tdata[15:4],4'h0,hold_tdata[3:0],i_tdata[63:56],4'h0,i_tdata[55:44], 4'h0,i_tdata[43:32],4'h0};
+       
+       ODD_LINE_TWO: o_tdata <= {hold_tdata[31:20], 4'h0, hold_tdata[19:8],4'h0, hold_tdata[7:0],i_tdata[63:60],4'h0,i_tdata[59:48],4'h0};
+       
+       EVEN_LINE_THREE: o_tdata <= {hold_tdata[47:36],4'h0,hold_tdata[35:24],4'h0,hold_tdata[23:12],4'h0,hold_tdata[11:0],4'h0};
+       
+
+       default: o_tdata <= i_tdata;
+       
+     endcase
+   
+   assign o_tvalid = (in_exline)? 1'b1: i_tvalid;
+   assign i_tready = (state != EVEN_LINE_THREE) & o_tready & !in_exline;
+   assign o_tlast  = (has_exline)? in_exline: ((state != EVEN_LINE_THREE) && i_tlast);
+
+endmodule
diff --git a/fpga/usrp3/lib/vita/chdr_12sc_to_16sc_tb.v b/fpga/usrp3/lib/vita/chdr_12sc_to_16sc_tb.v
new file mode 100644
index 000000000..6c91171e0
--- /dev/null
+++ b/fpga/usrp3/lib/vita/chdr_12sc_to_16sc_tb.v
@@ -0,0 +1,188 @@
+`timescale 1ns/1ps
+
+module chdr_12sc_to_16sc_tb();
+   
+   reg clk = 0;
+   reg reset = 1;
+   //generate clock
+   always #10 clk = ~clk; 
+
+   initial $dumpfile("chdr_12sc_to_16sc_tb.vcd");
+   initial $dumpvars(0,chdr_12sc_to_16sc_tb);
+   
+   //tells when to finish
+   initial
+     begin
+   	#50 reset = 0;
+   	#50000; 
+   	$finish;
+     end
+
+   //setting registers and wire
+   reg [63:0] i_tdata;
+   reg        i_tlast = 0;
+   reg        i_tvalid = 0;
+   wire       i_tready ;
+   reg [7:0]  set_addr;
+   reg [31:0] set_data;
+   reg 	      set_stb;
+   
+
+   wire [63:0] o_tdata;
+   wire        o_tlast;
+   
+   wire	       o_tvalid;
+   reg 	       o_tready;
+
+   chdr_12sc_to_16sc #(.BASE(89))dut
+     (.clk(clk), .reset(reset),
+      .set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
+   
+   //if you want to feed a bigger input change array sizes here
+
+   reg [63:0]  data[0:11];
+   initial $readmemh("from12_to_x.hex", data);
+
+   //test packet loop
+   task test_packet;
+      input [15:0] len;
+      input [31:0] sid;
+      reg [1:0]    index;
+      
+      begin
+	 index <= 0;
+	 @(posedge clk) ;
+	 //send header 
+   	 i_tdata = {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, (len + 16'd16),sid};
+	 i_tvalid <= 1;
+	 i_tlast <= 0;
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tdata <= {64'b0};
+   	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 
+	 //-1 for last bit accounting
+	 repeat (len[15:3] + (len[2]|len[1]|len[0]) - 1)
+	   begin
+	      i_tdata <= {data[index]}; 
+   	      index <= index+1;
+	      @(posedge clk);
+	      while (i_tready != 1)
+		@(posedge clk);     
+	   end
+   	 i_tlast <= 1'b1;
+	 i_tdata <= {data[index]}; 
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 
+	 i_tvalid <= 0;
+      end
+   endtask // test_packet
+
+   //test_destination loop
+
+   task test_destination;
+      input enable;
+      input [15:0] dest_home;
+      
+      
+      begin
+         @(posedge clk);
+         
+         set_data <= {enable,dest_home};
+         set_addr <= 89;
+         set_stb <= 1;
+         
+         @(posedge clk);
+         set_stb <= 0;
+      end
+   endtask
+
+
+
+   
+   
+   //main loop	
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 1;
+	i_tdata <= 0;
+	
+	@(negedge reset);
+	@(posedge clk);
+	@(posedge clk);
+
+
+//testing ending positions
+
+//from 1 to 7 should be line zero
+/*
+	test_destination(1,16'hFEED);
+	test_packet(0, 32'hDEAD_BEEF);
+	#100
+*/
+
+	test_destination(1,16'hFEED);
+	test_packet(3, 32'hDEAD_BEEF);
+	#100
+
+	test_destination(1,16'hFEED);
+	test_packet(6, 32'hDEAD_BEEF);
+	#100
+
+	test_destination(1,16'hFEED);
+	test_packet(9, 32'hDEAD_BEEF);
+	#100
+
+
+
+
+//from 8 to 13 should be line one
+
+	test_destination(1,16'hFEED);
+	test_packet(12, 32'hDEAD_BEEF);
+	#100
+
+	test_destination(1,16'hFEED);
+	test_packet(15, 32'hDEAD_BEEF);
+	#100
+
+	test_destination(1,16'hFEED);
+	test_packet(18, 32'hDEAD_BEEF);
+	#100
+
+	test_destination(1,16'hFEED);
+	test_packet(21, 32'hDEAD_BEEF);
+	#100
+
+	
+	test_destination(1,16'hFEED);
+	test_packet(24, 32'hDEAD_BEEF);
+	
+	#100
+
+	test_destination(1,16'hFEED);
+	test_packet(27, 32'hDEAD_BEEF);
+	  
+
+	
+
+	  
+
+
+	
+
+	
+
+     end
+
+
+
+endmodule
diff --git a/fpga/usrp3/lib/vita/chdr_16sc_to_12sc.v b/fpga/usrp3/lib/vita/chdr_16sc_to_12sc.v
new file mode 100644
index 000000000..c91d9cbd1
--- /dev/null
+++ b/fpga/usrp3/lib/vita/chdr_16sc_to_12sc.v
@@ -0,0 +1,221 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+module chdr_16sc_to_12sc
+  #(parameter BASE=0)
+   ( input set_stb, input [7:0] set_addr, input [31:0] set_data,
+     //left side of device
+     input 	       clk, input reset,
+     input [63:0]      i_tdata,
+     input 	       i_tlast,
+     input 	       i_tvalid,
+     output 	       i_tready,
+     //right side of device
+     output reg [63:0] o_tdata = 0,
+     output 	       o_tlast,
+     output 	       o_tvalid,
+     input 	       o_tready,
+
+     output [31:0]     debug
+     );
+   
+   wire 	       chdr_has_hdr = 1'b1;
+   wire 	       chdr_has_time = i_tdata[61];
+   wire 	       chdr_has_tlr = 1'b0;
+
+   wire [11:0] 	       imag0;
+   wire [11:0] 	       real0;
+   wire [11:0] 	       imag1;
+   wire [11:0] 	       real1;
+   wire [11:0] 	       imag2;
+   wire [11:0] 	       real2;
+   
+   
+
+   wire [16:0] 	       round_i0;
+   wire [16:0] 	       round_r0;
+   wire [16:0] 	       round_i1;
+   wire [16:0] 	       round_r1;
+   wire [16:0] 	       round_i2;
+   wire [16:0] 	       round_r2;
+
+//pipiline registers
+
+   reg [11:0] 	       imag0_out;
+   reg [11:0] 	       real0_out;
+   reg [11:0] 	       imag1_out;
+   reg [11:0] 	       real1_out;
+
+   reg [15:0] 	       len_data;
+
+   //chdr length calculations
+   wire [15:0] 	       chdr_header_lines = chdr_has_time? 16 : 8;
+   wire [15:0] 	       in_samples = i_tdata[47:32] - chdr_header_lines;
+   wire [15:0] 	       samples = (in_samples*3) >> 2;
+   wire [15:0] 	       chdr_payload_lines = samples + chdr_header_lines;  
+
+
+   reg 		       needs_exline = 0;
+   reg                 in_exline = 0;
+ 
+   
+   wire 	       set_sid;
+   wire [15:0] 	       my_newhome;
+ 	       
+   setting_reg #(.my_addr(BASE), .width(17)) new_destination
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out({set_sid, my_newhome[15:0]}));
+   
+   //state machine
+
+   localparam HEADER = 3'd0; // IDLE
+   localparam TIME     = 3'd1;
+   localparam LINE_ODD_ZERO = 3'd2;
+   localparam LINE_EVEN_ONE = 3'd3;
+   localparam LINE_ODD_TWO = 3'd4;
+   localparam REG_STATE = 3'd5;
+   
+   reg [2:0] 	       state;
+   
+   
+   
+   always @(posedge clk) begin
+      if (reset) begin
+	 state <= HEADER;
+	 needs_exline <= 0;
+	 in_exline <= 0;
+      end
+  
+
+      else if ((o_tvalid && o_tready) || (i_tready && i_tvalid)) case(state)
+
+								   
+								   HEADER: begin
+								      
+								      needs_exline <= (in_samples[4:2] == 3 || in_samples[4:2] == 4 || in_samples[4:2] == 6);
+								      state <= (i_tdata[61])? TIME: REG_STATE;
+								      
+								   end
+
+								   TIME: begin
+								      state <= (i_tlast) ? HEADER: REG_STATE;     
+								   end
+
+								   REG_STATE: begin
+								      if (i_tlast & !needs_exline || in_exline) begin
+									 state <= HEADER;
+									 in_exline <= 0;
+								      end
+								      else if (i_tlast & needs_exline) begin
+									 state <= LINE_EVEN_ONE;
+									 in_exline <= 1;
+									 
+								      end
+								      else
+									state <= LINE_EVEN_ONE;
+								   end
+
+
+								   LINE_EVEN_ONE: begin
+								      if (i_tlast & !needs_exline || in_exline) begin
+									 state <= HEADER;
+									 in_exline <= 0;
+								      end
+								      else if (i_tlast & needs_exline) begin
+									 state <= LINE_ODD_TWO;
+									 in_exline <= 1;
+									 
+								      end
+								      else
+									state <= LINE_ODD_TWO;
+								   end
+
+								   
+								   
+
+								   LINE_ODD_TWO: begin
+								      if (i_tlast & !needs_exline || in_exline) begin
+									 state <= HEADER;
+									 in_exline <= 0;
+								      end
+								      else if (i_tlast & needs_exline) begin
+									 state <= LINE_ODD_ZERO;
+									 in_exline <= 1;
+									 
+								      end
+								      else
+									state <= LINE_ODD_ZERO;
+								   end
+
+								   LINE_ODD_ZERO: begin
+								      if (i_tlast & !needs_exline || in_exline) begin
+									 state <= HEADER;
+									 in_exline <= 0;
+								      end
+								      else if (i_tlast & needs_exline) begin
+									 state <= REG_STATE;
+									 in_exline <= 1;
+								      end
+								      else
+									state <= REG_STATE;
+								   end
+
+								   default: state <= HEADER;
+
+								 endcase
+   end 
+   
+   assign	round_i0 = ({i_tdata[63],i_tdata[63:48]} + 'h0008);
+   assign	round_r0 = ({i_tdata[47],i_tdata[47:32]} + 'h0008);
+   
+   assign imag0 = (round_i0[16] == 0 && round_i0[15] == 1)?(12'h7FF):(round_i0[16] == 1 && round_i0[15] == 0)? (12'h800):(round_i0[15:4]);
+   
+   assign	real0 = (round_r0[16] == 0 && round_r0[15] == 1)?(12'h7FF):(round_r0[16] == 1 && round_r0[15] == 0)? (12'h800):(round_r0[15:4]);
+   
+   assign round_i1 = ({i_tdata[31],i_tdata[31:16]} + 'h0008);
+   assign round_r1 = ({i_tdata[15],i_tdata[15:0]} + 'h0008);
+   
+   assign imag1 = (round_i1[16] == 0 && round_i1[15] == 1)?(12'h7FF):(round_i1[16] == 1 && round_i1[15] == 0)? (12'h800):(round_i1[15:4]);
+   
+   assign	real1 = (round_r1[16] == 0 && round_r1[15] == 1)?(12'h7FF):(round_r1[16] == 1 && round_r1[15] == 0)? (12'h800):(round_r1[15:4]);
+
+
+   
+   
+   always @(posedge clk)
+     if (i_tvalid && o_tready)
+       begin
+	  imag0_out <= imag0;
+	  real0_out <= real0;
+	  imag1_out <= imag1;
+	  real1_out <= real1;
+       end
+
+
+
+   always @(*)
+     case(state)
+       
+        HEADER: o_tdata <= {i_tdata[63:48], chdr_payload_lines,
+			  set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
+        TIME: o_tdata <= i_tdata;
+
+       
+        REG_STATE: o_tdata <= {imag0,real0,imag1, real1, 16'b0};
+       
+	LINE_EVEN_ONE: o_tdata <= {imag0_out, real0_out, imag1_out, real1_out, imag0, real0[11:8]};
+	LINE_ODD_TWO: o_tdata <= {real0_out[7:0], imag1_out, real1_out, imag0, real0,imag1[11:4]};
+	LINE_ODD_ZERO: o_tdata <= {imag1_out[3:0], real1_out, imag0, real0, imag1, real1};
+	      
+       default : o_tdata <= i_tdata;
+     endcase 
+   
+   assign o_tvalid =((in_exline) || (state != REG_STATE & i_tvalid) || (i_tlast & i_tvalid & !needs_exline)); 
+   assign i_tready = (o_tready & !in_exline)||(state == REG_STATE && !i_tlast);
+   assign o_tlast =  (needs_exline)? in_exline: i_tlast;
+   
+   
+
+endmodule
diff --git a/fpga/usrp3/lib/vita/chdr_16sc_to_12sc_tb.v b/fpga/usrp3/lib/vita/chdr_16sc_to_12sc_tb.v
new file mode 100644
index 000000000..e6f81daeb
--- /dev/null
+++ b/fpga/usrp3/lib/vita/chdr_16sc_to_12sc_tb.v
@@ -0,0 +1,165 @@
+//Purpose: to test 8 to 16 converter
+`timescale 1ns/1ps
+
+module chdr_16sc_to_12sc_tb();
+   
+   reg clk = 0;
+   reg reset = 1;
+   //generate clock
+   always #10 clk = ~clk; 
+
+   initial $dumpfile("chdr_16sc_to_12sc_tb.vcd");
+   initial $dumpvars(0,chdr_16sc_to_12sc_tb);
+   
+   //tells when to finish
+   initial
+     begin
+   	#50 reset = 0;
+   	#50000; 
+   	$finish;
+     end
+
+   //setting registers and wire
+   reg [63:0] i_tdata;
+   reg        i_tlast = 0;
+   reg        i_tvalid = 0;
+   wire       i_tready ;
+   reg [7:0]  set_addr;
+   reg [31:0] set_data;
+   reg 	      set_stb;
+   
+
+   wire [63:0] o_tdata;
+   wire        o_tlast;
+   
+   wire	       o_tvalid;
+   reg 	       o_tready;
+
+   chdr_16sc_to_12sc #(.BASE(89))dut
+     (.clk(clk), .reset(reset),
+      .set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
+   
+   //if you want to feed a bigger input change array sizes here
+
+   reg [63:0]  data[0:7];
+   initial $readmemh("from16_to_x.hex", data);
+
+   //test packet loop
+   task test_packet;
+      input [15:0] len;
+      input [31:0] sid;
+      reg [1:0]    index;
+      
+      begin
+	 index <= 0;
+	 @(posedge clk) ;
+	 //send header 
+   	 i_tdata = {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, len + 16'd16,sid};
+	 i_tvalid <= 1;
+	 i_tlast <= 0;
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tdata <= {64'b0};
+   	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 
+	 //-1 for last bit accounting
+	repeat (len[15:3] + (len[2]|len[1]|len[0]) - 1)
+	   begin
+	      i_tdata <= {data[index]}; 
+   	      index <= index+1;
+	      //while (i_tready != 1)
+		//@(posedge clk);
+	      @(posedge clk);
+	      while (i_tready != 1)
+		@(posedge clk);
+	      
+	   end
+   	 i_tlast <= 1'b1;
+	 i_tdata <= {data[index]}; 
+
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 
+	 i_tvalid <= 0;
+      end
+   endtask // test_packet
+
+   //test_destination loop
+
+   task test_destination;
+      input enable;
+      input [15:0] dest_home;
+      
+      
+      begin
+         @(posedge clk);
+         
+         set_data <= {enable,dest_home};
+         set_addr <= 89;
+         set_stb <= 1;
+         
+         @(posedge clk);
+         set_stb <= 0;
+      end
+   endtask
+
+
+
+   
+   
+   //main loop	
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 1;
+	
+	i_tdata <= 0;
+	
+	@(negedge reset);
+	@(posedge clk);
+	@(posedge clk);
+
+//end on line one
+//1
+	test_destination(1,16'hFEED);
+	test_packet(4, 32'hDEAD_BEEF);
+//2
+	test_destination(1,16'hFEED);
+	test_packet(8, 32'hDEAD_BEEF);
+//3
+	test_destination(1,16'hFEED);
+	test_packet(12, 32'hDEAD_BEEF);
+//4
+
+	test_destination(1,16'hFEED);
+	test_packet(16, 32'hDEAD_BEEF);
+//5
+	test_destination(1,16'hFEED);
+	test_packet(20, 32'hDEAD_BEEF);
+//6
+	test_destination(1,16'hFEED);
+	test_packet(24, 32'hDEAD_BEEF);
+
+//end on line two 
+
+//7
+
+	test_destination(1,16'hFEED);
+	test_packet(28, 32'hDEAD_BEEF);
+//8
+	
+	test_destination(1,16'hFEED);
+	test_packet(32, 32'hDEAD_BEEF);
+	
+
+     end
+
+
+
+endmodule
diff --git a/fpga/usrp3/lib/vita/chdr_16sc_to_32f.v b/fpga/usrp3/lib/vita/chdr_16sc_to_32f.v
new file mode 100644
index 000000000..74aff2f08
--- /dev/null
+++ b/fpga/usrp3/lib/vita/chdr_16sc_to_32f.v
@@ -0,0 +1,138 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+
+
+
+module chdr_16sc_to_32f
+  #(parameter BASE=0)
+   ( input clk, input reset, input set_stb, input [7:0] set_addr,
+    input [31:0]      set_data,
+    input [63:0]      i_tdata,
+    input 	      i_tlast,
+    input 	      i_tvalid,
+    output 	      i_tready,
+
+   
+    output reg [63:0] o_tdata,
+    output 	      o_tlast,
+    output 	      o_tvalid,
+    input 	      o_tready,
+
+    output [31:0]     debug
+    );
+
+
+   wire [31:0] 	      s0_real;
+   wire [31:0] 	      s0_imag;
+   wire [31:0] 	      s1_real;
+   wire [31:0] 	      s1_imag;
+
+
+   wire 	      chdr_has_hdr = 1'b1;
+   wire 	      chdr_has_time = i_tdata[61];
+   wire 	      chdr_has_tlr = 1'b0;
+
+ 	      
+   //chdr length calculations
+
+   wire [15:0] 	      chdr_header_lines = chdr_has_time? 16:8;
+   wire [15:0] 	      samples = ((i_tdata[47:32] - chdr_header_lines) << 1);
+   wire [15:0] 	      i_samples = (i_tdata[47:32] - chdr_header_lines);
+   
+
+   wire [15:0] 	      chdr_payload_lines = samples + chdr_header_lines;
+
+   
+   
+    wire 	      set_sid;
+   wire [15:0] 	      my_newhome;
+
+   setting_reg #(.my_addr(BASE), .width(17)) new_destination
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),.out({set_sid, my_newhome[15:0]}));
+
+ 
+
+		    
+   
+   //state machines
+   localparam HEADER        = 2'd0;//IDLE
+   localparam TIME          = 2'd1;
+   localparam ODD           = 2'd2;
+   localparam EVEN          = 2'd3;
+   reg [1:0] 	      state;
+   reg      end_on_odd;
+   
+   
+ 	      
+   
+
+   always @(posedge clk) begin
+      
+      
+      if (reset) begin
+	 state <= HEADER;
+	 end_on_odd <= 1'b0;
+      end
+      else if (o_tready && i_tvalid)  case(state)
+
+	     HEADER: begin
+		   state <= (i_tdata[61])? TIME : ODD;
+		   end_on_odd <= (i_samples[2:1] == 2 || i_samples[2:1] == 1);	
+	     end
+
+	     TIME: begin
+		   state <= (i_tlast)? HEADER: ODD;
+	     end
+
+	     ODD: begin
+		   state <= (i_tlast & end_on_odd)? HEADER:EVEN;
+	     end
+
+	     EVEN: begin
+		  state <= (i_tlast) ? HEADER: ODD;
+	     end
+					
+		default: state <= HEADER;
+	   endcase
+   end
+   
+
+ 
+
+   iq_to_float #(.BITS_IN(16), .BITS_OUT(32))
+   iq_to_float_imag0 (.in(i_tdata[63:48]), .out(s0_imag[31:0]));
+   
+   iq_to_float #(.BITS_IN(16), .BITS_OUT(32))
+   iq_to_float_real0 (.in(i_tdata[47:32]), .out(s0_real[31:0]));
+
+   iq_to_float #(.BITS_IN(16), .BITS_OUT(32))
+   iq_to_float_imag1 (.in(i_tdata[31:16]), .out(s1_imag[31:0]));	
+
+   iq_to_float #(.BITS_IN(16), .BITS_OUT(32))
+   iq_to_float_real1 (.in(i_tdata[15:0]), .out(s1_real[31:0]));	
+   
+
+
+
+
+   always @(*) 
+     case(state)
+     
+       HEADER: o_tdata <= {i_tdata[63:48], chdr_payload_lines,
+			  set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
+       TIME: o_tdata <= i_tdata;
+       ODD: o_tdata <= {s0_imag,s0_real};
+       EVEN: o_tdata <= {s1_imag,s1_real};
+  
+       
+       default : o_tdata = i_tdata;
+     endcase
+   
+   assign o_tvalid = i_tvalid;
+   assign i_tready = o_tready && ((state != ODD) || (i_tlast && end_on_odd));
+   assign o_tlast  = i_tlast && ((state == EVEN) || (state == ODD && end_on_odd));
+
+endmodule
diff --git a/fpga/usrp3/lib/vita/chdr_16sc_to_32f_tb.v b/fpga/usrp3/lib/vita/chdr_16sc_to_32f_tb.v
new file mode 100644
index 000000000..57d1be0cc
--- /dev/null
+++ b/fpga/usrp3/lib/vita/chdr_16sc_to_32f_tb.v
@@ -0,0 +1,145 @@
+//Purpose: to test 8 to 16 converter
+`timescale 1ns/1ps
+
+module chdr_16sc_to_32f_tb();
+
+   reg clk = 0;
+   reg reset = 1;
+   //generate clock
+   always #10 clk = ~clk; 
+
+   initial $dumpfile("chdr_16sc_to_32f_tb.vcd");
+   initial $dumpvars(0,chdr_16sc_to_32f_tb);
+   
+
+   //tells when to finish
+   initial
+     begin
+   	#50 reset = 0;
+   	#50000; 
+   	$finish;
+     end
+
+   //setting registers and wire
+   reg [63:0] i_tdata;
+   reg        i_tlast = 0;
+   reg        i_tvalid = 0;
+   wire       i_tready ;
+   reg [7:0] set_addr;
+   reg [31:0] set_data;
+   reg set_stb;
+   
+
+   wire [63:0] o_tdata;
+   wire        o_tlast;
+   
+   wire	       o_tvalid;
+   reg 	       o_tready;
+
+   chdr_16sc_to_32f #(.BASE(89))dut
+    (.clk(clk), .reset(reset),
+       .set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
+   
+
+//change [15:0] to whatever amount of samples you want to test. however float to iq was tested thouroughly independently. so it works
+  reg [15:0]data[0:15];
+  initial $readmemh("iq_to_float_input.txt", data);
+
+//test packet loop
+  task test_packet;
+      input [15:0] len;
+      input [31:0] sid;
+      reg [3:0] index;
+            
+      begin
+
+	  index <= 0;
+	 
+	 
+	 @(posedge clk);
+	 //send header 
+   	 i_tdata <= {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, (len + 16'd16),sid};
+	 i_tvalid <= 1;
+	 i_tlast <= 0;
+	 
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tdata <= {64'b0};
+	 
+   	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+     //-1 for last bit accounting
+	  repeat (len[15:3] + (len[2]|len[1]|len[0])-1)
+	   begin
+	      i_tdata <= {data[index], data[index+1], data[index+2], data[index+3]}; 
+   	      index <= index+4;
+	      
+	      @(posedge clk);
+	      while (i_tready != 1)
+		@(posedge clk);
+	   end
+   	 i_tlast <= 1'b1;
+	 i_tdata <= {data[index], data[index+1], data[index+2], data[index+3]}; 
+	 
+   
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tvalid <= 0;
+      end
+   endtask // test_packet
+
+//test_destination loop
+
+   task test_destination;
+      input enable;
+      input [15:0] dest_home;
+      
+      
+      begin
+         @(posedge clk);
+            
+         set_data <= {enable,dest_home};
+         set_addr <= 89;
+         set_stb <= 1;
+            
+         @(posedge clk);
+         set_stb <= 0;
+         end
+      endtask
+	
+//main loop	
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 1;
+	
+    i_tdata <= 0;
+   
+	@(negedge reset);
+	@(posedge clk);
+	@(posedge clk);
+
+
+	test_destination(1,16'hFEED);
+	test_packet(2, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(4, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(6, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(8, 32'hDEAD_BEEF);
+
+     end
+
+
+
+
+endmodule
diff --git a/fpga/usrp3/lib/vita/chdr_16sc_to_8sc.v b/fpga/usrp3/lib/vita/chdr_16sc_to_8sc.v
new file mode 100644
index 000000000..d87a9021d
--- /dev/null
+++ b/fpga/usrp3/lib/vita/chdr_16sc_to_8sc.v
@@ -0,0 +1,186 @@
+module chdr_16sc_to_8sc
+  #(parameter BASE=0)
+   (input clk, input reset,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    //input side of device
+    input [63:0] i_tdata,
+    input i_tlast,
+    input i_tvalid,
+    output i_tready,
+    //output side of device
+    output reg [63:0] o_tdata,
+    output o_tlast,
+    output o_tvalid,
+    input o_tready,
+
+    output [31:0] debug
+    );
+   
+   //pipeline register
+   reg [63:0] 	  hold_tdata;
+   //bit assignments
+   wire 	  chdr_has_hdr = 1'b1;
+   wire 	  chdr_has_time = i_tdata[61];
+   wire 	  chdr_has_tlr = 1'b0;
+
+   wire [7:0] 	  rounded_i1;
+   wire [7:0] 	  rounded_q1;
+   wire [7:0] 	  rounded_i0;
+   wire [7:0] 	  rounded_q0;
+
+   wire [7:0] 	  rounded_i2;
+   wire [7:0] 	  rounded_q2;
+   wire [7:0] 	  rounded_i3;
+   wire [7:0] 	  rounded_q3;
+
+   //chdr length calculations
+   wire [15:0] 	  chdr_header_lines8 = chdr_has_time? 16 : 8;
+
+   wire [15:0] 	  chdr_almost_payload_lines8 = ((i_tdata[47:32] - chdr_header_lines8) >> 1);
+
+   wire [15:0] 	  chdr_payload_lines8 = chdr_almost_payload_lines8 + chdr_header_lines8;
+   wire [15:0] 	  my_newhome;
+
+   wire 	  set_sid;
+   
+   setting_reg #(.my_addr(BASE), .width(17)) new_destination
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out({set_sid, my_newhome[15:0]}));
+
+   localparam HEADER        = 2'd0;//IDLE
+   localparam TIME          = 2'd1;
+   localparam ODD           = 2'd2;
+   localparam EVEN          = 2'd3;
+   
+
+   reg [1:0] 		    state;
+   
+
+
+   always @(posedge clk) begin
+      if (reset) begin
+         state <= HEADER;
+	 hold_tdata <= 0;
+	end	
+  else case(state)
+
+             HEADER: begin
+		if (i_tvalid && o_tready) begin
+		   state <= (i_tdata[61])? TIME : ODD;
+		end
+
+             end
+
+             TIME: begin
+		if (i_tvalid && o_tready) begin
+		   state <= (i_tlast)? HEADER: ODD;
+		   hold_tdata <= i_tdata;
+		end
+             end
+
+             ODD: begin
+		if (i_tvalid && o_tready) begin
+		   state <= (i_tlast)? HEADER: EVEN;
+		   hold_tdata <= i_tdata;
+
+		end
+             end
+
+             EVEN: begin
+		if (i_tvalid && o_tready)
+		  state <= (i_tlast) ? HEADER: ODD;
+		  hold_tdata <= i_tdata;
+		
+             end
+	     	     
+	     default: state <= HEADER;
+	     
+	   endcase
+   end
+   
+   //assign 8 bit i and q signals from this line and last
+   
+   //new data processing
+   round #(.bits_in(16),
+	   .bits_out(8))
+   round_i2
+     (.in(i_tdata[63:48]), 
+      .out(rounded_i2[7:0])
+	    );
+
+   round #(.bits_in(16),
+           .bits_out(8))
+   round_q2
+     (.in(i_tdata[47:32]),
+      .out(rounded_q2[7:0])
+      );
+
+   round #(.bits_in(16),
+           .bits_out(8))
+   round_i3
+     (.in(i_tdata[31:16]),
+      .out(rounded_i3[7:0])
+      );
+
+   round #(.bits_in(16),
+           .bits_out(8))
+   round_q3
+     (.in(i_tdata[15:0]),
+      .out(rounded_q3[7:0])
+      );
+
+   // old data processing 
+   round #(.bits_in(16),
+	   .bits_out(8))
+   round_i0(.in(hold_tdata[63:48]), .out(rounded_i0[7:0])
+	    );
+
+   round #(.bits_in(16),
+           .bits_out(8))
+   round_q0
+     (.in(hold_tdata[47:32]),
+      .out(rounded_q0[7:0])
+      );
+
+   round #(.bits_in(16),
+           .bits_out(8))
+   round_i1
+     (.in(hold_tdata[31:16]),
+      .out(rounded_i1[7:0])
+      );
+
+   round #(.bits_in(16),
+           .bits_out(8))
+   round_q1
+     (.in(hold_tdata[15:0]),
+      .out(rounded_q1[7:0])
+      );
+   
+   // main mux
+   always @(*) 
+     case(state)
+       HEADER: o_tdata = {i_tdata[63:48], chdr_payload_lines8,
+			  set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
+       TIME: o_tdata = i_tdata;
+       ODD: o_tdata = {rounded_i2, rounded_q2, rounded_i3, rounded_q3,rounded_i0, rounded_q0, rounded_i1, rounded_q1};
+       EVEN: o_tdata = {rounded_i0, rounded_q0, rounded_i1, rounded_q1,rounded_i2, rounded_q2, rounded_i3, rounded_q3};
+       default : o_tdata = i_tdata;
+     endcase
+   
+   assign o_tvalid = i_tvalid && (state != ODD || i_tlast);
+   assign i_tready = o_tready || (state == ODD && !i_tlast);
+   assign o_tlast  = i_tlast;
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/fpga/usrp3/lib/vita/chdr_16sc_to_8sc_tb.v b/fpga/usrp3/lib/vita/chdr_16sc_to_8sc_tb.v
new file mode 100644
index 000000000..d2838d588
--- /dev/null
+++ b/fpga/usrp3/lib/vita/chdr_16sc_to_8sc_tb.v
@@ -0,0 +1,146 @@
+`timescale 1ns/1ps
+
+module chdr_16sc_to_8sc_tb();
+
+   reg clk = 0;
+   reg reset = 1;
+   //generate clock
+   always #10 clk = ~clk; 
+
+   initial $dumpfile("chdr_16sc_to_8sc_tb.vcd");
+   initial $dumpvars(0,chdr_16sc_to_8sc_tb);
+   
+   //tells when to finish
+   initial
+     begin
+   	#50 reset = 0;
+   	#50000; 
+   	$finish;
+     end
+
+   //setting registers and wire
+   reg [63:0] i_tdata;
+   reg        i_tlast = 0;
+   reg        i_tvalid = 0;
+   wire       i_tready;
+
+   wire [63:0] o_tdata;
+   wire        o_tlast;
+   
+   wire	       o_tvalid;
+   reg 	       o_tready;
+
+   reg [7:0]   set_addr;
+   reg [31:0]  set_data;
+   reg 	       set_stb;
+
+   chdr_16sc_to_8sc #(.BASE(89))dut
+     (.clk(clk), .reset(reset),
+      .set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
+
+   reg [63:0]  data[0:7];
+   initial $readmemh("from16_to_x.hex", data);
+   task test_packet;
+      input [15:0] len;
+      input [31:0] sid;
+      reg [4:0]    index;
+      
+      begin
+
+	 index <= 0;
+	 @(posedge clk) ;
+	 //send header 
+   	 i_tdata <= {4'h2 /* flags */ , 12'h0 /* seqnum */, (len + 16'd16), sid};
+	 i_tvalid <= 1;
+	 i_tlast <= 0;
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tdata <= {64'b0};
+   	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 //-1 for last bit accounting
+	 repeat (len[15:3] + (len[2]|len[1]|len[0])-1)
+	   begin
+	      i_tdata <= {data[index]}; 
+	      index <= index+1;
+	      @(posedge clk);
+	      while (i_tready != 1)
+		@(posedge clk);
+	   end
+   	 i_tlast <= 1'b1;
+	 i_tdata <= {data[index]}; 
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tvalid <= 0;
+      end
+   endtask // test_packet
+
+   task test_destination;
+      input enable;
+      input [15:0] dest_home;
+      
+      
+      begin
+         @(posedge clk);
+         
+         set_data <= {enable,dest_home};
+         set_addr <= 89;
+         set_stb <= 1;
+         
+         @(posedge clk);
+         set_stb <= 0;
+      end
+   endtask
+   
+   
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 1;
+	
+	i_tdata <= 0;
+	
+	@(negedge reset);
+	@(posedge clk);
+	@(posedge clk);
+
+	test_destination(1,16'hFEED);
+	test_packet(2, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(4, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(6, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(8, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(10, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(12, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(14, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(16, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(32, 32'hDEAD_BEEF);
+
+	
+     end
+
+
+   
+
+
+endmodule
diff --git a/fpga/usrp3/lib/vita/chdr_16sc_to_xxxx_chain.v b/fpga/usrp3/lib/vita/chdr_16sc_to_xxxx_chain.v
new file mode 100644
index 000000000..506f7b49f
--- /dev/null
+++ b/fpga/usrp3/lib/vita/chdr_16sc_to_xxxx_chain.v
@@ -0,0 +1,105 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+//selectable conversion chain
+
+module chdr_16sc_to_xxxx_chain
+  #(parameter BASE = 0)
+   (input 	  clk, input reset,
+
+    input 	  set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    input [63:0]  i_tdata,
+    input 	  i_tlast,
+    input 	  i_tvalid,
+    output 	  i_tready,
+
+    output [63:0] o_tdata,
+    output 	  o_tlast,
+    output 	  o_tvalid,
+    input 	  o_tready,
+
+    output [31:0] debug
+    );
+
+   //------------------------------------------------------------------
+   // Demux destination setting register - safe switch for demux
+   //------------------------------------------------------------------
+   wire [1:0] 	  demux_dst;
+   setting_reg #(.my_addr(BASE), .width(2), .at_reset(2'b00)) sr_demux_dst
+     (.clk(clk),.rst(reset),
+      .strobe(set_stb),.addr(set_addr), .in(set_data),
+      .out({demux_dst}),.changed());
+
+   //------------------------------------------------------------------
+   // All FIFO IO lines
+   //------------------------------------------------------------------
+   wire [63:0] 	  i0_tdata; wire i0_tlast, i0_tvalid, i0_tready;
+   wire [63:0] 	  i1_tdata; wire i1_tlast, i1_tvalid, i1_tready;
+   wire [63:0] 	  i2_tdata; wire i2_tlast, i2_tvalid, i2_tready;
+   wire [63:0] 	  i3_tdata; wire i3_tlast, i3_tvalid, i3_tready;
+
+   wire [63:0] 	  o0_tdata; wire o0_tlast, o0_tvalid, o0_tready;
+   wire [63:0] 	  o1_tdata; wire o1_tlast, o1_tvalid, o1_tready;
+   wire [63:0] 	  o2_tdata; wire o2_tlast, o2_tvalid, o2_tready;
+   wire [63:0] 	  o3_tdata; wire o3_tlast, o3_tvalid, o3_tready;
+
+   //------------------------------------------------------------------
+   // Instantiate converters
+   //------------------------------------------------------------------
+   assign {o0_tdata, o0_tlast, o0_tvalid, i0_tready} = {i0_tdata, i0_tlast, i0_tvalid, o0_tready};
+   //assign {o1_tdata, o1_tlast, o1_tvalid, i1_tready} = {i1_tdata, i1_tlast, i1_tvalid, o1_tready};
+   //assign {o2_tdata, o2_tlast, o2_tvalid, i2_tready} = {i2_tdata, i2_tlast, i2_tvalid, o2_tready};
+   //assign {o3_tdata, o3_tlast, o3_tvalid, i3_tready} = {i3_tdata, i3_tlast, i3_tvalid, o3_tready};
+
+   //leave path 0 for pass through
+   
+   chdr_16sc_to_12sc
+     #(.BASE(89)) convert_16sc_to_12sc
+      
+       (.clk(clk), .reset(reset),.set_data(0), .set_stb(0), .set_addr(0),
+       .i_tdata(i1_tdata), .i_tlast(i1_tlast), .i_tvalid(i1_tvalid), .i_tready(i1_tready),
+       .o_tdata(o1_tdata), .o_tlast(o1_tlast), .o_tvalid(o1_tvalid), .o_tready(o1_tready)
+       );
+
+   chdr_16sc_to_32f
+     #(.BASE(89)) convert_16sc_to_32f
+      
+       (.clk(clk), .reset(reset),.set_data(0), .set_stb(0), .set_addr(0),
+       .i_tdata(i2_tdata), .i_tlast(i2_tlast), .i_tvalid(i2_tvalid), .i_tready(i2_tready),
+       .o_tdata(o2_tdata), .o_tlast(o2_tlast), .o_tvalid(o2_tvalid), .o_tready(o2_tready)
+       );
+
+   chdr_16sc_to_8sc #(.BASE(89)) convert_16sc_to_8sc
+     (.clk(clk), .reset(reset),.set_data(0), .set_stb(0), .set_addr(0),
+      .i_tdata(i3_tdata), .i_tlast(i3_tlast), .i_tvalid(i3_tvalid), .i_tready(i3_tready),
+      .o_tdata(o3_tdata), .o_tlast(o3_tlast), .o_tvalid(o3_tvalid), .o_tready(o3_tready)
+      );
+   
+
+   //------------------------------------------------------------------
+   // Ingress and Outgress muxing
+   //------------------------------------------------------------------
+   //assign {o_tdata, o_tlast, o_tvalid, i_tready} = {i_tdata, i_tlast, i_tvalid, o_tready};
+   ///*
+   axi_demux4 #(.ACTIVE_CHAN(4'b1111), .WIDTH(64), .BUFFER(1)) demux_pack_chain
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .header(), .dest(demux_dst),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o0_tdata(i0_tdata), .o0_tlast(i0_tlast), .o0_tvalid(i0_tvalid), .o0_tready(i0_tready),
+      .o1_tdata(i1_tdata), .o1_tlast(i1_tlast), .o1_tvalid(i1_tvalid), .o1_tready(i1_tready),
+      .o2_tdata(i2_tdata), .o2_tlast(i2_tlast), .o2_tvalid(i2_tvalid), .o2_tready(i2_tready),
+      .o3_tdata(i3_tdata), .o3_tlast(i3_tlast), .o3_tvalid(i3_tvalid), .o3_tready(i3_tready));
+
+   axi_mux4 #(.PRIO(1), .WIDTH(64), .BUFFER(1)) mux_pack_chain
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i0_tdata(o0_tdata), .i0_tlast(o0_tlast), .i0_tvalid(o0_tvalid), .i0_tready(o0_tready),
+      .i1_tdata(o1_tdata), .i1_tlast(o1_tlast), .i1_tvalid(o1_tvalid), .i1_tready(o1_tready),
+      .i2_tdata(o2_tdata), .i2_tlast(o2_tlast), .i2_tvalid(o2_tvalid), .i2_tready(o2_tready),
+      .i3_tdata(o3_tdata), .i3_tlast(o3_tlast), .i3_tvalid(o3_tvalid), .i3_tready(o3_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+   //*/
+
+endmodule //chdr_16sc_to_xxxx_chain
diff --git a/fpga/usrp3/lib/vita/chdr_32f_to_16sc.v b/fpga/usrp3/lib/vita/chdr_32f_to_16sc.v
new file mode 100644
index 000000000..681379b1a
--- /dev/null
+++ b/fpga/usrp3/lib/vita/chdr_32f_to_16sc.v
@@ -0,0 +1,142 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+
+module chdr_32f_to_16sc
+  #(parameter BASE=0)
+   (input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    
+    input 	      clk, input reset,
+    input [63:0]      i_tdata,
+    input 	      i_tlast,
+    input 	      i_tvalid,
+    output 	      i_tready,
+  
+    output reg [63:0] o_tdata,
+    output 	      o_tlast,
+    output 	      o_tvalid,
+    input 	      o_tready,
+
+    output [31:0]     debug
+    );
+
+ 
+   wire 	      chdr_has_hdr = 1'b1;
+   wire 	      chdr_has_time = i_tdata[61];
+   wire 	      chdr_has_tlr = 1'b0;
+
+   wire [15:0] 	      s0_imag;
+   wire [15:0] 	      s0_real;
+   wire [15:0] 	      s1_imag;
+   wire [15:0] 	      s1_real;
+   
+
+   reg [15:0] 	      imag0;
+   reg [15:0] 	      real0;
+   wire [15:0] 	      imag1;
+   wire [15:0] 	      real1;
+   
+
+
+
+   
+
+
+   //chdr length calculations
+   wire [15:0] 	      chdr_header_lines = chdr_has_time? 16 : 8;
+
+   wire [15:0] 	      samples = ((i_tdata[47:32] - chdr_header_lines) >> 1);
+
+   wire [15:0] 	      chdr_payload_lines = samples + chdr_header_lines;
+
+
+   wire 	      set_sid;
+   wire [15:0] 	      my_newhome;
+
+   setting_reg #(.my_addr(BASE), .width(17)) new_destination
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out({set_sid, my_newhome[15:0]}));
+
+ 
+
+   localparam HEADER        = 2'd0;//IDLE
+   localparam TIME    = 2'd1;
+   localparam ODD           = 2'd2;
+   localparam EVEN          = 2'd3;
+
+   reg [1:0] 	      state;
+   
+   always @(posedge clk) begin
+      if (reset) begin
+         state <= HEADER;
+
+      end
+      else if (i_tvalid && i_tready) case(state)
+
+	      HEADER: begin
+		if (!i_tlast) state <= (i_tdata[61])? TIME : ODD;
+	      end
+	      
+	      TIME: begin
+		state <= (i_tlast)? HEADER: ODD;
+	      end
+	      
+	      ODD: begin
+		state <= (i_tlast)? HEADER: EVEN;
+	      end
+
+	      EVEN: begin
+		state <= (i_tlast)? HEADER: ODD;
+	      end
+	      
+	      default: state <= HEADER;
+	    endcase
+   end // always @ (posedge clk)
+
+   //hold data after each input transfer
+   reg [63:0] 	       hold_tdata;
+   always @(posedge clk) begin
+    	if (i_tvalid && i_tready) hold_tdata <= i_tdata;
+   end
+
+
+   
+   float_to_iq #(.BITS_IN(32),.BITS_OUT(16))
+   float_to_iq_imag0 (.in(i_tdata[63:32]),.out(s1_imag[15:0]));
+
+   float_to_iq #(.BITS_IN(32),.BITS_OUT(16))
+   float_to_iq_real0 (.in(i_tdata[31:0]),.out(s1_real[15:0]));
+
+   
+   float_to_iq #(.BITS_IN(32),.BITS_OUT(16))
+   float_to_iq_imag1 (.in(hold_tdata[63:32]),.out(s0_imag[15:0]));
+
+   
+   float_to_iq #(.BITS_IN(32),.BITS_OUT(16))
+   float_to_iq_real1 (.in(hold_tdata[31:0]),.out(s0_real[15:0]));
+
+
+   
+
+   always @(*) 
+     case(state)
+       
+       HEADER: o_tdata <= {i_tdata[63:48], chdr_payload_lines,
+			   set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
+       TIME: o_tdata <= i_tdata;
+       ODD: o_tdata <= {s1_imag, s1_real, 32'h0};
+       EVEN: o_tdata <= {s0_imag, s0_real, s1_imag, s1_real};
+       
+      default : o_tdata = i_tdata;
+     endcase
+   
+   assign o_tvalid =  i_tvalid && (state != ODD || i_tlast);  
+   assign i_tready =  o_tready || (state == ODD && !i_tlast); 
+   assign o_tlast  = i_tlast;
+
+endmodule
+
+
+
diff --git a/fpga/usrp3/lib/vita/chdr_32f_to_16sc_tb.v b/fpga/usrp3/lib/vita/chdr_32f_to_16sc_tb.v
new file mode 100644
index 000000000..7ba06bbc6
--- /dev/null
+++ b/fpga/usrp3/lib/vita/chdr_32f_to_16sc_tb.v
@@ -0,0 +1,152 @@
+`timescale 1ns/1ps
+
+module chdr_32f_to_16sc_tb();
+
+   reg clk = 0;
+   reg reset = 1;
+   //generate clock
+   always #10 clk = ~clk; 
+
+   initial $dumpfile("chdr_32f_to_16sc_tb.vcd");
+   initial $dumpvars(0,chdr_32f_to_16sc_tb);
+   
+
+
+   //tells when to finish
+   initial
+     begin
+   	#50 reset = 0;
+   	#50000; 
+   	$finish;
+     end
+
+   //setting registers and wire
+   reg [63:0] i_tdata;
+   reg        i_tlast = 0;
+   reg        i_tvalid = 0;
+   wire       i_tready;
+
+   wire [63:0] o_tdata;
+   wire        o_tlast;
+   
+   wire	       o_tvalid;
+   reg 	       o_tready;
+
+   reg [7:0] set_addr;
+   reg [31:0] set_data;
+   reg set_stb;
+
+   chdr_32f_to_16sc #(.BASE(89))dut
+     (.clk(clk), .reset(reset),
+      .set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
+
+
+  reg [31:0]data[0:7];
+  initial $readmemh("iq_to_float_output.txt", data);
+ 
+   
+  task test_packet;
+      input [15:0] len;
+      input [31:0] sid;
+      reg [4:0] index;
+            
+      begin
+
+	index <= 0;
+	 
+	 
+	 @(posedge clk) ;
+	 //send header 
+   	 i_tdata <= {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, (len + 16'd16), sid};
+	 i_tvalid <= 1;
+	 i_tlast <= 0;
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tdata <= {64'b0};
+	
+   	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+     //-1 for last bit accounting
+	 repeat (len[15:3] + (len[2]|len[1]|len[0]) - 1)
+	   begin
+	      
+	      i_tdata <= {data[index],data[index+1]};
+   	      index <= index+2;
+	      
+	      @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	   end
+	 
+
+	 
+   	 i_tlast <= 1'b1;
+	 i_tdata <= {data[index], data[index+1]};
+
+	 
+
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tvalid <= 0;
+      end
+   endtask // test_packet
+
+ task test_destination;
+      input enable;
+      input [15:0] dest_home;
+      
+      
+      begin
+         @(posedge clk);
+            
+         set_data <= {enable,dest_home};
+         set_addr <= 89;
+         set_stb <= 1;
+            
+         @(posedge clk);
+         set_stb <= 0;
+         end
+      endtask
+	
+	
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 1;
+	
+    	i_tdata <= 0;
+   
+	@(negedge reset);
+	@(posedge clk);
+	@(posedge clk);
+
+
+	test_destination(1,16'hFEED);
+	test_packet(4, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(8, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(16, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(20, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(24, 32'hDEAD_BEEF);
+
+	test_destination(1,16'hFEED);
+	test_packet(28, 32'hDEAD_BEEF);
+	
+     end
+
+ 
+
+
+endmodule
diff --git a/fpga/usrp3/lib/vita/chdr_8sc_to_16sc.hex b/fpga/usrp3/lib/vita/chdr_8sc_to_16sc.hex
new file mode 100644
index 000000000..b7cfd19fd
--- /dev/null
+++ b/fpga/usrp3/lib/vita/chdr_8sc_to_16sc.hex
@@ -0,0 +1,5 @@
+7F805A6B11006792
+88990011CCDD00AA
+
+
+
diff --git a/fpga/usrp3/lib/vita/chdr_8sc_to_16sc.v b/fpga/usrp3/lib/vita/chdr_8sc_to_16sc.v
new file mode 100644
index 000000000..068f599de
--- /dev/null
+++ b/fpga/usrp3/lib/vita/chdr_8sc_to_16sc.v
@@ -0,0 +1,115 @@
+module chdr_8sc_to_16sc
+  #(parameter BASE=0)
+   (input clk, input reset,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    input [63:0] i_tdata,
+    input  i_tlast,
+    input  i_tvalid,
+    output i_tready,
+
+    output reg [63:0] o_tdata,
+    output        o_tlast,
+    output        o_tvalid,
+    input         o_tready,
+
+    output [31:0] debug
+    );
+
+   //bit assignments
+   wire 	  chdr_has_hdr = 1'b1;
+   wire 	  chdr_has_time = i_tdata[61];
+   wire 	  chdr_has_tlr = 1'b0;
+   wire 	  set_sid;
+
+   //chdr length calculations
+   wire [15:0] 	  chdr_header_lines16 = chdr_has_time? 16 : 8;
+
+   wire [15:0] 	  chdr_almost_payload_lines16 = ((i_tdata[47:32] - chdr_header_lines16) << 1);
+
+   wire [15:0] 	  chdr_payload_lines16 = chdr_almost_payload_lines16 + chdr_header_lines16;
+
+   //new destination reg set
+   wire [15:0] 	  my_newhome;
+
+
+   setting_reg #(.my_addr(BASE), .width(17)) new_destination
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out({set_sid, my_newhome[15:0]}));
+
+
+   //state declarations
+
+
+   localparam HEADER        = 2'd0;//IDLE
+   localparam TIME = 2'd1;
+   localparam ODD           = 2'd2;
+   localparam EVEN          = 2'd3;
+
+   reg [1:0] 	   state;
+   reg 		   end_on_odd;
+
+   always @(posedge clk) begin
+      if (reset) begin
+         state <= HEADER;
+	 end_on_odd <= 1'b0;
+      end
+      else case(state)
+
+             HEADER: begin
+		if (i_tvalid && o_tready) begin
+		   state <= (i_tdata[61])? TIME : ODD;
+           	   end_on_odd <= (i_tdata[34:32] > 0) && (i_tdata[34:32] < 5);
+		end
+
+             end
+
+             TIME: begin
+		if (i_tvalid && o_tready) begin
+
+		   state <= (i_tlast)? HEADER: ODD;
+		end
+             end
+
+             ODD: begin
+		if (i_tvalid && o_tready) begin
+		   state <= (i_tlast & end_on_odd) ? HEADER : EVEN;
+		end
+             end
+
+             EVEN: begin
+		if (i_tvalid && o_tready)
+		  state <= (i_tlast) ? HEADER: ODD;
+             end
+	     default: state <= HEADER;
+	     
+	   endcase
+   end
+   
+   always @(*) 
+     case(state)
+	HEADER: o_tdata <= {i_tdata[63:48], chdr_payload_lines16,
+			  set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
+	TIME: o_tdata <= i_tdata;
+       ODD: o_tdata <= {i_tdata[63:56], 8'h0, i_tdata[55:48] , 8'h0, i_tdata[47:40], 8'h0, i_tdata[39:32] , 8'h0};
+       EVEN: o_tdata <= {i_tdata[31:24], 8'h0, i_tdata[23:16], 8'h0, i_tdata[15:8], 8'h0, i_tdata[7:0], 8'h0};
+   
+       
+       default : o_tdata = i_tdata;
+     endcase
+      
+   assign o_tvalid = i_tvalid;
+   assign i_tready = o_tready && ((state != ODD) || (i_tlast & end_on_odd));
+   assign o_tlast  = i_tlast && ((state == EVEN)||((state == ODD) & end_on_odd));
+
+endmodule
+
+
+
+
+
+
+
+
+
+
diff --git a/fpga/usrp3/lib/vita/chdr_8sc_to_16sc_tb.v b/fpga/usrp3/lib/vita/chdr_8sc_to_16sc_tb.v
new file mode 100644
index 000000000..203bfe7a4
--- /dev/null
+++ b/fpga/usrp3/lib/vita/chdr_8sc_to_16sc_tb.v
@@ -0,0 +1,148 @@
+//Purpose: to test 8 to 16 converter
+`timescale 1ns/1ps
+
+module chdr_8sc_to_16sc_tb();
+   
+   reg clk = 0;
+   reg reset = 1;
+   //generate clock
+   always #10 clk = ~clk; 
+
+   initial $dumpfile("chdr_8sc_to_16sc_tb.vcd");
+   initial $dumpvars(0,chdr_8sc_to_16sc_tb);
+   
+   //tells when to finish
+   initial
+     begin
+   	#50 reset = 0;
+   	#50000; 
+   	$finish;
+     end
+
+   //setting registers and wire
+   reg [63:0] i_tdata;
+   reg        i_tlast = 0;
+   reg        i_tvalid = 0;
+   wire       i_tready ;
+   reg [7:0]  set_addr;
+   reg [31:0] set_data;
+   reg 	      set_stb;
+   
+
+   wire [63:0] o_tdata;
+   wire        o_tlast;
+   
+   wire	       o_tvalid;
+   reg 	       o_tready;
+
+   chdr_8sc_to_16sc #(.BASE(89))dut
+     (.clk(clk), .reset(reset),
+      .set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
+   
+   //if you want to feed a bigger input change array sizes here
+
+   reg [63:0]  data[0:7];
+   initial $readmemh("from8_to_x.hex", data);
+
+   //test packet loop
+   task test_packet;
+      input [15:0] len;
+      input [31:0] sid;
+      reg [1:0]    index;
+      
+      begin
+	 index <= 0;
+	 @(posedge clk) ;
+	 //send header 
+   	 i_tdata <= {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, (len + 16'd16),sid};
+	 i_tvalid <= 1;
+	 i_tlast <= 0;
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tdata <= {64'b0};
+   	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 //-1 for last bit accounting
+	 repeat ( len[15:3] + (len[2]|len[1]|len[0]) - 1 )
+	   begin
+	      i_tdata <= {data[index]}; 
+   	      index <= index+1;
+	      @(posedge clk);
+	      while (i_tready != 1)
+		@(posedge clk);
+	   end
+   	 i_tlast <= 1'b1;
+	 i_tdata <= {data[index]}; 
+	 @(posedge clk);
+	 while (i_tready != 1)
+	   @(posedge clk);
+	 i_tvalid <= 0;
+      end
+   endtask // test_packet
+
+   //test_destination loop
+
+   task test_destination;
+      input enable;
+      input [15:0] dest_home;
+      
+      
+      begin
+         @(posedge clk);
+         
+         set_data <= {enable,dest_home};
+         set_addr <= 89;
+         set_stb <= 1;
+         
+         @(posedge clk);
+         set_stb <= 0;
+      end
+   endtask
+
+
+
+   
+   
+   //main loop	
+   initial
+     begin
+	i_tvalid <= 0;
+	o_tready <= 1;
+	
+	i_tdata <= 0;
+	
+	@(negedge reset);
+	@(posedge clk);
+	@(posedge clk);
+
+	/* Uncomment to test without changed sid
+	 test_destination(0,16'hFEED);
+	 test_packet(20, 32'hDEAD_BEEF);
+	 */
+	test_destination(1,16'hFEED);
+	test_packet(2, 32'hDEAD_BEEF);
+	#1000;
+	test_packet(4, 32'hDEAD_BEEF);
+	#1000;
+	test_packet(6, 32'hDEAD_BEEF);
+	#1000;
+	test_packet(8, 32'hDEAD_BEEF);
+	#1000;
+	test_packet(10, 32'hDEAD_BEEF);
+	#1000;
+	test_packet(12, 32'hDEAD_BEEF);
+	#1000;
+	test_packet(14, 32'hDEAD_BEEF);
+	#1000;
+	test_packet(16, 32'hDEAD_BEEF);
+	#1000;
+	
+     end
+
+
+
+endmodule
diff --git a/fpga/usrp3/lib/vita/chdr_xxxx_to_16sc_chain.v b/fpga/usrp3/lib/vita/chdr_xxxx_to_16sc_chain.v
new file mode 100644
index 000000000..dad252d95
--- /dev/null
+++ b/fpga/usrp3/lib/vita/chdr_xxxx_to_16sc_chain.v
@@ -0,0 +1,107 @@
+
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+//selectable conversion chain
+
+module chdr_xxxx_to_16sc_chain
+  #(parameter BASE = 0)
+   (input 	  clk, input reset,
+
+    input 	  set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    input [63:0]  i_tdata,
+    input 	  i_tlast,
+    input 	  i_tvalid,
+    output 	  i_tready,
+
+    output [63:0] o_tdata,
+    output 	  o_tlast,
+    output 	  o_tvalid,
+    input 	  o_tready,
+
+    output [31:0] debug
+    );
+
+   //------------------------------------------------------------------
+   // Demux destination setting register - safe switch for demux
+   //------------------------------------------------------------------
+   wire [1:0] 	  demux_dst;
+   setting_reg #(.my_addr(BASE), .width(2), .at_reset(2'b00)) sr_demux_dst
+     (.clk(clk),.rst(reset),
+      .strobe(set_stb),.addr(set_addr), .in(set_data),
+      .out({demux_dst}),.changed());
+
+   //------------------------------------------------------------------
+   // All FIFO IO lines
+   //------------------------------------------------------------------
+   wire [63:0] 	  i0_tdata; wire i0_tlast, i0_tvalid, i0_tready;
+   wire [63:0] 	  i1_tdata; wire i1_tlast, i1_tvalid, i1_tready;
+   wire [63:0] 	  i2_tdata; wire i2_tlast, i2_tvalid, i2_tready;
+   wire [63:0] 	  i3_tdata; wire i3_tlast, i3_tvalid, i3_tready;
+
+   wire [63:0] 	  o0_tdata; wire o0_tlast, o0_tvalid, o0_tready;
+   wire [63:0] 	  o1_tdata; wire o1_tlast, o1_tvalid, o1_tready;
+   wire [63:0] 	  o2_tdata; wire o2_tlast, o2_tvalid, o2_tready;
+   wire [63:0] 	  o3_tdata; wire o3_tlast, o3_tvalid, o3_tready;
+
+   //------------------------------------------------------------------
+   // Instantiate converters
+   //------------------------------------------------------------------
+   assign {o0_tdata, o0_tlast, o0_tvalid, i0_tready} = {i0_tdata, i0_tlast, i0_tvalid, o0_tready};
+   //assign {o1_tdata, o1_tlast, o1_tvalid, i1_tready} = {i1_tdata, i1_tlast, i1_tvalid, o1_tready};
+   //assign {o2_tdata, o2_tlast, o2_tvalid, i2_tready} = {i2_tdata, i2_tlast, i2_tvalid, o2_tready};
+   //assign {o3_tdata, o3_tlast, o3_tvalid, i3_tready} = {i3_tdata, i3_tlast, i3_tvalid, o3_tready};
+
+   //leave path 0 for pass through
+   
+    chdr_12sc_to_16sc
+    #(.BASE(89)) convert_12sc_to_16sc
+    
+    (.clk(clk), .reset(reset),.set_data(0), .set_stb(0), .set_addr(0),
+    .i_tdata(i1_tdata), .i_tlast(i1_tlast), .i_tvalid(i1_tvalid), .i_tready(i1_tready),
+    .o_tdata(o1_tdata), .o_tlast(o1_tlast), .o_tvalid(o1_tvalid), .o_tready(o1_tready)
+    );
+
+    chdr_32f_to_16sc
+    #(.BASE(89)) convert_32f_to_16sc
+    
+    (.clk(clk), .reset(reset),.set_data(0), .set_stb(0), .set_addr(0),
+    .i_tdata(i2_tdata), .i_tlast(i2_tlast), .i_tvalid(i2_tvalid), .i_tready(i2_tready),
+    .o_tdata(o2_tdata), .o_tlast(o2_tlast), .o_tvalid(o2_tvalid), .o_tready(o2_tready)
+    );
+
+    
+   chdr_8sc_to_16sc #(.BASE(89)) convert_8sc_to_16sc
+     (.clk(clk), .reset(reset),.set_data(0), .set_stb(0), .set_addr(0),
+      .i_tdata(i3_tdata), .i_tlast(i3_tlast), .i_tvalid(i3_tvalid), .i_tready(i3_tready),
+      .o_tdata(o3_tdata), .o_tlast(o3_tlast), .o_tvalid(o3_tvalid), .o_tready(o3_tready)
+      );
+   
+
+   //------------------------------------------------------------------
+   // Ingress and Outgress muxing
+   //------------------------------------------------------------------
+   //assign {o_tdata, o_tlast, o_tvalid, i_tready} = {i_tdata, i_tlast, i_tvalid, o_tready};
+   ///*
+   axi_demux4 #(.ACTIVE_CHAN(4'b1111), .WIDTH(64), .BUFFER(1)) demux_pack_chain
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .header(), .dest(demux_dst),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .o0_tdata(i0_tdata), .o0_tlast(i0_tlast), .o0_tvalid(i0_tvalid), .o0_tready(i0_tready),
+      .o1_tdata(i1_tdata), .o1_tlast(i1_tlast), .o1_tvalid(i1_tvalid), .o1_tready(i1_tready),
+      .o2_tdata(i2_tdata), .o2_tlast(i2_tlast), .o2_tvalid(i2_tvalid), .o2_tready(i2_tready),
+      .o3_tdata(i3_tdata), .o3_tlast(i3_tlast), .o3_tvalid(i3_tvalid), .o3_tready(i3_tready));
+
+   axi_mux4 #(.PRIO(1), .WIDTH(64), .BUFFER(1)) mux_pack_chain
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i0_tdata(o0_tdata), .i0_tlast(o0_tlast), .i0_tvalid(o0_tvalid), .i0_tready(o0_tready),
+      .i1_tdata(o1_tdata), .i1_tlast(o1_tlast), .i1_tvalid(o1_tvalid), .i1_tready(o1_tready),
+      .i2_tdata(o2_tdata), .i2_tlast(o2_tlast), .i2_tvalid(o2_tvalid), .i2_tready(o2_tready),
+      .i3_tdata(o3_tdata), .i3_tlast(o3_tlast), .i3_tvalid(o3_tvalid), .i3_tready(o3_tready),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+   //*/
+
+endmodule //chdr_xxxx_to_16sc_chain
diff --git a/fpga/usrp3/lib/vita/context_packet_gen.v b/fpga/usrp3/lib/vita/context_packet_gen.v
new file mode 100644
index 000000000..2782f66df
--- /dev/null
+++ b/fpga/usrp3/lib/vita/context_packet_gen.v
@@ -0,0 +1,51 @@
+
+module context_packet_gen
+  (input clk, input reset, input clear,
+   input trigger,
+   input [11:0] seqnum,
+   input [31:0] sid,
+   input [63:0] body,
+   input [63:0] vita_time,
+
+   output done,
+   output reg [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+   
+   reg [1:0] 	     cp_state;
+   localparam CP_IDLE = 2'd0;
+   localparam CP_HEAD = 2'd1;
+   localparam CP_TIME = 2'd2;
+   localparam CP_DATA = 2'd3;
+   
+   always @(posedge clk)
+     if(reset|clear)
+       cp_state <= CP_IDLE;
+     else
+       case(cp_state)
+	 CP_IDLE :
+	   if(trigger)
+	     cp_state <= CP_HEAD;
+	 CP_HEAD :
+	   if(o_tready)
+	     cp_state <= CP_TIME;
+	 CP_TIME :
+	   if(o_tready)
+	     cp_state <= CP_DATA;
+	 CP_DATA :
+	   if(o_tready)
+	     cp_state <= CP_IDLE;
+       endcase // case (cp_state)
+
+   assign o_tvalid = (cp_state != CP_IDLE);
+   assign o_tlast = (cp_state == CP_DATA);
+
+   always @*
+     case(cp_state)
+       CP_HEAD : o_tdata <= { 4'hA, seqnum, 16'd24, sid };
+       CP_TIME : o_tdata <= vita_time;
+       CP_DATA : o_tdata <= body;
+       default : o_tdata <= body;
+     endcase // case (cp_state)
+
+   assign done = o_tlast & o_tvalid & o_tready;
+   
+endmodule // context_packet_gen
diff --git a/fpga/usrp3/lib/vita/float_to_iq.v b/fpga/usrp3/lib/vita/float_to_iq.v
new file mode 100644
index 000000000..c7efbc4d3
--- /dev/null
+++ b/fpga/usrp3/lib/vita/float_to_iq.v
@@ -0,0 +1,79 @@
+module float_to_iq
+
+  #(parameter BITS_IN = 32,
+    parameter BITS_OUT = 16
+    )
+
+   (
+
+    input [31:0]   in,
+    output [15:0] out
+    );
+
+   //flags
+
+   wire 		   neg_inf;
+   wire 		   pos_inf;
+   wire 		   denorm;
+   wire tiny_exp;
+   
+
+
+   assign pos_inf = (in[31] == 0 && in[30:23] == 1 && in[22:0] == 0);
+   assign neg_inf = (in[31] == 1 && in[30:23] == 1 && in[22:0] == 0);
+   assign denorm = (in[30:23] == 0);
+   assign tiny_exp = (in[30:23] < 'd111);
+   
+   
+   
+
+
+
+   wire [23:0] 		   implied_bit_fraction;
+   wire [24:0] 		   operation_round;
+   wire [15:0] 		   round_fraction;
+   wire [15:0] 		   shifted_fraction;
+   wire [7:0] 		   shift_val;
+
+   wire [22:0] 		   true_frac;
+   
+
+   
+   
+   assign shift_val = (in[30:23] > 127)? (in[30:23] - 127): (127 - in[30:23]);
+   assign implied_bit_fraction = {1'b1,in[22:0]};
+ 
+   
+   
+   assign operation_round = (implied_bit_fraction + 'h000080);
+   
+
+   //testing for overflow
+   assign round_fraction = (operation_round[24] == 0)?(operation_round[23:8]):(16'h7FFF);
+   //shift the rounded value
+   wire [15:0] shift = round_fraction >> (15 - shift_val);
+   //2's complement the shifted output if the signed bit is 1
+   wire [15:0] final_val = (in[31] == 1)?(~shift + 1'b1):shift;
+   
+   
+
+   assign out = (pos_inf)?{1'b0,15'h7FFF}:(neg_inf)?{1'b1,15'h8000}:(denorm || tiny_exp)? 16'b0: final_val;
+   
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/fpga/usrp3/lib/vita/float_to_iq_tb.v b/fpga/usrp3/lib/vita/float_to_iq_tb.v
new file mode 100644
index 000000000..847547e30
--- /dev/null
+++ b/fpga/usrp3/lib/vita/float_to_iq_tb.v
@@ -0,0 +1,69 @@
+module float_to_iq_tb();
+
+reg clk, reset;
+
+integer x,file;
+reg [31:0]  in;
+wire [15:0] out;
+
+initial clk = 0;
+
+always #10 clk = ~clk;
+
+initial $dumpfile("float_to_iq_tb.vcd");
+initial $dumpvars(0,float_to_iq_tb);
+
+initial 
+   begin
+
+      x <= 0;
+      reset <= 1;
+      in <= 0;
+      file = $fopen("float_to_iq_VER.txt");
+
+      repeat(65536) @(posedge clk);
+      reset <=0;
+      repeat(65536) @(posedge clk)
+         begin
+            in <= data[x];
+            x <= x+1;
+            $fdisplayh(file,out);
+         end
+         $fclose(file);
+         repeat(65536) @(posedge clk);
+         $finish;
+      end
+
+      float_to_iq #(.BITS_IN(32),.BITS_OUT(16))
+      dut 
+         (
+            .in(in), .out(out), .clk(clk), .reset(reset)
+         );
+//input
+         reg    [31:0] data [0:65535];
+         initial $readmemh("iq_to_float_output.txt",data);
+//golden output
+//
+/*
+         reg    [15:0] out_array [0:65535];
+         initial $readmemh("my_data.txt",out_array);
+         reg fail;
+         initial 
+            fail <= 0;
+//compare golden output with your output
+
+         always @(posedge clk) begin
+            if (out != out_array[index]) begin
+               $display("Line %d : Expected %x, got %x",index,out_array[index],out);
+            fail <= 1;
+         end
+      end
+*/
+         end
+
+
+
+
+
+         endmodule
+
diff --git a/fpga/usrp3/lib/vita/from12_to_x.hex b/fpga/usrp3/lib/vita/from12_to_x.hex
new file mode 100644
index 000000000..32d8cc754
--- /dev/null
+++ b/fpga/usrp3/lib/vita/from12_to_x.hex
@@ -0,0 +1,12 @@
+7FF8000001115AB6
+B6EEFEE599A577E9
+F0005AB800CCE7FF
+F0005AB800CCE7FF
+B6EEFEE599A577E9
+7FF8000001115AB6
+B6EEFEE599A577E9
+7FF8000001115AB6
+B6EEFEE599A577E9
+9999ACCAEEEEFFFF
+7878000065568799
+6543111122223333
diff --git a/fpga/usrp3/lib/vita/from16_to_x.hex b/fpga/usrp3/lib/vita/from16_to_x.hex
new file mode 100644
index 000000000..e26b06234
--- /dev/null
+++ b/fpga/usrp3/lib/vita/from16_to_x.hex
@@ -0,0 +1,8 @@
+8000FFFF7FFF1111
+00005A6BEEEE9999
+7AAAEEEE7FFF0000
+5AB890874676BBBB
+EEEE888800007FFF
+DACCCADBEEFFEED0
+FEEDBEEF0000BAAB
+CAB8000BACEDEED0
diff --git a/fpga/usrp3/lib/vita/from8_to_x.hex b/fpga/usrp3/lib/vita/from8_to_x.hex
new file mode 100644
index 000000000..5b4bcb016
--- /dev/null
+++ b/fpga/usrp3/lib/vita/from8_to_x.hex
@@ -0,0 +1,12 @@
+8000FFFF7FFF1111
+00005A6BEEEE9999
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
+7AAAEEEE7FFF0000
diff --git a/fpga/usrp3/lib/vita/generate_bits.cpp b/fpga/usrp3/lib/vita/generate_bits.cpp
new file mode 100644
index 000000000..f5ea60fc1
--- /dev/null
+++ b/fpga/usrp3/lib/vita/generate_bits.cpp
@@ -0,0 +1,87 @@
+//PURPOSE: C test bench for floating point converter IQ_to_FLOAT
+
+#include <cstdlib>
+#include <iostream>
+#include <stdio.h>
+#include <stdlib.h>
+#include <bitset>
+#include <cmath>
+#include "math.h"
+#include <iomanip>
+
+using namespace std;
+//INITIAL TESTING PURPOSES: Use if you want to print individual bits	
+	template <typename T>
+
+	void print_bits(T n) {
+		T mask = 1 << (sizeof(T)*8-1);
+		while (mask) {
+			cout << ((mask & n) ? "1" : "0");
+			mask >>= 1;
+		}
+	cout << endl;
+	}
+
+	int main()	{
+		
+
+		FILE *convFile;
+		FILE *newFile;
+
+
+		
+		
+
+
+		convFile = fopen("iq_to_float_input.txt", "w");
+		newFile =  fopen("iq_to_float_output.txt", "w");
+        //iterate through test cases
+    
+        for (signed int i = -0x8000; i <= 0x7FFF; i++)   {
+
+		float end = float(i*exp2(-15));
+        
+
+		unsigned int n = *(reinterpret_cast<unsigned int*>(&end));
+
+        //IN CASE YOU NEED TO LOOK AT SPECIFIC EXPONENT, FRAC, ETC VALUES
+        //ACTIVATE BY UNCOMMENTING
+        /*
+
+		unsigned int signed_bit = n>>31;
+		
+		unsigned int exp =  ((n>>23) &0xFF);
+		
+		unsigned int frac =  (n &0x7FFFFF);
+
+		cout << "end: " << end << endl;
+		cout << "n: " << hex << n << endl;
+
+
+
+		cout << "signed bit:" << hex << signed_bit << endl;
+		cout << "exp: " << hex <<  exp << endl;
+		cout << "fract: " << hex << frac << endl;
+
+		float f = *(float*)&n;
+		cout << "f" << f << endl;
+*/		
+		
+	//	print_bits<unsigned short>(start);
+	//	print_bits<unsigned int>(n);
+	    unsigned int something = i;
+        something &= 0xFFFF;
+
+		fprintf(convFile, "%x\n",something);
+		fprintf(newFile, "%x\n",n);
+        }
+
+	fclose(convFile);
+	fclose(newFile);
+
+
+	return 0;
+} 
+	 
+
+	
diff --git a/fpga/usrp3/lib/vita/iq_to_float.v b/fpga/usrp3/lib/vita/iq_to_float.v
new file mode 100644
index 000000000..957b350db
--- /dev/null
+++ b/fpga/usrp3/lib/vita/iq_to_float.v
@@ -0,0 +1,92 @@
+module iq_to_float
+  
+  #(parameter BITS_IN =16,
+    parameter BITS_OUT = 32
+    )
+
+   (
+    input [15:0] in,
+    output [31:0] out
+
+    );
+
+   //imaginary
+   
+
+   //2s complement
+   wire [15:0] unsigned_mag;
+   wire [15:0] complement;
+ 
+   //leading bit registers
+   wire [15:0] lead;
+   wire [15:0] reversed_mag;
+   
+   //16-4 encoder
+   wire [3:0] binary_out;
+
+   wire [22:0] fraction;
+   wire [7:0] exponent;
+
+   wire [15:0] binary_in;
+   
+   binary_encoder #(.SIZE(16))
+   encoding
+     (.in(binary_in),.out(binary_out));
+   
+   
+
+   
+  
+   
+   // Detect sign, if negative detected perform 2's complement
+   
+   assign unsigned_mag = (in[15] == 1)?((~in[15:0])+1'b1):in[15:0];
+
+   //detect leading one 
+   
+   assign complement = ((~reversed_mag[BITS_IN-1:0])+1'b1);
+   
+   assign lead = complement & reversed_mag;
+
+   
+   
+   
+   
+   //calculate fraction and exponent using shift value generated
+
+  wire [15:0] pre_frac = unsigned_mag << ((15 - binary_out));
+  assign fraction = {pre_frac[14:0],8'h0};
+  assign exponent = (in == 16'b0)?(8'b0):(binary_out +'d127);
+
+
+      
+   
+   //construct the output
+   assign out = {in[15], exponent, fraction};
+
+   //reverse the signed input
+
+   genvar r;
+   
+   generate
+      for (r = 0; r < 16; r = r+1) begin:bit_reverse
+	assign reversed_mag[r] = unsigned_mag[BITS_IN-r-1];
+      end
+   endgenerate
+
+   //reversed the output of the detect the leading bit procedure
+
+   genvar i;
+    generate 
+	for (i= 0; i < 16; i = i+1) begin: i_rev
+			assign binary_in[i] = lead[BITS_IN-i-1];
+	end
+	endgenerate 
+	
+   
+   
+
+
+endmodule
+
+
diff --git a/fpga/usrp3/lib/vita/iq_to_float_input.txt b/fpga/usrp3/lib/vita/iq_to_float_input.txt
new file mode 100644
index 000000000..c2efee360
--- /dev/null
+++ b/fpga/usrp3/lib/vita/iq_to_float_input.txt
@@ -0,0 +1,65536 @@
+8000
+8001
+8002
+8003
+8004
+8005
+8006
+8007
+8008
+8009
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diff --git a/fpga/usrp3/lib/vita/iq_to_float_output.txt b/fpga/usrp3/lib/vita/iq_to_float_output.txt
new file mode 100644
index 000000000..f1e10da1c
--- /dev/null
+++ b/fpga/usrp3/lib/vita/iq_to_float_output.txt
@@ -0,0 +1,65536 @@
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diff --git a/fpga/usrp3/lib/vita/iq_to_float_tb.v b/fpga/usrp3/lib/vita/iq_to_float_tb.v
new file mode 100644
index 000000000..3ab7ffbd5
--- /dev/null
+++ b/fpga/usrp3/lib/vita/iq_to_float_tb.v
@@ -0,0 +1,61 @@
+module iq_to_float_tb();
+
+
+   reg clk, reset;
+   integer x,file;
+   reg [15:0] in;
+   wire [31:0] out;
+   
+   initial clk = 0;
+   
+   always #10 clk = ~clk;
+
+   initial $dumpfile("iq_to_float_tb.vcd");
+   initial $dumpvars(0,iq_to_float_tb);
+   integer f;
+   initial
+    
+     begin
+	x <= 0;
+	reset <= 1;
+	in <= 0;
+    file = $fopen("iq_to_float_VER.txt");
+	
+	repeat(65536) @(posedge clk);
+	reset <= 0;
+	repeat(65536) @(posedge clk)
+	  begin
+	     in <= data[x];
+	     x  <= x+1;
+         $fdisplayh(file,out);
+	  end
+      $fclose(file);
+	
+	     
+	repeat(65536) @(posedge clk);
+	$finish;
+
+     end
+   
+  
+   
+
+    iq_to_float #(.BITS_IN(16), .BITS_OUT(32))
+   dut
+     (
+      .in(in), .out(out), .clk(clk), .reset(reset)
+      );
+
+   
+
+   reg 	     [15:0] data [0:65535];
+   initial $readmemh("iq_to_float_input.txt",data);
+
+  
+
+	
+	
+   
+   
+endmodule
+
diff --git a/fpga/usrp3/lib/vita/new_rx_control.v b/fpga/usrp3/lib/vita/new_rx_control.v
new file mode 100644
index 000000000..810fa1ce9
--- /dev/null
+++ b/fpga/usrp3/lib/vita/new_rx_control.v
@@ -0,0 +1,242 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+// HALT brings RX to an idle state as quickly as possible if RX is running
+// without running the risk of leaving a packet fragment in downstream FIFO's.
+// HALT also flushes all remaining pending commands in the commmand FIFO.
+// Unlike STOP, HALT doesn't ever create an ERROR packet.
+
+
+module new_rx_control
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    
+    input [63:0] vita_time,
+    
+    // DDC connections
+    output run, output eob,
+    input strobe, input full,
+    input [11:0] seqnum,
+    input [31:0] sid,
+
+    output [63:0] err_tdata, output err_tlast, output err_tvalid, input err_tready,
+    output [31:0] debug
+    );
+
+   wire [31:0] 	  command_i;
+   wire [63:0] 	  time_i;
+   wire 	  store_command;
+
+   wire 	  send_imm, chain, reload, stop;
+   wire [27:0] 	  numlines;
+   wire [63:0] 	  rcvtime;
+
+   wire 	  now, early, late;
+   wire 	  command_valid;
+   reg 		  command_ready;
+   
+   reg 		  chain_sav, reload_sav;
+
+   
+   reg 		  clear_halt;
+   reg 		  halt;
+   wire 	  set_halt;
+    
+   reg [63:0] 	  err_tdata_int;
+   wire 	  err_tlast_int;
+   wire 	  err_tvalid_int;
+   wire 	  err_tready_int;
+   
+
+   setting_reg #(.my_addr(BASE)) sr_cmd
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(command_i),.changed());
+
+   setting_reg #(.my_addr(BASE+1)) sr_time_h
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(time_i[63:32]),.changed());
+   
+   setting_reg #(.my_addr(BASE+2)) sr_time_l
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(time_i[31:0]),.changed(store_command));
+
+   setting_reg #(.my_addr(BASE+3)) sr_rx_halt
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(),.changed(set_halt));
+
+   always @(posedge clk)
+     if (reset | clear | clear_halt)
+       halt <= 1'b0;
+     else
+       halt <= set_halt;
+   
+   
+   axi_fifo_short #(.WIDTH(96)) commandfifo
+     (.clk(clk),.reset(reset),.clear(clear | clear_halt),
+      .i_tdata({command_i,time_i}), .i_tvalid(store_command), .i_tready(),
+      .o_tdata({send_imm,chain,reload,stop,numlines,rcvtime}),
+      .o_tvalid(command_valid), .o_tready(command_ready),
+      .occupied(), .space() );
+
+   time_compare 
+     time_compare (.clk(clk), .reset(reset), .time_now(vita_time), .trigger_time(rcvtime), .now(now), .early(early), .late(late));
+
+   localparam IBS_IDLE         = 0;
+   localparam IBS_RUNNING      = 1;
+   
+   localparam IBS_OVERRUN      = 2;
+   localparam IBS_OVR_TIME     = 3;
+   localparam IBS_OVR_DATA     = 4;
+   
+   localparam IBS_BROKENCHAIN  = 5;
+   localparam IBS_BRK_TIME     = 6;
+   localparam IBS_BRK_DATA     = 7;
+      
+   localparam IBS_LATECMD      = 8;
+   localparam IBS_LATE_TIME    = 9;
+   localparam IBS_LATE_DATA    = 10;
+   
+   localparam IBS_ZEROLEN      = 11;
+   localparam IBS_ZERO_TIME    = 12;
+   localparam IBS_ZERO_DATA    = 13;
+   
+   reg [3:0] 	  ibs_state;
+   reg [27:0] 	  lines_left, repeat_lines;
+
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  ibs_state <= IBS_IDLE;
+	  chain_sav <= 1'b0;
+	  reload_sav <= 1'b0;
+	  clear_halt <= 1'b0;
+       end
+     else
+       case(ibs_state)
+	 IBS_IDLE : begin
+	   clear_halt <= 1'b0; // Incase we got here through a HALT.
+	   if(command_valid)
+	     if(stop)
+	       ibs_state <= IBS_IDLE;//IBS_ZEROLEN;
+	     else if(late & ~send_imm)
+	       ibs_state <= IBS_LATECMD;
+	     else if(now | send_imm)
+	       begin
+		  ibs_state <= IBS_RUNNING;
+		  lines_left <= numlines;
+		  repeat_lines <= numlines;
+		  chain_sav <= chain;
+		  reload_sav <= reload;
+	       end
+	 end // case: IBS_IDLE
+	 
+	 IBS_RUNNING : // need to check for full
+	   if(strobe)
+	     if(full)
+	       ibs_state <= IBS_OVERRUN;
+	     else
+	       if(lines_left == 1)
+		 // Provide Halt mechanism used to bring RX into known IDLE state
+		 // at re-initialization.
+		 if (halt)
+		   begin
+		      ibs_state <= IBS_IDLE;
+		      clear_halt <= 1'b1;
+		   end
+		 else if(chain_sav)
+		    if(command_valid)
+		     begin
+			lines_left <= numlines;
+			repeat_lines <= numlines;
+			chain_sav <= chain;
+			reload_sav <= reload;
+			if(stop)
+			  ibs_state <= IBS_IDLE;
+		     end
+		   else if(reload_sav)
+		     lines_left <= repeat_lines;
+		   else
+		     ibs_state <= IBS_BROKENCHAIN;
+		 else
+		   ibs_state <= IBS_IDLE;
+	       else
+		 lines_left <= lines_left - 28'd1;
+
+
+	IBS_OVERRUN: if(err_tready_int) ibs_state <= IBS_OVR_TIME;
+	IBS_OVR_TIME: if(err_tready_int) ibs_state <= IBS_OVR_DATA;
+	IBS_OVR_DATA: if(err_tready_int) ibs_state <= IBS_IDLE;
+
+	IBS_BROKENCHAIN: if(err_tready_int) ibs_state <= IBS_BRK_TIME;
+	IBS_BRK_TIME: if(err_tready_int) ibs_state <= IBS_BRK_DATA;
+	IBS_BRK_DATA: if(err_tready_int) ibs_state <= IBS_IDLE;
+
+	IBS_LATECMD: if(err_tready_int) ibs_state <= IBS_LATE_TIME;
+	IBS_LATE_TIME: if(err_tready_int) ibs_state <= IBS_LATE_DATA;
+	IBS_LATE_DATA: if(err_tready_int) ibs_state <= IBS_IDLE;
+
+	IBS_ZEROLEN: if(err_tready_int) ibs_state <= IBS_ZERO_TIME;
+	IBS_ZERO_TIME: if(err_tready_int) ibs_state <= IBS_ZERO_DATA;
+	IBS_ZERO_DATA: if(err_tready_int) ibs_state <= IBS_IDLE;
+
+	default: ibs_state <= IBS_IDLE;
+
+       endcase // case (ibs_state)
+
+   always @*
+     case(ibs_state)
+       IBS_IDLE    : command_ready <= stop | late | now | send_imm;
+       IBS_RUNNING : command_ready <= strobe & (lines_left == 1) & chain_sav;
+       default     : command_ready <= 1'b0;
+     endcase // case (ibs_state)
+
+   assign run = (ibs_state == IBS_RUNNING);
+   assign eob = strobe & (lines_left == 1) & ( ~chain_sav | (command_valid & stop) | (~command_valid & ~reload_sav) | halt);
+
+   always @*
+     case (ibs_state)
+       IBS_OVERRUN : err_tdata_int <= { 4'hA, seqnum, 16'd24, sid };
+       IBS_OVR_TIME : err_tdata_int <= vita_time;
+       IBS_OVR_DATA : err_tdata_int <= {32'h8, 32'b0};
+
+       IBS_BROKENCHAIN : err_tdata_int <= { 4'hA, seqnum, 16'd24, sid };
+       IBS_BRK_TIME : err_tdata_int <= vita_time;
+       IBS_BRK_DATA : err_tdata_int <= {32'h4, 32'b0};
+
+       IBS_LATECMD : err_tdata_int <= { 4'hA, seqnum, 16'd24, sid };
+       IBS_LATE_TIME : err_tdata_int <= vita_time;
+       IBS_LATE_DATA : err_tdata_int <= {32'h2, 32'b0};
+
+       IBS_ZEROLEN : err_tdata_int <= { 4'hA, seqnum, 16'd24, sid };
+       IBS_ZERO_TIME : err_tdata_int <= vita_time;
+       IBS_ZERO_DATA : err_tdata_int <= {32'hd, 32'b0};
+
+       default : err_tdata_int <= {32'he, 32'b0};
+     endcase // case (ibs_state)
+   
+   assign err_tlast_int = (ibs_state == IBS_OVR_DATA) 
+     | (ibs_state == IBS_BRK_DATA) 
+       | (ibs_state == IBS_LATE_DATA) 
+	 | (ibs_state == IBS_ZERO_DATA);
+   
+   assign err_tvalid_int = ibs_state >= IBS_OVERRUN;
+
+
+   assign debug[3:0] =  ibs_state;
+   assign debug[7:4] =  {2'b0, command_valid, command_ready};
+   
+   axi_fifo_short #(.WIDTH(65)) output_fifo
+     (
+      .clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({err_tlast_int,err_tdata_int}), .i_tvalid(err_tvalid_int), .i_tready(err_tready_int),
+      .o_tdata({err_tlast,err_tdata}), .o_tvalid(err_tvalid), .o_tready(err_tready),
+      .space(), .occupied()
+      );
+
+
+   
+endmodule // new_rx_control
diff --git a/fpga/usrp3/lib/vita/new_rx_framer.v b/fpga/usrp3/lib/vita/new_rx_framer.v
new file mode 100644
index 000000000..6b031a314
--- /dev/null
+++ b/fpga/usrp3/lib/vita/new_rx_framer.v
@@ -0,0 +1,219 @@
+
+module new_rx_framer
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    
+    input [63:0] vita_time,
+
+    input strobe,
+    input [31:0] sample,
+    input run,
+    input eob,
+    output full,
+    output reg [11:0] seqnum,
+    output [31:0] sid,
+
+    output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
+
+    output [31:0] debug
+    );
+  
+   reg [15:0] 	  len;
+   reg [63:0] 	  hold_time;
+   
+   wire [63:0] 	  dfifo_tdata;
+   wire 	  dfifo_tlast, dfifo_tvalid, dfifo_tready;
+
+   wire [80:0] 	  hfifo_tdata;
+   wire 	  hfifo_tvalid, hfifo_tready;
+
+   wire [63:0] 	  o_tdata_int;
+   wire 	  o_tlast_int, o_tvalid_int, o_tready_int;
+
+   wire [15:0] 	  sample_space;
+
+   wire [15:0] 	  maxlen;
+   reg [31:0] 	  holding;
+
+   // FIXME need to handle case where hdr fifo is full (i.e. too many tiny packets)
+   assign full = (sample_space == 16'd0) | (sample_space == 16'd1) | ~hdr_tready;
+   
+   setting_reg #(.my_addr(BASE), .width(16)) sr_maxlen
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(maxlen),.changed());
+
+   wire sid_changed;
+   setting_reg #(.my_addr(BASE+1), .width(32)) sr_sid
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(sid),.changed(sid_changed));
+
+   reg [1:0] 	  instate;
+   reg [15:0] 	  numsamps;
+   reg 		  nearly_eop;
+   
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  instate <= 0;
+	  numsamps <= 0;
+	  nearly_eop <= 0;
+	  
+       end
+     else if (run)
+       case(instate)
+	 0 :
+	   if(strobe)
+	     if(eop)
+	       begin
+		  instate <= 0;
+		  numsamps <= 0;
+		  nearly_eop <= 0;
+	       end
+	     else
+	       begin
+		  instate <= 1;
+		  numsamps <= numsamps + 1;
+		  nearly_eop <= (numsamps >= (maxlen-2));
+	       end
+	 1 :
+	   if(strobe)
+	     if(eop)
+	       begin
+		  instate <= 0;
+		  numsamps <= 0;
+		  nearly_eop <= 0;
+	       end
+	     else
+	       begin
+		  instate <= 2;
+		  numsamps <= numsamps + 1;
+		  nearly_eop <= (numsamps >= (maxlen-2));
+	       end
+	 2 :
+	   if(strobe)
+	     if(eop)
+	       begin
+		  instate <= 0;
+		  numsamps <= 0;
+		  nearly_eop <= 0;
+	       end
+	     else
+	       begin
+		  instate <= 1;
+		  numsamps <= numsamps + 1;
+		  nearly_eop <= (numsamps >= (maxlen-2));
+	       end
+       endcase // case (instate)
+
+   always @(posedge clk)
+     if(strobe)
+       begin
+	  holding <= sample;
+	  if(instate == 0)
+	    hold_time <= vita_time;
+       end
+
+   always @(posedge clk)
+     if(reset | clear)
+       len <= 5;
+     else
+       if(strobe)
+	 if(sample_tlast)
+	   len <= 5;
+	 else
+	   len <= len + 1;
+   
+   always @(posedge clk)
+     if(reset | clear | sid_changed)
+       seqnum <= 12'd0;
+     else
+       if(o_tlast_int & o_tvalid_int & o_tready_int)
+	 seqnum <= seqnum + 12'd1;
+   
+
+ 
+   wire 	  eop = eob | nearly_eop | full;
+   
+   wire [63:0] 	  sample_tdata = instate == 1 ? {holding, sample} : {sample, 32'h0};
+   wire 	  sample_tlast = eop;
+   wire 	  sample_tvalid = run & strobe & ( (instate == 1) | eop );
+   wire 	  sample_tready;
+   
+   wire [80:0] 	  hdr_tdata = {eob,len[13:0],2'b0,(instate == 0) ? vita_time : hold_time};
+   wire 	  hdr_tvalid = sample_tlast && sample_tvalid && sample_tready;
+   wire 	  hdr_tready;
+
+   
+   axi_fifo #(.WIDTH(65), .SIZE(10)) datafifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({sample_tlast,sample_tdata}), .i_tvalid(sample_tvalid), .i_tready(sample_tready),
+      .o_tdata({dfifo_tlast,dfifo_tdata}), .o_tvalid(dfifo_tvalid), .o_tready(dfifo_tready),
+      .space(sample_space), .occupied());
+   
+   axi_fifo_short #(.WIDTH(81)) hdrfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(hdr_tdata), .i_tvalid(hdr_tvalid), .i_tready(hdr_tready),
+      .o_tdata(hfifo_tdata), .o_tvalid(hfifo_tvalid), .o_tready(hfifo_tready),
+      .space(), .occupied());
+
+   // The output state machine is responsible for forming output packets.
+   // Output packets are formed by combining the entries in the header fifo,
+   // and the samples in the data fifo. A single entry in the header fifo
+   // contains both the compressed header and the 64 bit time stamp.
+
+   reg [1:0] 	  outstate;
+   localparam OUT_IDLE = 2'd0;
+   localparam OUT_HEAD = 2'd1;
+   localparam OUT_TIME = 2'd2;
+   localparam OUT_BODY = 2'd3;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       outstate <= OUT_IDLE;
+     else
+       case(outstate)
+	 OUT_IDLE :
+	   if(hfifo_tvalid) //having a header signals a complete packet
+	     outstate <= OUT_HEAD;
+	 OUT_HEAD :
+	   if(o_tvalid_int && o_tready_int)
+	     outstate <= OUT_TIME;
+	 OUT_TIME :
+	   if(o_tvalid_int && o_tready_int)
+	     outstate <= OUT_BODY;
+	 OUT_BODY :
+	   if(o_tvalid_int && o_tready_int && o_tlast_int)
+	     outstate <= OUT_IDLE;
+       endcase // case (outstate)
+
+   //output data mux feeds from single line of header fifo or the data fifo
+   assign o_tdata_int = (outstate == OUT_HEAD) ? { 3'b001, hfifo_tdata[80], seqnum, hfifo_tdata[79:64], sid} : 
+			(outstate == OUT_TIME) ? hfifo_tdata[63:0] : dfifo_tdata;
+
+   //output the last signal from the data fifo
+   assign o_tlast_int = (outstate == OUT_BODY) ? dfifo_tlast : 1'b0;
+
+   //output valid connected to data valid in non-IDLE states
+   assign o_tvalid_int = (outstate != OUT_IDLE) & dfifo_tvalid;
+
+   //only pop from header fifo on the very last transaction
+   assign hfifo_tready = o_tvalid_int && o_tready_int && o_tlast_int;
+
+   //connect data fifo ready with out ready in the BODY state
+   assign dfifo_tready = (outstate == OUT_BODY) ? o_tready_int : 1'b0;
+   
+   axi_fifo_short #(.WIDTH(65)) output_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata({o_tlast_int, o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
+      .o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .space(), .occupied());
+
+    assign debug[3:0] =  {instate, outstate};
+    assign debug[7:4] =  {1'b0, sample_tlast, sample_tvalid, sample_tready};
+    assign debug[11:8] =  {1'b0, 1'b0, hfifo_tvalid, hfifo_tready};
+    assign debug[15:12] =  {1'b0, dfifo_tlast, dfifo_tvalid, dfifo_tready};
+    assign debug[19:16] =  {1'b0, o_tlast_int, o_tvalid_int, o_tready_int};
+
+endmodule // new_rx_framer
diff --git a/fpga/usrp3/lib/vita/new_rx_tb.v b/fpga/usrp3/lib/vita/new_rx_tb.v
new file mode 100644
index 000000000..5a1529786
--- /dev/null
+++ b/fpga/usrp3/lib/vita/new_rx_tb.v
@@ -0,0 +1,135 @@
+`timescale 1ns/1ps
+
+module new_rx_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("new_rx_tb.vcd");
+   initial $dumpvars(0,new_rx_tb);
+
+   initial
+     begin
+	#1000 reset = 0;
+	#30000;
+	$finish;
+     end
+   
+   reg [7:0]   set_addr;
+   reg [31:0]  set_data;
+   reg 	       set_stb = 1'b0;
+   
+   reg [63:0]  vita_time;
+   reg [31:0]  sample;
+   reg 	       strobe;
+   
+   wire        run, full;
+
+   wire [63:0] err_tdata;
+   wire        err_tlast, err_tvalid, err_tready;
+
+   wire [63:0] o_tdata;
+   wire        o_tlast, o_tvalid;
+   reg 	       o_tready;
+   
+   task send_command;
+      input [63:0] send_time;
+      input 	   send_at;
+      input 	   chain;
+      input 	   reload;
+      input 	   stop;
+      input [31:0] len;
+
+      begin
+	 set_stb <= 1;
+	 set_addr <= 0;
+	 set_data <= { send_at, chain, reload, stop, len };
+	 @(posedge clk);
+	 set_stb <= 1;
+	 set_addr <= 1;
+	 set_data <= send_time[63:32];
+	 @(posedge clk);
+	 set_stb <= 1;
+	 set_addr <= 2;
+	 set_data <= send_time[31:0];
+	 @(posedge clk);
+	 set_stb <= 0;
+	 @(posedge clk);
+      end
+   endtask // send_command
+   
+   initial
+     begin
+	o_tready <= 0;
+	while(reset)
+	  @(posedge clk);
+	set_stb <= 1;   // Set Max Length of Packet
+	set_addr <= 8; 
+	set_data <= 18;
+	@(posedge clk);
+	set_stb <= 1;   // Set SID
+	set_addr <= 9; 
+	set_data <= 32'hF00D_1234;
+	@(posedge clk);
+	
+	send_command(64'h100/*time*/, 1/*send at*/, 0/*chain*/, 0/*reload*/,0/*stop*/,150/*len*/);
+	send_command(64'h200/*time*/, 1/*send at*/, 0/*chain*/, 0/*reload*/,0/*stop*/,4/*len*/);
+	//send_command(64'h100/*time*/, 1/*send at*/, 0/*chain*/, 0/*reload*/,0/*stop*/,5/*len*/);
+
+	#8000;
+	o_tready <= 1;
+     end // initial begin
+   
+   always @(posedge clk)
+     if(reset)
+       vita_time <= 0;
+     else
+       vita_time <= vita_time + 1;
+
+   new_rx_control #(.BASE(0)) rx_control
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .vita_time(vita_time),
+      .run(run), .eob(eob), .strobe(strobe), .full(full),
+      .err_tdata(err_tdata), .err_tlast(err_tlast), .err_tvalid(err_tvalid), .err_tready(err_tready),
+      .debug());
+
+   new_rx_framer #(.BASE(8)) rx_framer
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .vita_time(vita_time),
+      .strobe(strobe), .sample(sample), .run(run), .eob(eob), .full(full),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
+      );
+   
+   always @*
+     strobe <= run;
+
+   /*
+   always @(posedge clk)
+     if(reset)
+       sample <= 0;
+     else if(run)
+       sample <= sample + 1;
+    */
+   always @* sample <= vita_time[31:0];
+   
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       if(o_tlast)
+	 $display("%x\tLAST\n",o_tdata);
+       else
+	 $display("%x",o_tdata);
+
+   assign err_tready = 1;
+   
+   always @(posedge clk)
+     if(err_tvalid & err_tready)
+       if(err_tlast)
+	 $display("\t\t\t\tERR LAST \t%x",err_tdata);
+       else
+	 $display("\t\t\t\tERR\t\t%x",err_tdata);
+   
+endmodule // new_rx_tb
diff --git a/fpga/usrp3/lib/vita/new_tx_control.v b/fpga/usrp3/lib/vita/new_tx_control.v
new file mode 100644
index 000000000..ad1300e26
--- /dev/null
+++ b/fpga/usrp3/lib/vita/new_tx_control.v
@@ -0,0 +1,171 @@
+
+
+module new_tx_control
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    
+    input [63:0] vita_time,
+    output reg ack_or_error,
+    output packet_consumed,
+    output [11:0] seqnum,
+    output reg [63:0] error_code,
+    output [31:0] sid,
+    
+    // From tx_deframer
+    input [175:0] sample_tdata,
+    input sample_tvalid,
+    output sample_tready,
+    
+    // To DSP Core
+    output [31:0] sample,    
+    output run,    input strobe,
+    
+    output [31:0] debug
+    );
+   
+   wire [31:0] 	  sample1 = sample_tdata[31:0];
+   wire [31:0] 	  sample0 = sample_tdata[63:32];
+   wire [63:0] 	  send_time = sample_tdata[127:64];
+   assign         sid = sample_tdata[159:128];
+   assign 	  seqnum = sample_tdata[171:160];
+   wire 	  eop = sample_tdata[172];
+   wire 	  eob = sample_tdata[173];
+   wire 	  send_at = sample_tdata[174];
+   wire 	  odd = sample_tdata[175];
+   
+   wire 	  now, early, late, too_early;
+   wire 	  policy_next_burst, policy_next_packet, policy_wait;
+   wire 	  clear_seqnum;
+   
+   setting_reg #(.my_addr(BASE), .width(3)) sr_error_policy
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({policy_next_burst,policy_next_packet,policy_wait}),.changed(clear_seqnum));
+
+   time_compare 
+     time_compare (.clk(clk), .reset(reset), .time_now(vita_time), .trigger_time(send_time),
+		   .now(now), .early(early), .late(late), .too_early(too_early));
+
+   assign run = (state == ST_SAMP0) | (state == ST_SAMP1);
+   
+   assign sample = (state == ST_SAMP0) ? sample0 : sample1;
+   
+   reg [2:0] 	 state;
+   
+   localparam ST_IDLE  = 0;
+   localparam ST_SAMP0 = 1;
+   localparam ST_SAMP1 = 2;
+   localparam ST_ERROR = 3;
+   localparam ST_WAIT  = 4;
+
+   wire [63:0] CODE_EOB_ACK            = {32'd1,20'd0,seqnum};
+   wire [63:0] CODE_UNDERRUN           = {32'd2,20'd0,seqnum};
+   wire [63:0] CODE_SEQ_ERROR          = {32'd4,20'd0,seqnum};
+   wire [63:0] CODE_TIME_ERROR         = {32'd8,20'd0,seqnum};
+   wire [63:0] CODE_UNDERRUN_MIDPKT    = {32'd16,20'd0,seqnum};
+   wire [63:0] CODE_SEQ_ERROR_MIDBURST = {32'd32,20'd0,seqnum};
+
+   reg [11:0]  expected_seqnum;
+
+   always @(posedge clk)
+     if(reset | clear | clear_seqnum)
+       expected_seqnum <= 12'd0;
+     else
+       if(sample_tvalid & sample_tready & eop)
+	 expected_seqnum <= seqnum + 12'd1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  state <= ST_IDLE;
+	  ack_or_error <= 1'b0;
+	  error_code <= 64'd0;
+       end     
+     else
+       case(state)
+	 ST_IDLE :
+	   begin
+	      ack_or_error <= 1'b0;
+	      if(sample_tvalid)
+		if(~send_at | now)
+		  if(expected_seqnum != seqnum)
+		    begin
+		       state <= ST_ERROR;
+		       ack_or_error <= 1'b1;
+		       error_code <= CODE_SEQ_ERROR;
+		    end
+		  else
+		    state <= ST_SAMP0;
+		else if(late)
+		  begin
+		     state <= ST_ERROR;
+		     ack_or_error <= 1'b1;
+		     error_code <= CODE_TIME_ERROR;
+		  end
+	   end // case: ST_IDLE
+	 ST_SAMP0 :
+	   if(strobe)
+	     if(~sample_tvalid)
+	       begin
+		  state <= ST_ERROR;
+		  ack_or_error <= 1'b1;
+		  error_code <= CODE_UNDERRUN;
+	       end
+	     else if(eop & odd & eob)
+	       begin
+		  state <= ST_IDLE;
+		  ack_or_error <= 1'b1;
+		  error_code <= CODE_EOB_ACK;
+	       end
+	     else if(eop & odd)
+	       state <= ST_SAMP0;
+	     else if(expected_seqnum != seqnum)
+	       begin
+		  state <= ST_ERROR;
+		  ack_or_error <= 1'b1;
+		  error_code <= CODE_SEQ_ERROR_MIDBURST;
+	       end
+	     else
+	       state <= ST_SAMP1;
+	 ST_SAMP1 :
+	   if(strobe)
+	     if(eop & eob)
+	       begin
+		  state <= ST_IDLE;
+		  ack_or_error <= 1'b1;
+		  error_code <= CODE_EOB_ACK;
+	       end
+	     else
+	       state <= ST_SAMP0;
+	 ST_ERROR :
+	   begin
+	      ack_or_error <= 1'b0;
+	      if(sample_tvalid & eop)
+		if(policy_next_packet | (policy_next_burst & eob))
+		  state <= ST_IDLE;
+		else if(policy_wait)
+		  state <= ST_WAIT;
+	   end
+       endcase // case (state)
+
+   assign sample_tready = (state == ST_ERROR) | (strobe & ( (state == ST_SAMP1) | ((state == ST_SAMP0) & eop & odd) ) );
+
+   assign packet_consumed = eop & sample_tvalid & sample_tready;
+   
+   assign debug = {
+		   error_code[15:0], // [28:13]
+		   sample_tvalid, //[12]
+		   now, // [11]
+		   early, // [10]
+		   late, // [9]
+		   too_early, // [8]
+		   strobe,  // [7]
+		   eop, // [6]
+		   eob, // [5]
+		   send_at, // [4]
+		   odd,  // [3]
+		   state //  [2:0]
+		   };
+
+   
+endmodule // new_tx_control
diff --git a/fpga/usrp3/lib/vita/new_tx_control_tb.v b/fpga/usrp3/lib/vita/new_tx_control_tb.v
new file mode 100644
index 000000000..720c8f15e
--- /dev/null
+++ b/fpga/usrp3/lib/vita/new_tx_control_tb.v
@@ -0,0 +1,140 @@
+`timescale 1ns/1ps
+
+module new_tx_control_tb();
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("new_tx_control_tb.vcd");
+   initial $dumpvars(0,new_tx_control_tb);
+
+   initial
+     begin
+	#1000 reset = 0;
+	#30000;
+	$finish;
+     end
+   
+   reg [143:0]  tdata;
+   reg 		tlast;
+   wire 	tlast_int;
+   reg 		tvalid = 1'b0;
+   wire 	tready;
+   
+   reg [7:0] 	set_addr;
+   reg [31:0] 	set_data;
+   reg 		set_stb = 1'b0;
+   
+   reg [31:0] 	samp0, samp1;
+   
+   task send_packet;
+      input [31:0] count;
+      input [31:0] start_data;
+      input [63:0] send_time;
+      input [11:0] pkt_seqnum;
+      input 	   eop;
+      input 	   eob;
+      input 	   send_at;
+      input 	   odd;
+      
+      begin
+	 // Send a packet
+	 samp0 <= start_data;
+	 samp1 <= start_data + 1;
+	 @(posedge clk);
+	 repeat (count-1)
+	   begin
+	      tdata <= { 1'b0,send_at,1'b0,1'b0,1'b0,pkt_seqnum,send_time,samp0,samp1 };
+	      tvalid <= 1;
+	      samp0 <= samp0 + 2;
+	      samp1 <= samp1 + 2;
+	      @(posedge clk);
+	   end
+	 
+	 tdata <= { odd,send_at,1'b0,eob,eop,pkt_seqnum,send_time,samp0,samp1 };
+	 @(posedge clk);
+	 
+	 tvalid <= 0;	 
+	 @(posedge clk);
+      end
+   endtask // send_packet
+   
+   initial
+     begin
+	tvalid <= 1'b0;
+	while(reset)
+	  @(posedge clk);
+	set_addr <= 8'd0;
+	set_data <= 32'd2;
+	set_stb <= 1'b1;
+	@(posedge clk);
+	set_stb <= 1'b0;
+	
+	// Single Packet burst, timed
+	send_packet(3/*count*/,32'hA000_0000/*data*/,64'h100/*time*/,1/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,0/*odd*/);
+
+	// 2 packet burst, timed
+	//send_packet(3/*count*/,32'hB000_0000/*data*/,64'h200/*time*/,2/*SEQ*/,1/*EOP*/,0/*eob*/,1/*timed*/,0/*odd*/);
+	//send_packet(3/*count*/,32'hC000_0000/*data*/,64'h0/*time*/,3/*SEQ*/,1/*EOP*/,1/*eob*/,0/*timed*/,0/*odd*/);
+	
+	// single odd packet
+	//send_packet(3/*count*/,32'h0A00_0000/*data*/,64'h300/*time*/,4/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,1/*odd*/);
+
+	// 2 packet burst, timed, odd
+	//send_packet(3/*count*/,32'hD000_0000/*data*/,64'h400/*time*/,5/*SEQ*/,1/*EOP*/,0/*eob*/,1/*timed*/,1/*odd*/);
+	//send_packet(3/*count*/,32'hE000_0000/*data*/,64'd0/*time*/,6/*SEQ*/,1/*EOP*/,1/*eob*/,0/*timed*/,1/*odd*/);
+
+	// 2 packet burst, untimed, no eob set
+	//send_packet(3/*count*/,32'hF000_0000/*data*/,64'd0/*time*/,7/*SEQ*/,1/*EOP*/,0/*eob*/,0/*timed*/,0/*odd*/);
+	//send_packet(3/*count*/,32'h9000_0000/*data*/,64'd0/*time*/,8/*SEQ*/,1/*EOP*/,0/*eob*/,0/*timed*/,0/*odd*/);
+	
+	// single packet late
+	send_packet(3/*count*/,32'hD000_0000/*data*/,64'h0/*time*/,4/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,1/*odd*/);
+
+     end
+
+   reg [63:0] vita_time;
+   wire [31:0] sample;
+   wire [143:0] sample_tdata;
+   wire 	sample_tready, sample_tvalid;
+   wire [11:0] 	seqnum;
+   wire [31:0] 	error_code;
+   
+   always @(posedge clk)
+     if(reset)
+       vita_time <= 0;
+     else
+       vita_time <= vita_time + 1;
+   
+   axi_fifo #(.WIDTH(144)) axi_fifo_short
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(tdata), .i_tvalid(tvalid), .i_tready(tready),
+      .o_tdata(sample_tdata), .o_tvalid(sample_tvalid), .o_tready(sample_tready));
+
+   new_tx_control new_tx_control
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+
+      .vita_time(vita_time),
+      .error(error), .ack(ack), .packet_consumed(consumed), .seqnum(seqnum), .error_code(error_code),
+
+      .sample_tdata(sample_tdata), .sample_tvalid(sample_tvalid), .sample_tready(sample_tready),
+
+      .sample(sample), .run(run), .strobe(strobe),
+      .debug()
+      );
+
+   assign strobe = run;
+   
+   always @(posedge clk)
+     begin
+	if(strobe)
+	  $display("%x\t%x", vita_time, sample);
+	if(consumed) $display("CONSUMED %x", seqnum);
+	if(ack) $display("ACK %x", seqnum);
+	if(error) $display("ERROR %x\t%x", seqnum,error_code);
+     end
+   
+endmodule // new_tx_control_tb
diff --git a/fpga/usrp3/lib/vita/new_tx_deframer.v b/fpga/usrp3/lib/vita/new_tx_deframer.v
new file mode 100644
index 000000000..76e4cf9e2
--- /dev/null
+++ b/fpga/usrp3/lib/vita/new_tx_deframer.v
@@ -0,0 +1,92 @@
+
+
+module new_tx_deframer
+  (input clk, input reset, input clear,
+   input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
+   output [175:0] sample_tdata, output sample_tvalid, input sample_tready, output [31:0] debug);
+
+   reg 		  odd, send_at, eob;
+   reg [11:0] 	  seqnum;
+   reg [31:0] 	  sid;
+   reg [63:0] 	  send_time;
+      
+   wire [175:0]   fifo_tdata = { odd, send_at, eob, i_tlast, seqnum/*12*/, sid, send_time/*64*/, i_tdata/*64*/ };
+   wire 	  fifo_tvalid, fifo_tready;
+
+   reg [1:0] 	  td_state;
+   localparam TD_HEAD = 0;
+   localparam TD_TIME = 1;
+   localparam TD_BODY = 2;
+   localparam TD_DUMP = 3;
+
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  td_state <= TD_HEAD;
+	  odd <= 1'b0;
+	  send_at <= 1'b0;
+	  eob <= 1'b0;
+	  seqnum <= 12'd0;
+	  sid <= 32'd0;
+	  send_time <= 64'h0;
+       end // if (reset | clear)
+     else
+       case(td_state)
+	 TD_HEAD :
+	   if(i_tvalid)
+	     begin
+		if(~i_tlast)
+		  if(i_tdata[63])
+		    td_state <= TD_DUMP;
+		  else if(i_tdata[61])
+		    td_state <= TD_TIME;
+		  else
+		    td_state <= TD_BODY;
+		odd <= i_tdata[34];
+		send_at <= i_tdata[61];
+		eob <= i_tdata[60];
+		seqnum <= i_tdata[59:48];
+		sid <= i_tdata[31:0];
+		// FIXME record trailer, length, and SID here
+	     end
+	 TD_TIME :
+	   if(i_tvalid)
+	     begin
+		send_time <= i_tdata;
+		if(~i_tlast)
+		  td_state <= TD_BODY;
+		else
+		  td_state <= TD_HEAD;
+	     end
+	 TD_BODY :
+	   if(i_tvalid & fifo_tready)
+	     if(i_tlast)
+	       td_state <= TD_HEAD;
+	 TD_DUMP :
+	   if(i_tvalid)
+	     if(i_tlast)
+	       td_state <= TD_HEAD;
+       endcase // case (td_state)
+
+   assign fifo_tvalid = i_tvalid & (td_state == TD_BODY);
+   assign i_tready = (td_state == TD_BODY) ? fifo_tready : 1'b1;
+   
+   axi_fifo_short #(.WIDTH(176)) ofifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(fifo_tdata), .i_tvalid(fifo_tvalid), .i_tready(fifo_tready),
+      .o_tdata(sample_tdata), .o_tvalid(sample_tvalid), .o_tready(sample_tready),
+      .space(), .occupied());
+
+
+   assign debug = {
+		   sample_tvalid, // [8]
+		   sample_tready, // [7]
+		   i_tvalid,  // [6]
+		   i_tready,  // [5]
+		   td_state,  // [4:3]
+		   odd,       // [2]
+		   send_at,   // [1]
+		   eob        // [0]
+		   };
+   
+endmodule // new_tx_deframer
diff --git a/fpga/usrp3/lib/vita/new_tx_tb.v b/fpga/usrp3/lib/vita/new_tx_tb.v
new file mode 100644
index 000000000..0ee69b3e8
--- /dev/null
+++ b/fpga/usrp3/lib/vita/new_tx_tb.v
@@ -0,0 +1,361 @@
+`timescale 1ns/1ps
+
+module new_tx_tb();
+`ifdef ISIM
+`else //iverilog implied.
+   xlnx_glbl glbl (.GSR(),.GTS());
+`endif
+   
+
+   localparam SR_TX_DSP        = 8;
+   localparam SR_TX_RESPONDER  = 16;
+   localparam SR_TX_CTRL       = 24;
+      
+   localparam SR_CYCLES =    SR_TX_RESPONDER + 0;
+   localparam SR_PACKETS =   SR_TX_RESPONDER + 1;
+   
+   localparam SR_PHASE_INC =    SR_TX_DSP + 0;
+   localparam SR_SCALE_FACTOR = SR_TX_DSP + 1;
+   localparam SR_INTERP =       SR_TX_DSP + 2;
+
+   localparam SR_ERROR_POLICY = SR_TX_CTRL + 0;
+   
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("new_tx_tb.vcd");
+   initial $dumpvars(0,new_tx_tb);
+   wire run, strobe;
+   
+   initial
+     begin
+	#1000 reset = 0;
+	#30000;
+	$finish;
+     end
+   
+   reg [63:0]  tdata;
+   reg 	       tlast;
+   reg 	       tvalid = 1'b0;
+   wire        tready;
+
+   wire [63:0] i_tdata;
+   wire        i_tlast, i_tvalid, i_tready;
+   
+   reg [7:0]   set_addr;
+   reg [31:0]  set_data;
+   reg 	       set_stb = 1'b0;
+   
+   reg [63:0]  vita_time;
+   wire [31:0] sample;
+   
+   wire [175:0] sample_tdata;
+   wire 	sample_tready, sample_tvalid;
+   
+   wire [11:0] 	seqnum;
+   wire [63:0] 	error_code;
+   wire [31:0] 	sid;
+   
+   reg [31:0] 	samp0, samp1;
+
+   reg [11:0] 	seqno;
+
+   wire 	ack_or_error, packet_consumed;
+   
+   
+   //
+   // Task Libaray
+   //
+   task write_setting_bus;
+      input [7:0] address;
+      input [31:0] data;
+
+      begin
+
+	 @(negedge clk);
+	 set_stb = 1'b0;
+	 set_addr = 8'h0;
+	 set_data = 32'h0;
+	 @(negedge clk);
+	 set_stb = 1'b1;
+	 set_addr = address;
+	 set_data = data;
+	 @(negedge clk);
+	 set_stb = 1'b0;
+	 set_addr = 8'h0;
+	 set_data = 32'h0;
+
+      end
+   endtask // write_setting_bus
+
+
+   task send_ramp;
+      input [31:0] burst_count;
+      input [31:0] len;
+      input [31:0] sid;
+
+      reg [31:0] data;
+
+      begin
+	 seqno = 0;
+	 data = 0;
+	 send_packet(len, data, 0, seqno, (burst_count==1), 0, sid);
+	 seqno = seqno + 1;
+	 data <= data + len;
+
+	 if(burst_count > 2)
+	   repeat (burst_count - 2)
+	     begin
+		send_packet(len, data, 64'h0, seqno, 0, 0, sid);
+		seqno = seqno + 1;
+		data <= data + len;
+	     end
+	 if(burst_count > 1)
+	   send_packet(len, data, 64'h0, seqno, 1, 0, sid);
+      end
+   endtask // send_ramp
+
+
+   task send_dc;
+      input [31:0] burst_count;
+      input [31:0] len;
+      input [31:0] sid;
+
+      reg [31:0] data;
+
+      begin
+	 seqno = 0;
+	 data = 1 << 14;
+	 send_packet(len, data, 0, seqno, (burst_count==1), 0, sid);
+	 seqno = seqno + 1;
+
+
+	 if(burst_count > 2)
+	   repeat (burst_count - 2)
+	     begin
+		send_packet(len, data, 64'h0, seqno, 0, 0, sid);
+		seqno = seqno + 1;
+
+	     end
+	 if(burst_count > 1)
+	   send_packet(len, data, 64'h0, seqno, 1, 0, sid);
+      end
+   endtask // send_ramp
+
+   task send_burst;
+      input [31:0] burst_count;
+      input [31:0] len;
+      input [31:0] start_data;
+      input [63:0] send_time;
+      input [11:0] start_seqnum;
+      input 	   send_at;
+      input [31:0] sid;
+      
+      begin
+	 seqno = start_seqnum;
+	 send_packet(len, {seqno,start_data[15:0]}, send_time, seqno, (burst_count==1), send_at, sid);
+	 seqno = seqno + 1;
+	 
+	 if(burst_count > 2)
+	   repeat (burst_count - 2)
+	     begin
+		send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 0, 0, sid);
+		seqno = seqno + 1;
+	     end
+	 if(burst_count > 1)
+	   send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 1, 0, sid);
+      end
+   endtask // send_burst
+
+   task send_burst_with_seqid_error;
+      input [31:0] burst_count;
+      input [31:0] len;
+      input [31:0] start_data;
+      input [63:0] send_time;
+      input [11:0] start_seqnum;
+      input 	   send_at;
+      input [31:0] sid;
+
+     
+      begin
+	 seqno = start_seqnum;
+	 send_packet(len, {seqno,start_data[15:0]}, send_time, seqno, (burst_count==1), send_at, sid);
+	 seqno = seqno + 1;
+	 
+	 if(burst_count > 2)
+	   repeat (burst_count - 2)
+	     begin
+		// Add a SeqID error in the middle of the packet burst
+		if (seqno == (start_seqnum + burst_count/2))
+		  seqno = seqno + 1;
+		send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 0, 0, sid);
+		seqno = seqno + 1;
+	     end
+	 if(burst_count > 1)
+	   send_packet(len, {seqno,start_data[15:0]}, 64'h0, seqno, 1, 0, sid);
+      end
+   endtask // send_burst
+   
+   task send_packet;
+      input [31:0] len;
+      input [31:0] start_data;
+      input [63:0] send_time;
+      input [11:0] pkt_seqnum;
+      input 	   eob;
+      input 	   send_at;
+      input [31:0] sid;
+      
+      begin
+	 // Send a packet
+	 samp0 <= start_data;
+	 samp1 <= start_data + 1;
+	 @(posedge clk);
+
+	 tlast <= 0;
+	 tdata <= { 1'b0, 1'b0 /*trl*/, send_at, eob, pkt_seqnum, len[15:0]+16'd2+send_at+send_at, sid };
+	 tvalid <= 1;
+	 @(posedge clk)
+	 if(send_at)
+	   begin
+	      tdata <= send_time;
+	      @(posedge clk);
+	   end
+
+	 repeat (len[31:1]+len[0]-1)
+	   begin
+	      tdata <= {samp0,samp1};
+	      samp0 <= samp0 + 2;
+	      samp1 <= samp1 + 2;
+	      @(posedge clk);
+	   end
+	 
+	 tdata <= {samp0,samp1};
+	 tlast <= 1'b1;
+	 @(posedge clk);
+	 tvalid <= 0;	 
+	 @(posedge clk);
+      end
+   endtask // send_packet
+
+`ifdef SIM_SCRIPT
+   // Load simulation script from local directory
+`include "simulation_script.v"
+   
+`else
+   initial
+     begin
+	tvalid <= 1'b0;
+	while(reset)
+	  @(posedge clk);
+	write_setting_bus(SR_ERROR_POLICY,32'h4);
+	write_setting_bus(SR_PACKETS,32'h8000_0002);
+
+	write_setting_bus(SR_INTERP,32'h1);
+	
+	send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+	//send_burst(3/*count*/,6/*len*/,32'hB000_0000/*start*/,64'h0/*time*/,12'h004/*seqnum*/,0/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+	//Intra burst seq_id error
+	send_burst_with_seqid_error(8/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+	
+	// Inter burst sequence error
+	send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h015/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+	// Single Packet burst, timed
+	//send_packet(3/*count*/,32'hA000_0000/*data*/,64'h100/*time*/,1/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,0/*odd*/);
+
+	// 2 packet burst, timed
+	//send_packet(3/*count*/,32'hB000_0000/*data*/,64'h200/*time*/,2/*SEQ*/,1/*EOP*/,0/*eob*/,1/*timed*/,0/*odd*/);
+	//send_packet(3/*count*/,32'hC000_0000/*data*/,64'h0/*time*/,3/*SEQ*/,1/*EOP*/,1/*eob*/,0/*timed*/,0/*odd*/);
+	
+	// single odd packet
+	//send_packet(3/*count*/,32'h0A00_0000/*data*/,64'h300/*time*/,4/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,1/*odd*/);
+
+	// 2 packet burst, timed, odd
+	//send_packet(3/*count*/,32'hD000_0000/*data*/,64'h400/*time*/,5/*SEQ*/,1/*EOP*/,0/*eob*/,1/*timed*/,1/*odd*/);
+	//send_packet(3/*count*/,32'hE000_0000/*data*/,64'd0/*time*/,6/*SEQ*/,1/*EOP*/,1/*eob*/,0/*timed*/,1/*odd*/);
+
+	// 2 packet burst, untimed, no eob set
+	//send_packet(3/*count*/,32'hF000_0000/*data*/,64'd0/*time*/,7/*SEQ*/,1/*EOP*/,0/*eob*/,0/*timed*/,0/*odd*/);
+	//send_packet(3/*count*/,32'h9000_0000/*data*/,64'd0/*time*/,8/*SEQ*/,1/*EOP*/,0/*eob*/,0/*timed*/,0/*odd*/);
+	
+	// single packet late
+	//send_packet(3/*count*/,32'hD000_0000/*data*/,64'h0/*time*/,4/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,1/*odd*/);
+
+     end
+`endif // !`ifdef SIM_SCRIPT
+   
+   always @(posedge clk)
+     if(reset)
+       vita_time <= 0;
+     else
+       vita_time <= vita_time + 1;
+   
+   axi_fifo #(.WIDTH(65)) axi_fifo_short
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata({tlast,tdata}), .i_tvalid(tvalid), .i_tready(tready),
+      .o_tdata({i_tlast,i_tdata}), .o_tvalid(i_tvalid), .o_tready(i_tready));
+
+   new_tx_deframer new_tx_deframer
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
+      .sample_tdata(sample_tdata), .sample_tvalid(sample_tvalid), .sample_tready(sample_tready));
+   
+   new_tx_control #(.BASE(SR_TX_CTRL)) new_tx_control
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+
+      .vita_time(vita_time),
+      .ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
+      .seqnum(seqnum), .error_code(error_code), .sid(sid),
+
+      .sample_tdata(sample_tdata), .sample_tvalid(sample_tvalid), .sample_tready(sample_tready),
+
+      .sample(sample), .run(run), .strobe(strobe),
+      .debug()
+      );
+
+   wire [63:0] o_tdata;
+   wire        o_tlast, o_tvalid, o_tready;
+   assign o_tready = 1;
+   
+   tx_responder #(.BASE(SR_TX_RESPONDER)) tx_responder
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
+      .seqnum(seqnum), .error_code(error_code), .sid(sid),
+      .vita_time(vita_time),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+   
+   always @(posedge clk)
+     if(o_tvalid & o_tready)
+       $display("\t\t\t\t\tRESP %x\t%x",o_tdata,o_tlast);
+   
+   always @(posedge clk)
+     if(~reset)
+       begin
+	  if(strobe & run)
+	    $display("%x\t%x", vita_time, sample);
+	  if(strobe & ~run) $display("Spurious Strobe at time %x",vita_time);
+	  if(packet_consumed) $display("CONSUMED %x", seqnum);
+	  if(ack_or_error)
+	    if(error_code[63:32] == 1)
+	      $display("ACK -- SEQNUM %x", error_code[31:0]);
+	    else
+	      $display("ERROR -- SEQNUM %x ERRCODE %x", error_code[31:0],error_code[63:32]);
+       end
+   
+   wire [23:0] tx_fe_i, tx_fe_q;
+
+   duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0), .WIDTH(24)) duc_chain
+     (.clk(clk), .rst(reset), .clr(1'b0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
+      .sample(sample), .run(run), .strobe(strobe),
+      .debug() );
+   
+endmodule // new_tx_tb
diff --git a/fpga/usrp3/lib/vita/trigger_context_pkt.v b/fpga/usrp3/lib/vita/trigger_context_pkt.v
new file mode 100644
index 000000000..b67fa4313
--- /dev/null
+++ b/fpga/usrp3/lib/vita/trigger_context_pkt.v
@@ -0,0 +1,50 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+
+module trigger_context_pkt
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input packet_consumed, output trigger);
+
+   wire [23:0] cycles;
+   wire [15:0] packets;
+   wire [6:0]  dummy1;
+   wire [14:0] dummy2;
+   wire        enable_cycle, enable_consumed;
+   reg [30:0]  cycle_count, packet_count;
+
+   
+   setting_reg #(.my_addr(BASE), .at_reset(0)) sr_cycles
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({enable_cycle,dummy1,cycles}),.changed());
+
+   setting_reg #(.my_addr(BASE+1), .at_reset(0)) sr_packets
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({enable_consumed,dummy2,packets}),.changed());
+
+   always @(posedge clk)
+     if(reset | clear)
+       cycle_count <= 0;
+     else
+       if(trigger)
+	 cycle_count <= 0;
+       else if((enable_cycle & packet_consumed) | (cycle_count != 0))
+	 cycle_count <= cycle_count + 1;
+
+   always @(posedge clk)
+     if(reset | clear)
+       packet_count <= 0;
+     else
+       if(trigger)
+	 packet_count <= 0;
+       else if(packet_consumed & enable_consumed)
+	 packet_count <= packet_count + 1;
+
+   assign trigger = (enable_cycle & (cycle_count >= cycles)) | (enable_consumed & (packet_count >= packets));
+   
+endmodule // trigger_context_pkt
diff --git a/fpga/usrp3/lib/vita/tx_responder.v b/fpga/usrp3/lib/vita/tx_responder.v
new file mode 100644
index 000000000..7b0194620
--- /dev/null
+++ b/fpga/usrp3/lib/vita/tx_responder.v
@@ -0,0 +1,52 @@
+
+module tx_responder
+  #(parameter BASE = 0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    
+    input ack_or_error, input packet_consumed,
+    input [11:0] seqnum,
+    input [63:0] error_code,
+    input [31:0] sid,
+    
+    input [63:0] vita_time,
+    output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
+
+   reg [11:0] 	  seqnum_int;
+
+   always @(posedge clk)
+     if(packet_consumed)
+       seqnum_int <= seqnum;
+   
+   wire 	  trigger_fc, trigger_ctxt;
+   wire [95:0] 	  msg_data = { sid[15:0], sid[31:16], (ack_or_error ? error_code : {32'h0,20'h0,seqnum_int}) };
+   wire [95:0] 	  ctxt_data;
+
+   reg [11:0] 	  reply_seqnum;
+   wire 	  done;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       reply_seqnum <= 12'd0;
+     else if(done)
+       reply_seqnum <= reply_seqnum + 12'd1;
+   
+   trigger_context_pkt #(.BASE(BASE)) trig
+     (.clk(clk), .reset(reset), .clear(clear),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .packet_consumed(packet_consumed), .trigger(trigger_fc));
+
+   axi_fifo_short #(.WIDTH(64+32)) ack_queue
+     (.clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(msg_data), .i_tvalid(ack_or_error | trigger_fc), .i_tready(),
+      .o_tdata(ctxt_data), .o_tvalid(trigger_ctxt), .o_tready(done),
+      .space(), .occupied());
+   
+   context_packet_gen ack_err_gen
+     (.clk(clk), .reset(reset), .clear(clear),
+      .trigger(trigger_ctxt), .seqnum(reply_seqnum), .sid(ctxt_data[95:64]),
+      .body(ctxt_data[63:0]), .vita_time(vita_time),
+      .done(done),
+      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
+      
+endmodule // tx_responder
diff --git a/fpga/usrp3/lib/wishbone/Makefile.srcs b/fpga/usrp3/lib/wishbone/Makefile.srcs
new file mode 100644
index 000000000..6459de834
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/Makefile.srcs
@@ -0,0 +1,19 @@
+#
+# Copyright 2010-2012 Ettus Research LLC
+#
+
+##################################################
+# Wishbone Perifs
+##################################################
+WISHBONE_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/wishbone/, \
+simple_uart_rx.v \
+simple_uart_tx.v \
+simple_uart.v \
+wb_1master.v \
+settings_bus.v \
+settings_readback.v \
+i2c_master_top.v \
+i2c_master_bit_ctrl.v \
+i2c_master_byte_ctrl.v \
+axi_stream_to_wb.v \
+))
diff --git a/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v b/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v
new file mode 100644
index 000000000..a71daf063
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v
@@ -0,0 +1,246 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+
+
+// AXI stream to/from wishbone
+// Input is an axi stream which wites into a BRAM.
+// Output is an axi stream which reads from a BRAM.
+// This RAM can also be accessed from a wishbone interface.
+
+// From the wishbone interface we need to be able to:
+
+// Ask the module if a completed packet is available.
+// Read number of bytes/lines in the BRAM.
+// Release the completed packet.
+
+// Ask the module if an outgoing slot is available.
+// Write number of bytes/lines in the BRAM.
+// Release the completed packet.
+
+module axi_stream_to_wb
+#(
+    parameter AWIDTH = 13, //WB addr width and buffering size in bytes
+    parameter UWIDTH = 4, //stream user width
+    parameter CTRL_ADDR = 0 //ctrl/status register
+)
+(
+    //-- the wishbone interface
+    input clk_i, input rst_i,
+    input we_i, input stb_i, input cyc_i, output reg ack_o,
+    input [AWIDTH-1:0] adr_i, input [31:0] dat_i, output [31:0] dat_o,
+
+    //-- the axi stream interface input
+    input [63:0] rx_tdata,
+    input [3:0] rx_tuser,
+    input rx_tlast,
+    input rx_tvalid,
+    output rx_tready,
+
+    //-- the axi stream interface output
+    output [63:0] tx_tdata,
+    output [3:0] tx_tuser,
+    output tx_tlast,
+    output tx_tvalid,
+    input tx_tready,
+
+    output [31:0] debug_rx,
+    output [31:0] debug_tx
+);
+
+    //drive the ack signal
+    always @(posedge clk_i) begin
+        if (rst_i) ack_o <= 0;
+        else ack_o <= stb_i & ~ack_o;
+    end
+
+    //control registers, status
+    reg [AWIDTH-1:0] tx_bytes, rx_bytes;
+    reg tx_error, rx_error;
+    wire rx_state_flag, tx_state_flag;
+    reg rx_proc_flag, tx_proc_flag;
+
+    //assign status
+    wire [31:0] status;
+    assign status[31] = rx_state_flag;
+    assign status[30] = tx_state_flag;
+    assign status[29] = rx_error;
+    assign status[AWIDTH-1:0] = rx_bytes;
+
+   // Create some piplining to break timing paths.
+   reg 		ctrl_addressed;
+   always @(posedge clk_i)
+     if (rst_i)
+       ctrl_addressed <= 1'b0;
+     else if(adr_i == CTRL_ADDR)
+       ctrl_addressed <= 1'b1;
+     else
+       ctrl_addressed <= 1'b0;
+       
+    //assign control
+    always @(posedge clk_i) begin
+        if (rst_i) begin
+            rx_proc_flag <= 0;
+            tx_proc_flag <= 0;
+            tx_error <= 0;
+            tx_bytes <= 0;
+        end
+        else if (we_i && ack_o && ctrl_addressed) begin
+            rx_proc_flag <= dat_i[31];
+            tx_proc_flag <= dat_i[30];
+            tx_error <= dat_i[29];
+            tx_bytes <= dat_i[AWIDTH-1:0];
+        end
+    end
+
+    //------------------------------------------------------------------
+    //-- block ram interface between wb and input stream
+    //------------------------------------------------------------------
+    reg [AWIDTH-4:0] rx_counter;
+    wire [63:0] rx_bram_data64;
+    ram_2port #(.DWIDTH(64), .AWIDTH(AWIDTH-3)) input_stream_bram
+    (
+        .clka(clk_i), .ena(rx_tready), .wea(rx_tvalid),
+        .addra(rx_counter), .dia(rx_tdata), .doa(),
+        .clkb(clk_i), .enb(stb_i), .web(1'b0),
+        .addrb(adr_i[AWIDTH-1:3]), .dib({64{1'b1}}), .dob(rx_bram_data64)
+    );
+
+    //select the data source, status, or upper/lower 32 from bram
+    assign dat_o = ctrl_addressed ? status : ((!adr_i[2])? rx_bram_data64[63:32]: rx_bram_data64[31:0]);
+
+    //------------------------------------------------------------------
+    //-- block ram interface between wb and output stream
+    //------------------------------------------------------------------
+    reg [AWIDTH-4:0] tx_counter;
+    wire enb_out;
+    wire [63:0] tx_bram_data64;
+    ram_2port #(.DWIDTH(64), .AWIDTH(AWIDTH-3)) output_stream_bram
+    (
+        .clka(clk_i), .ena(enb_out), .wea(1'b0),
+        .addra(tx_counter), .dia({64{1'b1}}), .doa(tx_tdata),
+        .clkb(clk_i), .enb(stb_i), .web(we_i && adr_i[2]),
+        .addrb(adr_i[AWIDTH-1:3]), .dib(tx_bram_data64), .dob()
+    );
+
+    //write 64 bit chunks, so register the lower write
+    reg [31:0] dat_i_reg;
+    always @(posedge clk_i) begin
+        if (we_i && stb_i && !adr_i[2]) dat_i_reg <= dat_i;
+    end
+    assign tx_bram_data64 = {dat_i_reg, dat_i};
+
+    //------------------------------------------------------------------
+    //-- state machine to drive input stream
+    //------------------------------------------------------------------
+    localparam RX_STATE_READY = 0; //waits for proc flag 0
+    localparam RX_STATE_WRITE = 1; //writes stream to bram
+    localparam RX_STATE_RELEASE = 2; //waits for proc to flag 1
+    reg [1:0] rx_state;
+
+    always @(posedge clk_i) begin
+        if (rst_i) begin
+            rx_state <= RX_STATE_READY;
+            rx_counter <= 0;
+            rx_error <= 0;
+            rx_bytes <= 0;
+        end
+        else case (rx_state)
+
+        RX_STATE_READY: begin
+            if (!rx_proc_flag) rx_state <= RX_STATE_WRITE;
+            rx_counter <= 0;
+        end
+
+        RX_STATE_WRITE: begin
+            if (rx_tready && rx_tvalid) begin
+                rx_counter <= rx_counter + 1'b1;
+                if (rx_tlast) begin
+                    rx_state <= RX_STATE_RELEASE;
+                    rx_bytes <= {rx_counter + 1'b1, rx_tuser[2:0]};
+                    rx_error <= rx_tuser[3];
+                end
+            end
+        end
+
+        RX_STATE_RELEASE: begin
+            if (rx_proc_flag) rx_state <= RX_STATE_READY;
+            rx_counter <= 0;
+        end
+
+        default: rx_state <= RX_STATE_READY;
+        endcase //rx_state
+    end
+
+    //flag tells the processor when it can grab some input buffer
+    assign rx_state_flag = (rx_state == RX_STATE_RELEASE);
+
+    //always ready to accept input data in the write state
+    assign rx_tready = (rx_state == RX_STATE_WRITE);
+
+    //------------------------------------------------------------------
+    //-- state machine to drive output stream
+    //------------------------------------------------------------------
+    localparam TX_STATE_READY = 0;  //waits for proc flag 0
+    localparam TX_STATE_WRITE = 1; //writes bram to stream
+    localparam TX_STATE_RELEASE = 2; //waits for proc to flag 1
+    reg [1:0] tx_state;
+
+    always @(posedge clk_i) begin
+        if (rst_i) begin
+            tx_state <= TX_STATE_READY;
+            tx_counter <= 0;
+        end
+        else case (tx_state)
+
+        TX_STATE_READY: begin
+            if (tx_proc_flag) begin
+                tx_state <= TX_STATE_WRITE;
+                tx_counter <= 1;
+            end
+            else tx_counter <= 0;
+        end
+
+        TX_STATE_WRITE: begin
+            if (tx_tready && tx_tvalid) begin
+                tx_counter <= tx_counter + 1'b1;
+                if (tx_tlast) begin
+                    tx_state <= TX_STATE_RELEASE;
+                end
+            end
+        end
+
+        TX_STATE_RELEASE: begin
+            if (!tx_proc_flag) tx_state <= TX_STATE_READY;
+            tx_counter <= 0;
+        end
+
+        default: tx_state <= TX_STATE_READY;
+        endcase //tx_state
+    end
+
+    //flag tells the processor when it can grab available out buffer
+    assign tx_state_flag = (tx_state == TX_STATE_READY);
+
+    //the output user bus assignment (non-zero only at end)
+    assign tx_tuser = (tx_tlast)? {tx_error, tx_bytes[2:0]} : 4'b0;
+
+    //end of frame signal
+    assign tx_tlast = (tx_counter == tx_bytes[AWIDTH-1:3]);
+
+    //output is always valid in state write
+    assign tx_tvalid = (tx_state == TX_STATE_WRITE);
+
+    //enable the read so we can pre-read due to read 1 cycle delay
+    assign enb_out = (tx_state == TX_STATE_WRITE)? (tx_tvalid && tx_tready) : 1'b1;
+
+    assign debug_rx = {
+        rx_state, rx_tlast, rx_tvalid, rx_tready, rx_tuser[2:0], //8
+        rx_proc_flag, rx_state_flag, rx_tdata[21:0] //24
+    };
+    assign debug_tx = {
+        tx_state, tx_tlast, tx_tvalid, tx_tready, tx_tuser[2:0], //8
+        tx_proc_flag, tx_state_flag, tx_tdata[21:0] //24
+    };
+
+endmodule //axi_stream_to_wb
diff --git a/fpga/usrp3/lib/wishbone/i2c_master_bit_ctrl.v b/fpga/usrp3/lib/wishbone/i2c_master_bit_ctrl.v
new file mode 100644
index 000000000..68ec27004
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/i2c_master_bit_ctrl.v
@@ -0,0 +1,538 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE rev.B2 compliant I2C Master bit-controller        ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_master_bit_ctrl.v,v 1.12 2006/09/04 09:08:13 rherveille Exp $
+//
+//  $Date: 2006/09/04 09:08:13 $
+//  $Revision: 1.12 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: i2c_master_bit_ctrl.v,v $
+//               Revision 1.12  2006/09/04 09:08:13  rherveille
+//               fixed short scl high pulse after clock stretch
+//               fixed slave model not returning correct '(n)ack' signal
+//
+//               Revision 1.11  2004/05/07 11:02:26  rherveille
+//               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
+//
+//               Revision 1.10  2003/08/09 07:01:33  rherveille
+//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
+//               Fixed a potential bug in the byte controller's host-acknowledge generation.
+//
+//               Revision 1.9  2003/03/10 14:26:37  rherveille
+//               Fixed cmd_ack generation item (no bug).
+//
+//               Revision 1.8  2003/02/05 00:06:10  rherveille
+//               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
+//
+//               Revision 1.7  2002/12/26 16:05:12  rherveille
+//               Small code simplifications
+//
+//               Revision 1.6  2002/12/26 15:02:32  rherveille
+//               Core is now a Multimaster I2C controller
+//
+//               Revision 1.5  2002/11/30 22:24:40  rherveille
+//               Cleaned up code
+//
+//               Revision 1.4  2002/10/30 18:10:07  rherveille
+//               Fixed some reported minor start/stop generation timing issuess.
+//
+//               Revision 1.3  2002/06/15 07:37:03  rherveille
+//               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
+//
+//               Revision 1.2  2001/11/05 11:59:25  rherveille
+//               Fixed wb_ack_o generation bug.
+//               Fixed bug in the byte_controller statemachine.
+//               Added headers.
+//
+
+//
+/////////////////////////////////////
+// Bit controller section
+/////////////////////////////////////
+//
+// Translate simple commands into SCL/SDA transitions
+// Each command has 5 states, A/B/C/D/idle
+//
+// start:	SCL	~~~~~~~~~~\____
+//	SDA	~~~~~~~~\______
+//		 x | A | B | C | D | i
+//
+// repstart	SCL	____/~~~~\___
+//	SDA	__/~~~\______
+//		 x | A | B | C | D | i
+//
+// stop	SCL	____/~~~~~~~~
+//	SDA	==\____/~~~~~
+//		 x | A | B | C | D | i
+//
+//- write	SCL	____/~~~~\____
+//	SDA	==X=========X=
+//		 x | A | B | C | D | i
+//
+//- read	SCL	____/~~~~\____
+//	SDA	XXXX=====XXXX
+//		 x | A | B | C | D | i
+//
+
+// Timing:     Normal mode      Fast mode
+///////////////////////////////////////////////////////////////////////
+// Fscl        100KHz           400KHz
+// Th_scl      4.0us            0.6us   High period of SCL
+// Tl_scl      4.7us            1.3us   Low period of SCL
+// Tsu:sta     4.7us            0.6us   setup time for a repeated start condition
+// Tsu:sto     4.0us            0.6us   setup time for a stop conditon
+// Tbuf        4.7us            1.3us   Bus free time between a stop and start condition
+//
+
+// synopsys translate_off
+//`include "timescale.v"
+// synopsys translate_on
+
+`include "i2c_master_defines.v"
+
+module i2c_master_bit_ctrl(
+	clk, rst, nReset, 
+	clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,
+	scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen
+	);
+
+	//
+	// inputs & outputs
+	//
+	input clk;
+	input rst;
+	input nReset;
+	input ena;            // core enable signal
+
+	input [15:0] clk_cnt; // clock prescale value
+
+	input  [3:0] cmd;
+	output       cmd_ack; // command complete acknowledge
+	reg cmd_ack;
+	output       busy;    // i2c bus busy
+	reg busy;
+	output       al;      // i2c bus arbitration lost
+	reg al;
+
+	input  din;
+	output dout;
+	reg dout;
+
+	// I2C lines
+	input  scl_i;         // i2c clock line input
+	output scl_o;         // i2c clock line output
+	output scl_oen;       // i2c clock line output enable (active low)
+	reg scl_oen;
+	input  sda_i;         // i2c data line input
+	output sda_o;         // i2c data line output
+	output sda_oen;       // i2c data line output enable (active low)
+	reg sda_oen;
+
+
+	//
+	// variable declarations
+	//
+
+	reg sSCL, sSDA;             // synchronized SCL and SDA inputs
+	reg dscl_oen;               // delayed scl_oen
+	reg sda_chk;                // check SDA output (Multi-master arbitration)
+	reg clk_en;                 // clock generation signals
+	wire slave_wait;
+//	reg [15:0] cnt = clk_cnt;   // clock divider counter (simulation)
+	reg [15:0] cnt;             // clock divider counter (synthesis)
+
+	// state machine variable
+	reg [16:0] c_state; // synopsys enum_state
+
+	//
+	// module body
+	//
+
+	// whenever the slave is not ready it can delay the cycle by pulling SCL low
+	// delay scl_oen
+	always @(posedge clk)
+	  dscl_oen <= #1 scl_oen;
+
+	assign slave_wait = dscl_oen && !sSCL;
+
+
+	// generate clk enable signal
+	always @(posedge clk or negedge nReset)
+	  if(~nReset)
+	    begin
+	        cnt    <= #1 16'h0;
+	        clk_en <= #1 1'b1;
+	    end
+	  else if (rst)
+	    begin
+	        cnt    <= #1 16'h0;
+	        clk_en <= #1 1'b1;
+	    end
+	  else if ( ~|cnt || !ena)
+	    begin
+	        cnt    <= #1 clk_cnt;
+	        clk_en <= #1 1'b1;
+	    end
+	  else if (slave_wait)
+	    begin
+	        cnt    <= #1 cnt;
+	        clk_en <= #1 1'b0;    
+	    end
+	  else
+	    begin
+	        cnt    <= #1 cnt - 16'h1;
+	        clk_en <= #1 1'b0;
+	    end
+
+
+	// generate bus status controller
+	reg dSCL, dSDA;
+	reg sta_condition;
+	reg sto_condition;
+
+	// synchronize SCL and SDA inputs
+	// reduce metastability risc
+	always @(posedge clk or negedge nReset)
+	  if (~nReset)
+	    begin
+	        sSCL <= #1 1'b1;
+	        sSDA <= #1 1'b1;
+
+	        dSCL <= #1 1'b1;
+	        dSDA <= #1 1'b1;
+	    end
+	  else if (rst)
+	    begin
+	        sSCL <= #1 1'b1;
+	        sSDA <= #1 1'b1;
+
+	        dSCL <= #1 1'b1;
+	        dSDA <= #1 1'b1;
+	    end
+	  else
+	    begin
+	        sSCL <= #1 scl_i;
+	        sSDA <= #1 sda_i;
+
+	        dSCL <= #1 sSCL;
+	        dSDA <= #1 sSDA;
+	    end
+
+	// detect start condition => detect falling edge on SDA while SCL is high
+	// detect stop condition => detect rising edge on SDA while SCL is high
+	always @(posedge clk or negedge nReset)
+	  if (~nReset)
+	    begin
+	        sta_condition <= #1 1'b0;
+	        sto_condition <= #1 1'b0;
+	    end
+	  else if (rst)
+	    begin
+	        sta_condition <= #1 1'b0;
+	        sto_condition <= #1 1'b0;
+	    end
+	  else
+	    begin
+	        sta_condition <= #1 ~sSDA &  dSDA & sSCL;
+	        sto_condition <= #1  sSDA & ~dSDA & sSCL;
+	    end
+
+	// generate i2c bus busy signal
+	always @(posedge clk or negedge nReset)
+	  if(!nReset)
+	    busy <= #1 1'b0;
+	  else if (rst)
+	    busy <= #1 1'b0;
+	  else
+	    busy <= #1 (sta_condition | busy) & ~sto_condition;
+
+	// generate arbitration lost signal
+	// aribitration lost when:
+	// 1) master drives SDA high, but the i2c bus is low
+	// 2) stop detected while not requested
+	reg cmd_stop;
+	always @(posedge clk or negedge nReset)
+	  if (~nReset)
+	    cmd_stop <= #1 1'b0;
+	  else if (rst)
+	    cmd_stop <= #1 1'b0;
+	  else if (clk_en)
+	    cmd_stop <= #1 cmd == `I2C_CMD_STOP;
+
+	always @(posedge clk or negedge nReset)
+	  if (~nReset)
+	    al <= #1 1'b0;
+	  else if (rst)
+	    al <= #1 1'b0;
+	  else
+	    al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
+
+
+	// generate dout signal (store SDA on rising edge of SCL)
+	always @(posedge clk)
+	  if(sSCL & ~dSCL)
+	    dout <= #1 sSDA;
+
+	// generate statemachine
+
+	// nxt_state decoder
+	parameter [16:0] idle    = 17'b0_0000_0000_0000_0000;
+	parameter [16:0] start_a = 17'b0_0000_0000_0000_0001;
+	parameter [16:0] start_b = 17'b0_0000_0000_0000_0010;
+	parameter [16:0] start_c = 17'b0_0000_0000_0000_0100;
+	parameter [16:0] start_d = 17'b0_0000_0000_0000_1000;
+	parameter [16:0] start_e = 17'b0_0000_0000_0001_0000;
+	parameter [16:0] stop_a  = 17'b0_0000_0000_0010_0000;
+	parameter [16:0] stop_b  = 17'b0_0000_0000_0100_0000;
+	parameter [16:0] stop_c  = 17'b0_0000_0000_1000_0000;
+	parameter [16:0] stop_d  = 17'b0_0000_0001_0000_0000;
+	parameter [16:0] rd_a    = 17'b0_0000_0010_0000_0000;
+	parameter [16:0] rd_b    = 17'b0_0000_0100_0000_0000;
+	parameter [16:0] rd_c    = 17'b0_0000_1000_0000_0000;
+	parameter [16:0] rd_d    = 17'b0_0001_0000_0000_0000;
+	parameter [16:0] wr_a    = 17'b0_0010_0000_0000_0000;
+	parameter [16:0] wr_b    = 17'b0_0100_0000_0000_0000;
+	parameter [16:0] wr_c    = 17'b0_1000_0000_0000_0000;
+	parameter [16:0] wr_d    = 17'b1_0000_0000_0000_0000;
+
+	always @(posedge clk or negedge nReset)
+	  if (!nReset)
+	    begin
+	        c_state <= #1 idle;
+	        cmd_ack <= #1 1'b0;
+	        scl_oen <= #1 1'b1;
+	        sda_oen <= #1 1'b1;
+	        sda_chk <= #1 1'b0;
+	    end
+	  else if (rst | al)
+	    begin
+	        c_state <= #1 idle;
+	        cmd_ack <= #1 1'b0;
+	        scl_oen <= #1 1'b1;
+	        sda_oen <= #1 1'b1;
+	        sda_chk <= #1 1'b0;
+	    end
+	  else
+	    begin
+	        cmd_ack   <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
+
+	        if (clk_en)
+	          case (c_state) // synopsys full_case parallel_case
+	            // idle state
+	            idle:
+	            begin
+	                case (cmd) // synopsys full_case parallel_case
+	                  `I2C_CMD_START:
+	                     c_state <= #1 start_a;
+
+	                  `I2C_CMD_STOP:
+	                     c_state <= #1 stop_a;
+
+	                  `I2C_CMD_WRITE:
+	                     c_state <= #1 wr_a;
+
+	                  `I2C_CMD_READ:
+	                     c_state <= #1 rd_a;
+
+	                  default:
+	                    c_state <= #1 idle;
+	                endcase
+
+	                scl_oen <= #1 scl_oen; // keep SCL in same state
+	                sda_oen <= #1 sda_oen; // keep SDA in same state
+	                sda_chk <= #1 1'b0;    // don't check SDA output
+	            end
+
+	            // start
+	            start_a:
+	            begin
+	                c_state <= #1 start_b;
+	                scl_oen <= #1 scl_oen; // keep SCL in same state
+	                sda_oen <= #1 1'b1;    // set SDA high
+	                sda_chk <= #1 1'b0;    // don't check SDA output
+	            end
+
+	            start_b:
+	            begin
+	                c_state <= #1 start_c;
+	                scl_oen <= #1 1'b1; // set SCL high
+	                sda_oen <= #1 1'b1; // keep SDA high
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            start_c:
+	            begin
+	                c_state <= #1 start_d;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 1'b0; // set SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            start_d:
+	            begin
+	                c_state <= #1 start_e;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 1'b0; // keep SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            start_e:
+	            begin
+	                c_state <= #1 idle;
+	                cmd_ack <= #1 1'b1;
+	                scl_oen <= #1 1'b0; // set SCL low
+	                sda_oen <= #1 1'b0; // keep SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            // stop
+	            stop_a:
+	            begin
+	                c_state <= #1 stop_b;
+	                scl_oen <= #1 1'b0; // keep SCL low
+	                sda_oen <= #1 1'b0; // set SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            stop_b:
+	            begin
+	                c_state <= #1 stop_c;
+	                scl_oen <= #1 1'b1; // set SCL high
+	                sda_oen <= #1 1'b0; // keep SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            stop_c:
+	            begin
+	                c_state <= #1 stop_d;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 1'b0; // keep SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            stop_d:
+	            begin
+	                c_state <= #1 idle;
+	                cmd_ack <= #1 1'b1;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 1'b1; // set SDA high
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            // read
+	            rd_a:
+	            begin
+	                c_state <= #1 rd_b;
+	                scl_oen <= #1 1'b0; // keep SCL low
+	                sda_oen <= #1 1'b1; // tri-state SDA
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            rd_b:
+	            begin
+	                c_state <= #1 rd_c;
+	                scl_oen <= #1 1'b1; // set SCL high
+	                sda_oen <= #1 1'b1; // keep SDA tri-stated
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            rd_c:
+	            begin
+	                c_state <= #1 rd_d;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 1'b1; // keep SDA tri-stated
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            rd_d:
+	            begin
+	                c_state <= #1 idle;
+	                cmd_ack <= #1 1'b1;
+	                scl_oen <= #1 1'b0; // set SCL low
+	                sda_oen <= #1 1'b1; // keep SDA tri-stated
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            // write
+	            wr_a:
+	            begin
+	                c_state <= #1 wr_b;
+	                scl_oen <= #1 1'b0; // keep SCL low
+	                sda_oen <= #1 din;  // set SDA
+	                sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
+	            end
+
+	            wr_b:
+	            begin
+	                c_state <= #1 wr_c;
+	                scl_oen <= #1 1'b1; // set SCL high
+	                sda_oen <= #1 din;  // keep SDA
+	                sda_chk <= #1 1'b1; // check SDA output
+	            end
+
+	            wr_c:
+	            begin
+	                c_state <= #1 wr_d;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 din;
+	                sda_chk <= #1 1'b1; // check SDA output
+	            end
+
+	            wr_d:
+	            begin
+	                c_state <= #1 idle;
+	                cmd_ack <= #1 1'b1;
+	                scl_oen <= #1 1'b0; // set SCL low
+	                sda_oen <= #1 din;
+	                sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
+	            end
+
+	          endcase
+	    end
+
+
+	// assign scl and sda output (always gnd)
+	assign scl_o = 1'b0;
+	assign sda_o = 1'b0;
+
+endmodule
diff --git a/fpga/usrp3/lib/wishbone/i2c_master_byte_ctrl.v b/fpga/usrp3/lib/wishbone/i2c_master_byte_ctrl.v
new file mode 100644
index 000000000..784b58188
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/i2c_master_byte_ctrl.v
@@ -0,0 +1,344 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE rev.B2 compliant I2C Master byte-controller       ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $
+//
+//  $Date: 2004/02/18 11:40:46 $
+//  $Revision: 1.7 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: i2c_master_byte_ctrl.v,v $
+//               Revision 1.7  2004/02/18 11:40:46  rherveille
+//               Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
+//
+//               Revision 1.6  2003/08/09 07:01:33  rherveille
+//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
+//               Fixed a potential bug in the byte controller's host-acknowledge generation.
+//
+//               Revision 1.5  2002/12/26 15:02:32  rherveille
+//               Core is now a Multimaster I2C controller
+//
+//               Revision 1.4  2002/11/30 22:24:40  rherveille
+//               Cleaned up code
+//
+//               Revision 1.3  2001/11/05 11:59:25  rherveille
+//               Fixed wb_ack_o generation bug.
+//               Fixed bug in the byte_controller statemachine.
+//               Added headers.
+//
+
+// synopsys translate_off
+//`include "timescale.v"
+// synopsys translate_on
+
+`include "i2c_master_defines.v"
+
+module i2c_master_byte_ctrl (
+	clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
+	cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
+
+	//
+	// inputs & outputs
+	//
+	input clk;     // master clock
+	input rst;     // synchronous active high reset
+	input nReset;  // asynchronous active low reset
+	input ena;     // core enable signal
+
+	input [15:0] clk_cnt; // 4x SCL
+
+	// control inputs
+	input       start;
+	input       stop;
+	input       read;
+	input       write;
+	input       ack_in;
+	input [7:0] din;
+
+	// status outputs
+	output       cmd_ack;
+	reg cmd_ack;
+	output       ack_out;
+	reg ack_out;
+	output       i2c_busy;
+	output       i2c_al;
+	output [7:0] dout;
+
+	// I2C signals
+	input  scl_i;
+	output scl_o;
+	output scl_oen;
+	input  sda_i;
+	output sda_o;
+	output sda_oen;
+
+
+	//
+	// Variable declarations
+	//
+
+	// statemachine
+	parameter [4:0] ST_IDLE  = 5'b0_0000;
+	parameter [4:0] ST_START = 5'b0_0001;
+	parameter [4:0] ST_READ  = 5'b0_0010;
+	parameter [4:0] ST_WRITE = 5'b0_0100;
+	parameter [4:0] ST_ACK   = 5'b0_1000;
+	parameter [4:0] ST_STOP  = 5'b1_0000;
+
+	// signals for bit_controller
+	reg  [3:0] core_cmd;
+	reg        core_txd;
+	wire       core_ack, core_rxd;
+
+	// signals for shift register
+	reg [7:0] sr; //8bit shift register
+	reg       shift, ld;
+
+	// signals for state machine
+	wire       go;
+	reg  [2:0] dcnt;
+	wire       cnt_done;
+
+	//
+	// Module body
+	//
+
+	// hookup bit_controller
+	i2c_master_bit_ctrl bit_controller (
+		.clk     ( clk      ),
+		.rst     ( rst      ),
+		.nReset  ( nReset   ),
+		.ena     ( ena      ),
+		.clk_cnt ( clk_cnt  ),
+		.cmd     ( core_cmd ),
+		.cmd_ack ( core_ack ),
+		.busy    ( i2c_busy ),
+		.al      ( i2c_al   ),
+		.din     ( core_txd ),
+		.dout    ( core_rxd ),
+		.scl_i   ( scl_i    ),
+		.scl_o   ( scl_o    ),
+		.scl_oen ( scl_oen  ),
+		.sda_i   ( sda_i    ),
+		.sda_o   ( sda_o    ),
+		.sda_oen ( sda_oen  )
+	);
+
+	// generate go-signal
+	assign go = (read | write | stop) & ~cmd_ack;
+
+	// assign dout output to shift-register
+	assign dout = sr;
+
+	// generate shift register
+	always @(posedge clk or negedge nReset)
+	  if (!nReset)
+	    sr <= #1 8'h0;
+	  else if (rst)
+	    sr <= #1 8'h0;
+	  else if (ld)
+	    sr <= #1 din;
+	  else if (shift)
+	    sr <= #1 {sr[6:0], core_rxd};
+
+	// generate counter
+	always @(posedge clk or negedge nReset)
+	  if (!nReset)
+	    dcnt <= #1 3'h0;
+	  else if (rst)
+	    dcnt <= #1 3'h0;
+	  else if (ld)
+	    dcnt <= #1 3'h7;
+	  else if (shift)
+	    dcnt <= #1 dcnt - 3'h1;
+
+	assign cnt_done = ~(|dcnt);
+
+	//
+	// state machine
+	//
+	reg [4:0] c_state; // synopsis enum_state
+
+	always @(posedge clk or negedge nReset)
+	  if (!nReset)
+	    begin
+	        core_cmd <= #1 `I2C_CMD_NOP;
+	        core_txd <= #1 1'b0;
+	        shift    <= #1 1'b0;
+	        ld       <= #1 1'b0;
+	        cmd_ack  <= #1 1'b0;
+	        c_state  <= #1 ST_IDLE;
+	        ack_out  <= #1 1'b0;
+	    end
+	  else if (rst | i2c_al)
+	   begin
+	       core_cmd <= #1 `I2C_CMD_NOP;
+	       core_txd <= #1 1'b0;
+	       shift    <= #1 1'b0;
+	       ld       <= #1 1'b0;
+	       cmd_ack  <= #1 1'b0;
+	       c_state  <= #1 ST_IDLE;
+	       ack_out  <= #1 1'b0;
+	   end
+	else
+	  begin
+	      // initially reset all signals
+	      core_txd <= #1 sr[7];
+	      shift    <= #1 1'b0;
+	      ld       <= #1 1'b0;
+	      cmd_ack  <= #1 1'b0;
+
+	      case (c_state) // synopsys full_case parallel_case
+	        ST_IDLE:
+	          if (go)
+	            begin
+	                if (start)
+	                  begin
+	                      c_state  <= #1 ST_START;
+	                      core_cmd <= #1 `I2C_CMD_START;
+	                  end
+	                else if (read)
+	                  begin
+	                      c_state  <= #1 ST_READ;
+	                      core_cmd <= #1 `I2C_CMD_READ;
+	                  end
+	                else if (write)
+	                  begin
+	                      c_state  <= #1 ST_WRITE;
+	                      core_cmd <= #1 `I2C_CMD_WRITE;
+	                  end
+	                else // stop
+	                  begin
+	                      c_state  <= #1 ST_STOP;
+	                      core_cmd <= #1 `I2C_CMD_STOP;
+	                  end
+
+	                ld <= #1 1'b1;
+	            end
+
+	        ST_START:
+	          if (core_ack)
+	            begin
+	                if (read)
+	                  begin
+	                      c_state  <= #1 ST_READ;
+	                      core_cmd <= #1 `I2C_CMD_READ;
+	                  end
+	                else
+	                  begin
+	                      c_state  <= #1 ST_WRITE;
+	                      core_cmd <= #1 `I2C_CMD_WRITE;
+	                  end
+
+	                ld <= #1 1'b1;
+	            end
+
+	        ST_WRITE:
+	          if (core_ack)
+	            if (cnt_done)
+	              begin
+	                  c_state  <= #1 ST_ACK;
+	                  core_cmd <= #1 `I2C_CMD_READ;
+	              end
+	            else
+	              begin
+	                  c_state  <= #1 ST_WRITE;       // stay in same state
+	                  core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
+	                  shift    <= #1 1'b1;
+	              end
+
+	        ST_READ:
+	          if (core_ack)
+	            begin
+	                if (cnt_done)
+	                  begin
+	                      c_state  <= #1 ST_ACK;
+	                      core_cmd <= #1 `I2C_CMD_WRITE;
+	                  end
+	                else
+	                  begin
+	                      c_state  <= #1 ST_READ;       // stay in same state
+	                      core_cmd <= #1 `I2C_CMD_READ; // read next bit
+	                  end
+
+	                shift    <= #1 1'b1;
+	                core_txd <= #1 ack_in;
+	            end
+
+	        ST_ACK:
+	          if (core_ack)
+	            begin
+	               if (stop)
+	                 begin
+	                     c_state  <= #1 ST_STOP;
+	                     core_cmd <= #1 `I2C_CMD_STOP;
+	                 end
+	               else
+	                 begin
+	                     c_state  <= #1 ST_IDLE;
+	                     core_cmd <= #1 `I2C_CMD_NOP;
+
+	                     // generate command acknowledge signal
+	                     cmd_ack  <= #1 1'b1;
+	                 end
+
+	                 // assign ack_out output to bit_controller_rxd (contains last received bit)
+	                 ack_out <= #1 core_rxd;
+
+	                 core_txd <= #1 1'b1;
+	             end
+	           else
+	             core_txd <= #1 ack_in;
+
+	        ST_STOP:
+	          if (core_ack)
+	            begin
+	                c_state  <= #1 ST_IDLE;
+	                core_cmd <= #1 `I2C_CMD_NOP;
+
+	                // generate command acknowledge signal
+	                cmd_ack  <= #1 1'b1;
+	            end
+
+	      endcase
+	  end
+endmodule
diff --git a/fpga/usrp3/lib/wishbone/i2c_master_defines.v b/fpga/usrp3/lib/wishbone/i2c_master_defines.v
new file mode 100644
index 000000000..ee3b694fa
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/i2c_master_defines.v
@@ -0,0 +1,64 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE rev.B2 compliant I2C Master controller defines    ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_master_defines.v,v 1.3 2001/11/05 11:59:25 rherveille Exp $
+//
+//  $Date: 2001/11/05 11:59:25 $
+//  $Revision: 1.3 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: i2c_master_defines.v,v $
+//               Revision 1.3  2001/11/05 11:59:25  rherveille
+//               Fixed wb_ack_o generation bug.
+//               Fixed bug in the byte_controller statemachine.
+//               Added headers.
+//
+
+
+// I2C registers wishbone addresses
+
+// bitcontroller states
+`define I2C_CMD_NOP   4'b0000
+`define I2C_CMD_START 4'b0001
+`define I2C_CMD_STOP  4'b0010
+`define I2C_CMD_WRITE 4'b0100
+`define I2C_CMD_READ  4'b1000
diff --git a/fpga/usrp3/lib/wishbone/i2c_master_top.v b/fpga/usrp3/lib/wishbone/i2c_master_top.v
new file mode 100644
index 000000000..be1fcfe55
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/i2c_master_top.v
@@ -0,0 +1,301 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE revB.2 compliant I2C Master controller Top-level  ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_master_top.v,v 1.11 2005/02/27 09:26:24 rherveille Exp $
+//
+//  $Date: 2005/02/27 09:26:24 $
+//  $Revision: 1.11 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: i2c_master_top.v,v $
+//               Revision 1.11  2005/02/27 09:26:24  rherveille
+//               Fixed register overwrite issue.
+//               Removed full_case pragma, replaced it by a default statement.
+//
+//               Revision 1.10  2003/09/01 10:34:38  rherveille
+//               Fix a blocking vs. non-blocking error in the wb_dat output mux.
+//
+//               Revision 1.9  2003/01/09 16:44:45  rherveille
+//               Fixed a bug in the Command Register declaration.
+//
+//               Revision 1.8  2002/12/26 16:05:12  rherveille
+//               Small code simplifications
+//
+//               Revision 1.7  2002/12/26 15:02:32  rherveille
+//               Core is now a Multimaster I2C controller
+//
+//               Revision 1.6  2002/11/30 22:24:40  rherveille
+//               Cleaned up code
+//
+//               Revision 1.5  2001/11/10 10:52:55  rherveille
+//               Changed PRER reset value from 0x0000 to 0xffff, conform specs.
+//
+
+// synopsys translate_off
+//`include "timescale.v"
+// synopsys translate_on
+
+`include "i2c_master_defines.v"
+
+module i2c_master_top(
+	wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
+	wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
+	scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
+
+	// parameters
+	parameter ARST_LVL = 1'b0; // asynchronous reset level
+
+	//
+	// inputs & outputs
+	//
+
+	// wishbone signals
+	input        wb_clk_i;     // master clock input
+	input        wb_rst_i;     // synchronous active high reset
+	input        arst_i;       // asynchronous reset
+	input  [2:0] wb_adr_i;     // lower address bits
+	input  [7:0] wb_dat_i;     // databus input
+	output [7:0] wb_dat_o;     // databus output
+	input        wb_we_i;      // write enable input
+	input        wb_stb_i;     // stobe/core select signal
+	input        wb_cyc_i;     // valid bus cycle input
+	output       wb_ack_o;     // bus cycle acknowledge output
+	output       wb_inta_o;    // interrupt request signal output
+
+	reg [7:0] wb_dat_o;
+	reg wb_ack_o;
+	reg wb_inta_o;
+
+	// I2C signals
+	// i2c clock line
+	input  scl_pad_i;       // SCL-line input
+	output scl_pad_o;       // SCL-line output (always 1'b0)
+	output scl_padoen_o;    // SCL-line output enable (active low)
+
+	// i2c data line
+	input  sda_pad_i;       // SDA-line input
+	output sda_pad_o;       // SDA-line output (always 1'b0)
+	output sda_padoen_o;    // SDA-line output enable (active low)
+
+
+	//
+	// variable declarations
+	//
+
+	// registers
+	reg  [15:0] prer; // clock prescale register
+	reg  [ 7:0] ctr;  // control register
+	reg  [ 7:0] txr;  // transmit register
+	wire [ 7:0] rxr;  // receive register
+	reg  [ 7:0] cr;   // command register
+	wire [ 7:0] sr;   // status register
+
+	// done signal: command completed, clear command register
+	wire done;
+
+	// core enable signal
+	wire core_en;
+	wire ien;
+
+	// status register signals
+	wire irxack;
+	reg  rxack;       // received aknowledge from slave
+	reg  tip;         // transfer in progress
+	reg  irq_flag;    // interrupt pending flag
+	wire i2c_busy;    // bus busy (start signal detected)
+	wire i2c_al;      // i2c bus arbitration lost
+	reg  al;          // status register arbitration lost bit
+
+	//
+	// module body
+	//
+
+	// generate internal reset
+	wire rst_i = arst_i ^ ARST_LVL;
+
+	// generate wishbone signals
+	wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
+
+	// generate acknowledge output signal
+	always @(posedge wb_clk_i)
+	  wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
+
+	// assign DAT_O
+	always @(posedge wb_clk_i)
+	begin
+	  case (wb_adr_i) // synopsis parallel_case
+	    3'b000: wb_dat_o <= #1 prer[ 7:0];
+	    3'b001: wb_dat_o <= #1 prer[15:8];
+	    3'b010: wb_dat_o <= #1 ctr;
+	    3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
+	    3'b100: wb_dat_o <= #1 sr;  // write is command register (cr)
+	    3'b101: wb_dat_o <= #1 txr;
+	    3'b110: wb_dat_o <= #1 cr;
+	    3'b111: wb_dat_o <= #1 0;   // reserved
+	  endcase
+	end
+
+	// generate registers
+	always @(posedge wb_clk_i or negedge rst_i)
+	  if (!rst_i)
+	    begin
+	        prer <= #1 16'hffff;
+	        ctr  <= #1  8'h0;
+	        txr  <= #1  8'h0;
+	    end
+	  else if (wb_rst_i)
+	    begin
+	        prer <= #1 16'hffff;
+	        ctr  <= #1  8'h0;
+	        txr  <= #1  8'h0;
+	    end
+	  else
+	    if (wb_wacc)
+	      case (wb_adr_i) // synopsis parallel_case
+	         3'b000 : prer [ 7:0] <= #1 wb_dat_i;
+	         3'b001 : prer [15:8] <= #1 wb_dat_i;
+	         3'b010 : ctr         <= #1 wb_dat_i;
+	         3'b011 : txr         <= #1 wb_dat_i;
+	         default: ;
+	      endcase
+
+	// generate command register (special case)
+	always @(posedge wb_clk_i or negedge rst_i)
+	  if (~rst_i)
+	    cr <= #1 8'h0;
+	  else if (wb_rst_i)
+	    cr <= #1 8'h0;
+	  else if (wb_wacc)
+	    begin
+	        if (core_en & (wb_adr_i == 3'b100) )
+	          cr <= #1 wb_dat_i;
+	    end
+	  else
+	    begin
+	        if (done | i2c_al)
+	          cr[7:4] <= #1 4'h0;           // clear command bits when done
+	                                        // or when aribitration lost
+	        cr[2:1] <= #1 2'b0;             // reserved bits
+	        cr[0]   <= #1 2'b0;             // clear IRQ_ACK bit
+	    end
+
+
+	// decode command register
+	wire sta  = cr[7];
+	wire sto  = cr[6];
+	wire rd   = cr[5];
+	wire wr   = cr[4];
+	wire ack  = cr[3];
+	wire iack = cr[0];
+
+	// decode control register
+	assign core_en = ctr[7];
+	assign ien = ctr[6];
+
+	// hookup byte controller block
+	i2c_master_byte_ctrl byte_controller (
+		.clk      ( wb_clk_i     ),
+		.rst      ( wb_rst_i     ),
+		.nReset   ( rst_i        ),
+		.ena      ( core_en      ),
+		.clk_cnt  ( prer         ),
+		.start    ( sta          ),
+		.stop     ( sto          ),
+		.read     ( rd           ),
+		.write    ( wr           ),
+		.ack_in   ( ack          ),
+		.din      ( txr          ),
+		.cmd_ack  ( done         ),
+		.ack_out  ( irxack       ),
+		.dout     ( rxr          ),
+		.i2c_busy ( i2c_busy     ),
+		.i2c_al   ( i2c_al       ),
+		.scl_i    ( scl_pad_i    ),
+		.scl_o    ( scl_pad_o    ),
+		.scl_oen  ( scl_padoen_o ),
+		.sda_i    ( sda_pad_i    ),
+		.sda_o    ( sda_pad_o    ),
+		.sda_oen  ( sda_padoen_o )
+	);
+
+	// status register block + interrupt request signal
+	always @(posedge wb_clk_i or negedge rst_i)
+	  if (!rst_i)
+	    begin
+	        al       <= #1 1'b0;
+	        rxack    <= #1 1'b0;
+	        tip      <= #1 1'b0;
+	        irq_flag <= #1 1'b0;
+	    end
+	  else if (wb_rst_i)
+	    begin
+	        al       <= #1 1'b0;
+	        rxack    <= #1 1'b0;
+	        tip      <= #1 1'b0;
+	        irq_flag <= #1 1'b0;
+	    end
+	  else
+	    begin
+	        al       <= #1 i2c_al | (al & ~sta);
+	        rxack    <= #1 irxack;
+	        tip      <= #1 (rd | wr);
+	        irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
+	    end
+
+	// generate interrupt request signals
+	always @(posedge wb_clk_i or negedge rst_i)
+	  if (!rst_i)
+	    wb_inta_o <= #1 1'b0;
+	  else if (wb_rst_i)
+	    wb_inta_o <= #1 1'b0;
+	  else
+	    wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
+
+	// assign status register bits
+	assign sr[7]   = rxack;
+	assign sr[6]   = i2c_busy;
+	assign sr[5]   = al;
+	assign sr[4:2] = 3'h0; // reserved
+	assign sr[1]   = tip;
+	assign sr[0]   = irq_flag;
+
+endmodule
diff --git a/fpga/usrp3/lib/wishbone/settings_bus.v b/fpga/usrp3/lib/wishbone/settings_bus.v
new file mode 100644
index 000000000..39f148916
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/settings_bus.v
@@ -0,0 +1,46 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+
+
+
+// Grab settings off the wishbone bus, send them out to our simpler bus on the fast clock
+
+module settings_bus
+  #(parameter AWIDTH=16, parameter DWIDTH=32, parameter SWIDTH=8)
+    (input wb_clk, 
+     input wb_rst, 
+     input [AWIDTH-1:0] wb_adr_i,
+     input [DWIDTH-1:0] wb_dat_i,
+     input wb_stb_i,
+     input wb_we_i,
+     output reg wb_ack_o,
+     output reg strobe,
+     output reg [SWIDTH-1:0] addr,
+     output reg [31:0] data);
+
+   reg 	    stb_int, stb_int_d1;
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       begin
+	  strobe <= 1'b0;
+	  addr <= {SWIDTH{1'b0}};
+	  data <= 32'd0;
+       end
+     else if(wb_we_i & wb_stb_i & ~wb_ack_o)
+       begin
+	  strobe <= 1'b1;
+	  addr <= wb_adr_i[SWIDTH+1:2];
+	  data <= wb_dat_i;
+       end
+     else
+       strobe <= 1'b0;
+
+   always @(posedge wb_clk)
+     if(wb_rst)
+       wb_ack_o <= 0;
+     else
+       wb_ack_o <= wb_stb_i & ~wb_ack_o;
+
+endmodule // settings_bus
diff --git a/fpga/usrp3/lib/wishbone/settings_readback.v b/fpga/usrp3/lib/wishbone/settings_readback.v
new file mode 100644
index 000000000..745571717
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/settings_readback.v
@@ -0,0 +1,40 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+
+
+//
+// Use this module in conjunction with settings_bus.v to add stateful reads
+// to the settings bis. This enables you to do things like have registers reset atomicly
+// as they are read. It also pipelines the address path to ease timing.
+//
+
+module settings_readback
+  #(parameter AWIDTH=16, parameter DWIDTH=32, parameter RB_ADDRW=2)
+   (
+    input wb_clk, 
+    input wb_rst, 
+    input [AWIDTH-1:0] wb_adr_i,
+    input wb_stb_i,
+    input wb_we_i,
+    input [DWIDTH-1:0] rb_data,
+    output reg [RB_ADDRW-1:0] rb_addr,
+    output [DWIDTH-1:0] wb_dat_o,
+    output reg rb_rd_stb
+    );
+
+   always @(posedge wb_clk)
+     if (wb_stb_i && ~wb_we_i) begin
+	rb_addr <= wb_adr_i[RB_ADDRW+1:2];
+	rb_rd_stb <= 1'b1;	
+     end else begin
+	rb_rd_stb <= 1'b0;	
+     end
+   
+   assign wb_dat_o = rb_data;
+
+   
+
+endmodule // settings_readback
+
+  
\ No newline at end of file
diff --git a/fpga/usrp3/lib/wishbone/simple_uart.v b/fpga/usrp3/lib/wishbone/simple_uart.v
new file mode 100644
index 000000000..51dc23f16
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/simple_uart.v
@@ -0,0 +1,65 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+
+
+
+module simple_uart
+  #(parameter CLKDIV_DEFAULT = 16'd0)
+   (input clk_i, input rst_i,
+    input we_i, input stb_i, input cyc_i, output reg ack_o,
+    input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+    output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
+   
+   // Register Map
+   localparam SUART_CLKDIV = 0;
+   localparam SUART_TXLEVEL = 1;
+   localparam SUART_RXLEVEL = 2;
+   localparam SUART_TXCHAR = 3;
+   localparam SUART_RXCHAR = 4;
+   
+   wire       wb_acc = cyc_i & stb_i;            // WISHBONE access
+   wire       wb_wr  = wb_acc & we_i;            // WISHBONE write access
+   
+   reg [15:0] clkdiv;
+   wire [7:0] rx_char;
+   wire       tx_fifo_full, rx_fifo_empty;
+   wire [5:0] tx_fifo_level, rx_fifo_level;
+   
+   always @(posedge clk_i)
+     if (rst_i)
+       ack_o <= 1'b0;
+     else
+       ack_o <= wb_acc & ~ack_o;
+   
+   always @(posedge clk_i)
+     if (rst_i)
+       clkdiv <= CLKDIV_DEFAULT;
+     else if (wb_wr)
+       case(adr_i)
+	 SUART_CLKDIV : clkdiv <= dat_i[15:0];
+       endcase // case(adr_i)
+   
+   always @(posedge clk_i)
+     case (adr_i)
+       SUART_TXLEVEL : dat_o <= tx_fifo_level;
+       SUART_RXLEVEL : dat_o <= rx_fifo_level;
+       SUART_RXCHAR : dat_o <= rx_char;
+     endcase // case(adr_i)
+   
+   simple_uart_tx simple_uart_tx
+     (.clk(clk_i),.rst(rst_i),
+      .fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i == SUART_TXCHAR)),
+      .fifo_level(tx_fifo_level),.fifo_full(tx_fifo_full),
+      .clkdiv(clkdiv),.baudclk(baud_o),.tx(tx_o));
+   
+   simple_uart_rx simple_uart_rx
+     (.clk(clk_i),.rst(rst_i),
+      .fifo_out(rx_char),.fifo_read(ack_o && ~wb_wr && (adr_i == SUART_RXCHAR)),
+      .fifo_level(rx_fifo_level),.fifo_empty(rx_fifo_empty),
+      .clkdiv(clkdiv),.rx(rx_i));
+   
+   assign     tx_int_o = ~tx_fifo_full;
+   assign     rx_int_o = ~rx_fifo_empty;
+   
+endmodule // simple_uart
diff --git a/fpga/usrp3/lib/wishbone/simple_uart_rx.v b/fpga/usrp3/lib/wishbone/simple_uart_rx.v
new file mode 100644
index 000000000..7790a0a87
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/simple_uart_rx.v
@@ -0,0 +1,71 @@
+//
+// Copyright 2011-2013 Ettus Research LLC
+//
+
+
+
+
+module simple_uart_rx
+    #(parameter SIZE=0)
+    (input clk, input rst, 
+     output [7:0] fifo_out, input fifo_read, output [5:0] fifo_level, output fifo_empty, 
+     input [15:0] clkdiv, input rx);
+
+   reg 		  rx_d1, rx_d2;
+   always @(posedge clk)
+     if(rst)
+       {rx_d2,rx_d1} <= 0;
+     else
+       {rx_d2,rx_d1} <= {rx_d1,rx};
+   
+   reg [15:0] 	  baud_ctr;
+   reg [3:0] 	  bit_ctr;
+   reg [7:0] 	  sr;
+
+   wire 	  neg_trans = rx_d2 & ~rx_d1;
+   wire 	  shift_now = baud_ctr == (clkdiv>>1);
+   wire 	  stop_now = (bit_ctr == 10) && shift_now;
+   wire 	  go_now = (bit_ctr == 0) && neg_trans;
+   
+   always @(posedge clk)
+     if(rst)
+       sr <= 0;
+     else if(shift_now)
+       sr <= {rx_d2,sr[7:1]};
+   
+   always @(posedge clk)
+     if(rst)
+       baud_ctr <= 0;
+     else
+       if(go_now)
+	 baud_ctr <= 1;
+       else if(stop_now)
+	 baud_ctr <= 0;
+       else if(baud_ctr >= clkdiv)
+	 baud_ctr <= 1;
+       else if(baud_ctr != 0)
+	 baud_ctr <= baud_ctr + 1;
+
+   always @(posedge clk)
+     if(rst)
+       bit_ctr <= 0;
+     else 
+       if(go_now)
+	 bit_ctr <= 1;
+       else if(stop_now)
+	 bit_ctr <= 0;
+       else if(baud_ctr == clkdiv)
+	 bit_ctr <= bit_ctr + 1;
+
+   wire 	  i_tready, o_tvalid;
+   wire 	  full = ~i_tready;
+   wire 	  write = ~full & rx_d2 & stop_now;
+   assign fifo_empty = ~o_tvalid;
+   
+   axi_fifo #(.WIDTH(8), .SIZE(SIZE)) fifo
+     (.clk(clk),.reset(rst), .clear(1'b0),
+      .i_tdata(sr),.i_tvalid(write),.i_tready(i_tready),
+      .o_tdata(fifo_out),.o_tvalid(o_tvalid),.o_tready(fifo_read),
+      .space(),.occupied(fifo_level) );
+   
+endmodule // simple_uart_rx
diff --git a/fpga/usrp3/lib/wishbone/simple_uart_tb.v b/fpga/usrp3/lib/wishbone/simple_uart_tb.v
new file mode 100644
index 000000000..8b1427f99
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/simple_uart_tb.v
@@ -0,0 +1,127 @@
+module simple_uart_tb();
+   
+   localparam SUART_CLKDIV = 0;
+   localparam SUART_TXLEVEL = 1;
+   localparam SUART_RXLEVEL = 2;
+   localparam SUART_TXCHAR = 3;
+   localparam SUART_RXCHAR = 4;
+   
+   reg           clk;
+   reg 		 rst;
+
+   reg 		 we_i;
+   reg 		 stb_i;
+   reg 		 cyc_i;
+   wire 	 ack_o;
+   reg [2:0] 	 adr_i;
+   reg [31:0] 	 dat_i;
+   wire [31:0] 	 dat_o;
+   wire 	 rx_int_o;
+   wire 	 tx_int_o;
+   wire 	 tx_o;
+   reg 		 rx_i;
+   wire 	 baud_o;
+
+   reg [31:0] 	 read_data;
+   
+
+   initial 
+     clk = 0;
+
+   // 200MHz clock
+   always
+     #2.5 clk = ~clk;
+
+   initial begin
+      rst <= 0;
+      we_i <= 0;
+      stb_i <= 0;
+      cyc_i <= 0;
+      adr_i <= 0;
+      dat_i <= 0;
+      rx_i <= 0;
+   end
+   
+   
+   task write_wb;
+      input [31:0] data_in;
+      input [2:0]  addr_in;
+
+      begin
+	 @(negedge clk);	 
+	 dat_i <= data_in;
+	 adr_i <= addr_in;
+	 we_i <= 1;
+	 stb_i <= 1;
+	 cyc_i <= 1;
+	 @(negedge clk);
+	 while (ack_o == 0) begin
+	    @(negedge clk);
+	 end
+	 dat_i <= 0;
+	 adr_i <= 0;
+	 we_i <= 0;
+	 stb_i <= 0;
+	 cyc_i <= 0;
+      end
+   endtask // write_wb
+
+   
+   task read_wb;
+      output [31:0] data_out;
+      input [2:0]  addr_in;
+
+      begin
+	 @(negedge clk);	 
+	 adr_i <= addr_in;
+	 we_i <= 0;
+	 stb_i <= 1;
+	 cyc_i <= 1;
+	 @(negedge clk);
+	 while (ack_o == 0) begin
+	    @(negedge clk);
+	 end
+	 data_out <= dat_o;
+	 adr_i <= 0;
+	 stb_i <= 0;
+	 cyc_i <= 0;
+      end
+   endtask // write_wb
+
+   initial begin
+      @(negedge clk);    
+      rst <= 1;
+      repeat(10) @(negedge clk);
+      rst <= 0;
+      repeat(10) @(negedge clk);
+      write_wb(4'h0620,SUART_CLKDIV);
+      repeat(10) @(negedge clk);
+      read_wb(read_data,SUART_TXLEVEL);
+      repeat(10) @(negedge clk);
+   end // initial begin
+   
+   
+   
+   simple_uart
+     #(.CLKDIV_DEFAULT(16'd0))
+   simple_uart_i
+     (
+      .clk_i(clk),
+      .rst_i(rst),
+      .we_i(we_i),
+      .stb_i(stb_i),
+      .cyc_i(cyc_i),
+      .ack_o(ack_o),
+      .adr_i(adr_i),
+      .dat_i(dat_i),
+      .dat_o(dat_o),
+      .rx_int_o(rx_int_o),
+      .tx_int_o(tx_int_o), 
+      .tx_o(tx_o), 
+      .rx_i(rx_i),
+      .baud_o(baud_o)
+      );
+
+   
+
+endmodule // simple_uart_tb
diff --git a/fpga/usrp3/lib/wishbone/simple_uart_tx.v b/fpga/usrp3/lib/wishbone/simple_uart_tx.v
new file mode 100644
index 000000000..3eb1a1ecd
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/simple_uart_tx.v
@@ -0,0 +1,69 @@
+//
+// Copyright 2011-2013 Ettus Research LLC
+//
+
+
+
+module simple_uart_tx
+    #(parameter SIZE=0)
+    (input clk, input rst, 
+     input [7:0] fifo_in, input fifo_write, output [5:0] fifo_level, output fifo_full, 
+     input [15:0] clkdiv, output baudclk, output reg tx);
+   
+   reg [15:0] 	  baud_ctr;
+   reg [3:0] 	  bit_ctr;
+   
+   wire 	  read, empty;
+   wire [7:0] 	  char_to_send;
+   wire 	  i_tready, o_tvalid;
+   
+   assign fifo_full = ~i_tready;
+   assign empty = ~o_tvalid;
+   
+   axi_fifo #(.WIDTH(8), .SIZE(SIZE)) fifo
+     (.clk(clk),.reset(rst), .clear(1'b0),
+      .i_tdata(fifo_in), .i_tvalid(fifo_write), .i_tready(i_tready),
+      .o_tdata(char_to_send),.o_tvalid(o_tvalid),.o_tready(read),
+      .space(fifo_level),.occupied() );
+   
+   always @(posedge clk)
+     if(rst)
+       baud_ctr <= 0;
+     else if (baud_ctr >= clkdiv)
+       baud_ctr <= 0;
+     else
+       baud_ctr <= baud_ctr + 1;
+
+   always @(posedge clk)
+     if(rst)
+       bit_ctr <= 0;
+     else if(baud_ctr == clkdiv)
+       if(bit_ctr == 10)
+	 bit_ctr <= 0;
+       else if(bit_ctr != 0)
+	 bit_ctr <= bit_ctr + 1;
+       else if(~empty)
+	 bit_ctr <= 1;
+   
+   always @(posedge clk)
+     if(rst)
+       tx <= 1;
+     else
+       case(bit_ctr)
+	 0 : tx <= 1;
+	 1 : tx <= 0;
+	 2 : tx <= char_to_send[0];
+	 3 : tx <= char_to_send[1];
+	 4 : tx <= char_to_send[2];
+	 5 : tx <= char_to_send[3];
+	 6 : tx <= char_to_send[4];
+	 7 : tx <= char_to_send[5];
+	 8 : tx <= char_to_send[6];
+	 9 : tx <= char_to_send[7];
+	 default : tx <= 1;
+       endcase // case(bit_ctr)
+
+   assign 	  read = (bit_ctr == 9) && (baud_ctr == clkdiv);
+   assign 	  baudclk = (baud_ctr == 1);  // Only for debug purposes
+   
+endmodule // simple_uart_tx
diff --git a/fpga/usrp3/lib/wishbone/wb_1master.v b/fpga/usrp3/lib/wishbone/wb_1master.v
new file mode 100644
index 000000000..fb313efae
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/wb_1master.v
@@ -0,0 +1,464 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE Connection Bus Top Level		                 ////
+////                                                             ////
+////                                                             ////
+////  Original Author: Johny Chi		                 ////
+////                   chisuhua@yahoo.com.cn                     ////
+////  Modified By Matt Ettus, matt@ettus.com                     ////
+////                                                             ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000, 2007 Authors and OPENCORES.ORG           ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//   Up to 8 slaves share a Wishbone Bus connection to 1 master
+
+  module wb_1master
+    #(parameter	decode_w = 8,			// address decode width
+      parameter	s0_addr = 8'h0,			// slave 0 address
+      parameter	s0_mask = 8'h0,			// slave 0 don't cares
+      parameter	s1_addr = 8'h0,			// slave 1 address
+      parameter	s1_mask = 8'h0,			// slave 1 don't cares
+      parameter	s2_addr = 8'h0,			// slave 2 address
+      parameter	s2_mask = 8'h0,			// slave 2 don't cares
+      parameter	s3_addr = 8'h0,			// slave 3 address
+      parameter	s3_mask = 8'h0,			// slave 3 don't cares
+      parameter	s4_addr = 8'h0,			// slave 4 address
+      parameter	s4_mask = 8'h0,			// slave 4 don't cares
+      parameter	s5_addr = 8'h0,			// slave 5 address
+      parameter	s5_mask = 8'h0,			// slave 5 don't cares
+      parameter	s6_addr = 8'h0,			// slave 6 address
+      parameter	s6_mask = 8'h0,			// slave 6 don't cares
+      parameter	s7_addr = 8'h0,			// slave 7 address
+      parameter	s7_mask = 8'h0,			// slave 7 don't cares
+      parameter	s8_addr = 8'h0,			// slave 8 address
+      parameter	s8_mask = 8'h0,			// slave 8 don't cares
+      parameter	s9_addr = 8'h0,			// slave 9 address
+      parameter	s9_mask = 8'h0,			// slave 9 don't cares
+      parameter	sa_addr = 8'h0,			// slave a address
+      parameter	sa_mask = 8'h0,			// slave a don't cares
+      parameter	sb_addr = 8'h0,			// slave b address
+      parameter	sb_mask = 8'h0,			// slave b don't cares
+      parameter	sc_addr = 8'h0,			// slave c address
+      parameter	sc_mask = 8'h0,			// slave c don't cares
+      parameter	sd_addr = 8'h0,			// slave d address
+      parameter	sd_mask = 8'h0,			// slave d don't cares
+      parameter	se_addr = 8'h0,			// slave e address
+      parameter	se_mask = 8'h0,			// slave e don't cares
+      parameter	sf_addr = 8'h0,			// slave f address
+      parameter	sf_mask = 8'h0,			// slave f don't cares
+            
+      parameter	dw = 32,		// Data bus Width
+      parameter	aw = 32,		// Address bus Width
+      parameter	sw = 4)                 // Number of Select Lines
+      
+      (input clk_i, 
+       input rst_i,
+       
+       // Master  Interface
+       input [dw-1:0]   m0_dat_i,
+       output [dw-1:0] 	m0_dat_o,
+       input [aw-1:0] 	m0_adr_i,
+       input [sw-1:0] 	m0_sel_i,
+       input 		m0_we_i,
+       input 		m0_cyc_i,
+       input 		m0_stb_i,
+       output 		m0_ack_o,
+       output 		m0_err_o,
+       output 		m0_rty_o,
+       
+       // Slave Interfaces
+       input [dw-1:0] 	s0_dat_i,
+       output [dw-1:0] 	s0_dat_o,
+       output [aw-1:0] 	s0_adr_o,
+       output [sw-1:0] 	s0_sel_o,
+       output 		s0_we_o,
+       output 		s0_cyc_o,
+       output 		s0_stb_o,
+       input 		s0_ack_i,
+       input 		s0_err_i,
+       input 		s0_rty_i,
+       
+       input [dw-1:0] 	s1_dat_i,
+       output [dw-1:0] 	s1_dat_o,
+       output [aw-1:0] 	s1_adr_o,
+       output [sw-1:0] 	s1_sel_o,
+       output 		s1_we_o,
+       output 		s1_cyc_o,
+       output 		s1_stb_o,
+       input 		s1_ack_i,
+       input 		s1_err_i,
+       input 		s1_rty_i,
+       
+       input [dw-1:0] 	s2_dat_i,
+       output [dw-1:0] 	s2_dat_o,
+       output [aw-1:0] 	s2_adr_o,
+       output [sw-1:0] 	s2_sel_o,
+       output 		s2_we_o,
+       output 		s2_cyc_o,
+       output 		s2_stb_o,
+       input 		s2_ack_i,
+       input 		s2_err_i,
+       input 		s2_rty_i,
+       
+       input [dw-1:0] 	s3_dat_i,
+       output [dw-1:0] 	s3_dat_o,
+       output [aw-1:0] 	s3_adr_o,
+       output [sw-1:0] 	s3_sel_o,
+       output 		s3_we_o,
+       output 		s3_cyc_o,
+       output 		s3_stb_o,
+       input 		s3_ack_i,
+       input 		s3_err_i,
+       input 		s3_rty_i,
+       
+       input [dw-1:0] 	s4_dat_i,
+       output [dw-1:0] 	s4_dat_o,
+       output [aw-1:0] 	s4_adr_o,
+       output [sw-1:0] 	s4_sel_o,
+       output 		s4_we_o,
+       output 		s4_cyc_o,
+       output 		s4_stb_o,
+       input 		s4_ack_i,
+       input 		s4_err_i,
+       input 		s4_rty_i,
+       
+       input [dw-1:0] 	s5_dat_i,
+       output [dw-1:0] 	s5_dat_o,
+       output [aw-1:0] 	s5_adr_o,
+       output [sw-1:0] 	s5_sel_o,
+       output 		s5_we_o,
+       output 		s5_cyc_o,
+       output 		s5_stb_o,
+       input 		s5_ack_i,
+       input 		s5_err_i,
+       input 		s5_rty_i,
+       
+       input [dw-1:0] 	s6_dat_i,
+       output [dw-1:0] 	s6_dat_o,
+       output [aw-1:0] 	s6_adr_o,
+       output [sw-1:0] 	s6_sel_o,
+       output 		s6_we_o,
+       output 		s6_cyc_o,
+       output 		s6_stb_o,
+       input 		s6_ack_i,
+       input 		s6_err_i,
+       input 		s6_rty_i,
+       
+       input [dw-1:0] 	s7_dat_i,
+       output [dw-1:0] 	s7_dat_o,
+       output [aw-1:0] 	s7_adr_o,
+       output [sw-1:0] 	s7_sel_o,
+       output 		s7_we_o,
+       output 		s7_cyc_o,
+       output 		s7_stb_o,
+       input 		s7_ack_i,
+       input 		s7_err_i,
+       input 		s7_rty_i,
+
+       input [dw-1:0] 	s8_dat_i,
+       output [dw-1:0] 	s8_dat_o,
+       output [aw-1:0] 	s8_adr_o,
+       output [sw-1:0] 	s8_sel_o,
+       output 		s8_we_o,
+       output 		s8_cyc_o,
+       output 		s8_stb_o,
+       input 		s8_ack_i,
+       input 		s8_err_i,
+       input 		s8_rty_i,
+       
+       input [dw-1:0] 	s9_dat_i,
+       output [dw-1:0] 	s9_dat_o,
+       output [aw-1:0] 	s9_adr_o,
+       output [sw-1:0] 	s9_sel_o,
+       output 		s9_we_o,
+       output 		s9_cyc_o,
+       output 		s9_stb_o,
+       input 		s9_ack_i,
+       input 		s9_err_i,
+       input 		s9_rty_i,
+       
+       input [dw-1:0] 	sa_dat_i,
+       output [dw-1:0] 	sa_dat_o,
+       output [aw-1:0] 	sa_adr_o,
+       output [sw-1:0] 	sa_sel_o,
+       output 		sa_we_o,
+       output 		sa_cyc_o,
+       output 		sa_stb_o,
+       input 		sa_ack_i,
+       input 		sa_err_i,
+       input 		sa_rty_i,
+       
+       input [dw-1:0] 	sb_dat_i,
+       output [dw-1:0] 	sb_dat_o,
+       output [aw-1:0] 	sb_adr_o,
+       output [sw-1:0] 	sb_sel_o,
+       output 		sb_we_o,
+       output 		sb_cyc_o,
+       output 		sb_stb_o,
+       input 		sb_ack_i,
+       input 		sb_err_i,
+       input 		sb_rty_i,
+       
+       input [dw-1:0] 	sc_dat_i,
+       output [dw-1:0] 	sc_dat_o,
+       output [aw-1:0] 	sc_adr_o,
+       output [sw-1:0] 	sc_sel_o,
+       output 		sc_we_o,
+       output 		sc_cyc_o,
+       output 		sc_stb_o,
+       input 		sc_ack_i,
+       input 		sc_err_i,
+       input 		sc_rty_i,
+       
+       input [dw-1:0] 	sd_dat_i,
+       output [dw-1:0] 	sd_dat_o,
+       output [aw-1:0] 	sd_adr_o,
+       output [sw-1:0] 	sd_sel_o,
+       output 		sd_we_o,
+       output 		sd_cyc_o,
+       output 		sd_stb_o,
+       input 		sd_ack_i,
+       input 		sd_err_i,
+       input 		sd_rty_i,
+       
+       input [dw-1:0] 	se_dat_i,
+       output [dw-1:0] 	se_dat_o,
+       output [aw-1:0] 	se_adr_o,
+       output [sw-1:0] 	se_sel_o,
+       output 		se_we_o,
+       output 		se_cyc_o,
+       output 		se_stb_o,
+       input 		se_ack_i,
+       input 		se_err_i,
+       input 		se_rty_i,
+       
+       input [dw-1:0] 	sf_dat_i,
+       output [dw-1:0] 	sf_dat_o,
+       output [aw-1:0] 	sf_adr_o,
+       output [sw-1:0] 	sf_sel_o,
+       output 		sf_we_o,
+       output 		sf_cyc_o,
+       output 		sf_stb_o,
+       input 		sf_ack_i,
+       input 		sf_err_i,
+       input 		sf_rty_i
+       );
+   
+   // ////////////////////////////////////////////////////////////////
+   //
+   // Local wires
+   //
+   
+   wire [15:0] 		ssel_dec;
+   reg [dw-1:0] 	i_dat_s;	// internal share bus , slave data to master
+   
+   // Master output Interface
+   assign 		m0_dat_o = i_dat_s;
+   
+   always @*
+     case(ssel_dec)
+       1   : i_dat_s <= s0_dat_i;
+       2   : i_dat_s <= s1_dat_i;
+       4   : i_dat_s <= s2_dat_i;
+       8   : i_dat_s <= s3_dat_i;
+       16  : i_dat_s <= s4_dat_i;
+       32  : i_dat_s <= s5_dat_i;
+       64  : i_dat_s <= s6_dat_i;
+       128 : i_dat_s <= s7_dat_i;
+       256 : i_dat_s <= s8_dat_i;
+       512 : i_dat_s <= s9_dat_i;
+       1024 : i_dat_s <= sa_dat_i;
+       2048 : i_dat_s <= sb_dat_i;
+       4096 : i_dat_s <= sc_dat_i;
+       8192 : i_dat_s <= sd_dat_i;
+       16384 : i_dat_s <= se_dat_i;
+       32768 : i_dat_s <= sf_dat_i;
+       default : i_dat_s <= s0_dat_i;
+     endcase // case(ssel_dec)
+   
+   assign 		{m0_ack_o, m0_err_o, m0_rty_o} 
+     =  {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i |
+	 s8_ack_i | s9_ack_i | sa_ack_i | sb_ack_i | sc_ack_i | sd_ack_i | se_ack_i | sf_ack_i ,
+	 s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i |
+	 s8_err_i | s9_err_i | sa_err_i | sb_err_i | sc_err_i | sd_err_i | se_err_i | sf_err_i ,
+	 s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i |
+	 s8_rty_i | s9_rty_i | sa_rty_i | sb_rty_i | sc_rty_i | sd_rty_i | se_rty_i | sf_rty_i };
+
+   // Slave output interfaces
+   assign 		s0_adr_o = m0_adr_i;
+   assign 		s0_sel_o = m0_sel_i;
+   assign 		s0_dat_o = m0_dat_i;
+   assign 		s0_we_o = m0_we_i;
+   assign 		s0_cyc_o = m0_cyc_i;
+   assign 		s0_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[0];   
+   
+   assign 		s1_adr_o = m0_adr_i;
+   assign 		s1_sel_o = m0_sel_i;
+   assign 		s1_dat_o = m0_dat_i;
+   assign 		s1_we_o = m0_we_i;
+   assign 		s1_cyc_o = m0_cyc_i;
+   assign 		s1_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[1];   
+   
+   assign 		s2_adr_o = m0_adr_i;
+   assign 		s2_sel_o = m0_sel_i;
+   assign 		s2_dat_o = m0_dat_i;
+   assign 		s2_we_o = m0_we_i;
+   assign 		s2_cyc_o = m0_cyc_i;
+   assign 		s2_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[2];   
+   
+   assign 		s3_adr_o = m0_adr_i;
+   assign 		s3_sel_o = m0_sel_i;
+   assign 		s3_dat_o = m0_dat_i;
+   assign 		s3_we_o = m0_we_i;
+   assign 		s3_cyc_o = m0_cyc_i;
+   assign 		s3_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[3];   
+   
+   assign 		s4_adr_o = m0_adr_i;
+   assign 		s4_sel_o = m0_sel_i;
+   assign 		s4_dat_o = m0_dat_i;
+   assign 		s4_we_o = m0_we_i;
+   assign 		s4_cyc_o = m0_cyc_i;
+   assign 		s4_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[4];   
+   
+   assign 		s5_adr_o = m0_adr_i;
+   assign 		s5_sel_o = m0_sel_i;
+   assign 		s5_dat_o = m0_dat_i;
+   assign 		s5_we_o = m0_we_i;
+   assign 		s5_cyc_o = m0_cyc_i;
+   assign 		s5_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[5];   
+   
+   assign 		s6_adr_o = m0_adr_i;
+   assign 		s6_sel_o = m0_sel_i;
+   assign 		s6_dat_o = m0_dat_i;
+   assign 		s6_we_o = m0_we_i;
+   assign 		s6_cyc_o = m0_cyc_i;
+   assign 		s6_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[6];   
+   
+   assign 		s7_adr_o = m0_adr_i;
+   assign 		s7_sel_o = m0_sel_i;
+   assign 		s7_dat_o = m0_dat_i;
+   assign 		s7_we_o = m0_we_i;
+   assign 		s7_cyc_o = m0_cyc_i;
+   assign 		s7_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[7];   
+   
+   assign 		s8_adr_o = m0_adr_i;
+   assign 		s8_sel_o = m0_sel_i;
+   assign 		s8_dat_o = m0_dat_i;
+   assign 		s8_we_o = m0_we_i;
+   assign 		s8_cyc_o = m0_cyc_i;
+   assign 		s8_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[8];   
+   
+   assign 		s9_adr_o = m0_adr_i;
+   assign 		s9_sel_o = m0_sel_i;
+   assign 		s9_dat_o = m0_dat_i;
+   assign 		s9_we_o = m0_we_i;
+   assign 		s9_cyc_o = m0_cyc_i;
+   assign 		s9_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[9];   
+   
+   assign 		sa_adr_o = m0_adr_i;
+   assign 		sa_sel_o = m0_sel_i;
+   assign 		sa_dat_o = m0_dat_i;
+   assign 		sa_we_o = m0_we_i;
+   assign 		sa_cyc_o = m0_cyc_i;
+   assign 		sa_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10];   
+   
+   assign 		sb_adr_o = m0_adr_i;
+   assign 		sb_sel_o = m0_sel_i;
+   assign 		sb_dat_o = m0_dat_i;
+   assign 		sb_we_o = m0_we_i;
+   assign 		sb_cyc_o = m0_cyc_i;
+   assign 		sb_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11];   
+   
+   assign 		sc_adr_o = m0_adr_i;
+   assign 		sc_sel_o = m0_sel_i;
+   assign 		sc_dat_o = m0_dat_i;
+   assign 		sc_we_o = m0_we_i;
+   assign 		sc_cyc_o = m0_cyc_i;
+   assign 		sc_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12];   
+   
+   assign 		sd_adr_o = m0_adr_i;
+   assign 		sd_sel_o = m0_sel_i;
+   assign 		sd_dat_o = m0_dat_i;
+   assign 		sd_we_o = m0_we_i;
+   assign 		sd_cyc_o = m0_cyc_i;
+   assign 		sd_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13];   
+   
+   assign 		se_adr_o = m0_adr_i;
+   assign 		se_sel_o = m0_sel_i;
+   assign 		se_dat_o = m0_dat_i;
+   assign 		se_we_o = m0_we_i;
+   assign 		se_cyc_o = m0_cyc_i;
+   assign 		se_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14];   
+   
+   assign 		sf_adr_o = m0_adr_i;
+   assign 		sf_sel_o = m0_sel_i;
+   assign 		sf_dat_o = m0_dat_i;
+   assign 		sf_we_o = m0_we_i;
+   assign 		sf_cyc_o = m0_cyc_i;
+   assign 		sf_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15];   
+   
+   // Address decode logic
+   // WARNING -- must make sure these are mutually exclusive!
+
+
+   assign 		ssel_dec[0] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s0_addr) & s0_mask);
+   assign 		ssel_dec[1] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s1_addr) & s1_mask);
+   assign 		ssel_dec[2] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s2_addr) & s2_mask);
+   assign 		ssel_dec[3] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s3_addr) & s3_mask);
+   assign 		ssel_dec[4] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s4_addr) & s4_mask);
+   assign 		ssel_dec[5] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s5_addr) & s5_mask);
+   assign 		ssel_dec[6] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s6_addr) & s6_mask);
+   assign 		ssel_dec[7] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s7_addr) & s7_mask);
+   assign 		ssel_dec[8] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s8_addr) & s8_mask);
+   assign 		ssel_dec[9] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s9_addr) & s9_mask);
+   assign 		ssel_dec[10] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sa_addr) & sa_mask);
+   assign 		ssel_dec[11] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sb_addr) & sb_mask);
+   assign 		ssel_dec[12] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sc_addr) & sc_mask);
+   assign 		ssel_dec[13] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sd_addr) & sd_mask);
+   assign 		ssel_dec[14] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ se_addr) & se_mask);
+   assign 		ssel_dec[15] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sf_addr) & sf_mask);
+
+/*
+   assign 		ssel_dec[0] = (m0_adr_i[aw -1 : aw - decode_w ] == s0_addr);
+   assign 		ssel_dec[1] = (m0_adr_i[aw -1 : aw - decode_w ] == s1_addr);
+   assign 		ssel_dec[2] = (m0_adr_i[aw -1 : aw - decode_w ] == s2_addr);
+   assign 		ssel_dec[3] = (m0_adr_i[aw -1 : aw - decode_w ] == s3_addr);
+   assign 		ssel_dec[4] = (m0_adr_i[aw -1 : aw - decode_w ] == s4_addr);
+   assign 		ssel_dec[5] = (m0_adr_i[aw -1 : aw - decode_w ] == s5_addr);
+   assign 		ssel_dec[6] = (m0_adr_i[aw -1 : aw - decode_w ] == s6_addr);
+   assign 		ssel_dec[7] = (m0_adr_i[aw -1 : aw - decode_w ] == s7_addr);
+   assign 		ssel_dec[8] = (m0_adr_i[aw -1 : aw - decode_w ] == s8_addr);
+   assign 		ssel_dec[9] = (m0_adr_i[aw -1 : aw - decode_w ] == s9_addr);
+   assign 		ssel_dec[10] = (m0_adr_i[aw -1 : aw - decode_w ] == sa_addr);
+   assign 		ssel_dec[11] = (m0_adr_i[aw -1 : aw - decode_w ] == sb_addr);
+   assign 		ssel_dec[12] = (m0_adr_i[aw -1 : aw - decode_w ] == sc_addr);
+   assign 		ssel_dec[13] = (m0_adr_i[aw -1 : aw - decode_w ] == sd_addr);
+   assign 		ssel_dec[14] = (m0_adr_i[aw -1 : aw - decode_w ] == se_addr);
+   assign 		ssel_dec[15] = (m0_adr_i[aw -1 : aw - decode_w ] == sf_addr);
+ */ 
+endmodule // wb_1master
diff --git a/fpga/usrp3/top/Makefile.common b/fpga/usrp3/top/Makefile.common
new file mode 100644
index 000000000..e005fcb8a
--- /dev/null
+++ b/fpga/usrp3/top/Makefile.common
@@ -0,0 +1,59 @@
+#
+# Copyright 2008-2013 Ettus Research LLC
+#
+
+##################################################
+# Constants
+##################################################
+ISE_VER = $(shell xtclsh -h | head -n1 | cut -f2 -d" " | cut -f1 -d.)
+ifeq ($(ISE_VER),10)
+	ISE_EXT = ise
+else
+	ISE_EXT = xise
+endif
+BASE_DIR = $(abspath ..)
+ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl
+SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py
+TIMING_CHECKER = python $(BASE_DIR)/python/check_timing.py
+ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT)
+BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin
+BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit
+TWR_FILE = $(BUILD_DIR)/$(TOP_MODULE).twr
+
+##################################################
+# Global Targets
+##################################################
+all: bin
+
+proj: $(ISE_FILE)
+
+check: $(ISE_FILE)
+	#$(SANITY_CHECKER) $(TOP_MODULE).v $(TOP_MODULE).ucf
+	$(ISE_HELPER) "Check Syntax"
+
+synth: $(ISE_FILE)
+	$(ISE_HELPER) "Synthesize - XST"
+
+#bin: check $(BIN_FILE)
+bin: $(BIN_FILE) $(BIT_FILE)
+	$(TIMING_CHECKER) $(TWR_FILE)
+
+clean:
+	$(RM) -r $(BUILD_DIR)
+
+.PHONY: all proj check synth bin mcs clean
+
+##################################################
+# Dependency Targets
+##################################################
+.SECONDEXPANSION:
+$(ISE_FILE): $$(SOURCES) $$(MAKEFILE_LIST)
+	@echo $@
+	$(ISE_HELPER) ""
+
+$(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST)
+	@echo $@
+	$(ISE_HELPER) "Generate Programming File" 2>&1 | tee $(BUILD_DIR)/build.log
+	touch $@
+
+.EXPORT_ALL_VARIABLES:
diff --git a/fpga/usrp3/top/README.txt b/fpga/usrp3/top/README.txt
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/.gitignore b/fpga/usrp3/top/b200/.gitignore
new file mode 100644
index 000000000..376246b05
--- /dev/null
+++ b/fpga/usrp3/top/b200/.gitignore
@@ -0,0 +1,5 @@
+build*
+catcap_tb
+catgen_tb
+fuse*
+isim*
diff --git a/fpga/usrp3/top/b200/Makefile b/fpga/usrp3/top/b200/Makefile
new file mode 100644
index 000000000..ad5e5cf7a
--- /dev/null
+++ b/fpga/usrp3/top/b200/Makefile
@@ -0,0 +1,20 @@
+#
+# Copyright 2012-2013 Ettus Research LLC
+#
+
+all: B200 B210
+	find -name "*.twr" | xargs grep constraint | grep met
+	mkdir -p build
+	cp build-B200/b200.bin build/usrp_b200_fpga.bin
+	cp build-B210/b200.bin build/usrp_b210_fpga.bin
+
+clean:
+	rm -rf build*
+
+B200:
+	make -f Makefile.b200.inc bin NAME=B200 DEVICE=XC6SLX75
+
+B210:
+	make -f Makefile.b200.inc bin NAME=B210 DEVICE=XC6SLX150 EXTRA_DEFS="B200_CAN_HAZ_R1=1"
+
+.PHONY: all clean
diff --git a/fpga/usrp3/top/b200/Makefile.b200.inc b/fpga/usrp3/top/b200/Makefile.b200.inc
new file mode 100644
index 000000000..da7561cab
--- /dev/null
+++ b/fpga/usrp3/top/b200/Makefile.b200.inc
@@ -0,0 +1,127 @@
+#
+# Copyright 2012-2013 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE := b200
+BUILD_DIR := build-$(NAME)/
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
+include ../Makefile.common
+include ../../lib/gpif2/Makefile.srcs
+include ../../lib/fifo/Makefile.srcs
+include ../../lib/dsp/Makefile.srcs
+include ../../lib/control/Makefile.srcs
+include ../../lib/packet_proc/Makefile.srcs
+include ../../lib/timing/Makefile.srcs
+include ../../lib/vita/Makefile.srcs
+include ../../lib/wishbone/Makefile.srcs
+
+B200_COREGEN_SRCS = \
+coregen/b200_clk_gen.v \
+coregen/fifo_4k_2clk.xco \
+coregen/fifo_short_2clk.xco \
+coregen/chipscope_icon.v \
+coregen/chipscope_icon.xco \
+coregen/chipscope_ila_32.v \
+coregen/chipscope_ila_32.xco \
+coregen/chipscope_ila_128.v \
+coregen/chipscope_ila_128.xco \
+coregen/chipscope_ila_256.v \
+coregen/chipscope_ila_256.xco 
+
+
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan6" \
+device $(DEVICE) \
+package fgg484 \
+speed -3 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+b200.v \
+b200_core.v \
+radio_b200.v \
+catcap_ddr_cmos.v \
+catgen_ddr_cmos.v \
+catcodec_ddr_cmos.v \
+b200.ucf \
+timing.ucf \
+S6CLK2PIN.v \
+$(B200_COREGEN_SRCS)
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) \
+$(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(COREGEN_SRCS) \
+$(GPIF2_SRCS) $(PACKET_PROC_SRCS) \
+$(WISHBONE_SRCS) \
+$(TIMING_SRCS) \
+$(DSP_SRCS) \
+$(VITA_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto \
+"Verilog Macros" "SPARTAN6=1 $(EXTRA_DEFS) $(CUSTOM_DEFS)"
+
+#"Number of Clock Buffers" 8 \
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Unused IOB Pins" "Pull Up"
+
+#"Configuration Rate" 6 \
+#"Enable Outputs (Output Events)" 6 \
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp3/top/b200/S6CLK2PIN.v b/fpga/usrp3/top/b200/S6CLK2PIN.v
new file mode 100644
index 000000000..a9d6332ef
--- /dev/null
+++ b/fpga/usrp3/top/b200/S6CLK2PIN.v
@@ -0,0 +1,23 @@
+module S6CLK2PIN
+(
+    input I,
+    output O
+);
+
+    ODDR2 #(
+           .DDR_ALIGNMENT("NONE"), // to "NONE", "C0" or "C1"
+           .INIT(1'b0),            // output to 1'b0 or 1'b1
+           .SRTYPE("ASYNC"))        // set/reset "SYNC" or "ASYNC"
+
+         ODDR2_S6CLK2PIN
+           (
+        .Q(O),  // 1-bit DDR output data
+        .C0(I), // 1-bit clock input
+        .C1(~I), // 1-bit clock input
+        .CE(1'b1), // 1-bit clock enable input
+        .D0(1'b1), // 1-bit data input (associated with C0)
+        .D1(1'b0), // 1-bit data input (associated with C1)
+        .R(1'b0),  // 1-bit reset input
+        .S(1'b0) );// 1-bit set input
+
+endmodule //S6CLK2PIN
diff --git a/fpga/usrp3/top/b200/b200.ucf b/fpga/usrp3/top/b200/b200.ucf
new file mode 100644
index 000000000..6a088c51d
--- /dev/null
+++ b/fpga/usrp3/top/b200/b200.ucf
@@ -0,0 +1,244 @@
+## SPI Nets
+
+NET "cat_ce"  LOC = "Y1"    | IOSTANDARD = LVCMOS18;
+NET "cat_miso"  LOC = "V1"  | IOSTANDARD = LVCMOS18;
+NET "cat_mosi"  LOC = "T4"  | IOSTANDARD = LVCMOS18;
+NET "cat_sclk"  LOC = "P7"  | IOSTANDARD = LVCMOS18;
+
+NET "fx3_ce"  LOC = "H20" | IOSTANDARD = LVCMOS18 ;
+NET "fx3_miso"  LOC = "G20" | IOSTANDARD = LVCMOS18 ;
+NET "fx3_mosi"  LOC = "AA20" | IOSTANDARD = LVCMOS18 ;
+#NET "fx3_mosi"  LOC = "A9" | IOSTANDARD = LVCMOS33 ;
+NET "fx3_sclk"  LOC = "Y21" | IOSTANDARD = LVCMOS18 ;
+
+NET "pll_ce"  LOC = "W11" | IOSTANDARD = LVCMOS18 ;
+NET "pll_mosi"  LOC = "AB11" | IOSTANDARD = LVCMOS18 ;
+NET "pll_sclk"  LOC = "Y12" | IOSTANDARD = LVCMOS18 ;
+
+NET "FPGA_RXD0"  LOC = "AB8" | IOSTANDARD = LVCMOS18 ;
+NET "FPGA_TXD0"  LOC = "AB7" | IOSTANDARD = LVCMOS18 ;
+
+## Catalina Controls
+
+NET "codec_enable"  LOC = "J6"  | IOSTANDARD = LVCMOS18;
+NET "codec_en_agc"  LOC = "P6"  | IOSTANDARD = LVCMOS18;
+NET "codec_reset"  LOC = "Y2"  | IOSTANDARD = LVCMOS18;
+NET "codec_sync"  LOC = "M3"  | IOSTANDARD = LVCMOS18;
+NET "codec_txrx"  LOC = "M7"  | IOSTANDARD = LVCMOS18;
+
+NET "codec_ctrl_in<0>"  LOC = "E3"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_in<1>"  LOC = "F2"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_in<2>"  LOC = "F1"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_in<3>"  LOC = "E1"  | IOSTANDARD = LVCMOS18;
+
+NET "codec_ctrl_out<0>"  LOC = "D1"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out<1>"  LOC = "C1"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out<2>"  LOC = "H3"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out<3>"  LOC = "F3"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out<4>"  LOC = "P1"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out<5>"  LOC = "J1"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out<6>"  LOC = "B1"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out<7>"  LOC = "H2"  | IOSTANDARD = LVCMOS18;
+
+## Catalina Data TX
+
+NET "tx_codec_d<0>"  LOC = "T2"  | IOSTANDARD = LVCMOS18 ;
+NET "tx_codec_d<1>"  LOC = "R1"  | IOSTANDARD = LVCMOS18 ;
+NET "tx_codec_d<2>"  LOC = "V2"  | IOSTANDARD = LVCMOS18 ;
+NET "tx_codec_d<3>"  LOC = "N1"  | IOSTANDARD = LVCMOS18 ;
+NET "tx_codec_d<4>"  LOC = "V3"  | IOSTANDARD = LVCMOS18 ;
+NET "tx_codec_d<5>"  LOC = "T1"  | IOSTANDARD = LVCMOS18 ;
+NET "tx_codec_d<6>"  LOC = "W1"  | IOSTANDARD = LVCMOS18 ;
+NET "tx_codec_d<7>"  LOC = "U1"  | IOSTANDARD = LVCMOS18 ;
+NET "tx_codec_d<8>"  LOC = "W3"  | IOSTANDARD = LVCMOS18 ;
+NET "tx_codec_d<9>"  LOC = "U3"  | IOSTANDARD = LVCMOS18 ;
+NET "tx_codec_d<10>"  LOC = "P2"  | IOSTANDARD = LVCMOS18 ;
+NET "tx_codec_d<11>"  LOC = "R3"  | IOSTANDARD = LVCMOS18 ;
+NET "tx_codec_d*" DRIVE = 2;
+
+## Catalina Data RX
+
+NET "rx_codec_d<0>"  LOC = "M1"  | IOSTANDARD = LVCMOS18 ;
+NET "rx_codec_d<1>"  LOC = "K1"  | IOSTANDARD = LVCMOS18 ;
+NET "rx_codec_d<2>"  LOC = "K2"  | IOSTANDARD = LVCMOS18 ;
+NET "rx_codec_d<3>"  LOC = "G3"  | IOSTANDARD = LVCMOS18 ;
+NET "rx_codec_d<4>"  LOC = "M2"  | IOSTANDARD = LVCMOS18 ;
+NET "rx_codec_d<5>"  LOC = "J4"  | IOSTANDARD = LVCMOS18 ;
+NET "rx_codec_d<6>"  LOC = "L3"  | IOSTANDARD = LVCMOS18 ;
+NET "rx_codec_d<7>"  LOC = "H1"  | IOSTANDARD = LVCMOS18 ;
+NET "rx_codec_d<8>"  LOC = "L4"  | IOSTANDARD = LVCMOS18 ;
+NET "rx_codec_d<9>"  LOC = "G1"  | IOSTANDARD = LVCMOS18 ;
+NET "rx_codec_d<10>"  LOC = "N3"  | IOSTANDARD = LVCMOS18 ;
+NET "rx_codec_d<11>"  LOC = "M4"  | IOSTANDARD = LVCMOS18 ;
+NET "rx_codec_d*" DRIVE = 2;
+
+## Catalina Clocks
+
+NET "cat_clkout_fpga"  LOC = "J3"  | IOSTANDARD = LVCMOS18;
+NET "codec_data_clk_p"  LOC = "K3"  | IOSTANDARD = LVCMOS18;
+NET "codec_fb_clk_p"  LOC = "P3"  | IOSTANDARD = LVCMOS18  | DRIVE = 2 ;
+NET "codec_main_clk_p"  LOC = "K5"   | IOSTANDARD = LVDS_25;
+NET "codec_main_clk_n"  LOC = "K4"   | IOSTANDARD = LVDS_25;
+
+NET "rx_frame_p"  LOC = "U4"  | IOSTANDARD = LVCMOS18;
+NET "tx_frame_p"  LOC = "T3"  | IOSTANDARD = LVCMOS18  | DRIVE = 2 ;
+
+## Debug Bus
+
+NET "debug<0>"  LOC = "D10" | IOSTANDARD = LVCMOS33 ;
+NET "debug<1>"  LOC = "D9" | IOSTANDARD = LVCMOS33 ;
+NET "debug<2>"  LOC = "A8" | IOSTANDARD = LVCMOS33 ;
+NET "debug<3>"  LOC = "B8" | IOSTANDARD = LVCMOS33 ;
+NET "debug<4>"  LOC = "C8" | IOSTANDARD = LVCMOS33 ;
+NET "debug<5>"  LOC = "D8" | IOSTANDARD = LVCMOS33 ;
+NET "debug<6>"  LOC = "A7" | IOSTANDARD = LVCMOS33 ;
+NET "debug<7>"  LOC = "D7" | IOSTANDARD = LVCMOS33 ;
+NET "debug<8>"  LOC = "A6" | IOSTANDARD = LVCMOS33 ;
+NET "debug<9>"  LOC = "B6" | IOSTANDARD = LVCMOS33 ;
+NET "debug<10>"  LOC = "C6" | IOSTANDARD = LVCMOS33 ;
+NET "debug<11>"  LOC = "D6" | IOSTANDARD = LVCMOS33 ;
+NET "debug<12>"  LOC = "A5" | IOSTANDARD = LVCMOS33 ;
+NET "debug<13>"  LOC = "A4" | IOSTANDARD = LVCMOS33 ;
+NET "debug<14>"  LOC = "C5" | IOSTANDARD = LVCMOS33 ;
+NET "debug<15>"  LOC = "A3" | IOSTANDARD = LVCMOS33 ;
+NET "debug<16>"  LOC = "A18" | IOSTANDARD = LVCMOS33 ;
+NET "debug<17>"  LOC = "B18" | IOSTANDARD = LVCMOS33 ;
+NET "debug<18>"  LOC = "A17" | IOSTANDARD = LVCMOS33 ;
+NET "debug<19>"  LOC = "C17" | IOSTANDARD = LVCMOS33 ;
+NET "debug<20>"  LOC = "C14" | IOSTANDARD = LVCMOS33 ;
+NET "debug<21>"  LOC = "D12" | IOSTANDARD = LVCMOS33 ;
+NET "debug<22>"  LOC = "C10" | IOSTANDARD = LVCMOS33 ;
+NET "debug<23>"  LOC = "F15" | IOSTANDARD = LVCMOS33 ;
+NET "debug<24>"  LOC = "E14" | IOSTANDARD = LVCMOS33 ;
+NET "debug<25>"  LOC = "F14" | IOSTANDARD = LVCMOS33 ;
+NET "debug<26>"  LOC = "H14" | IOSTANDARD = LVCMOS33 ;
+NET "debug<27>"  LOC = "D13" | IOSTANDARD = LVCMOS33 ;
+NET "debug<28>"  LOC = "F13" | IOSTANDARD = LVCMOS33 ;
+NET "debug<29>"  LOC = "G13" | IOSTANDARD = LVCMOS33 ;
+NET "debug<30>"  LOC = "E12" | IOSTANDARD = LVCMOS33 ;
+NET "debug<31>"  LOC = "H13" | IOSTANDARD = LVCMOS33 ;
+
+NET "debug_clk<0>"  LOC = "A12" | IOSTANDARD = LVCMOS33 ;
+NET "debug_clk<1>"  LOC = "C12" | IOSTANDARD = LVCMOS33 ;
+
+NET "debug*" DRIVE = 2;
+
+## GPIF
+
+NET "IFCLK"  LOC = "H21" | IOSTANDARD = LVCMOS18 ;
+NET "FX3_EXTINT"  LOC = "U20" | IOSTANDARD = LVCMOS18 ;
+
+NET "IFCLK" DRIVE = 8;
+NET "IFCLK" SLEW = SLOW;
+
+NET "GPIF_CTL0"  LOC = "P22" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_CTL1"  LOC = "N22" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_CTL2"  LOC = "AA18" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_CTL3"  LOC = "AB18" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_CTL4"  LOC = "P19" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_CTL5"  LOC = "AA2" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_CTL6"  LOC = "M22" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_CTL7"  LOC = "AB19" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_CTL8"  LOC = "M19" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_CTL9"  LOC = "R20" | IOSTANDARD = LVCMOS18 ;
+##GPIF_CTL10 is "FPGA_CFG_DONE", defined later.
+NET "GPIF_CTL11"  LOC = "M21" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_CTL12"  LOC = "M20" | IOSTANDARD = LVCMOS18 ;
+
+NET "GPIF_D<0>"  LOC = "T17" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<1>"  LOC = "U14" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<2>"  LOC = "U13" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<3>"  LOC = "AA6" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<4>"  LOC = "AB6" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<5>"  LOC = "Y3" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<6>"  LOC = "AB3" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<7>"  LOC = "AA4" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<8>"  LOC = "V20" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<9>"  LOC = "AB2" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<10>"  LOC = "V21" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<11>"  LOC = "T22" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<12>"  LOC = "U22" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<13>"  LOC = "R22" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<14>"  LOC = "AA12" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<15>"  LOC = "AB12" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<16>"  LOC = "Y13" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<17>"  LOC = "N20" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<18>"  LOC = "T21" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<19>"  LOC = "K18" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<20>"  LOC = "H22" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<21>"  LOC = "J20" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<22>"  LOC = "K19" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<23>"  LOC = "L19" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<24>"  LOC = "N19" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<25>"  LOC = "K22" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<26>"  LOC = "L22" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<27>"  LOC = "L20" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<28>"  LOC = "J22" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<29>"  LOC = "K20" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<30>"  LOC = "G22" | IOSTANDARD = LVCMOS18 ;
+NET "GPIF_D<31>"  LOC = "F22" | IOSTANDARD = LVCMOS18 ;
+
+NET "GPIF_*" DRIVE = 2;
+NET "GPIF_*" SLEW = SLOW;
+
+## GPS
+
+NET "gps_lock"  LOC = "B14" | IOSTANDARD = LVCMOS33 ;
+NET "gps_rxd"  LOC = "A15" | IOSTANDARD = LVCMOS33 ;
+NET "gps_txd"  LOC = "A14" | IOSTANDARD = LVCMOS33 ;
+NET "gps_txd_nmea"  LOC = "C15" | IOSTANDARD = LVCMOS33 ;
+
+## LEDS
+
+NET "LED_RX1"  LOC = "C22" | IOSTANDARD = LVCMOS18 ;
+NET "LED_RX2"  LOC = "L15" | IOSTANDARD = LVCMOS18 ;
+NET "LED_TXRX1_TX"  LOC = "C20" | IOSTANDARD = LVCMOS18 ;
+NET "LED_TXRX2_RX"  LOC = "D21" | IOSTANDARD = LVCMOS18 ;
+NET "LED_TXRX1_RX"  LOC = "K16" | IOSTANDARD = LVCMOS18 ;
+NET "LED_TXRX2_TX"  LOC = "D22" | IOSTANDARD = LVCMOS18 ;
+
+## Misc Hardware Control
+NET "ref_sel"  LOC = "AA14" | IOSTANDARD = LVCMOS18 ;
+NET "pll_lock"  LOC = "AB10" | IOSTANDARD = LVCMOS18 ;
+NET "AUX_PWR_ON"  LOC = "B16" | IOSTANDARD = LVCMOS33 ;
+#NET "RFUSE"  LOC = "P15" | IOSTANDARD = LVCMOS33 ;
+
+## PPS
+
+NET "PPS_IN_EXT"  LOC = "B10" | IOSTANDARD = LVCMOS33 ;
+NET "PPS_IN_INT"  LOC = "A10" | IOSTANDARD = LVCMOS33 ;
+
+## RF Hardware Control
+
+NET "SFDX1_RX"  LOC = "A16" | IOSTANDARD = LVCMOS33 ;
+NET "SFDX1_TX"  LOC = "D14" | IOSTANDARD = LVCMOS33 ;
+NET "SFDX2_RX"  LOC = "C11" | IOSTANDARD = LVCMOS33 ;
+NET "SFDX2_TX"  LOC = "A11" | IOSTANDARD = LVCMOS33 ;
+NET "SRX1_RX"  LOC = "D15" | IOSTANDARD = LVCMOS33 ;
+NET "SRX1_TX"  LOC = "C16" | IOSTANDARD = LVCMOS33 ;
+NET "SRX2_RX"  LOC = "B12" | IOSTANDARD = LVCMOS33 ;
+NET "SRX2_TX"  LOC = "D11" | IOSTANDARD = LVCMOS33 ;
+NET "tx_bandsel_a"  LOC = "C13" | IOSTANDARD = LVCMOS33 ;
+NET "tx_bandsel_b"  LOC = "D17" | IOSTANDARD = LVCMOS33 ;
+NET "tx_enable1"  LOC = "Y4" | IOSTANDARD = LVCMOS18 ;
+NET "tx_enable2"  LOC = "R19" | IOSTANDARD = LVCMOS18 ;
+NET "rx_bandsel_a"  LOC = "C9" | IOSTANDARD = LVCMOS33 ;
+NET "rx_bandsel_b"  LOC = "A13" | IOSTANDARD = LVCMOS33 ;
+NET "rx_bandsel_c"  LOC = "E16" | IOSTANDARD = LVCMOS33 ;
+
+## FPGA Config Pins
+
+#NET "FPGA_CFG_INIT_B"  LOC = "T6" | IOSTANDARD = LVCMOS18 ;
+#NET "FPGA_CFG_DONE"  LOC = "Y22" | IOSTANDARD = LVCMOS18 ;
+#NET "FPGA_CFG_M0"  LOC = "AA22" | IOSTANDARD = LVCMOS18 ;
+#NET "FPGA_CFG_M1"  LOC = "U15" | IOSTANDARD = LVCMOS18 ;
+#NET "FPGA_CFG_PROG_B"  LOC = "AA1" | IOSTANDARD = LVCMOS18 ;
+
+## Special Pins
+
+#NET "VFS"  LOC = "P16" | IOSTANDARD = LVCMOS33 ;
+#NET "TMS"  LOC = "C18" | IOSTANDARD = LVCMOS33 ;
+#NET "TDO"  LOC = "A19" | IOSTANDARD = LVCMOS33 ;
+#NET "TDI"  LOC = "E18" | IOSTANDARD = LVCMOS33 ;
+#NET "TCK"  LOC = "G15" | IOSTANDARD = LVCMOS33 ;
+#NET "GND"  LOC = "N15" | IOSTANDARD = LVCMOS33 ;
diff --git a/fpga/usrp3/top/b200/b200.v b/fpga/usrp3/top/b200/b200.v
new file mode 100644
index 000000000..86ccc51b0
--- /dev/null
+++ b/fpga/usrp3/top/b200/b200.v
@@ -0,0 +1,286 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+/***********************************************************
+ * B200 Module Declaration
+ **********************************************************/
+module b200 (
+   // SPI Interfaces
+   output cat_ce,
+   input cat_miso,
+   output cat_mosi,
+   output cat_sclk,
+
+   input fx3_ce,
+   output fx3_miso,
+   input fx3_mosi,
+   input fx3_sclk,
+
+   output pll_ce,
+   output pll_mosi,
+   output pll_sclk,
+
+   // UART
+   input FPGA_RXD0,
+   input FPGA_TXD0,
+
+   // Catalina Controls
+   output codec_enable,
+   output codec_en_agc,
+   output codec_reset,
+   output codec_sync,
+   output codec_txrx,
+   output [3:0] codec_ctrl_in,      // These should be outputs
+   input [7:0] codec_ctrl_out,      // MUST BE INPUT
+
+   // Catalina Data
+   input codec_data_clk_p,          // Clock from CAT (RX)
+   output codec_fb_clk_p,           // Clock to CAT (TX)
+   input [11:0] rx_codec_d,
+   output [11:0] tx_codec_d,
+   input rx_frame_p,
+   output tx_frame_p,
+
+   input cat_clkout_fpga,
+
+   //always on 40MHz clock
+   input codec_main_clk_p,
+   input codec_main_clk_n,
+
+   // Debug Bus
+   output [31:0] debug,
+   output [1:0] debug_clk,
+
+   // GPIF, FX3 Slave FIFO
+   output IFCLK,        // pclk
+   input FX3_EXTINT,
+   output GPIF_CTL0,    // n_slcs
+   output GPIF_CTL1,    // n_slwr
+   output GPIF_CTL2,    // n_sloe
+   output GPIF_CTL3,    // n_slrd
+   output GPIF_CTL7,    // n_pktend
+   input GPIF_CTL4,     // slfifo_flags[0]
+   input GPIF_CTL5,     // slfifo_flags[1]
+   input GPIF_CTL6,     // slfifo_flags[2]
+   input GPIF_CTL8,     // slfifo_flags[3]
+   output GPIF_CTL11,   // slfifo_addr[1]
+   output GPIF_CTL12,   // slfifo_addr[0]
+   inout [31:0] GPIF_D,
+   input GPIF_CTL9,     // global_reset
+
+   // GPS
+   input gps_lock,
+   output gps_rxd,
+   input gps_txd,
+   input gps_txd_nmea,
+
+   // LEDS
+   output LED_RX1,
+   output LED_RX2,
+   output LED_TXRX1_RX,
+   output LED_TXRX1_TX,
+   output LED_TXRX2_RX,
+   output LED_TXRX2_TX,
+
+   // Misc Hardware Control
+   output ref_sel,
+   input pll_lock,
+   input FPGA_CFG_CS,           // Driven by FX3 gpio.
+   input AUX_PWR_ON,            // Driven by FX3 gpio.
+
+   // PPS
+   input PPS_IN_EXT,
+   input PPS_IN_INT,
+
+   // RF Hardware Control
+   output SFDX1_RX,
+   output SFDX1_TX,
+   output SFDX2_RX,
+   output SFDX2_TX,
+   output SRX1_RX,
+   output SRX1_TX,
+   output SRX2_RX,
+   output SRX2_TX,
+   output tx_bandsel_a,
+   output tx_bandsel_b,
+   output tx_enable1,
+   output tx_enable2,
+   output rx_bandsel_a,
+   output rx_bandsel_b,
+   output rx_bandsel_c
+   );
+
+    wire reset_global = GPIF_CTL9;
+
+    ///////////////////////////////////////////////////////////////////////
+    // generate clocks from always on codec main clk
+    ///////////////////////////////////////////////////////////////////////
+    wire bus_clk, gpif_clk, radio_clk;
+    wire locked;
+    b200_clk_gen gen_clks
+    (
+        .CLK_IN1_40_P(codec_main_clk_p), .CLK_IN1_40_N(codec_main_clk_n),
+        .CLK_OUT1_40_int(), .CLK_OUT2_100_gpif(gpif_clk), .CLK_OUT3_100_bus(bus_clk),
+        .RESET(reset_global), .LOCKED(locked)
+    );
+
+    //hold-off logic for clocks ready
+    reg [15:0] clocks_ready_count;
+    reg clocks_ready;
+    always @(posedge bus_clk or posedge reset_global or negedge locked) begin
+        if (reset_global | !locked) begin
+            clocks_ready_count <= 16'b0;
+            clocks_ready <= 1'b0;
+        end
+        else if (!clocks_ready) begin
+            clocks_ready_count <= clocks_ready_count + 1'b1;
+            clocks_ready <= (clocks_ready_count == 16'hffff);
+        end
+    end
+
+    ///////////////////////////////////////////////////////////////////////
+    // drive output clocks
+    ///////////////////////////////////////////////////////////////////////
+    wire [1:0] debug_clk_int;
+    //S6CLK2PIN S6CLK2PIN_dbg0 (.I(debug_clk_int[0]), .O(debug_clk[0]));
+    //S6CLK2PIN S6CLK2PIN_dbg1 (.I(debug_clk_int[1]), .O(debug_clk[1]));
+    assign      debug_clk[1:0] = 2'b0;
+    S6CLK2PIN S6CLK2PIN_gpif (.I(gpif_clk), .O(IFCLK));
+   
+    ///////////////////////////////////////////////////////////////////////
+    // Create sync reset signals
+    ///////////////////////////////////////////////////////////////////////
+    wire gpif_rst, bus_rst, radio_rst;
+    reset_sync gpif_sync(.clk(gpif_clk), .reset_in(!clocks_ready), .reset_out(gpif_rst));
+    reset_sync bus_sync(.clk(bus_clk), .reset_in(!clocks_ready), .reset_out(bus_rst));
+    reset_sync radio_sync(.clk(radio_clk), .reset_in(!clocks_ready), .reset_out(radio_rst));
+
+   ///////////////////////////////////////////////////////////////////////
+   // CODEC capture/gen
+   ///////////////////////////////////////////////////////////////////////
+   wire [31:0] rx_data1, rx_data2;
+   wire [31:0] tx_data1, tx_data2;
+   wire mimo, codec_arst;
+
+   catcodec_ddr_cmos catcodec
+   (
+        .radio_clk(radio_clk), .arst(codec_arst), .mimo(mimo),
+        .rx1(rx_data1), .rx2(rx_data2), .tx1(tx_data1), .tx2(tx_data2),
+        .rx_clk(codec_data_clk_p), .rx_frame(rx_frame_p), .rx_d(rx_codec_d),
+        .tx_clk(codec_fb_clk_p), .tx_frame(tx_frame_p), .tx_d(tx_codec_d)
+   );
+
+   ///////////////////////////////////////////////////////////////////////
+   // SPI connections
+   ///////////////////////////////////////////////////////////////////////
+   wire mosi, miso, sclk; wire [7:0]  sen;
+   assign cat_ce = sen[0] & fx3_ce;
+   assign cat_mosi = (~sen[0] & mosi) | (~fx3_ce & fx3_mosi);
+   assign cat_sclk = (~sen[0] & sclk) | (~fx3_ce & fx3_sclk);
+   assign miso = cat_miso;
+   assign fx3_miso = ~fx3_ce & cat_miso;
+   assign pll_ce = sen[1];
+   assign pll_mosi = ~sen[1] & mosi;
+   assign pll_sclk = ~sen[1] & sclk;
+
+    ///////////////////////////////////////////////////////////////////////
+    // bus signals
+    ///////////////////////////////////////////////////////////////////////
+    wire [63:0] ctrl_tdata, resp_tdata, rx_tdata, tx_tdata;
+    wire ctrl_tlast, resp_tlast, rx_tlast, tx_tlast;
+    wire ctrl_tvalid, resp_tvalid, rx_tvalid, tx_tvalid;
+    wire ctrl_tready, resp_tready, rx_tready, tx_tready;
+
+    ///////////////////////////////////////////////////////////////////////
+    // loopback testers
+    ///////////////////////////////////////////////////////////////////////
+    /*
+    axi_fifo #(.WIDTH(65), .SIZE(13)) f0
+    (
+        .clk(bus_clk), .reset(bus_rst), .clear(1'b0),
+        .i_tdata({ctrl_tlast, ctrl_tdata}), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .space(),
+        .o_tdata({resp_tlast, resp_tdata}), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .occupied()
+    );
+    //*/
+
+    /*
+    axi_fifo #(.WIDTH(65), .SIZE(13)) f1
+    (
+        .clk(bus_clk), .reset(bus_rst), .clear(1'b0),
+        .i_tdata({tx_tlast, tx_tdata}), .i_tvalid(tx_tvalid), .i_tready(tx_tready), .space(),
+        .o_tdata({rx_tlast, rx_tdata}), .o_tvalid(rx_tvalid), .o_tready(rx_tready), .occupied()
+    );
+    //*/
+
+    ///////////////////////////////////////////////////////////////////////
+    // frontend assignments
+    ///////////////////////////////////////////////////////////////////////
+    wire [31:0] debug_radio;
+
+    wire [31:0] fe_atr1, fe_atr2;
+    assign {tx_enable1, SFDX1_RX, SFDX1_TX, SRX1_RX, SRX1_TX, LED_RX1, LED_TXRX1_RX, LED_TXRX1_TX} = fe_atr1[7:0];
+    assign {tx_enable2, SFDX2_RX, SFDX2_TX, SRX2_RX, SRX2_TX, LED_RX2, LED_TXRX2_RX, LED_TXRX2_TX} = fe_atr2[7:0];
+
+    wire [31:0] misc_outs; reg [31:0] misc_outs_r;
+    always @(posedge bus_clk) misc_outs_r <= misc_outs; //register misc ios to ease routing to flop
+    assign { tx_bandsel_a, tx_bandsel_b, rx_bandsel_a, rx_bandsel_b, rx_bandsel_c, codec_arst, mimo, ref_sel } = misc_outs_r[7:0];
+
+    assign codec_ctrl_in = 4'b1;
+    assign codec_en_agc = 1'b1;
+    assign codec_txrx = 1'b1;
+    assign codec_enable = 1'b1;
+    assign codec_reset = !reset_global;   // Codec Reset // RESETB // Operates active-low
+    assign codec_sync = 1'b0;
+
+    ///////////////////////////////////////////////////////////////////////
+    // b200 core
+    ///////////////////////////////////////////////////////////////////////
+    b200_core #(.EXTRA_BUFF_SIZE(12)) b200_xfusion_core
+    (
+        .bus_clk(bus_clk), .bus_rst(bus_rst),
+        .tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
+        .rx_tdata(rx_tdata), .rx_tlast(rx_tlast),  .rx_tvalid(rx_tvalid), .rx_tready(rx_tready),
+        .ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast),  .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready),
+        .resp_tdata(resp_tdata), .resp_tlast(resp_tlast),  .resp_tvalid(resp_tvalid), .resp_tready(resp_tready),
+
+        .radio_clk(radio_clk), .radio_rst(radio_rst),
+        .rx0(rx_data2), .rx1(rx_data1),
+        .tx0(tx_data2), .tx1(tx_data1),
+        .fe_atr0(fe_atr2), .fe_atr1(fe_atr1),
+        .pps_int(PPS_IN_INT), .pps_ext(PPS_IN_EXT),
+
+        .rxd(gps_txd), .txd(gps_rxd),
+        .sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso),
+        .rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs)
+    );
+
+    ///////////////////////////////////////////////////////////////////////
+    // GPIF2
+    ///////////////////////////////////////////////////////////////////////
+    wire [31:0] debug_gpif;
+
+    gpif2_slave_fifo32 #(.DATA_RX_FIFO_SIZE(14), .DATA_TX_FIFO_SIZE(14)) slave_fifo32
+    (
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_enb(1'b1),
+        .gpif_ctl({GPIF_CTL8, GPIF_CTL6, GPIF_CTL5, GPIF_CTL4}), .fifoadr({GPIF_CTL11,GPIF_CTL12}),
+        .slwr(GPIF_CTL1), .sloe(GPIF_CTL2), .slcs(GPIF_CTL0), .slrd(GPIF_CTL3), .pktend(GPIF_CTL7),
+        .gpif_d(GPIF_D),
+
+        .fifo_clk(bus_clk), .fifo_rst(bus_rst),
+        .tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
+        .rx_tdata(rx_tdata), .rx_tlast(rx_tlast),  .rx_tvalid(rx_tvalid), .rx_tready(rx_tready),
+        .ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast),  .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready),
+        .resp_tdata(resp_tdata), .resp_tlast(resp_tlast),  .resp_tvalid(resp_tvalid), .resp_tready(resp_tready),
+
+        .debug(debug_gpif)
+    );
+
+   ///////////////////////////////////////////////////////////////////////
+   // Debug port
+   ///////////////////////////////////////////////////////////////////////
+   assign debug_clk_int = { 1'b0, 1'b0 };
+   assign debug = 32'b0;
+
+endmodule // B200
diff --git a/fpga/usrp3/top/b200/b200_core.v b/fpga/usrp3/top/b200/b200_core.v
new file mode 100644
index 000000000..d17066366
--- /dev/null
+++ b/fpga/usrp3/top/b200/b200_core.v
@@ -0,0 +1,305 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+/***********************************************************
+ * B200 Core Guts
+ **********************************************************/
+module b200_core
+#(
+    parameter R0_CTRL_SID = 8'h10,
+    parameter R1_CTRL_SID = 8'h20,
+    parameter U0_CTRL_SID = 8'h30,
+    parameter L0_CTRL_SID = 8'h40,
+    parameter R0_DATA_SID = 8'h50,
+    parameter R1_DATA_SID = 8'h60,
+    parameter DEMUX_SID_MASK = 8'hf0,
+    parameter EXTRA_BUFF_SIZE = 0
+)
+(
+    ////////////////////////////////////////////////////////////////////
+    // bus interfaces
+    ////////////////////////////////////////////////////////////////////
+    input bus_clk,
+    input bus_rst,
+
+    input [63:0] tx_tdata, input tx_tlast, input tx_tvalid, output tx_tready,
+    output [63:0] rx_tdata, output rx_tlast, output rx_tvalid, input rx_tready,
+    input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output ctrl_tready,
+    output [63:0] resp_tdata, output resp_tlast, output resp_tvalid, input resp_tready,
+
+    ////////////////////////////////////////////////////////////////////
+    // radio interfaces
+    ////////////////////////////////////////////////////////////////////
+    input radio_clk,
+    input radio_rst,
+
+    input [31:0] rx0, input [31:0] rx1,
+    output [31:0] tx0, output [31:0] tx1,
+    inout [31:0] fe_atr0,
+    inout [31:0] fe_atr1,
+    input pps_int, input pps_ext,
+
+    ////////////////////////////////////////////////////////////////////
+    // gpsdo uart
+    ////////////////////////////////////////////////////////////////////
+    input rxd,
+    output txd,
+
+    ////////////////////////////////////////////////////////////////////
+    // core interfaces
+    ////////////////////////////////////////////////////////////////////
+    output [7:0] sen, output sclk, output mosi, input miso,
+    input [31:0] rb_misc,
+    output [31:0] misc_outs,
+
+    output [31:0] debug
+);
+    localparam SR_CORE_SPI       = 8'd8;
+    localparam SR_CORE_MISC      = 8'd16;
+    localparam SR_CORE_COMPAT    = 8'd24;
+    localparam SR_CORE_READBACK  = 8'd32;
+    localparam SR_CORE_GPSDO_ST  = 8'd40;
+    localparam SR_CORE_PPS_SEL   = 8'd48;
+    localparam COMPAT_MAJOR      = 16'h0002;
+    localparam COMPAT_MINOR      = 16'h0000;
+
+    /*******************************************************************
+     * PPS Timing stuff
+     ******************************************************************/
+    reg [1:0] 	 int_pps_del, ext_pps_del;
+    always @(posedge radio_clk) ext_pps_del[1:0] <= {ext_pps_del[0], pps_ext};
+    always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], pps_int};
+    wire pps_select;
+    wire pps = pps_select? ext_pps_del[1] : int_pps_del[1];
+
+    /*******************************************************************
+     * Response mux Routing logic
+     ******************************************************************/
+    wire [63:0] r0_resp_tdata; wire r0_resp_tlast, r0_resp_tvalid, r0_resp_tready;
+    wire [63:0] r1_resp_tdata; wire r1_resp_tlast, r1_resp_tvalid, r1_resp_tready;
+    wire [63:0] u0_resp_tdata; wire u0_resp_tlast, u0_resp_tvalid, u0_resp_tready;
+    wire [63:0] l0_resp_tdata; wire l0_resp_tlast, l0_resp_tvalid, l0_resp_tready;
+
+    axi_mux4 #(.WIDTH(64), .BUFFER(1)) mux_for_resp
+     (.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
+      .i0_tdata(r0_resp_tdata), .i0_tlast(r0_resp_tlast), .i0_tvalid(r0_resp_tvalid), .i0_tready(r0_resp_tready),
+      .i1_tdata(r1_resp_tdata), .i1_tlast(r1_resp_tlast), .i1_tvalid(r1_resp_tvalid), .i1_tready(r1_resp_tready),
+      .i2_tdata(u0_resp_tdata), .i2_tlast(u0_resp_tlast), .i2_tvalid(u0_resp_tvalid), .i2_tready(u0_resp_tready),
+      .i3_tdata(l0_resp_tdata), .i3_tlast(l0_resp_tlast), .i3_tvalid(l0_resp_tvalid), .i3_tready(l0_resp_tready),
+      .o_tdata(resp_tdata), .o_tlast(resp_tlast), .o_tvalid(resp_tvalid), .o_tready(resp_tready));
+
+    /*******************************************************************
+     * Control demux Routing logic
+     ******************************************************************/
+    wire [63:0] r0_ctrl_tdata; wire r0_ctrl_tlast, r0_ctrl_tvalid, r0_ctrl_tready;
+    wire [63:0] r1_ctrl_tdata; wire r1_ctrl_tlast, r1_ctrl_tvalid, r1_ctrl_tready;
+    wire [63:0] u0_ctrl_tdata; wire u0_ctrl_tlast, u0_ctrl_tvalid, u0_ctrl_tready;
+    wire [63:0] l0_ctrl_tdata; wire l0_ctrl_tlast, l0_ctrl_tvalid, l0_ctrl_tready;
+
+    wire [63:0] ctrl_hdr;
+    wire [1:0] ctrl_dst =
+        ((ctrl_hdr[7:0] & DEMUX_SID_MASK) == R0_CTRL_SID)? 0 : (
+        ((ctrl_hdr[7:0] & DEMUX_SID_MASK) == R1_CTRL_SID)? 1 : (
+        ((ctrl_hdr[7:0] & DEMUX_SID_MASK) == U0_CTRL_SID)? 2 : (
+        ((ctrl_hdr[7:0] & DEMUX_SID_MASK) == L0_CTRL_SID)? 3 : (
+    3))));
+    axi_demux4 #(.ACTIVE_CHAN(4'b1111), .WIDTH(64), .BUFFER(1)) demux_for_ctrl
+     (.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
+      .header(ctrl_hdr), .dest(ctrl_dst),
+      .i_tdata(ctrl_tdata), .i_tlast(ctrl_tlast), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready),
+      .o0_tdata(r0_ctrl_tdata), .o0_tlast(r0_ctrl_tlast), .o0_tvalid(r0_ctrl_tvalid), .o0_tready(r0_ctrl_tready),
+      .o1_tdata(r1_ctrl_tdata), .o1_tlast(r1_ctrl_tlast), .o1_tvalid(r1_ctrl_tvalid), .o1_tready(r1_ctrl_tready),
+      .o2_tdata(u0_ctrl_tdata), .o2_tlast(u0_ctrl_tlast), .o2_tvalid(u0_ctrl_tvalid), .o2_tready(u0_ctrl_tready),
+      .o3_tdata(l0_ctrl_tdata), .o3_tlast(l0_ctrl_tlast), .o3_tvalid(l0_ctrl_tvalid), .o3_tready(l0_ctrl_tready));
+
+    /*******************************************************************
+     * UART
+     ******************************************************************/
+    wire [63:0] u0i_ctrl_tdata; wire u0i_ctrl_tlast, u0i_ctrl_tvalid, u0i_ctrl_tready;
+
+    axi_fifo #(.WIDTH(65), .SIZE(0)) ushart_timing_fifo
+    (
+        .clk(bus_clk), .reset(bus_rst), .clear(1'b0),
+        .i_tdata({u0_ctrl_tlast, u0_ctrl_tdata}), .i_tvalid(u0_ctrl_tvalid), .i_tready(u0_ctrl_tready), .space(),
+        .o_tdata({u0i_ctrl_tlast, u0i_ctrl_tdata}), .o_tvalid(u0i_ctrl_tvalid), .o_tready(u0i_ctrl_tready), .occupied()
+    );
+
+    cvita_uart #(.SIZE(7)) ushart
+    (
+        .clk(bus_clk), .rst(bus_rst), .rxd(rxd), .txd(txd),
+        .i_tdata(u0i_ctrl_tdata), .i_tlast(u0i_ctrl_tlast), .i_tvalid(u0i_ctrl_tvalid), .i_tready(u0i_ctrl_tready),
+        .o_tdata(u0_resp_tdata), .o_tlast(u0_resp_tlast), .o_tvalid(u0_resp_tvalid), .o_tready(u0_resp_tready)
+    );
+
+    /*******************************************************************
+     * Misc controls
+     ******************************************************************/
+    wire 	set_stb;
+    wire [7:0] 	set_addr;
+    wire [31:0] 	set_data;
+
+    wire spi_ready;
+    wire [31:0] spi_readback;
+
+    wire [7:0] gpsdo_st;
+    wire [7:0] radio_st;
+
+    wire [1:0] rb_addr;
+    reg [63:0] rb_data;
+
+    wire [63:0] l0i_ctrl_tdata; wire l0i_ctrl_tlast, l0i_ctrl_tvalid, l0i_ctrl_tready;
+
+    axi_fifo #(.WIDTH(65), .SIZE(0)) radio_ctrl_proc_timing_fifo
+    (
+        .clk(bus_clk), .reset(bus_rst), .clear(1'b0),
+        .i_tdata({l0_ctrl_tlast, l0_ctrl_tdata}), .i_tvalid(l0_ctrl_tvalid), .i_tready(l0_ctrl_tready), .space(),
+        .o_tdata({l0i_ctrl_tlast, l0i_ctrl_tdata}), .o_tvalid(l0i_ctrl_tvalid), .o_tready(l0i_ctrl_tready), .occupied()
+    );
+
+    radio_ctrl_proc radio_ctrl_proc
+     (.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
+      .ctrl_tdata(l0i_ctrl_tdata), .ctrl_tlast(l0i_ctrl_tlast), .ctrl_tvalid(l0i_ctrl_tvalid), .ctrl_tready(l0i_ctrl_tready),
+      .resp_tdata(l0_resp_tdata), .resp_tlast(l0_resp_tlast), .resp_tvalid(l0_resp_tvalid), .resp_tready(l0_resp_tready),
+      .vita_time(64'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .ready(spi_ready), .readback(rb_data),
+      .debug());
+
+    setting_reg #(.my_addr(SR_CORE_MISC), .awidth(8), .width(32), .at_reset(8'h0)) sr_misc
+     (.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(misc_outs), .changed());
+
+    setting_reg #(.my_addr(SR_CORE_READBACK), .awidth(8), .width(2)) sr_rdback
+     (.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(rb_addr), .changed());
+
+    setting_reg #(.my_addr(SR_CORE_GPSDO_ST), .awidth(8), .width(8)) sr_gpsdo_st
+     (.clk(bus_clk), .rst(1'b0/*keep*/), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(gpsdo_st), .changed());
+
+    setting_reg #(.my_addr(SR_CORE_PPS_SEL), .awidth(8), .width(1)) sr_pps_sel
+     (.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(pps_select), .changed());
+
+    simple_spi_core #(.BASE(SR_CORE_SPI), .WIDTH(8), .CLK_IDLE(0), .SEN_IDLE(8'hFF)) misc_spi
+     (.clock(bus_clk), .reset(bus_rst),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .readback(spi_readback), .ready(spi_ready),
+      .sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso),
+      .debug());
+
+    always @*
+     case(rb_addr)
+       2'd0 : rb_data <= { 32'hACE0BA5E, COMPAT_MAJOR, COMPAT_MINOR };
+       2'd1 : rb_data <= { 32'b0, spi_readback };
+       2'd2 : rb_data <= { 16'b0, radio_st, gpsdo_st, rb_misc };
+       default : rb_data <= 64'd0;
+     endcase // case (rb_addr)
+
+    /*******************************************************************
+     * RX Data mux Routing logic
+     ******************************************************************/
+    wire [63:0] r0_rx_tdata; wire r0_rx_tlast, r0_rx_tvalid, r0_rx_tready;
+    wire [63:0] r1_rx_tdata; wire r1_rx_tlast, r1_rx_tvalid, r1_rx_tready;
+    wire [63:0] rx_tdata_int; wire rx_tlast_int, rx_tvalid_int, rx_tready_int;
+
+    axi_mux4 #(.WIDTH(64), .BUFFER(1)) mux_for_rx
+     (.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
+      .i0_tdata(r0_rx_tdata), .i0_tlast(r0_rx_tlast), .i0_tvalid(r0_rx_tvalid), .i0_tready(r0_rx_tready),
+      .i1_tdata(r1_rx_tdata), .i1_tlast(r1_rx_tlast), .i1_tvalid(r1_rx_tvalid), .i1_tready(r1_rx_tready),
+      .i2_tdata(64'b0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(),
+      .i3_tdata(64'b0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(),
+      .o_tdata(rx_tdata_int), .o_tlast(rx_tlast_int), .o_tvalid(rx_tvalid_int), .o_tready(rx_tready_int));
+
+    axi_fifo #(.WIDTH(65), .SIZE(EXTRA_BUFF_SIZE)) extra_rx_buff
+     (.clk(bus_clk), .reset(bus_rst),
+      .i_tdata({rx_tlast_int, rx_tdata_int}), .i_tvalid(rx_tvalid_int), .i_tready(rx_tready_int),
+      .o_tdata({rx_tlast, rx_tdata}), .o_tvalid(rx_tvalid), .o_tready(rx_tready));
+
+    /*******************************************************************
+     * TX Data mux Routing logic
+     ******************************************************************/
+    wire [63:0] r0_tx_tdata; wire r0_tx_tlast, r0_tx_tvalid, r0_tx_tready;
+    wire [63:0] r1_tx_tdata; wire r1_tx_tlast, r1_tx_tvalid, r1_tx_tready;
+    wire [63:0] tx_tdata_int; wire tx_tlast_int, tx_tvalid_int, tx_tready_int;
+
+    axi_fifo #(.WIDTH(65), .SIZE(EXTRA_BUFF_SIZE)) extra_tx_buff
+     (.clk(bus_clk), .reset(bus_rst),
+      .i_tdata({tx_tlast, tx_tdata}), .i_tvalid(tx_tvalid), .i_tready(tx_tready),
+      .o_tdata({tx_tlast_int, tx_tdata_int}), .o_tvalid(tx_tvalid_int), .o_tready(tx_tready_int));
+
+    wire [63:0] tx_hdr;
+    wire [1:0] tx_dst =
+        ((tx_hdr[7:0] & DEMUX_SID_MASK) == R0_DATA_SID)? 0 : (
+        ((tx_hdr[7:0] & DEMUX_SID_MASK) == R1_DATA_SID)? 1 : (
+    3));
+    axi_demux4 #(.ACTIVE_CHAN(4'b0011), .WIDTH(64), .BUFFER(1)) demux_for_tx
+     (.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
+      .header(tx_hdr), .dest(tx_dst),
+      .i_tdata(tx_tdata_int), .i_tlast(tx_tlast_int), .i_tvalid(tx_tvalid_int), .i_tready(tx_tready_int),
+      .o0_tdata(r0_tx_tdata), .o0_tlast(r0_tx_tlast), .o0_tvalid(r0_tx_tvalid), .o0_tready(r0_tx_tready),
+      .o1_tdata(r1_tx_tdata), .o1_tlast(r1_tx_tlast), .o1_tvalid(r1_tx_tvalid), .o1_tready(r1_tx_tready),
+      .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1),
+      .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1));
+
+    /*******************************************************************
+     * Radio 0
+     ******************************************************************/
+    radio_b200 #(.FIFO_SIZE(13)) the_radio
+    (
+        .radio_clk(radio_clk), .radio_rst(radio_rst),
+        .rx(rx0), .tx(tx0), .fe_atr(fe_atr0), .pps(pps),
+
+        .bus_clk(bus_clk), .bus_rst(bus_rst),
+        .tx_tdata(r0_tx_tdata), .tx_tlast(r0_tx_tlast), .tx_tvalid(r0_tx_tvalid), .tx_tready(r0_tx_tready),
+        .rx_tdata(r0_rx_tdata), .rx_tlast(r0_rx_tlast),  .rx_tvalid(r0_rx_tvalid), .rx_tready(r0_rx_tready),
+        .ctrl_tdata(r0_ctrl_tdata), .ctrl_tlast(r0_ctrl_tlast),  .ctrl_tvalid(r0_ctrl_tvalid), .ctrl_tready(r0_ctrl_tready),
+        .resp_tdata(r0_resp_tdata), .resp_tlast(r0_resp_tlast),  .resp_tvalid(r0_resp_tvalid), .resp_tready(r0_resp_tready),
+
+        .debug()
+    );
+
+    /*******************************************************************
+     * Radio 1
+     ******************************************************************/
+    `ifdef B200_CAN_HAZ_R1
+    assign radio_st = 8'h2;
+
+    radio_b200 #(.FIFO_SIZE(13)) the_radio_1
+    (
+        .radio_clk(radio_clk), .radio_rst(radio_rst),
+        .rx(rx1), .tx(tx1), .fe_atr(fe_atr1), .pps(pps),
+
+        .bus_clk(bus_clk), .bus_rst(bus_rst),
+        .tx_tdata(r1_tx_tdata), .tx_tlast(r1_tx_tlast), .tx_tvalid(r1_tx_tvalid), .tx_tready(r1_tx_tready),
+        .rx_tdata(r1_rx_tdata), .rx_tlast(r1_rx_tlast),  .rx_tvalid(r1_rx_tvalid), .rx_tready(r1_rx_tready),
+        .ctrl_tdata(r1_ctrl_tdata), .ctrl_tlast(r1_ctrl_tlast),  .ctrl_tvalid(r1_ctrl_tvalid), .ctrl_tready(r1_ctrl_tready),
+        .resp_tdata(r1_resp_tdata), .resp_tlast(r1_resp_tlast),  .resp_tvalid(r1_resp_tvalid), .resp_tready(r1_resp_tready),
+
+        .debug()
+    );
+
+    `else
+    assign radio_st = 8'h1;
+
+    //assign undriven outputs
+    assign fe_atr1 = 8'b0;
+    assign tx1 = 32'b0;
+
+    //unused control signals -- leave in loopback
+    assign r1_resp_tdata = r1_ctrl_tdata;
+    assign r1_resp_tlast = r1_ctrl_tlast;
+    assign r1_resp_tvalid = r1_ctrl_tvalid;
+    assign r1_ctrl_tready = r1_resp_tready;
+
+    //unused data signals -- leave in loopback
+    assign r1_rx_tdata = r1_tx_tdata;
+    assign r1_rx_tlast = r1_tx_tlast;
+    assign r1_rx_tvalid = r1_tx_tvalid;
+    assign r1_tx_tready = r1_tx_tready;
+
+    `endif
+
+endmodule // b200_core
diff --git a/fpga/usrp3/top/b200/catcap_ddr_cmos.v b/fpga/usrp3/top/b200/catcap_ddr_cmos.v
new file mode 100644
index 000000000..70ab94ef1
--- /dev/null
+++ b/fpga/usrp3/top/b200/catcap_ddr_cmos.v
@@ -0,0 +1,68 @@
+
+
+module catcap_ddr_cmos
+  (input data_clk,
+   input reset,
+   input mimo,
+   input rx_frame,
+   input [11:0] rx_d,
+   output rx_clk, output rx_strobe,
+   output reg [11:0] i0, output reg [11:0] q0,
+   output reg [11:0] i1, output reg [11:0] q1);
+   
+   //IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
+   //clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
+
+   wire [11:0] i,q;
+   wire frame_0, frame_1;
+   
+   genvar 	 z;
+   
+   generate
+      for(z = 0; z < 12; z = z + 1)
+	begin : gen_pins
+	   IDDR2 #(.DDR_ALIGNMENT("C0")) iddr2
+	     (.Q0(q[z]), .Q1(i[z]), .C0(data_clk), .C1(~data_clk),
+	      .CE(1'b1), .D(rx_d[z]), .R(1'b0), .S(1'b0));
+	end
+   endgenerate
+   IDDR2 #(.DDR_ALIGNMENT("C0")) iddr2_frame
+     (.Q0(frame_0), .Q1(frame_1), .C0(data_clk), .C1(~data_clk),
+      .CE(1'b1), .D(rx_frame), .R(1'b0), .S(1'b0));
+
+   reg frame_d1, frame_d2;
+   always @(posedge data_clk)
+     if(reset)
+       { frame_d2, frame_d1 } <= 0;
+     else if(~mimo)
+       { frame_d2, frame_d1 } <= { frame_1, 1'b0 };
+     else
+       { frame_d2, frame_d1 } <= { frame_d1, frame_1 };
+   
+   assign rx_strobe = frame_d2;
+
+   reg [11:0] i_del, q_del;
+   always @(posedge data_clk)
+     if(mimo)
+       if(frame_0)
+	 begin
+	    i_del <= i;
+	    q_del <= q;
+	 end
+       else
+	 begin
+	    i1 <= i;
+	    q1 <= q;
+	    i0 <= i_del;
+	    q0 <= q_del;
+	 end
+     else
+       begin
+	  i0 <= i;
+	  q0 <= q;
+	  i1 <= i;
+	  q1 <= q;
+       end
+   assign rx_clk = data_clk;
+   
+endmodule // catcap_ddr_cmos
diff --git a/fpga/usrp3/top/b200/catcap_tb.build b/fpga/usrp3/top/b200/catcap_tb.build
new file mode 100755
index 000000000..827ab0628
--- /dev/null
+++ b/fpga/usrp3/top/b200/catcap_tb.build
@@ -0,0 +1,21 @@
+
+#!/bin/sh
+
+rm -rf isim* 
+rm -rf catcap_tb
+rm -rf fuse*
+\
+#     --sourcelibdir ../../models \
+
+vlogcomp \
+    --sourcelibext .v \
+    --sourcelibdir ../../coregen \
+    --sourcelibdir ../../control_lib \
+    --sourcelibdir . \
+    --sourcelibdir $XILINX/verilog/src \
+    --sourcelibdir $XILINX/verilog/src/unisims \
+    --work work \
+    catcap_tb.v
+
+ 
+fuse -o catcap_tb catcap_tb
\ No newline at end of file
diff --git a/fpga/usrp3/top/b200/catcap_tb.v b/fpga/usrp3/top/b200/catcap_tb.v
new file mode 100644
index 000000000..f91830506
--- /dev/null
+++ b/fpga/usrp3/top/b200/catcap_tb.v
@@ -0,0 +1,109 @@
+`timescale 1ns/1ps
+
+module catcap_tb();
+
+   wire GSR, GTS;
+   glbl glbl( );
+
+   reg 	clk    = 0;
+   reg 	ddrclk = 0;
+   reg 	reset  = 1;
+
+   always #100 clk = ~clk;
+   always @(negedge clk) ddrclk <= ~ddrclk;
+
+   initial $dumpfile("catcap_tb.vcd");
+   initial $dumpvars(0,catcap_tb);
+
+   wire [11:0] i0 = {4'hA,count};
+   wire [11:0] q0 = {4'hB,count};
+   wire [11:0] i1 = {4'hC,count};
+   wire [11:0] q1 = {4'hD,count};
+
+   reg 	       mimo;
+   reg [11:0]  pins;
+   reg 	       frame;
+   reg [7:0]   count;
+   
+   initial
+     begin
+	#1000 reset = 0;
+	MIMO_BURST(4);
+	MIMO_BURST(5);
+	BURST(4);
+	BURST(5);
+	#2000;
+	$finish;
+     end
+   
+   task BURST;
+      input [7:0] len;
+      begin
+	 frame <= 0;
+	 @(posedge clk);
+	 @(posedge clk);
+	 mimo <= 0;
+	 @(posedge clk);
+	 @(posedge clk);
+	 @(posedge clk);
+	 @(posedge ddrclk);
+	 count <= 0;
+	 repeat(len)
+	   begin
+	      @(posedge clk);
+	      pins <= i0;
+	      frame <= 1;
+	      @(posedge clk);
+	      pins <= q0;
+	      frame <= 0;
+	      count <= count + 1;
+	   end
+      end
+   endtask // BURST
+   
+   task MIMO_BURST;
+      input [7:0] len;
+      begin
+	 frame <= 0;
+	 @(posedge clk);
+	 @(posedge clk);
+	 mimo <= 1;
+	 @(posedge clk);
+	 @(posedge clk);
+	 @(posedge clk);
+	 @(posedge ddrclk);
+	 count <= 0;
+	 repeat(len)
+	   begin
+	      @(posedge clk);
+	      pins <= i0;
+	      frame <= 1;
+	      @(posedge clk);
+	      pins <= q0;
+	      @(posedge clk);
+	      pins <= i1;
+	      frame <= 0;
+	      @(posedge clk);
+	      pins <= q1;
+	      count <= count + 1;
+	   end
+	 @(posedge clk);
+	 @(posedge clk);
+      end
+   endtask // MIMO_BURST
+      
+   wire        rx_clk, rx_strobe;
+   wire [11:0] i0o,i1o,q0o,q1o;
+   
+   catcap_ddr_cmos catcap
+     (.data_clk(ddrclk),
+      .reset(reset),
+      .mimo(mimo),
+      .rx_frame(frame),
+      .rx_d(pins),
+      .rx_clk(rx_clk),
+      .rx_strobe(rx_strobe),
+      .i0(i0o),.q0(q0o),
+      .i1(i1o),.q1(q1o));
+   
+endmodule // hb_chain_tb
diff --git a/fpga/usrp3/top/b200/catcodec_ddr_cmos.v b/fpga/usrp3/top/b200/catcodec_ddr_cmos.v
new file mode 100644
index 000000000..133267a56
--- /dev/null
+++ b/fpga/usrp3/top/b200/catcodec_ddr_cmos.v
@@ -0,0 +1,85 @@
+
+
+module catcodec_ddr_cmos
+(
+   //output source sync clock for baseband data
+   output radio_clk,
+
+   //async reset for clocking
+   input arst,
+
+   //control mimo mode
+   input mimo,
+
+   //baseband sample interface
+   output reg [31:0] rx1,
+   output reg [31:0] rx2,
+   input [31:0] tx1,
+   input [31:0] tx2,
+
+   //capture interface
+   input rx_clk,
+   input rx_frame,
+   input [11:0] rx_d,
+
+   //generate interface
+   output tx_clk,
+   output tx_frame,
+   output [11:0] tx_d
+);
+
+   //rx_clk to DCM - creates codec_clk and codec_clk/2
+   wire clk0, clkdv;
+   wire locked;
+   wire codec_rst = !locked;
+
+   DCM_SP #(
+        .CLKDV_DIVIDE(2),
+        .CLK_FEEDBACK("1X")
+   ) DCM_SP_codec_clk
+   (
+        .RST(arst),
+        .CLKIN(rx_clk), .CLKFB(clk0),
+        .CLK0(clk0), .CLKDV(clkdv),
+        .LOCKED(locked)
+   );
+
+   wire codec_clk, half_clk;
+   BUFG BUFG_codec_clk(.I(clk0), .O(codec_clk));
+   BUFG BUFG_half_clk(.I(clkdv), .O(half_clk));
+   BUFGMUX BUFGMUX_radio_clk (.I0(codec_clk), .I1(half_clk), .S(mimo), .O(radio_clk));
+
+   //make codec clock domain mimo mode signal
+   reg mimo_r;
+   always @(posedge codec_clk) mimo_r <= mimo;
+
+   //assign baseband sample interfaces
+   //all samples are registered on strobe
+   wire rx_strobe, tx_strobe;
+   wire [11:0] rx_i0, rx_q0, rx_i1, rx_q1;
+   reg [11:0] tx_i0, tx_q0, tx_i1, tx_q1;
+   //tx mux to feed single channel mode from either input
+   wire [31:0] txm = (mimo_r || (tx1 != 32'b0))? tx1: tx2;
+   always @(posedge codec_clk) begin
+        if (rx_strobe) rx2 <= {rx_i1, 4'b0, rx_q1, 4'b0};
+        if (rx_strobe) rx1 <= {rx_i0, 4'b0, rx_q0, 4'b0};
+        if (tx_strobe) {tx_i0, tx_q0} <= {txm[31:20], txm[15:4]};
+        if (tx_strobe) {tx_i1, tx_q1} <= {tx2[31:20], tx2[15:4]};
+   end
+
+   // CMOS Data interface to catalina, ignore _n pins
+   catcap_ddr_cmos catcap
+     (.data_clk(codec_clk), .reset(codec_rst), .mimo(mimo_r),
+      .rx_frame(rx_frame), .rx_d(rx_d),
+      .rx_clk(/*out*/), .rx_strobe(rx_strobe),
+      .i0(rx_i0), .q0(rx_q0),
+      .i1(rx_i1), .q1(rx_q1));
+
+   catgen_ddr_cmos catgen
+     (.data_clk(tx_clk), .reset(codec_rst), .mimo(mimo_r),
+      .tx_frame(tx_frame), .tx_d(tx_d),
+      .tx_clk(codec_clk), .tx_strobe(tx_strobe),
+      .i0(tx_i0), .q0(tx_q0),
+      .i1(tx_i1), .q1(tx_q1));
+
+endmodule // catcodec_ddr_cmos
diff --git a/fpga/usrp3/top/b200/catgen_ddr_cmos.v b/fpga/usrp3/top/b200/catgen_ddr_cmos.v
new file mode 100644
index 000000000..370ff4c95
--- /dev/null
+++ b/fpga/usrp3/top/b200/catgen_ddr_cmos.v
@@ -0,0 +1,49 @@
+
+
+module catgen_ddr_cmos
+  (output data_clk,
+   input reset,
+   input mimo,
+   output tx_frame,
+   output [11:0] tx_d,
+   input tx_clk, output reg tx_strobe,
+   input [11:0] i0, input [11:0] q0,
+   input [11:0] i1, input [11:0] q1);
+   
+   //IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
+   //clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
+
+   reg [11:0] 	i,q;
+   genvar 	z;
+   reg 		tx_strobe_d;
+   
+   generate
+      for(z = 0; z < 12; z = z + 1)
+	begin : gen_pins
+	   ODDR2 #(.DDR_ALIGNMENT("C0"),.SRTYPE("ASYNC")) oddr2
+	     (.Q(tx_d[z]), .C0(tx_clk), .C1(~tx_clk),
+	      .CE(1'b1), .D0(i[z]), .D1(q[z]), .R(1'b0), .S(1'b0));
+	end
+   endgenerate
+
+   ODDR2 #(.DDR_ALIGNMENT("C0"),.SRTYPE("ASYNC")) oddr2_frame
+     (.Q(tx_frame), .C0(tx_clk), .C1(~tx_clk),
+      .CE(1'b1), .D0(tx_strobe_d), .D1(mimo&tx_strobe_d), .R(1'b0), .S(1'b0));
+
+   ODDR2 #(.DDR_ALIGNMENT("C0"),.SRTYPE("ASYNC")) oddr2_clk
+     (.Q(data_clk), .C0(tx_clk), .C1(~tx_clk),
+      .CE(1'b1), .D0(1'b1), .D1(1'b0), .R(1'b0), .S(1'b0));
+
+   always @(posedge tx_clk)
+     tx_strobe <= (mimo)? ~tx_strobe : 1'b1;
+
+   always @(posedge tx_clk)
+     tx_strobe_d <= tx_strobe;
+   
+   always @(posedge tx_clk)
+     if(tx_strobe)
+       {i,q} <= {i0,q0};
+     else
+       {i,q} <= {i1,q1};
+   
+endmodule // catgen_ddr_cmos
diff --git a/fpga/usrp3/top/b200/catgen_tb.build b/fpga/usrp3/top/b200/catgen_tb.build
new file mode 100755
index 000000000..072495479
--- /dev/null
+++ b/fpga/usrp3/top/b200/catgen_tb.build
@@ -0,0 +1,21 @@
+
+#!/bin/sh
+
+rm -rf isim* 
+rm -rf catgen_tb
+rm -rf fuse*
+\
+#     --sourcelibdir ../../models \
+
+vlogcomp \
+    --sourcelibext .v \
+    --sourcelibdir ../../coregen \
+    --sourcelibdir ../../control_lib \
+    --sourcelibdir . \
+    --sourcelibdir $XILINX/verilog/src \
+    --sourcelibdir $XILINX/verilog/src/unisims \
+    --work work \
+    catgen_tb.v
+
+ 
+fuse -o catgen_tb catgen_tb
\ No newline at end of file
diff --git a/fpga/usrp3/top/b200/catgen_tb.v b/fpga/usrp3/top/b200/catgen_tb.v
new file mode 100644
index 000000000..bc8045a64
--- /dev/null
+++ b/fpga/usrp3/top/b200/catgen_tb.v
@@ -0,0 +1,97 @@
+`timescale 1ns/1ps
+
+module catgen_tb();
+
+   wire GSR, GTS;
+   glbl glbl( );
+
+   reg 	clk    = 0;
+   reg 	reset  = 1;
+   wire ddrclk;
+   
+   always #100 clk = ~clk;
+
+   initial $dumpfile("catgen_tb.vcd");
+   initial $dumpvars(0,catgen_tb);
+
+   wire [11:0] pins;
+   wire        frame;
+   
+   reg 	       mimo;
+   reg [7:0]   count;
+   reg 	       tx_strobe;
+   
+   wire [11:0] i0 = {4'hA,count};
+   wire [11:0] q0 = {4'hB,count};
+   wire [11:0] i1 = {4'hC,count};
+   wire [11:0] q1 = {4'hD,count};
+
+   initial
+     begin
+	#1000 reset = 0;
+	BURST(4);
+	BURST(5);
+	MIMO_BURST(4);
+	MIMO_BURST(5);
+	#2000;
+	$finish;
+     end
+   
+   task BURST;
+      input [7:0] len;
+
+      begin
+	 tx_strobe <= 0;
+	 mimo <= 0;
+	 count <= 0;
+	 @(posedge clk);
+	 @(posedge clk);
+	 repeat(len)
+	   begin
+	      tx_strobe <= 1;
+	      @(posedge clk);
+	      count <= count + 1;
+	   end
+	 tx_strobe <= 0;
+	 @(posedge clk);
+	 @(posedge clk);
+	 @(posedge clk);
+      end
+   endtask // BURST
+   
+   task MIMO_BURST;
+      input [7:0] len;
+
+      begin
+	 tx_strobe <= 0;
+	 mimo <= 1;
+	 count <= 0;
+	 @(posedge clk);
+	 @(posedge clk);
+	 repeat(len)
+	   begin
+	      tx_strobe <= 1;
+	      @(posedge clk);
+	      tx_strobe <= 0;
+	      @(posedge clk);
+	      count <= count + 1;
+	   end
+	 tx_strobe <= 0;
+	 @(posedge clk);
+	 @(posedge clk);
+	 @(posedge clk);
+      end
+   endtask // BURST
+   
+   catgen_ddr_cmos catgen
+     (.data_clk(ddrclk),
+      .reset(reset),
+      .mimo(mimo),
+      .tx_frame(frame),
+      .tx_d(pins),
+      .tx_clk(clk),
+      .tx_strobe(tx_strobe),
+      .i0(i0),.q0(q0),
+      .i1(i1),.q1(q1));
+   
+endmodule // hb_chain_tb
diff --git a/fpga/usrp3/top/b200/check.sh b/fpga/usrp3/top/b200/check.sh
new file mode 100644
index 000000000..5935de883
--- /dev/null
+++ b/fpga/usrp3/top/b200/check.sh
@@ -0,0 +1 @@
+iverilog ../top/b200/b200.v -y control/ -y timing/ -y fifo/ -y vita/ -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ -y ../top/b200/ -y ../top/b200/coregen/ -y gpif2/ -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/XilinxCoreLib/ -Wall | grep -v timescale
diff --git a/fpga/usrp3/top/b200/core_compile b/fpga/usrp3/top/b200/core_compile
new file mode 100755
index 000000000..553e9c8ad
--- /dev/null
+++ b/fpga/usrp3/top/b200/core_compile
@@ -0,0 +1 @@
+iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif2/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac B200.v  2>&1   | grep -v timescale | grep -v coregen | grep -v models
diff --git a/fpga/usrp3/top/b200/coregen/.gitignore b/fpga/usrp3/top/b200/coregen/.gitignore
new file mode 100644
index 000000000..5f2f0dd7d
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/.gitignore
@@ -0,0 +1,3 @@
+/tmp
+/_xmsgs
+/*.log
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.asy b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.asy
new file mode 100644
index 000000000..eb4747f81
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.asy
@@ -0,0 +1,9 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 b200_chipscope_icon
+RECTANGLE Normal 32 32 544 864
+LINE Wide 576 112 544 112
+PIN 576 112 RIGHT 36
+PINATTR PinName control0[35:0]
+PINATTR Polarity BOTH
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
new file mode 100644
index 000000000..b83296f8e
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
@@ -0,0 +1,9 @@
+NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
+TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
+#Update Constraints
+NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
+NET "U0/iSHIFT_OUT" TIG ;
+TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
+TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
+TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
+TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
new file mode 100644
index 000000000..903799425
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
@@ -0,0 +1,7 @@
+# icon XDC
+create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
+create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
+set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
+set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
+set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
+set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.gise b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.gise
new file mode 100644
index 000000000..d2bb766ed
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.gise
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="b200_chipscope_icon.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="b200_chipscope_icon.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="b200_chipscope_icon.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ncf b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ncf
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ngc b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ngc
new file mode 100644
index 000000000..d43ee8b57
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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3`=02c=57>5;h4b>5<<a?h1<75f6b83>>i?:3:17pll3;291?6=8r.2m796;I3;6>N6?m1/4>4>b79'2c<03`<26=44i7c94?=n>k0;66g9c;29?j>52900qom=:186>5<7s-3j6:74H0:1?M70l2.3?7?m6:&5b?0<a?31<75f6`83>>o1j3:17d8l:188k=4=831vnn?50;794?6|,0k1;45G1908L41c3-286<l9;%4e>0=n>00;66g9a;29?l0e2900e;m50;9l<7<722wio=4?:483>5}#1h0<56F>839K52b<,191=o84$7d90>o113:17d8n:188m3d=831b:n4?::m;6?6=3thij7>55;294~">i3=27E?72:J23a=#0:0:n;5+6g80?l0>2900e;o50;9j2g<722c=o7>5;n:1>5<<ukh36=4::183!?f2>30D<6=;I34`>"?;3;i:6*9f;08m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjm:1<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=9h80e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbe394?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(5751`08m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjmo1<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=90:0e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbed94?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(5751828m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjl:1<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=90;0e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbd394?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(5751838m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjl81<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=9080e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbd194?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(5751808m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjl>1<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=9090e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbd794?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(5751818m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjl<1<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=90>0e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbd594?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(5751868m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjl21<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=90?0e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbd;94?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(5751878m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjlk1<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=90=0e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbd`94?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(5751858m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjli1<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=9020e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbdf94?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(57518:8m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjlo1<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=9030e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbdd94?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(57518;8m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjm81<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=9h90e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbe194?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(5751`18m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjm>1<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=9h>0e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbe794?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(5751`68m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjm<1<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=91i0e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbe594?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(57519a8m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjm21<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=91n0e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbe;94?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(57519f8m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjmk1<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=91o0e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbe`94?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(57519g8m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjmi1<7;50;2x <g=?01C=5<4H05g?!>428h=7)8i:0;8 =?=91l0e;750;9j2d<722c=n7>5;h4`>5<<g181<75rbef94?3=83:p(4o5789K5=4<@8=o7)6<:0`5?!0a2830(57519d8m3?=831b:l4?::k5f?6=3`<h6=44o9094?=zjo;1<7=50;2x <g=?11C=5<4H05g?!>428h=7)8i:008 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\ No newline at end of file
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ucf
new file mode 100644
index 000000000..b83296f8e
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ucf
@@ -0,0 +1,9 @@
+NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
+TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
+#Update Constraints
+NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
+NET "U0/iSHIFT_OUT" TIG ;
+TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
+TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
+TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
+TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.v b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.v
new file mode 100644
index 000000000..30b31cca5
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.v
@@ -0,0 +1,27 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.4
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : b200_chipscope_icon.v
+// /___/   /\     Timestamp  : Tue Feb 19 14:28:40 PST 2013
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: Verilog Synthesis Wrapper
+///////////////////////////////////////////////////////////////////////////////
+// This wrapper is used to integrate with Project Navigator and PlanAhead
+
+`timescale 1ns/1ps
+
+module b200_chipscope_icon(
+    CONTROL0) /* synthesis syn_black_box syn_noprune=1 */;
+
+
+inout [35 : 0] CONTROL0;
+
+endmodule
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.veo b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.veo
new file mode 100644
index 000000000..6c82410b6
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.veo
@@ -0,0 +1,28 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.4
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : b200_chipscope_icon.veo
+// /___/   /\     Timestamp  : Tue Feb 19 14:28:40 PST 2013
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: ISE Instantiation template
+///////////////////////////////////////////////////////////////////////////////
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+b200_chipscope_icon YourInstanceName (
+    .CONTROL0(CONTROL0) // INOUT BUS [35:0]
+);
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xco b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xco
new file mode 100644
index 000000000..2b7395488
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xco
@@ -0,0 +1,56 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.4
+# Date: Tue Feb 19 22:27:58 2013
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fgg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
+# END Select
+# BEGIN Parameters
+CSET component_name=b200_chipscope_icon
+CSET constraint_type=external
+CSET enable_jtag_bufg=true
+CSET example_design=false
+CSET number_control_ports=1
+CSET use_ext_bscan=false
+CSET use_softbscan=false
+CSET use_unused_bscan=false
+CSET user_scan_chain=USER1
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-12-18T02:47:25Z
+# END Extra information
+GENERATE
+# CRC: 729764e8
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xdc
new file mode 100644
index 000000000..903799425
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xdc
@@ -0,0 +1,7 @@
+# icon XDC
+create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
+create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
+set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
+set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
+set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
+set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xise b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xise
new file mode 100644
index 000000000..4a695b8b0
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xise
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="b200_chipscope_icon.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="b200_chipscope_icon.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|b200_chipscope_icon" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="b200_chipscope_icon.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/b200_chipscope_icon" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="b200_chipscope_icon" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-02-19T14:28:45" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A24BB47ADAFD196B0AED5F1EDE7080BB" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_flist.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_flist.txt
new file mode 100644
index 000000000..97a36c09d
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_flist.txt
@@ -0,0 +1,15 @@
+# Output products list for <b200_chipscope_icon>
+b200_chipscope_icon.asy
+b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
+b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
+b200_chipscope_icon.gise
+b200_chipscope_icon.ngc
+b200_chipscope_icon.ucf
+b200_chipscope_icon.v
+b200_chipscope_icon.veo
+b200_chipscope_icon.xco
+b200_chipscope_icon.xdc
+b200_chipscope_icon.xise
+b200_chipscope_icon_flist.txt
+b200_chipscope_icon_readme.txt
+b200_chipscope_icon_xmdf.tcl
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_readme.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_readme.txt
new file mode 100644
index 000000000..c3b896f44
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_readme.txt
@@ -0,0 +1,45 @@
+The following files were generated for 'b200_chipscope_icon' in directory
+/home/bhilburn/xilinx/
+
+XCO file generator:
+   Generate an XCO file for compatibility with legacy flows.
+
+   * b200_chipscope_icon.xco
+
+Creates an implementation netlist:
+   Creates an implementation netlist for the IP.
+
+   * b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
+   * b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
+   * b200_chipscope_icon.ngc
+   * b200_chipscope_icon.ucf
+   * b200_chipscope_icon.v
+   * b200_chipscope_icon.veo
+   * b200_chipscope_icon.xdc
+   * b200_chipscope_icon_xmdf.tcl
+
+IP Symbol Generator:
+   Generate an IP symbol based on the current project options'.
+
+   * b200_chipscope_icon.asy
+
+Generate ISE subproject:
+   Create an ISE subproject for use when including this core in ISE designs
+
+   * b200_chipscope_icon.gise
+   * b200_chipscope_icon.xise
+
+Deliver Readme:
+   Readme file for the IP.
+
+   * b200_chipscope_icon_readme.txt
+
+Generate FLIST file:
+   Text file listing all of the output files produced when a customized core was
+   generated in the CORE Generator.
+
+   * b200_chipscope_icon_flist.txt
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_xmdf.tcl b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_xmdf.tcl
new file mode 100755
index 000000000..c9d1c0b14
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_xmdf.tcl
@@ -0,0 +1,88 @@
+# The package naming convention is <core_name>_xmdf
+package provide b200_chipscope_icon_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::b200_chipscope_icon_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::b200_chipscope_icon_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_chipscope_icon
+}
+# ::b200_chipscope_icon_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::b200_chipscope_icon_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.ncf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.xcf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_chipscope_icon
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
+
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.asy b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.asy
new file mode 100644
index 000000000..fcca7f4e0
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.asy
@@ -0,0 +1,21 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 b200_chipscope_ila
+RECTANGLE Normal 32 32 288 704
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName control[35:0]
+PINATTR Polarity IN
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName clk
+PINATTR Polarity IN
+LINE Wide 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName data[63:0]
+PINATTR Polarity IN
+LINE Wide 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName trig0[7:0]
+PINATTR Polarity IN
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.cdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.cdc
new file mode 100644
index 000000000..985834f8d
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.cdc
@@ -0,0 +1,83 @@
+#ChipScope Core Generator Project File Version 3.0
+#Tue Feb 19 16:52:47 PST 2013
+SignalExport.clockChannel=CLK
+SignalExport.dataChannel<0000>=DATA[0]
+SignalExport.dataChannel<0001>=DATA[1]
+SignalExport.dataChannel<0002>=DATA[2]
+SignalExport.dataChannel<0003>=DATA[3]
+SignalExport.dataChannel<0004>=DATA[4]
+SignalExport.dataChannel<0005>=DATA[5]
+SignalExport.dataChannel<0006>=DATA[6]
+SignalExport.dataChannel<0007>=DATA[7]
+SignalExport.dataChannel<0008>=DATA[8]
+SignalExport.dataChannel<0009>=DATA[9]
+SignalExport.dataChannel<0010>=DATA[10]
+SignalExport.dataChannel<0011>=DATA[11]
+SignalExport.dataChannel<0012>=DATA[12]
+SignalExport.dataChannel<0013>=DATA[13]
+SignalExport.dataChannel<0014>=DATA[14]
+SignalExport.dataChannel<0015>=DATA[15]
+SignalExport.dataChannel<0016>=DATA[16]
+SignalExport.dataChannel<0017>=DATA[17]
+SignalExport.dataChannel<0018>=DATA[18]
+SignalExport.dataChannel<0019>=DATA[19]
+SignalExport.dataChannel<0020>=DATA[20]
+SignalExport.dataChannel<0021>=DATA[21]
+SignalExport.dataChannel<0022>=DATA[22]
+SignalExport.dataChannel<0023>=DATA[23]
+SignalExport.dataChannel<0024>=DATA[24]
+SignalExport.dataChannel<0025>=DATA[25]
+SignalExport.dataChannel<0026>=DATA[26]
+SignalExport.dataChannel<0027>=DATA[27]
+SignalExport.dataChannel<0028>=DATA[28]
+SignalExport.dataChannel<0029>=DATA[29]
+SignalExport.dataChannel<0030>=DATA[30]
+SignalExport.dataChannel<0031>=DATA[31]
+SignalExport.dataChannel<0032>=DATA[32]
+SignalExport.dataChannel<0033>=DATA[33]
+SignalExport.dataChannel<0034>=DATA[34]
+SignalExport.dataChannel<0035>=DATA[35]
+SignalExport.dataChannel<0036>=DATA[36]
+SignalExport.dataChannel<0037>=DATA[37]
+SignalExport.dataChannel<0038>=DATA[38]
+SignalExport.dataChannel<0039>=DATA[39]
+SignalExport.dataChannel<0040>=DATA[40]
+SignalExport.dataChannel<0041>=DATA[41]
+SignalExport.dataChannel<0042>=DATA[42]
+SignalExport.dataChannel<0043>=DATA[43]
+SignalExport.dataChannel<0044>=DATA[44]
+SignalExport.dataChannel<0045>=DATA[45]
+SignalExport.dataChannel<0046>=DATA[46]
+SignalExport.dataChannel<0047>=DATA[47]
+SignalExport.dataChannel<0048>=DATA[48]
+SignalExport.dataChannel<0049>=DATA[49]
+SignalExport.dataChannel<0050>=DATA[50]
+SignalExport.dataChannel<0051>=DATA[51]
+SignalExport.dataChannel<0052>=DATA[52]
+SignalExport.dataChannel<0053>=DATA[53]
+SignalExport.dataChannel<0054>=DATA[54]
+SignalExport.dataChannel<0055>=DATA[55]
+SignalExport.dataChannel<0056>=DATA[56]
+SignalExport.dataChannel<0057>=DATA[57]
+SignalExport.dataChannel<0058>=DATA[58]
+SignalExport.dataChannel<0059>=DATA[59]
+SignalExport.dataChannel<0060>=DATA[60]
+SignalExport.dataChannel<0061>=DATA[61]
+SignalExport.dataChannel<0062>=DATA[62]
+SignalExport.dataChannel<0063>=DATA[63]
+SignalExport.dataEqualsTrigger=false
+SignalExport.dataPortWidth=64
+SignalExport.triggerChannel<0000><0000>=TRIG0[0]
+SignalExport.triggerChannel<0000><0001>=TRIG0[1]
+SignalExport.triggerChannel<0000><0002>=TRIG0[2]
+SignalExport.triggerChannel<0000><0003>=TRIG0[3]
+SignalExport.triggerChannel<0000><0004>=TRIG0[4]
+SignalExport.triggerChannel<0000><0005>=TRIG0[5]
+SignalExport.triggerChannel<0000><0006>=TRIG0[6]
+SignalExport.triggerChannel<0000><0007>=TRIG0[7]
+SignalExport.triggerPort<0000>.name=TRIG0
+SignalExport.triggerPortCount=1
+SignalExport.triggerPortIsData<0000>=false
+SignalExport.triggerPortWidth<0000>=8
+SignalExport.type=ila
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
new file mode 100644
index 000000000..e1ce12a9d
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
@@ -0,0 +1,17 @@
+#
+# Clock constraints
+#
+NET "CLK" TNM_NET = D_CLK ;
+INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
+TIMESPEC TS_D2_TO_T2_b200_chipscope_ila = FROM D2_CLK TO "FFS" TIG;
+TIMESPEC TS_J2_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J3_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J4_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
+
+#
+# Input keep/save net constraints
+#
+NET "TRIG0<*" S;
+NET "TRIG0<*" KEEP;
+NET "DATA<*" S;
+NET "DATA<*" KEEP;
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
new file mode 100644
index 000000000..49e2b9e7b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
@@ -0,0 +1,6 @@
+#
+# Clock constraints
+#
+set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
+set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
+set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.gise b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.gise
new file mode 100644
index 000000000..991df1547
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.gise
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="b200_chipscope_ila.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="b200_chipscope_ila.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="b200_chipscope_ila.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ncf b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ncf
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ngc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ngc
new file mode 100644
index 000000000..82baab030
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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>k;|l1e04=83;pD4>k;|l1e05=83;pD4>k;|l1e02=83;pD4>k;|l1e03=83;pD4>k;|l1e00=83;pD4>k;|l1e01=83;pD4>k;|l1e0>=83;pD4>k;|l1e0?=83;pD4>k;|l1e0g=83;pD4>k;|l1e0d=83;pD4>k;|l1e0e=83;pD4>k;|l1e0b=83;pD4>k;|l1e0c=83;pD4>k;|l1e0`=83;pD4>k;|l1e36=83;pD4>k;|l1e37=83;pD4>k;|l1e34=83;pD4>k;|l1e35=83;pD4>k;|l1e32=83;pD4>k;|l1e33=83;pD4>k;|l1e30=83;pD4>k;|l1e31=83;pD4>k;|l1e3>=83;pD4>k;|l1e3?=83;pD4>k;|l1e3g=83;pD4>k;|l1e3d=83;pD4>k;|l1e3e=83;pD4>k;|l1e3b=83;pD4>k;|l1e3c=83;pD4>k;|l1e3`=83;pD4>k;|l1e26=83;pD4>k;|l1e27=83;pD4>k;|l1e24=83;pD4>k;|l1e25=83;pD4>k;|l1e22=83;pD4>k;|l1e23=83;pD4>k;|l1e20=83;pD4>k;|l1e21=83;pD4>k;|l1e2>=83;pD4>k;|l1e2?=83;pD4>k;|l1e2g=83;pD4>k;|l1e2d=83;pD4>k;|l1e2e=83;pD4>k;|l1e2b=83;pD4>k;|l1e2c=83;pD4>k;|l1e2`=83;pD4>k;|l1e=6=83;pD4>k;|l1e=7=83;pD4>k;|l1e=4=83;pD4>k;|l1e=5=83;pD4>k;|l1e=2=83;pD4>k;|l1e=3=83;pD4>k;|l1e=0=83;pD4>k;|l1e=1=83;pD4>k;|l1e=>=83;pD4>k;|l1e=?=83;pD4>k;|l1e=g=83;pD4>k;|l1e=d=83;pD4>k;|l1e=e=83;pD4>k;|l1e=b=83;pD4>k;|l1e=c=83;pD4>k;|l1e=`=83;pD4>k;|l1e<6=83;pD4>k;|l1e<7=83;pD4>k;|l1e<4=83;pD4>k;|l1e<5=83;pD4>k;|l1e<2=83;pD4>k;|l1e<3=83;pD4>k;|l1e<0=83;pD4>k;|l1e<1=83;pD4>k;|l1e<>=83;pD4>k;|l1e<?=83;pD4>k;|l1e<g=83;pD4>k;|l1e<d=83;pD4>k;|l1e<e=83;pD4>k;|l1e<b=83;pD4>k;|l1e<c=83;pD4>k;|l1e<`=83;pD4>k;|l1ed6=83;pD4>k;|l1ed7=83;pD4>k;|l1ed4=83;pD4>k;|l1ed5=83;pD4>k;|l1ed2=83;pD4>k;|l1ed3=83;pD4>k;|l1ed0=83;pD4>k;|l1ed1=83;pD4>k;|l1ed>=83;pD4>k;|l1ed?=83;pD4>k;|l1edg=83;pD4>k;|l1edd=83;pD4>k;|l1ede=83;pD4>k;|l1edb=83;pD4>k;|l1edc=83;pD4>k;|l1ed`=83;pD4>k;|l1eg6=83;pD4>k;|l1eg7=83;pD4>k;|l1eg4=83;pD4>k;|l1eg5=83;pD4>k;|l1eg2=83;pD4>k;|l1eg3=83;pD4>k;|l1eg0=83;pD4>k;|l1eg1=83;pD4>k;|l1eg>=83;pD4>k;|l1eg?=83;pD4>k;|l1egg=83;pD4>k;|l1egd=83;pD4>k;|l1ege=83;pD4>k;|l1egb=83;pD4>k;|l1egc=83;pD4>k;|l1eg`=83;pD4>k;|l1ef6=83;pD4>k;|l1ef7=83;pD4>k;|l1ef4=83;pD4>k;|l1ef5=83;pD4>k;|l1ef2=83;pD4>k;|l1ef3=83;pD4>k;|l1ef0=83;pD4>k;|l1ef1=83;pD4>k;|l1ef>=83;pD4>k;|l1ef?=83;pD4>k;|l1efg=83;pD4>k;|l1efd=83;pD4>k;|l1efe=83;pD4>k;|l1efb=83;pD4>k;|l1efc=83;pD4>k;|l1ef`=83;pD4>k;|l1ea6=83;pD4>k;|l1ea7=83;pD4>k;|l1ea4=83;pD4>k;|l1ea5=83;pD4>k;|l1ea2=83;pD4>k;|l1ea3=83;pD4>k;|l1ea0=83;pD4>k;|l1ea1=83;pD4>k;|l1ea>=83;pD4>k;|l1ea?=83;pD4>k;|l1eag=83;pD4>k;|l1ead=83;pD4>k;|l1eae=83;pD4>k;|l1eab=83;pD4>k;|l1eac=83;pD4>k;|l1ea`=83;pD4>k;|l1e`6=83;pD4>k;|l1e`7=83;pD4>k;|l1e`4=83;pD4>k;|l1e`5=83;pD4>k;|l1e`2=83;pD4>k;|l1e`3=83;pD4>k;|l1e`0=83;pD4>k;|l1e`1=83;pD4>k;|l1e`>=83;pD4>k;|l1e`?=83;pD4>k;|l1e`g=83;pD4>k;|l1e`d=83;pD4>k;|l1e`e=83;pD4>k;|l1e`b=83;pD4>k;|l1e`c=83;pD4>k;|l1e``=83;pD4>k;|l1ec6=83;pD4>k;|l1ec7=83;pD4>k;|l1ec4=83;pD4>k;|l1ec5=83;pD4>k;|l1ec2=83;pD4>k;|l1ec3=83;pD4>k;|l1ec0=83;pD4>k;|l1ec1=83;pD4>k;|l1ec>=83;pD4>k;|l1ec?=83;pD4>k;|l1ecg=83;pD4>k;|l1ecd=83;pD4>k;|l1ece=83;pD4>k;|l1ecb=83;pD4>k;|l1ecc=83;pD4>k;|l1ec`=83;pD4>k;|l1f56=83;pD4>k;|l1f57=83;pD4>k;|l1f54=83;pD4>k;|l1f55=83;pD4>k;|l1f52=83;pD4>k;|l1f53=83;pD4>k;|l1f50=83;pD4>k;|l1f51=83;pD4>k;|l1f5>=83;pD4>k;|l1f5?=83;pD4>k;|l1f5g=83;pD4>k;|l1f5d=83;pD4>k;|l1f5e=83;pD4>k;|l1f5b=83;pD4>k;|l1f5c=83;pD4>k;|l1f5`=83;pD4>k;|l1f46=83;pD4>k;|l1f47=83;pD4>k;|l1f44=83;pD4>k;|l1f45=83;pD4>k;|l1f42=83;pD4>k;|l1f43=83;pD4>k;|l1f40=83;pD4>k;|l1f41=83;pD4>k;|l1f4>=83;pD4>k;|l1f4?=83;pD4>k;|l1f4g=83;pD4>k;|l1f4d=83;pD4>k;|l1f4e=83;pD4>k;|l1f4b=83;pD4>k;|l1f4c=83;pD4>k;|l1f4`=83;pD4>k;|l1f76=83;pD4>k;|l1f77=83;pD4>k;|l1f74=83;pD4>k;|l1f75=83;pD4>k;|l1f72=83;pD4>k;|l1f73=83;pD4>k;|l1f70=83;pD4>k;|l1f71=83;pD4>k;|l1f7>=83;pD4>k;|l1f7?=83;pD4>k;|l1f7g=83;pD4>k;|l1f7d=83;pD4>k;|l1f7e=83;pD4>k;|l1f7b=83;pD4>k;|l1f7c=83;pD4>k;|l1f7`=83;pD4>k;|l1f66=83;pD4>k;|l1f67=83;pD4>k;|l1f64=83;pD4>k;|l1f65=83;pD4>k;|l1f62=83;pD4>k;|l1f63=83;pD4>k;|l1f60=83;pD4>k;|l1f61=83;pD4>k;|l1f6>=83;pD4>k;|l1f6?=83;pD4>k;|l1f6g=83;pD4>k;|l1f6d=83;pD4>k;|l1f6e=83;pD4>k;|l1f6b=83;pD4>k;|l1f6c=83;pD4>k;|l1f6`=83;pD4>k;|l1f16=83;pD4>k;|l1f17=83;pD4>k;|l1f14=83;pD4>k;|l1f15=83;pD4>k;|l1f12=83;pD4>k;|l1f13=83;pD4>k;|l1f10=83;pD4>k;|l1f11=83;pD4>k;|l1f1>=83;pD4>k;|l1f1?=83;pD4>k;|l1f1g=83;pD4>k;|l1f1d=83;pD4>k;|l1f1e=83;pD4>k;|l1f1b=83;pD4>k;|l1f1c=83;pD4>k;|l1f1`=83;pD4>k;|l1f06=83;pD4>k;|l1f07=83;pD4>k;|l1f04=83;pD4>k;|l1f05=83;pD4>k;|l1f02=83;pD4>k;|l1f03=83;pD4>k;|l1f00=83;pD4>k;|l1f01=83;pD4>k;|l1f0>=83;pD4>k;|l1f0?=83;pD4>k;|l1f0g=83;pD4>k;|l1f0d=83;pD4>k;|l1f0e=83;pD4>k;|l1f0b=83;pD4>k;|l1f0c=83;pD4>k;|l1f0`=83;pD4>k;|l1f36=83;pD4>k;|l1f37=83;pD4>k;|l1f34=83;pD4>k;|l1f35=83;pD4>k;|l1f32=83;pD4>k;|l1f33=83;pD4>k;|l1f30=83;pD4>k;|l1f31=83;pD4>k;|l1f3>=83;pD4>k;|l1f3?=83;pD4>k;|l1f3g=83;pD4>k;|l1f3d=83;pD4>k;|l1f3e=83;pD4>k;|l1f3b=83;pD4>k;|l1f3c=83;pD4>k;|l1f3`=83;pD4>k;|l1f26=83;pD4>k;|l1f27=83;pD4>k;|l1f24=83;pD4>k;|l1f25=83;pD4>k;|l1f22=83;pD4>k;|l1f23=83;pD4>k;|l1f20=83;pD4>k;|l1f21=83;pD4>k;|l1f2>=83;pD4>k;|l1f2?=83;pD4>k;|l1f2g=83;pD4>k;|l1f2d=83;pD4>k;|l1f2e=83;pD4>k;|l1f2b=83;pD4>k;|l1f2c=83;pD4>k;|l1f2`=83;pD4>k;|l1f=6=83;pD4>k;|l1f=7=83;pD4>k;|l1f=4=83;pD4>k;|l1f=5=83;pD4>k;|l1f=2=83;pD4>k;|l1f=3=83;pD4>k;|l1f=0=83;pD4>k;|l1f=1=83;pD4>k;|l1f=>=83;pD4>k;|l1f=?=83;pD4>k;|l1f=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\ No newline at end of file
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ucf
new file mode 100644
index 000000000..e1ce12a9d
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ucf
@@ -0,0 +1,17 @@
+#
+# Clock constraints
+#
+NET "CLK" TNM_NET = D_CLK ;
+INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
+TIMESPEC TS_D2_TO_T2_b200_chipscope_ila = FROM D2_CLK TO "FFS" TIG;
+TIMESPEC TS_J2_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J3_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J4_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
+
+#
+# Input keep/save net constraints
+#
+NET "TRIG0<*" S;
+NET "TRIG0<*" KEEP;
+NET "DATA<*" S;
+NET "DATA<*" KEEP;
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.v b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.v
new file mode 100644
index 000000000..a9abb90e8
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.v
@@ -0,0 +1,33 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.4
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : b200_chipscope_ila.v
+// /___/   /\     Timestamp  : Tue Feb 19 16:52:47 PST 2013
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: Verilog Synthesis Wrapper
+///////////////////////////////////////////////////////////////////////////////
+// This wrapper is used to integrate with Project Navigator and PlanAhead
+
+`timescale 1ns/1ps
+
+module b200_chipscope_ila(
+    CONTROL,
+    CLK,
+    DATA,
+    TRIG0) /* synthesis syn_black_box syn_noprune=1 */;
+
+
+inout [35 : 0] CONTROL;
+input CLK;
+input [63 : 0] DATA;
+input [7 : 0] TRIG0;
+
+endmodule
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.veo b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.veo
new file mode 100644
index 000000000..f72d6853c
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.veo
@@ -0,0 +1,31 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.4
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : b200_chipscope_ila.veo
+// /___/   /\     Timestamp  : Tue Feb 19 16:52:47 PST 2013
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: ISE Instantiation template
+///////////////////////////////////////////////////////////////////////////////
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+b200_chipscope_ila YourInstanceName (
+    .CONTROL(CONTROL), // INOUT BUS [35:0]
+    .CLK(CLK), // IN
+    .DATA(DATA), // IN BUS [63:0]
+    .TRIG0(TRIG0) // IN BUS [7:0]
+);
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xco b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xco
new file mode 100644
index 000000000..ecae96127
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xco
@@ -0,0 +1,141 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.4
+# Date: Wed Feb 20 00:50:54 2013
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fgg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
+# END Select
+# BEGIN Parameters
+CSET check_bramcount=false
+CSET component_name=b200_chipscope_ila
+CSET constraint_type=external
+CSET counter_width_1=Disabled
+CSET counter_width_10=Disabled
+CSET counter_width_11=Disabled
+CSET counter_width_12=Disabled
+CSET counter_width_13=Disabled
+CSET counter_width_14=Disabled
+CSET counter_width_15=Disabled
+CSET counter_width_16=Disabled
+CSET counter_width_2=Disabled
+CSET counter_width_3=Disabled
+CSET counter_width_4=Disabled
+CSET counter_width_5=Disabled
+CSET counter_width_6=Disabled
+CSET counter_width_7=Disabled
+CSET counter_width_8=Disabled
+CSET counter_width_9=Disabled
+CSET data_port_width=64
+CSET data_same_as_trigger=false
+CSET disable_save_keep=false
+CSET enable_storage_qualification=true
+CSET enable_trigger_output_port=false
+CSET example_design=false
+CSET exclude_from_data_storage_1=true
+CSET exclude_from_data_storage_10=true
+CSET exclude_from_data_storage_11=true
+CSET exclude_from_data_storage_12=true
+CSET exclude_from_data_storage_13=true
+CSET exclude_from_data_storage_14=true
+CSET exclude_from_data_storage_15=true
+CSET exclude_from_data_storage_16=true
+CSET exclude_from_data_storage_2=true
+CSET exclude_from_data_storage_3=true
+CSET exclude_from_data_storage_4=true
+CSET exclude_from_data_storage_5=true
+CSET exclude_from_data_storage_6=true
+CSET exclude_from_data_storage_7=true
+CSET exclude_from_data_storage_8=true
+CSET exclude_from_data_storage_9=true
+CSET match_type_1=basic_with_edges
+CSET match_type_10=basic_with_edges
+CSET match_type_11=basic_with_edges
+CSET match_type_12=basic_with_edges
+CSET match_type_13=basic_with_edges
+CSET match_type_14=basic_with_edges
+CSET match_type_15=basic_with_edges
+CSET match_type_16=basic_with_edges
+CSET match_type_2=basic_with_edges
+CSET match_type_3=basic_with_edges
+CSET match_type_4=basic_with_edges
+CSET match_type_5=basic_with_edges
+CSET match_type_6=basic_with_edges
+CSET match_type_7=basic_with_edges
+CSET match_type_8=basic_with_edges
+CSET match_type_9=basic_with_edges
+CSET match_units_1=1
+CSET match_units_10=1
+CSET match_units_11=1
+CSET match_units_12=1
+CSET match_units_13=1
+CSET match_units_14=1
+CSET match_units_15=1
+CSET match_units_16=1
+CSET match_units_2=1
+CSET match_units_3=1
+CSET match_units_4=1
+CSET match_units_5=1
+CSET match_units_6=1
+CSET match_units_7=1
+CSET match_units_8=1
+CSET match_units_9=1
+CSET max_sequence_levels=1
+CSET number_of_trigger_ports=1
+CSET sample_data_depth=8192
+CSET sample_on=Rising
+CSET trigger_port_width_1=8
+CSET trigger_port_width_10=8
+CSET trigger_port_width_11=8
+CSET trigger_port_width_12=8
+CSET trigger_port_width_13=8
+CSET trigger_port_width_14=8
+CSET trigger_port_width_15=8
+CSET trigger_port_width_16=8
+CSET trigger_port_width_2=8
+CSET trigger_port_width_3=8
+CSET trigger_port_width_4=8
+CSET trigger_port_width_5=8
+CSET trigger_port_width_6=8
+CSET trigger_port_width_7=8
+CSET trigger_port_width_8=8
+CSET trigger_port_width_9=8
+CSET use_rpms=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-12-18T02:47:40Z
+# END Extra information
+GENERATE
+# CRC: 92d75d38
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xdc
new file mode 100644
index 000000000..49e2b9e7b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xdc
@@ -0,0 +1,6 @@
+#
+# Clock constraints
+#
+set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
+set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
+set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xise b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xise
new file mode 100644
index 000000000..2f85bcdc4
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xise
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="b200_chipscope_ila.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="b200_chipscope_ila.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|b200_chipscope_ila" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="b200_chipscope_ila.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/b200_chipscope_ila" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="b200_chipscope_ila" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-02-19T16:52:50" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1246592F65CAF06BF6A1D464FDE11DBE" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_flist.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_flist.txt
new file mode 100644
index 000000000..4dfd1b082
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_flist.txt
@@ -0,0 +1,18 @@
+# Output products list for <b200_chipscope_ila>
+_xmsgs/pn_parser.xmsgs
+b200_chipscope_ila.asy
+b200_chipscope_ila.cdc
+b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
+b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
+b200_chipscope_ila.gise
+b200_chipscope_ila.ncf
+b200_chipscope_ila.ngc
+b200_chipscope_ila.ucf
+b200_chipscope_ila.v
+b200_chipscope_ila.veo
+b200_chipscope_ila.xco
+b200_chipscope_ila.xdc
+b200_chipscope_ila.xise
+b200_chipscope_ila_flist.txt
+b200_chipscope_ila_readme.txt
+b200_chipscope_ila_xmdf.tcl
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_readme.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_readme.txt
new file mode 100644
index 000000000..28176abfb
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_readme.txt
@@ -0,0 +1,48 @@
+The following files were generated for 'b200_chipscope_ila' in directory
+/home/bhilburn/code/ettus/b200_dev/fpgapriv.git/usrp3/top/b200/coregen/
+
+XCO file generator:
+   Generate an XCO file for compatibility with legacy flows.
+
+   * b200_chipscope_ila.xco
+
+Creates an implementation netlist:
+   Creates an implementation netlist for the IP.
+
+   * b200_chipscope_ila.cdc
+   * b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
+   * b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
+   * b200_chipscope_ila.ncf
+   * b200_chipscope_ila.ngc
+   * b200_chipscope_ila.ucf
+   * b200_chipscope_ila.v
+   * b200_chipscope_ila.veo
+   * b200_chipscope_ila.xdc
+   * b200_chipscope_ila_xmdf.tcl
+
+IP Symbol Generator:
+   Generate an IP symbol based on the current project options'.
+
+   * b200_chipscope_ila.asy
+
+Generate ISE subproject:
+   Create an ISE subproject for use when including this core in ISE designs
+
+   * _xmsgs/pn_parser.xmsgs
+   * b200_chipscope_ila.gise
+   * b200_chipscope_ila.xise
+
+Deliver Readme:
+   Readme file for the IP.
+
+   * b200_chipscope_ila_readme.txt
+
+Generate FLIST file:
+   Text file listing all of the output files produced when a customized core was
+   generated in the CORE Generator.
+
+   * b200_chipscope_ila_flist.txt
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_xmdf.tcl b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_xmdf.tcl
new file mode 100755
index 000000000..a0922f3ec
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_xmdf.tcl
@@ -0,0 +1,87 @@
+# The package naming convention is <core_name>_xmdf
+package provide b200_chipscope_ila_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::b200_chipscope_ila_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::b200_chipscope_ila_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_chipscope_ila
+}
+# ::b200_chipscope_ila_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::b200_chipscope_ila_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.cdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
+incr fcount
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.ncf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_chipscope_ila
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.asy b/fpga/usrp3/top/b200/coregen/b200_clk_gen.asy
new file mode 100644
index 000000000..aad58f8d2
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.asy
@@ -0,0 +1,33 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 b200_clk_gen
+RECTANGLE Normal 32 32 576 1088
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName clk_in1_p
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName clk_in1_n
+PINATTR Polarity IN
+LINE Normal 0 432 32 432
+PIN 0 432 LEFT 36
+PINATTR PinName reset
+PINATTR Polarity IN
+LINE Normal 608 80 576 80
+PIN 608 80 RIGHT 36
+PINATTR PinName clk_out1
+PINATTR Polarity OUT
+LINE Normal 608 176 576 176
+PIN 608 176 RIGHT 36
+PINATTR PinName clk_out2
+PINATTR Polarity OUT
+LINE Normal 608 272 576 272
+PIN 608 272 RIGHT 36
+PINATTR PinName clk_out3
+PINATTR Polarity OUT
+LINE Normal 608 976 576 976
+PIN 608 976 RIGHT 36
+PINATTR PinName locked
+PINATTR Polarity OUT
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.gise b/fpga/usrp3/top/b200/coregen/b200_clk_gen.gise
new file mode 100644
index 000000000..70064d04f
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.gise
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="b200_clk_gen.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="b200_clk_gen.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="b200_clk_gen.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.ucf b/fpga/usrp3/top/b200/coregen/b200_clk_gen.ucf
new file mode 100755
index 000000000..e3776c72b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.ucf
@@ -0,0 +1,72 @@
+# file: b200_clk_gen.ucf
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+# Differential clock only needs one constraint
+NET "CLK_IN1_P" TNM_NET = "CLK_IN1_P";
+TIMESPEC "TS_CLK_IN1_P" = PERIOD "CLK_IN1_P" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps;
+
+# Derived clock periods. These are commented out because they are 
+#   automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you 
+#   can copy them into your module level timing checks
+#-----------------------------------------------------------------
+# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
+# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 40.000 MHz;
+
+# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
+# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz;
+# NET "clk_int[3]" TNM_NET = "CLK_OUT3";
+# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz;
+
+# FALSE PATH constraints 
+PIN "RESET" TIG;
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen.v
new file mode 100755
index 000000000..bb9a57dc2
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.v
@@ -0,0 +1,163 @@
+// file: b200_clk_gen.v
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+// "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+//----------------------------------------------------------------------------
+// CLK_OUT1____40.000______0.000______50.0______200.000____150.000
+// CLK_OUT2___100.000______0.000______50.0______400.000____150.000
+// CLK_OUT3___100.000______0.000______50.0______400.000____150.000
+//
+//----------------------------------------------------------------------------
+// "Input Clock   Freq (MHz)    Input Jitter (UI)"
+//----------------------------------------------------------------------------
+// __primary__________40.000____________0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "b200_clk_gen,clk_wiz_v3_6,{component_name=b200_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
+module b200_clk_gen
+ (// Clock in ports
+  input         CLK_IN1_40_P,
+  input         CLK_IN1_40_N,
+  // Clock out ports
+  output        CLK_OUT1_40_int,
+  output        CLK_OUT2_100_gpif,
+  output        CLK_OUT3_100_bus,
+  // Status and control signals
+  input         RESET,
+  output        LOCKED
+ );
+
+  // Input buffering
+  //------------------------------------
+  IBUFGDS clkin1_buf
+   (.O  (clkin1),
+    .I  (CLK_IN1_40_P),
+    .IB (CLK_IN1_40_N));
+
+
+  // Clocking primitive
+  //------------------------------------
+
+  // Instantiation of the DCM primitive
+  //    * Unused inputs are tied off
+  //    * Unused outputs are labeled unused
+  wire        psdone_unused;
+  wire        locked_int;
+  wire [7:0]  status_int;
+  wire clkfb;
+  wire clk0;
+  wire clkfx;
+
+  DCM_SP
+  #(.CLKDV_DIVIDE          (2.000),
+    .CLKFX_DIVIDE          (2),
+    .CLKFX_MULTIPLY        (5),
+    .CLKIN_DIVIDE_BY_2     ("FALSE"),
+    .CLKIN_PERIOD          (25.0),
+    .CLKOUT_PHASE_SHIFT    ("NONE"),
+    .CLK_FEEDBACK          ("1X"),
+    .DESKEW_ADJUST         ("SYSTEM_SYNCHRONOUS"),
+    .PHASE_SHIFT           (0),
+    .STARTUP_WAIT          ("FALSE"))
+  dcm_sp_inst
+    // Input clock
+   (.CLKIN                 (clkin1),
+    .CLKFB                 (clkfb),
+    // Output clocks
+    .CLK0                  (clk0),
+    .CLK90                 (),
+    .CLK180                (),
+    .CLK270                (),
+    .CLK2X                 (),
+    .CLK2X180              (),
+    .CLKFX                 (clkfx),
+    .CLKFX180              (),
+    .CLKDV                 (),
+    // Ports for dynamic phase shift
+    .PSCLK                 (1'b0),
+    .PSEN                  (1'b0),
+    .PSINCDEC              (1'b0),
+    .PSDONE                (),
+    // Other control and status signals
+    .LOCKED                (locked_int),
+    .STATUS                (status_int),
+ 
+    .RST                   (RESET),
+    // Unused pin- tie low
+    .DSSEN                 (1'b0));
+
+    assign LOCKED = locked_int;
+
+  // Output buffering
+  //-----------------------------------
+  assign clkfb = CLK_OUT1_40_int;
+
+  BUFG clkout1_buf
+   (.O   (CLK_OUT1_40_int),
+    .I   (clk0));
+
+
+  BUFG clkout2_buf
+   (.O   (CLK_OUT2_100_gpif),
+    .I   (clkfx));
+
+  BUFG clkout3_buf
+   (.O   (CLK_OUT3_100_bus),
+    .I   (clkfx));
+
+
+
+endmodule
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.veo b/fpga/usrp3/top/b200/coregen/b200_clk_gen.veo
new file mode 100755
index 000000000..111c02991
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.veo
@@ -0,0 +1,83 @@
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+// "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+//----------------------------------------------------------------------------
+// CLK_OUT1____40.000______0.000______50.0______200.000____150.000
+// CLK_OUT2___100.000______0.000______50.0______400.000____150.000
+// CLK_OUT3___100.000______0.000______50.0______400.000____150.000
+//
+//----------------------------------------------------------------------------
+// "Input Clock   Freq (MHz)    Input Jitter (UI)"
+//----------------------------------------------------------------------------
+// __primary__________40.000____________0.010
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+
+  b200_clk_gen instance_name
+   (// Clock in ports
+    .CLK_IN1_40_P(CLK_IN1_40_P),    // IN
+    .CLK_IN1_40_N(CLK_IN1_40_N),    // IN
+    // Clock out ports
+    .CLK_OUT1_40_int(CLK_OUT1_40_int),     // OUT
+    .CLK_OUT2_100_gpif(CLK_OUT2_100_gpif),     // OUT
+    .CLK_OUT3_100_bus(CLK_OUT3_100_bus),     // OUT
+    // Status and control signals
+    .RESET(RESET),// IN
+    .LOCKED(LOCKED));      // OUT
+// INST_TAG_END ------ End INSTANTIATION Template ---------
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.xco b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xco
new file mode 100644
index 000000000..96c8193b3
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xco
@@ -0,0 +1,269 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.4
+# Date: Fri Jan 25 20:00:48 2013
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:clk_wiz:3.6
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
+# END Select
+# BEGIN Parameters
+CSET calc_done=DONE
+CSET clk_in_sel_port=CLK_IN_SEL
+CSET clk_out1_port=CLK_OUT1_40_int
+CSET clk_out1_use_fine_ps_gui=false
+CSET clk_out2_port=CLK_OUT2_100_gpif
+CSET clk_out2_use_fine_ps_gui=false
+CSET clk_out3_port=CLK_OUT3_100_bus
+CSET clk_out3_use_fine_ps_gui=false
+CSET clk_out4_port=CLK_OUT4
+CSET clk_out4_use_fine_ps_gui=false
+CSET clk_out5_port=CLK_OUT5
+CSET clk_out5_use_fine_ps_gui=false
+CSET clk_out6_port=CLK_OUT6
+CSET clk_out6_use_fine_ps_gui=false
+CSET clk_out7_port=CLK_OUT7
+CSET clk_out7_use_fine_ps_gui=false
+CSET clk_valid_port=CLK_VALID
+CSET clkfb_in_n_port=CLKFB_IN_N
+CSET clkfb_in_p_port=CLKFB_IN_P
+CSET clkfb_in_port=CLKFB_IN
+CSET clkfb_in_signaling=SINGLE
+CSET clkfb_out_n_port=CLKFB_OUT_N
+CSET clkfb_out_p_port=CLKFB_OUT_P
+CSET clkfb_out_port=CLKFB_OUT
+CSET clkfb_stopped_port=CLKFB_STOPPED
+CSET clkin1_jitter_ps=250.0
+CSET clkin1_ui_jitter=0.010
+CSET clkin2_jitter_ps=100.0
+CSET clkin2_ui_jitter=0.010
+CSET clkout1_drives=BUFG
+CSET clkout1_requested_duty_cycle=50.000
+CSET clkout1_requested_out_freq=40.000
+CSET clkout1_requested_phase=0.000
+CSET clkout2_drives=BUFG
+CSET clkout2_requested_duty_cycle=50.000
+CSET clkout2_requested_out_freq=100.000
+CSET clkout2_requested_phase=0.000
+CSET clkout2_used=true
+CSET clkout3_drives=BUFG
+CSET clkout3_requested_duty_cycle=50.000
+CSET clkout3_requested_out_freq=100.000
+CSET clkout3_requested_phase=0.000
+CSET clkout3_used=true
+CSET clkout4_drives=BUFG
+CSET clkout4_requested_duty_cycle=50.000
+CSET clkout4_requested_out_freq=100.000
+CSET clkout4_requested_phase=0.000
+CSET clkout4_used=false
+CSET clkout5_drives=BUFG
+CSET clkout5_requested_duty_cycle=50.000
+CSET clkout5_requested_out_freq=100.000
+CSET clkout5_requested_phase=0.000
+CSET clkout5_used=false
+CSET clkout6_drives=BUFG
+CSET clkout6_requested_duty_cycle=50.000
+CSET clkout6_requested_out_freq=100.000
+CSET clkout6_requested_phase=0.000
+CSET clkout6_used=false
+CSET clkout7_drives=BUFG
+CSET clkout7_requested_duty_cycle=50.000
+CSET clkout7_requested_out_freq=100.000
+CSET clkout7_requested_phase=0.000
+CSET clkout7_used=false
+CSET clock_mgr_type=AUTO
+CSET component_name=b200_clk_gen
+CSET daddr_port=DADDR
+CSET dclk_port=DCLK
+CSET dcm_clk_feedback=1X
+CSET dcm_clk_out1_port=CLK0
+CSET dcm_clk_out2_port=CLKFX
+CSET dcm_clk_out3_port=CLKFX
+CSET dcm_clk_out4_port=CLK0
+CSET dcm_clk_out5_port=CLK0
+CSET dcm_clk_out6_port=CLK0
+CSET dcm_clkdv_divide=2.0
+CSET dcm_clkfx_divide=2
+CSET dcm_clkfx_multiply=5
+CSET dcm_clkgen_clk_out1_port=CLKFX
+CSET dcm_clkgen_clk_out2_port=CLKFX
+CSET dcm_clkgen_clk_out3_port=CLKFX
+CSET dcm_clkgen_clkfx_divide=1
+CSET dcm_clkgen_clkfx_md_max=0.000
+CSET dcm_clkgen_clkfx_multiply=4
+CSET dcm_clkgen_clkfxdv_divide=2
+CSET dcm_clkgen_clkin_period=10.000
+CSET dcm_clkgen_notes=None
+CSET dcm_clkgen_spread_spectrum=NONE
+CSET dcm_clkgen_startup_wait=false
+CSET dcm_clkin_divide_by_2=false
+CSET dcm_clkin_period=25.000
+CSET dcm_clkout_phase_shift=NONE
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
+CSET dcm_notes=None
+CSET dcm_phase_shift=0
+CSET dcm_pll_cascade=NONE
+CSET dcm_startup_wait=false
+CSET den_port=DEN
+CSET din_port=DIN
+CSET dout_port=DOUT
+CSET drdy_port=DRDY
+CSET dwe_port=DWE
+CSET feedback_source=FDBK_AUTO
+CSET in_freq_units=Units_MHz
+CSET in_jitter_units=Units_UI
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED
+CSET jitter_options=UI
+CSET jitter_sel=No_Jitter
+CSET locked_port=LOCKED
+CSET mmcm_bandwidth=OPTIMIZED
+CSET mmcm_clkfbout_mult_f=4.000
+CSET mmcm_clkfbout_phase=0.000
+CSET mmcm_clkfbout_use_fine_ps=false
+CSET mmcm_clkin1_period=10.000
+CSET mmcm_clkin2_period=10.000
+CSET mmcm_clkout0_divide_f=4.000
+CSET mmcm_clkout0_duty_cycle=0.500
+CSET mmcm_clkout0_phase=0.000
+CSET mmcm_clkout0_use_fine_ps=false
+CSET mmcm_clkout1_divide=1
+CSET mmcm_clkout1_duty_cycle=0.500
+CSET mmcm_clkout1_phase=0.000
+CSET mmcm_clkout1_use_fine_ps=false
+CSET mmcm_clkout2_divide=1
+CSET mmcm_clkout2_duty_cycle=0.500
+CSET mmcm_clkout2_phase=0.000
+CSET mmcm_clkout2_use_fine_ps=false
+CSET mmcm_clkout3_divide=1
+CSET mmcm_clkout3_duty_cycle=0.500
+CSET mmcm_clkout3_phase=0.000
+CSET mmcm_clkout3_use_fine_ps=false
+CSET mmcm_clkout4_cascade=false
+CSET mmcm_clkout4_divide=1
+CSET mmcm_clkout4_duty_cycle=0.500
+CSET mmcm_clkout4_phase=0.000
+CSET mmcm_clkout4_use_fine_ps=false
+CSET mmcm_clkout5_divide=1
+CSET mmcm_clkout5_duty_cycle=0.500
+CSET mmcm_clkout5_phase=0.000
+CSET mmcm_clkout5_use_fine_ps=false
+CSET mmcm_clkout6_divide=1
+CSET mmcm_clkout6_duty_cycle=0.500
+CSET mmcm_clkout6_phase=0.000
+CSET mmcm_clkout6_use_fine_ps=false
+CSET mmcm_clock_hold=false
+CSET mmcm_compensation=ZHOLD
+CSET mmcm_divclk_divide=1
+CSET mmcm_notes=None
+CSET mmcm_ref_jitter1=0.010
+CSET mmcm_ref_jitter2=0.010
+CSET mmcm_startup_wait=false
+CSET num_out_clks=3
+CSET override_dcm=false
+CSET override_dcm_clkgen=false
+CSET override_mmcm=false
+CSET override_pll=false
+CSET platform=lin64
+CSET pll_bandwidth=OPTIMIZED
+CSET pll_clk_feedback=CLKFBOUT
+CSET pll_clkfbout_mult=4
+CSET pll_clkfbout_phase=0.000
+CSET pll_clkin_period=10.000
+CSET pll_clkout0_divide=1
+CSET pll_clkout0_duty_cycle=0.500
+CSET pll_clkout0_phase=0.000
+CSET pll_clkout1_divide=1
+CSET pll_clkout1_duty_cycle=0.500
+CSET pll_clkout1_phase=0.000
+CSET pll_clkout2_divide=1
+CSET pll_clkout2_duty_cycle=0.500
+CSET pll_clkout2_phase=0.000
+CSET pll_clkout3_divide=1
+CSET pll_clkout3_duty_cycle=0.500
+CSET pll_clkout3_phase=0.000
+CSET pll_clkout4_divide=1
+CSET pll_clkout4_duty_cycle=0.500
+CSET pll_clkout4_phase=0.000
+CSET pll_clkout5_divide=1
+CSET pll_clkout5_duty_cycle=0.500
+CSET pll_clkout5_phase=0.000
+CSET pll_compensation=SYSTEM_SYNCHRONOUS
+CSET pll_divclk_divide=1
+CSET pll_notes=None
+CSET pll_ref_jitter=0.010
+CSET power_down_port=POWER_DOWN
+CSET prim_in_freq=40.000
+CSET prim_in_jitter=0.010
+CSET prim_source=Differential_clock_capable_pin
+CSET primary_port=CLK_IN1_40
+CSET primitive=MMCM
+CSET primtype_sel=PLL_BASE
+CSET psclk_port=PSCLK
+CSET psdone_port=PSDONE
+CSET psen_port=PSEN
+CSET psincdec_port=PSINCDEC
+CSET relative_inclk=REL_PRIMARY
+CSET reset_port=RESET
+CSET secondary_in_freq=100.000
+CSET secondary_in_jitter=0.010
+CSET secondary_port=CLK_IN2
+CSET secondary_source=Single_ended_clock_capable_pin
+CSET ss_mod_freq=250
+CSET ss_mode=CENTER_HIGH
+CSET status_port=STATUS
+CSET summary_strings=empty
+CSET use_clk_valid=false
+CSET use_clkfb_stopped=false
+CSET use_dyn_phase_shift=false
+CSET use_dyn_reconfig=false
+CSET use_freeze=false
+CSET use_freq_synth=true
+CSET use_inclk_stopped=false
+CSET use_inclk_switchover=false
+CSET use_locked=true
+CSET use_max_i_jitter=false
+CSET use_min_o_jitter=false
+CSET use_min_power=false
+CSET use_phase_alignment=true
+CSET use_power_down=false
+CSET use_reset=true
+CSET use_spread_spectrum=false
+CSET use_spread_spectrum_1=false
+CSET use_status=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-05-10T12:44:55Z
+# END Extra information
+GENERATE
+# CRC: af7323ea
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.xdc b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xdc
new file mode 100755
index 000000000..d57c7eec7
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xdc
@@ -0,0 +1,68 @@
+# file: b200_clk_gen.xdc
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+# Differential clock only needs one constraint
+create_clock -name CLK_IN1_P -period 25.0 [get_ports CLK_IN1_P]
+set_propagated_clock CLK_IN1_P
+set_input_jitter CLK_IN1_P 0.25
+
+set_false_path -from [get_ports "RESET"]
+
+# Derived clock periods. These are commented out because they are 
+#   automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you 
+#   can copy them into your module level timing checks
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.xise b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xise
new file mode 100644
index 000000000..0c90c5973
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xise
@@ -0,0 +1,408 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="b200_clk_gen/example_design/b200_clk_gen_exdes.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="b200_clk_gen/example_design/b200_clk_gen_exdes.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="b200_clk_gen.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|b200_clk_gen_exdes" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="b200_clk_gen/example_design/b200_clk_gen_exdes.v" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/b200_clk_gen_exdes" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="b200_clk_gen_exdes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="b200_clk_gen_exdes_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="b200_clk_gen_exdes_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="b200_clk_gen_exdes_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="b200_clk_gen_exdes_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="b200_clk_gen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-25T12:01:05" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BF4ABAECC95F189A3B1A35E026FF9799" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/clk_wiz_v3_6_readme.txt b/fpga/usrp3/top/b200/coregen/b200_clk_gen/clk_wiz_v3_6_readme.txt
new file mode 100644
index 000000000..19c5b73c6
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/clk_wiz_v3_6_readme.txt
@@ -0,0 +1,181 @@
+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: July 25, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_readme.txt b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_readme.txt
new file mode 100644
index 000000000..19c5b73c6
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_readme.txt
@@ -0,0 +1,181 @@
+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: July 25, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html
new file mode 100644
index 000000000..7176ddb81
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html
@@ -0,0 +1,192 @@
+<HTML>
+<HEAD>
+<TITLE>clk_wiz_v3_6_vinfo</TITLE>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
+</HEAD>
+<BODY>
+<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: July 25, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
+
+For system requirements:
+
+   <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   <A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A>
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
+</FONT>
+</PRE>
+</BODY>
+</HTML>
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/pg065_clk_wiz.pdf b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/pg065_clk_wiz.pdf
new file mode 100644
index 000000000..a7daa6089
Binary files /dev/null and b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/pg065_clk_wiz.pdf differ
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.ucf b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.ucf
new file mode 100755
index 000000000..62c243978
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.ucf
@@ -0,0 +1,73 @@
+# file: b200_clk_gen_exdes.ucf
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+# Differential clock only needs one constraint
+NET "CLK_IN1_P" TNM_NET = "CLK_IN1_P";
+TIMESPEC "TS_CLK_IN1_P" = PERIOD "CLK_IN1_P" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps;
+
+# Derived clock periods. These are commented out because they are 
+#   automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you 
+#   can copy them into your module level timing checks
+#-----------------------------------------------------------------
+# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
+# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 40.000 MHz;
+
+# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
+# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz;
+# NET "clk_int[3]" TNM_NET = "CLK_OUT3";
+# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz;
+
+# FALSE PATH constraints 
+PIN "COUNTER_RESET" TIG;
+PIN "RESET" TIG;
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.v
new file mode 100755
index 000000000..e22b83072
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.v
@@ -0,0 +1,180 @@
+// file: b200_clk_gen_exdes.v
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+
+//----------------------------------------------------------------------------
+// Clocking wizard example design
+//----------------------------------------------------------------------------
+// This example design instantiates the created clocking network, where each
+//   output clock drives a counter. The high bit of each counter is ported.
+//----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+module b200_clk_gen_exdes 
+ #( 
+  parameter TCQ = 100
+  )
+ (// Clock in ports
+  input         CLK_IN1_P,
+  input         CLK_IN1_N,
+  // Reset that only drives logic in example design
+  input         COUNTER_RESET,
+  output [3:1]  CLK_OUT,
+  // High bits of counters driven by clocks
+  output [3:1]  COUNT,
+  // Status and control signals
+  input         RESET,
+  output        LOCKED
+ );
+
+  // Parameters for the counters
+  //-------------------------------
+  // Counter width
+  localparam    C_W       = 16;
+  // Number of counters
+  localparam    NUM_C     = 3;
+  genvar        count_gen;
+  // When the clock goes out of lock, reset the counters
+  wire          reset_int = !LOCKED || RESET || COUNTER_RESET;
+
+   reg [NUM_C:1] rst_sync;
+   reg [NUM_C:1] rst_sync_int;
+   reg [NUM_C:1] rst_sync_int1;
+   reg [NUM_C:1] rst_sync_int2;
+
+
+  // Declare the clocks and counters
+  wire [NUM_C:1] clk_int;
+  wire [NUM_C:1] clk_n;
+  wire [NUM_C:1] clk;
+  reg [C_W-1:0]  counter [NUM_C:1];
+
+  // Instantiation of the clocking network
+  //--------------------------------------
+  b200_clk_gen clknetwork
+   (// Clock in ports
+    .CLK_IN1_40_P          (CLK_IN1_P),
+    .CLK_IN1_40_N          (CLK_IN1_N),
+    // Clock out ports
+    .CLK_OUT1_40_int           (clk_int[1]),
+    .CLK_OUT2_100_gpif           (clk_int[2]),
+    .CLK_OUT3_100_bus           (clk_int[3]),
+    // Status and control signals
+    .RESET              (RESET),
+    .LOCKED             (LOCKED));
+
+genvar clk_out_pins;
+
+generate 
+  for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1) 
+  begin: gen_outclk_oddr
+  assign clk_n[clk_out_pins] = ~clk[clk_out_pins];
+
+  ODDR2 clkout_oddr
+   (.Q  (CLK_OUT[clk_out_pins1]),
+    .C0 (clk[clk_out_pins]),
+    .C1 (clk_n[clk_out_pins]),
+    .CE (1'b1),
+    .D0 (1'b1),
+    .D1 (1'b0),
+    .R  (1'b0),
+    .S  (1'b0));
+  end
+endgenerate
+
+  // Connect the output clocks to the design
+  //-----------------------------------------
+  assign clk[1] = clk_int[1];
+  assign clk[2] = clk_int[2];
+  assign clk[3] = clk_int[3];
+
+
+  // Reset synchronizer
+  //-----------------------------------
+  generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
+    always @(posedge reset_int or posedge clk[count_gen]) begin
+       if (reset_int) begin
+            rst_sync[count_gen] <= 1'b1;
+            rst_sync_int[count_gen]<= 1'b1;
+            rst_sync_int1[count_gen]<= 1'b1;
+            rst_sync_int2[count_gen]<= 1'b1;
+       end
+       else begin
+            rst_sync[count_gen] <= 1'b0;
+            rst_sync_int[count_gen] <= rst_sync[count_gen];     
+            rst_sync_int1[count_gen] <= rst_sync_int[count_gen]; 
+            rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
+       end
+    end
+  end
+  endgenerate
+
+
+  // Output clock sampling
+  //-----------------------------------
+  generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
+
+    always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
+      if (rst_sync_int2[count_gen]) begin
+        counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
+      end else begin
+        counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
+      end
+    end
+    // alias the high bit of each counter to the corresponding
+    //   bit in the output bus
+    assign COUNT[count_gen] = counter[count_gen][C_W-1];
+  end
+  endgenerate
+
+
+
+
+
+endmodule
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.xdc b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.xdc
new file mode 100755
index 000000000..dc0aad84c
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.xdc
@@ -0,0 +1,70 @@
+# file: b200_clk_gen_exdes.xdc
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+# Differential clock only needs one constraint
+create_clock -name CLK_IN1_P -period 25.0 [get_ports CLK_IN1_P]
+set_propagated_clock CLK_IN1_P
+set_input_jitter CLK_IN1_P 0.25
+
+# FALSE PATH constraint added on COUNTER_RESET 
+set_false_path -from [get_ports "COUNTER_RESET"]
+set_false_path -from [get_ports "RESET"]
+
+# Derived clock periods. These are commented out because they are 
+#   automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you 
+#   can copy them into your module level timing checks
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.bat
new file mode 100755
index 000000000..32e315065
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.bat
@@ -0,0 +1,90 @@
+REM file: implement.bat
+REM 
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM 
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM 
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM 
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM 
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM 
+
+REM -----------------------------------------------------------------------------
+REM  Script to synthesize and implement the RTL provided for the clocking wizard
+REM -----------------------------------------------------------------------------
+
+REM Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+REM Copy unisim_comp.v file to results directory
+copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
+
+REM Synthesize the Verilog Wrapper Files
+echo 'Synthesizing Clocking Wizard design with XST'
+xst -ifn xst.scr
+move b200_clk_gen_exdes.ngc results\
+
+REM  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\b200_clk_gen_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -uc b200_clk_gen_exdes.ucf b200_clk_gen_exdes
+
+echo 'Running map'
+map -timing -pr b b200_clk_gen_exdes -o mapped.ncd
+
+echo 'Running par'
+par -w mapped.ncd routed mapped.pcf
+
+echo 'Running trce'
+trce -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level model for the clocking wizard example design'
+netgen -ofmt verilog -sim -sdf_anno false -tm b200_clk_gen_exdes -w routed.ncd routed.v
+cd ..
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.sh
new file mode 100755
index 000000000..d33e6c5f5
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.sh
@@ -0,0 +1,91 @@
+#!/bin/sh
+# file: implement.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the clocking wizard
+#-----------------------------------------------------------------------------
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+# Copy unisim_comp.v file to results directory
+cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
+
+# Synthesize the Verilog Wrapper Files
+echo 'Synthesizing Clocking Wizard design with XST'
+xst -ifn xst.scr
+mv b200_clk_gen_exdes.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/b200_clk_gen_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -uc b200_clk_gen_exdes.ucf b200_clk_gen_exdes
+
+echo 'Running map'
+map -timing b200_clk_gen_exdes -o mapped.ncd
+
+echo 'Running par'
+par -w mapped.ncd routed mapped.pcf
+
+echo 'Running trce'
+trce -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level model for the clocking wizard example design'
+netgen -ofmt verilog -sim -sdf_anno false -tm b200_clk_gen_exdes -w routed.ncd routed.v
+
+cd ..
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.bat
new file mode 100755
index 000000000..8ac771810
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.bat
@@ -0,0 +1,58 @@
+REM file: planAhead_ise.bat
+REM 
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM 
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM 
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM 
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM 
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM 
+
+REM-----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the clocking wizard
+REM-----------------------------------------------------------------------------
+
+del \f results
+mkdir results
+cd results
+
+planAhead -mode batch -source ..\planAhead_ise.tcl
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.sh
new file mode 100755
index 000000000..6c8c837d3
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.sh
@@ -0,0 +1,59 @@
+#!/bin/sh
+# file: planAhead_ise.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the clocking wizard
+#-----------------------------------------------------------------------------
+
+rm -rf results
+mkdir results
+cd results
+
+planAhead -mode batch -source ../planAhead_ise.tcl
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.tcl
new file mode 100755
index 000000000..b87b6e4d5
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.tcl
@@ -0,0 +1,78 @@
+# file: planAhead_ise.tcl
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+set projDir [file dirname [info script]]
+set projName b200_clk_gen
+set topName b200_clk_gen_exdes
+set device xc6slx75csg484-2
+
+create_project $projName $projDir/results/$projName -part $device
+
+set_property design_mode RTL [get_filesets sources_1]
+
+## Source files
+#set verilogSources [glob $srcDir/*.v]
+import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/b200_clk_gen_exdes.v
+import_files -fileset [get_filesets sources_1] -force -norecurse ../../../b200_clk_gen.v
+
+
+#UCF file
+import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/b200_clk_gen_exdes.ucf
+
+set_property top $topName [get_property srcset [current_run]]
+
+launch_runs -runs synth_1
+wait_on_run synth_1
+
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs -runs impl_1
+wait_on_run impl_1
+
+
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.bat
new file mode 100755
index 000000000..42273f5d4
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.bat
@@ -0,0 +1,58 @@
+REM file: planAhead_rdn.sh
+REM 
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM 
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM 
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM 
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM 
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM 
+
+REM-----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the XADC wizard
+REM-----------------------------------------------------------------------------
+
+del \f results
+mkdir results
+cd results
+
+planAhead -mode batch -source ..\planAhead_rdn.tcl
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.sh
new file mode 100755
index 000000000..f4c14729e
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.sh
@@ -0,0 +1,57 @@
+#!/bin/sh
+# file: planAhead_rdn.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the XADC wizard
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+planAhead -mode batch -source ../planAhead_rdn.tcl
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.tcl
new file mode 100755
index 000000000..5449fa5fb
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.tcl
@@ -0,0 +1,69 @@
+# file : planAhead_rdn.tcl
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+set device xc6slx75csg484-2
+set projName b200_clk_gen
+set design b200_clk_gen
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module b200_clk_gen_exdes
+set_property top b200_clk_gen_exdes [get_property srcset [current_run]]
+add_files -norecurse {../../../b200_clk_gen.v}
+add_files -norecurse {../../example_design/b200_clk_gen_exdes.v}
+import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/b200_clk_gen_exdes.xdc}
+synth_design
+opt_design 
+place_design 
+route_design 
+write_sdf -rename_top_module b200_clk_gen_exdes -file routed.sdf 
+write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module b200_clk_gen_exdes -file routed.v
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.prj b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.prj
new file mode 100755
index 000000000..51a950151
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.prj
@@ -0,0 +1,2 @@
+verilog work ../../b200_clk_gen.v
+verilog work ../example_design/b200_clk_gen_exdes.v
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.scr b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.scr
new file mode 100755
index 000000000..ae0a09163
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.scr
@@ -0,0 +1,9 @@
+run
+-ifmt MIXED
+-top b200_clk_gen_exdes
+-p xc6slx75-csg484-2
+-ifn xst.prj
+-ofn b200_clk_gen_exdes
+-keep_hierarchy soft 
+-equivalent_register_removal no 
+-max_fanout 65535
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/b200_clk_gen_tb.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/b200_clk_gen_tb.v
new file mode 100755
index 000000000..f7dba4105
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/b200_clk_gen_tb.v
@@ -0,0 +1,146 @@
+// file: b200_clk_gen_tb.v
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+
+//----------------------------------------------------------------------------
+// Clocking wizard demonstration testbench
+//----------------------------------------------------------------------------
+// This demonstration testbench instantiates the example design for the 
+//   clocking wizard. Input clocks are toggled, which cause the clocking
+//   network to lock and the counters to increment.
+//----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+`define wait_lock @(posedge LOCKED)
+
+module b200_clk_gen_tb ();
+
+  // Clock to Q delay of 100ps
+  localparam  TCQ              = 100;
+
+
+  // timescale is 1ps/1ps
+  localparam  ONE_NS      = 1000;
+  localparam  PHASE_ERR_MARGIN   = 100; // 100ps
+  // how many cycles to run
+  localparam  COUNT_PHASE = 1024;
+  // we'll be using the period in many locations
+  localparam time PER1    = 25.0*ONE_NS;
+  localparam time PER1_1  = PER1/2;
+  localparam time PER1_2  = PER1 - PER1/2;
+
+  // Declare the input clock signals
+  reg         CLK_IN1     = 1;
+  wire        CLK_IN1_P   =  CLK_IN1;
+  wire        CLK_IN1_N   = ~CLK_IN1;
+
+  // The high bits of the sampling counters
+  wire [3:1]  COUNT;
+  // Status and control signals
+  reg         RESET      = 0;
+  wire        LOCKED;
+  reg         COUNTER_RESET = 0;
+wire [3:1] CLK_OUT;
+//Freq Check using the M & D values setting and actual Frequency generated
+
+
+  // Input clock generation
+  //------------------------------------
+  always begin
+    CLK_IN1 = #PER1_1 ~CLK_IN1;
+    CLK_IN1 = #PER1_2 ~CLK_IN1;
+  end
+
+  // Test sequence
+  reg [15*8-1:0] test_phase = "";
+  initial begin
+    // Set up any display statements using time to be readable
+    $timeformat(-12, 2, "ps", 10);
+    COUNTER_RESET = 0;
+    test_phase = "reset";
+    RESET = 1;
+    #(PER1*6);
+    RESET = 0;
+    test_phase = "wait lock";
+    `wait_lock;
+    #(PER1*6);
+    COUNTER_RESET = 1;
+    #(PER1*20)
+    COUNTER_RESET = 0;
+
+    test_phase = "counting";
+    #(PER1*COUNT_PHASE);
+
+    $display("SIMULATION PASSED");
+    $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
+    $finish;
+  end
+
+  // Instantiation of the example design containing the clock
+  //    network and sampling counters
+  //---------------------------------------------------------
+  b200_clk_gen_exdes 
+  #(
+    .TCQ (TCQ)
+   ) dut
+   (// Clock in ports
+    .CLK_IN1_P          (CLK_IN1_P),
+    .CLK_IN1_N          (CLK_IN1_N),
+    // Reset for logic in example design
+    .COUNTER_RESET      (COUNTER_RESET),
+    .CLK_OUT            (CLK_OUT),
+    // High bits of the counters
+    .COUNT              (COUNT),
+    // Status and control signals
+    .RESET              (RESET),
+    .LOCKED             (LOCKED));
+
+// Freq Check 
+
+endmodule
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simcmds.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simcmds.tcl
new file mode 100755
index 000000000..f22f9e447
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simcmds.tcl
@@ -0,0 +1,8 @@
+# file: simcmds.tcl
+
+# create the simulation script
+vcd dumpfile isim.vcd
+vcd dumpvars -m /b200_clk_gen_tb -l 0
+wave add /
+run 50000ns
+quit
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.bat
new file mode 100755
index 000000000..227a07e0c
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.bat
@@ -0,0 +1,59 @@
+REM file: simulate_isim.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
+REM  of Xilinx, Inc. and is protected under U.S. and
+REM  international copyright and other intellectual property
+REM  laws.
+REM  
+REM  DISCLAIMER
+REM  This disclaimer is not a license and does not grant any
+REM  rights to the materials distributed herewith. Except as
+REM  otherwise provided in a valid license issued to you by
+REM  Xilinx, and to the maximum extent permitted by applicable
+REM  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM  (2) Xilinx shall not be liable (whether in contract or tort,
+REM  including negligence, or under any other theory of
+REM  liability) for any loss or damage of any kind or nature
+REM  related to, arising under or in connection with these
+REM  materials, including for any direct, or any indirect,
+REM  special, incidental, or consequential loss or damage
+REM  (including loss of data, profits, goodwill, or any type of
+REM  loss or damage suffered as a result of any action brought
+REM  by a third party) even if such damage or loss was
+REM  reasonably foreseeable or Xilinx had been advised of the
+REM  possibility of the same.
+REM  
+REM  CRITICAL APPLICATIONS
+REM  Xilinx products are not designed or intended to be fail-
+REM  safe, or for use in any application requiring fail-safe
+REM  performance, such as life-support or safety devices or
+REM  systems, Class III medical devices, nuclear facilities,
+REM  applications related to the deployment of airbags, or any
+REM  other applications that could lead to death, personal
+REM  injury, or severe property or environmental damage
+REM  (individually and collectively, "Critical
+REM  Applications"). Customer assumes the sole risk and
+REM  liability of any use of Xilinx products in Critical
+REM  Applications, subject only to applicable laws and
+REM  regulations governing limitations on product liability.
+REM  
+REM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM  PART OF THIS FILE AT ALL TIMES.
+REM  
+
+vlogcomp -work work %XILINX%\verilog\src\glbl.v
+vlogcomp -work work ..\..\..\b200_clk_gen.v
+vlogcomp -work work ..\..\example_design\b200_clk_gen_exdes.v
+vlogcomp -work work ..\b200_clk_gen_tb.v
+
+REM compile the project
+fuse work.b200_clk_gen_tb work.glbl -L unisims_ver -o b200_clk_gen_isim.exe
+
+REM run the simulation script
+.\b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.sh
new file mode 100755
index 000000000..db1b8cc4b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.sh
@@ -0,0 +1,61 @@
+# file: simulate_isim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# lin64
+# create the project
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work ../../../b200_clk_gen.v
+vlogcomp -work work ../../example_design/b200_clk_gen_exdes.v
+vlogcomp -work work ../b200_clk_gen_tb.v
+
+# compile the project
+fuse work.b200_clk_gen_tb work.glbl -L unisims_ver -o b200_clk_gen_isim.exe
+
+# run the simulation script
+./b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.bat
new file mode 100755
index 000000000..86e433ecb
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.bat
@@ -0,0 +1,61 @@
+REM file: simulate_mti.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
+REM  of Xilinx, Inc. and is protected under U.S. and
+REM  international copyright and other intellectual property
+REM  laws.
+REM  
+REM  DISCLAIMER
+REM  This disclaimer is not a license and does not grant any
+REM  rights to the materials distributed herewith. Except as
+REM  otherwise provided in a valid license issued to you by
+REM  Xilinx, and to the maximum extent permitted by applicable
+REM  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM  (2) Xilinx shall not be liable (whether in contract or tort,
+REM  including negligence, or under any other theory of
+REM  liability) for any loss or damage of any kind or nature
+REM  related to, arising under or in connection with these
+REM  materials, including for any direct, or any indirect,
+REM  special, incidental, or consequential loss or damage
+REM  (including loss of data, profits, goodwill, or any type of
+REM  loss or damage suffered as a result of any action brought
+REM  by a third party) even if such damage or loss was
+REM  reasonably foreseeable or Xilinx had been advised of the
+REM  possibility of the same.
+REM  
+REM  CRITICAL APPLICATIONS
+REM  Xilinx products are not designed or intended to be fail-
+REM  safe, or for use in any application requiring fail-safe
+REM  performance, such as life-support or safety devices or
+REM  systems, Class III medical devices, nuclear facilities,
+REM  applications related to the deployment of airbags, or any
+REM  other applications that could lead to death, personal
+REM  injury, or severe property or environmental damage
+REM  (individually and collectively, "Critical
+REM  Applications"). Customer assumes the sole risk and
+REM  liability of any use of Xilinx products in Critical
+REM  Applications, subject only to applicable laws and
+REM  regulations governing limitations on product liability.
+REM  
+REM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM  PART OF THIS FILE AT ALL TIMES.
+REM  
+
+REM set up the working directory
+vlib work
+
+REM compile all of the files
+vlog -work work %XILINX%\verilog\src\glbl.v
+vlog -work work ..\..\..\b200_clk_gen.v
+vlog -work work ..\..\example_design\b200_clk_gen_exdes.v
+vlog -work work ..\b200_clk_gen_tb.v
+
+REM run the simulation
+vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b200_clk_gen_tb work.glbl
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.do
new file mode 100755
index 000000000..fbb4124b9
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.do
@@ -0,0 +1,65 @@
+# file: simulate_mti.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $env(XILINX)/verilog/src/glbl.v
+vlog -work work ../../../b200_clk_gen.v
+vlog -work work ../../example_design/b200_clk_gen_exdes.v
+vlog -work work ../b200_clk_gen_tb.v
+
+# run the simulation
+vsim  -t ps -voptargs="+acc" -L unisims_ver work.b200_clk_gen_tb work.glbl
+do wave.do
+log b200_clk_gen_tb/dut/counter
+log -r /*
+run 50000ns
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.sh
new file mode 100755
index 000000000..1d9455134
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.sh
@@ -0,0 +1,61 @@
+#/bin/sh
+# file: simulate_mti.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $XILINX/verilog/src/glbl.v
+vlog -work work ../../../b200_clk_gen.v
+vlog -work work ../../example_design/b200_clk_gen_exdes.v
+vlog -work work ../b200_clk_gen_tb.v
+
+# run the simulation
+vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b200_clk_gen_tb work.glbl
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_ncsim.sh
new file mode 100755
index 000000000..eeb5b9712
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_ncsim.sh
@@ -0,0 +1,62 @@
+#/bin/sh
+# file: simulate_ncsim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+mkdir work
+
+# compile all of the files
+ncvlog -work work ${XILINX}/verilog/src/glbl.v
+ncvlog -work work ../../../b200_clk_gen.v
+ncvlog -work work ../../example_design/b200_clk_gen_exdes.v
+ncvlog -work work ../b200_clk_gen_tb.v
+
+# elaborate and run the simulation
+ncelab -work work -access +wc work.b200_clk_gen_tb work.glbl
+ncsim -input  "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.b200_clk_gen_tb
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_vcs.sh
new file mode 100755
index 000000000..66b2cfb09
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_vcs.sh
@@ -0,0 +1,72 @@
+#!/bin/sh
+# file: simulate_vcs.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# remove old files
+rm -rf simv* csrc DVEfiles AN.DB
+
+# compile all of the files
+# Note that -sverilog is not strictly required- You can
+#   remove the -sverilog if you change the type of the
+#   localparam for the periods in the testbench file to 
+#   [63:0] from time
+vlogan -sverilog \
+      ${XILINX}/verilog/src/glbl.v \
+      ../../../b200_clk_gen.v \
+      ../../example_design/b200_clk_gen_exdes.v \
+      ../b200_clk_gen_tb.v
+
+# prepare the simulation 
+vcs +vcs+lic+wait -debug b200_clk_gen_tb glbl
+
+# run the simulation
+./simv -ucli -i ucli_commands.key
+
+# launch the viewer
+dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/ucli_commands.key b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/ucli_commands.key
new file mode 100755
index 000000000..d35a8a813
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/ucli_commands.key
@@ -0,0 +1,5 @@
+call {$vcdpluson}
+call {$vcdplusmemon(b200_clk_gen_tb.dut.counter)}
+run
+call {$vcdplusclose}
+quit
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/vcs_session.tcl
new file mode 100755
index 000000000..b751d0624
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/vcs_session.tcl
@@ -0,0 +1,18 @@
+gui_open_window Wave
+gui_sg_create b200_clk_gen_group
+gui_list_add_group -id Wave.1 {b200_clk_gen_group}
+gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.test_phase}
+gui_set_radix -radix {ascii} -signals {b200_clk_gen_tb.test_phase}
+gui_sg_addsignal -group b200_clk_gen_group {{Input_clocks}} -divider
+gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.CLK_IN1}
+gui_sg_addsignal -group b200_clk_gen_group {{Output_clocks}} -divider
+gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.dut.clk}
+gui_list_expand -id Wave.1 b200_clk_gen_tb.dut.clk
+gui_sg_addsignal -group b200_clk_gen_group {{Status_control}} -divider
+gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.RESET}
+gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.LOCKED}
+gui_sg_addsignal -group b200_clk_gen_group {{Counters}} -divider
+gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.COUNT}
+gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.dut.counter}
+gui_list_expand -id Wave.1 b200_clk_gen_tb.dut.counter
+gui_zoom -window Wave.1 -full
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.do
new file mode 100755
index 000000000..f05bb5c2e
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.do
@@ -0,0 +1,60 @@
+# file: wave.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+add wave -noupdate -format Literal -radix ascii /b200_clk_gen_tb/test_phase
+add wave -noupdate -divider {Input clocks}
+add wave -noupdate -format Logic /b200_clk_gen_tb/CLK_IN1
+add wave -noupdate -divider {Output clocks}
+add wave -noupdate -format Literal -expand /b200_clk_gen_tb/dut/clk
+add wave -noupdate -divider Status/control
+add wave -noupdate -format Logic /b200_clk_gen_tb/RESET
+add wave -noupdate -format Logic /b200_clk_gen_tb/LOCKED
+add wave -noupdate -divider Counters
+add wave -noupdate -format Literal -radix hexadecimal /b200_clk_gen_tb/COUNT
+add wave -noupdate -format Literal -radix hexadecimal -expand /b200_clk_gen_tb/dut/counter
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.sv b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.sv
new file mode 100755
index 000000000..4bce3bcba
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.sv
@@ -0,0 +1,119 @@
+# file: wave.sv
+# 
+# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# Get the windows set up
+#
+if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {
+    window geometry "Design Browser 1" 1054x819+536+322
+}
+window target "Design Browser 1" on
+browser using {Design Browser 1}
+browser set \
+    -scope nc::b200_clk_gen_tb
+browser yview see nc::b200_clk_gen_tb
+browser timecontrol set -lock 0
+
+if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
+    window geometry "Waveform 1" 1010x600+0+541
+}
+window target "Waveform 1" on
+waveform using {Waveform 1}
+waveform sidebar visibility partial
+waveform set \
+    -primarycursor TimeA \
+    -signalnames name \
+    -signalwidth 175 \
+    -units ns \
+    -valuewidth 75
+cursor set -using TimeA -time 0
+waveform baseline set -time 0
+waveform xview limits 0 20000n
+
+#
+# Define signal groups
+#
+catch {group new -name {Output clocks} -overlay 0}
+catch {group new -name {Status/control} -overlay 0}
+catch {group new -name {Counters} -overlay 0}
+
+set id [waveform add -signals [list {nc::b200_clk_gen_tb.CLK_IN1}]]
+
+group using {Output clocks}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+    {b200_clk_gen_tb.dut.clk[1]} \
+    {b200_clk_gen_tb.dut.clk[2]}  \     {b200_clk_gen_tb.dut.clk[3]} 
+group using {Counters}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+    {b200_clk_gen_tb.dut.counter[1]} \
+    {b200_clk_gen_tb.dut.counter[2]}  \     {b200_clk_gen_tb.dut.counter[3]} 
+group using {Status/control}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+   {nc::b200_clk_gen_tb.RESET}    {nc::b200_clk_gen_tb.LOCKED}
+
+
+set id [waveform add -signals [list {nc::b200_clk_gen_tb.COUNT} ]]
+
+set id [waveform add -signals [list {nc::b200_clk_gen_tb.test_phase} ]]
+waveform format $id -radix %a
+
+set groupId [waveform add -groups {{Input clocks}}]
+set groupId [waveform add -groups {{Output clocks}}]
+set groupId [waveform add -groups {{Status/control}}]
+set groupId [waveform add -groups {{Counters}}]
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/b200_clk_gen_tb.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/b200_clk_gen_tb.v
new file mode 100755
index 000000000..4d0d01cb0
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/b200_clk_gen_tb.v
@@ -0,0 +1,160 @@
+// file: b200_clk_gen_tb.v
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+
+//----------------------------------------------------------------------------
+// Clocking wizard demonstration testbench
+//----------------------------------------------------------------------------
+// This demonstration testbench instantiates the example design for the 
+//   clocking wizard. Input clocks are toggled, which cause the clocking
+//   network to lock and the counters to increment.
+//----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+`define wait_lock @(posedge LOCKED)
+
+module b200_clk_gen_tb ();
+
+  // Clock to Q delay of 100ps
+  localparam  TCQ              = 100;
+
+
+  // timescale is 1ps/1ps
+  localparam  ONE_NS      = 1000;
+  localparam  PHASE_ERR_MARGIN   = 100; // 100ps
+  // how many cycles to run
+  localparam  COUNT_PHASE = 1024;
+  // we'll be using the period in many locations
+  localparam time PER1    = 25.0*ONE_NS;
+  localparam time PER1_1  = PER1/2;
+  localparam time PER1_2  = PER1 - PER1/2;
+
+  // Declare the input clock signals
+  reg         CLK_IN1     = 1;
+  wire        CLK_IN1_P   =  CLK_IN1;
+  wire        CLK_IN1_N   = ~CLK_IN1;
+
+  // The high bits of the sampling counters
+  wire [3:1]  COUNT;
+  // Status and control signals
+  reg         RESET      = 0;
+  wire        LOCKED;
+  reg         COUNTER_RESET = 0;
+wire [3:1] CLK_OUT;
+//Freq Check using the M & D values setting and actual Frequency generated 
+
+  reg [13:0]  timeout_counter = 14'b00000000000000;
+
+  // Input clock generation
+  //------------------------------------
+  always begin
+    CLK_IN1 = #PER1_1 ~CLK_IN1;
+    CLK_IN1 = #PER1_2 ~CLK_IN1;
+  end
+
+  // Test sequence
+  reg [15*8-1:0] test_phase = "";
+  initial begin
+    // Set up any display statements using time to be readable
+    $timeformat(-12, 2, "ps", 10);
+    $display ("Timing checks are not valid");
+    COUNTER_RESET = 0;
+    test_phase = "reset";
+    RESET = 1;
+    #(PER1*6);
+    RESET = 0;
+    test_phase = "wait lock";
+    `wait_lock;
+    #(PER1*6);
+    COUNTER_RESET = 1;
+    #(PER1*19.5)
+    COUNTER_RESET = 0;
+    #(PER1*1)
+    $display ("Timing checks are valid");
+    test_phase = "counting";
+    #(PER1*COUNT_PHASE);
+
+    $display("SIMULATION PASSED");
+    $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
+    $finish;
+  end
+
+
+   always@(posedge CLK_IN1) begin
+      timeout_counter <= timeout_counter + 1'b1;
+      if (timeout_counter == 14'b10000000000000) begin
+         if (LOCKED != 1'b1) begin
+            $display("ERROR : NO LOCK signal");
+            $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
+            $finish;
+         end
+      end
+   end
+
+  // Instantiation of the example design containing the clock
+  //    network and sampling counters
+  //---------------------------------------------------------
+  b200_clk_gen_exdes 
+    dut
+   (// Clock in ports
+    .CLK_IN1_P          (CLK_IN1_P),
+    .CLK_IN1_N          (CLK_IN1_N),
+    // Reset for logic in example design
+    .COUNTER_RESET      (COUNTER_RESET),
+    .CLK_OUT            (CLK_OUT),
+    // High bits of the counters
+    .COUNT              (COUNT),
+    // Status and control signals
+    .RESET              (RESET),
+    .LOCKED             (LOCKED));
+
+
+// Freq Check 
+
+endmodule
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/sdf_cmd_file b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/sdf_cmd_file
new file mode 100755
index 000000000..0e8696ce6
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/sdf_cmd_file
@@ -0,0 +1,2 @@
+COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
+SCOPE = b200_clk_gen_tb.dut;
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simcmds.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simcmds.tcl
new file mode 100755
index 000000000..00e00dd03
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simcmds.tcl
@@ -0,0 +1,9 @@
+# file: simcmds.tcl
+
+# create the simulation script
+vcd dumpfile isim.vcd
+vcd dumpvars -m /b200_clk_gen_tb -l 0
+wave add /
+run 50000ns
+quit
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_isim.sh
new file mode 100755
index 000000000..edf149164
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_isim.sh
@@ -0,0 +1,62 @@
+# file: simulate_isim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# create the project
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work ../../implement/results/routed.v
+vlogcomp -work work b200_clk_gen_tb.v
+
+# compile the project
+fuse work.b200_clk_gen_tb work.glbl -L secureip -L simprims_ver -o b200_clk_gen_isim.exe
+
+# run the simulation script
+./b200_clk_gen_isim.exe -tclbatch simcmds.tcl -sdfmax /b200_clk_gen_tb/dut=../../implement/results/routed.sdf
+
+# run the simulation script
+#./b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.bat
new file mode 100755
index 000000000..b759f9529
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.bat
@@ -0,0 +1,59 @@
+REM file: simulate_mti.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
+REM  of Xilinx, Inc. and is protected under U.S. and
+REM  international copyright and other intellectual property
+REM  laws.
+REM  
+REM  DISCLAIMER
+REM  This disclaimer is not a license and does not grant any
+REM  rights to the materials distributed herewith. Except as
+REM  otherwise provided in a valid license issued to you by
+REM  Xilinx, and to the maximum extent permitted by applicable
+REM  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM  (2) Xilinx shall not be liable (whether in contract or tort,
+REM  including negligence, or under any other theory of
+REM  liability) for any loss or damage of any kind or nature
+REM  related to, arising under or in connection with these
+REM  materials, including for any direct, or any indirect,
+REM  special, incidental, or consequential loss or damage
+REM  (including loss of data, profits, goodwill, or any type of
+REM  loss or damage suffered as a result of any action brought
+REM  by a third party) even if such damage or loss was
+REM  reasonably foreseeable or Xilinx had been advised of the
+REM  possibility of the same.
+REM  
+REM  CRITICAL APPLICATIONS
+REM  Xilinx products are not designed or intended to be fail-
+REM  safe, or for use in any application requiring fail-safe
+REM  performance, such as life-support or safety devices or
+REM  systems, Class III medical devices, nuclear facilities,
+REM  applications related to the deployment of airbags, or any
+REM  other applications that could lead to death, personal
+REM  injury, or severe property or environmental damage
+REM  (individually and collectively, "Critical
+REM  Applications"). Customer assumes the sole risk and
+REM  liability of any use of Xilinx products in Critical
+REM  Applications, subject only to applicable laws and
+REM  regulations governing limitations on product liability.
+REM  
+REM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM  PART OF THIS FILE AT ALL TIMES.
+REM  
+# set up the working directory
+set work work
+vlib work
+
+REM compile all of the files
+vlog -work work %XILINX%\verilog\src\glbl.v
+vlog -work work ..\..\implement\results\routed.v
+vlog -work work b200_clk_gen_tb.v
+
+REM run the simulation
+vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.do
new file mode 100755
index 000000000..cfe22dc41
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.do
@@ -0,0 +1,65 @@
+# file: simulate_mti.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $env(XILINX)/verilog/src/glbl.v
+vlog -work work ../../implement/results/routed.v
+vlog -work work b200_clk_gen_tb.v
+
+# run the simulation
+vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl
+#do wave.do
+#log -r /*
+run 50000ns
+
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.sh
new file mode 100755
index 000000000..497db4bbd
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.sh
@@ -0,0 +1,61 @@
+#/bin/sh
+# file: simulate_mti.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $XILINX/verilog/src/glbl.v
+vlog -work work ../../implement/results/routed.v
+vlog -work work b200_clk_gen_tb.v
+
+# run the simulation
+vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_ncsim.sh
new file mode 100755
index 000000000..8dd610f57
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_ncsim.sh
@@ -0,0 +1,64 @@
+#!/bin/sh
+# file: simulate_ncsim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+mkdir work
+
+# compile all of the files
+ncvlog -work work ${XILINX}/verilog/src/glbl.v
+ncvlog -work work ../../implement/results/routed.v
+ncvlog -work work b200_clk_gen_tb.v
+
+# elaborate and run the simulation
+ncsdfc ../../implement/results/routed.sdf
+
+ncelab -work work -access +wc -pulse_r 10 -nonotifier work.b200_clk_gen_tb work.glbl -sdf_cmd_file sdf_cmd_file
+ncsim -input  "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.b200_clk_gen_tb
+
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_vcs.sh
new file mode 100755
index 000000000..3566700b2
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_vcs.sh
@@ -0,0 +1,72 @@
+#!/bin/sh
+# file: simulate_vcs.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# remove old files
+rm -rf simv* csrc DVEfiles AN.DB
+
+# compile all of the files
+# Note that -sverilog is not strictly required- You can
+#   remove the -sverilog if you change the type of the
+#   localparam for the periods in the testbench file to 
+#   [63:0] from time
+  vlogan -sverilog \
+           b200_clk_gen_tb.v \
+           ../../implement/results/routed.v
+
+
+# prepare the simulation
+vcs -sdf max:b200_clk_gen_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
+        +libext+.v -debug b200_clk_gen_tb.v ../../implement/results/routed.v
+
+# run the simulation
+./simv -ucli -i ucli_commands.key
+
+# launch the viewer
+#dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/ucli_commands.key b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/ucli_commands.key
new file mode 100755
index 000000000..0548d1733
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/ucli_commands.key
@@ -0,0 +1,5 @@
+
+call {$vcdpluson}
+run 50000ns
+call {$vcdplusclose}
+quit
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/vcs_session.tcl
new file mode 100755
index 000000000..1438f6bed
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/vcs_session.tcl
@@ -0,0 +1 @@
+gui_open_window Wave
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/wave.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/wave.do
new file mode 100755
index 000000000..048ce6aa6
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/wave.do
@@ -0,0 +1,72 @@
+# file: wave.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /b200_clk_gen_tb/CLK_IN1
+add wave -noupdate /b200_clk_gen_tb/COUNT
+add wave -noupdate /b200_clk_gen_tb/LOCKED
+add wave -noupdate /b200_clk_gen_tb/RESET
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
+configure wave -namecolwidth 238
+configure wave -valuecolwidth 107
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {74848022 ps}
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen_flist.txt b/fpga/usrp3/top/b200/coregen/b200_clk_gen_flist.txt
new file mode 100644
index 000000000..044c06a12
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen_flist.txt
@@ -0,0 +1,53 @@
+# Output products list for <b200_clk_gen>
+b200_clk_gen/clk_wiz_v3_6_readme.txt
+b200_clk_gen/doc/clk_wiz_v3_6_readme.txt
+b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html
+b200_clk_gen/doc/pg065_clk_wiz.pdf
+b200_clk_gen/example_design/b200_clk_gen_exdes.ucf
+b200_clk_gen/example_design/b200_clk_gen_exdes.v
+b200_clk_gen/example_design/b200_clk_gen_exdes.xdc
+b200_clk_gen/implement/implement.bat
+b200_clk_gen/implement/implement.sh
+b200_clk_gen/implement/planAhead_ise.bat
+b200_clk_gen/implement/planAhead_ise.sh
+b200_clk_gen/implement/planAhead_ise.tcl
+b200_clk_gen/implement/planAhead_rdn.bat
+b200_clk_gen/implement/planAhead_rdn.sh
+b200_clk_gen/implement/planAhead_rdn.tcl
+b200_clk_gen/implement/xst.prj
+b200_clk_gen/implement/xst.scr
+b200_clk_gen/simulation/b200_clk_gen_tb.v
+b200_clk_gen/simulation/functional/simcmds.tcl
+b200_clk_gen/simulation/functional/simulate_isim.bat
+b200_clk_gen/simulation/functional/simulate_isim.sh
+b200_clk_gen/simulation/functional/simulate_mti.bat
+b200_clk_gen/simulation/functional/simulate_mti.do
+b200_clk_gen/simulation/functional/simulate_mti.sh
+b200_clk_gen/simulation/functional/simulate_ncsim.sh
+b200_clk_gen/simulation/functional/simulate_vcs.sh
+b200_clk_gen/simulation/functional/ucli_commands.key
+b200_clk_gen/simulation/functional/vcs_session.tcl
+b200_clk_gen/simulation/functional/wave.do
+b200_clk_gen/simulation/functional/wave.sv
+b200_clk_gen/simulation/timing/b200_clk_gen_tb.v
+b200_clk_gen/simulation/timing/sdf_cmd_file
+b200_clk_gen/simulation/timing/simcmds.tcl
+b200_clk_gen/simulation/timing/simulate_isim.sh
+b200_clk_gen/simulation/timing/simulate_mti.bat
+b200_clk_gen/simulation/timing/simulate_mti.do
+b200_clk_gen/simulation/timing/simulate_mti.sh
+b200_clk_gen/simulation/timing/simulate_ncsim.sh
+b200_clk_gen/simulation/timing/simulate_vcs.sh
+b200_clk_gen/simulation/timing/ucli_commands.key
+b200_clk_gen/simulation/timing/vcs_session.tcl
+b200_clk_gen/simulation/timing/wave.do
+b200_clk_gen.asy
+b200_clk_gen.gise
+b200_clk_gen.ucf
+b200_clk_gen.v
+b200_clk_gen.veo
+b200_clk_gen.xco
+b200_clk_gen.xdc
+b200_clk_gen.xise
+b200_clk_gen_flist.txt
+b200_clk_gen_xmdf.tcl
diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen_xmdf.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen_xmdf.tcl
new file mode 100755
index 000000000..58f510c56
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen_xmdf.tcl
@@ -0,0 +1,144 @@
+# The package naming convention is <core_name>_xmdf
+package provide b200_clk_gen_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::b200_clk_gen_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::b200_clk_gen_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_clk_gen
+}
+# ::b200_clk_gen_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::b200_clk_gen_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/clk_wiz_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/example_design/b200_clk_gen_exdes.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/doc/clk_wiz_ds709.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/doc/clk_wiz_gsg521.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/example_design/b200_clk_gen_exdes.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/implement.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/implement.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/xst.prj
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/xst.scr
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/b200_clk_gen_tb.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simcmds.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_isim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_vcs.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/ucli_commands.key
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/vcs_session.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/wave.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/wave.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.ejp
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_clk_gen
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.asy b/fpga/usrp3/top/b200/coregen/chipscope_icon.asy
new file mode 100644
index 000000000..a5c9ce410
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.asy
@@ -0,0 +1,13 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 chipscope_icon
+RECTANGLE Normal 32 32 544 864
+LINE Wide 576 112 544 112
+PIN 576 112 RIGHT 36
+PINATTR PinName control0[35:0]
+PINATTR Polarity BOTH
+LINE Wide 576 144 544 144
+PIN 576 144 RIGHT 36
+PINATTR PinName control1[35:0]
+PINATTR Polarity BOTH
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.ucf
new file mode 100644
index 000000000..b83296f8e
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.ucf
@@ -0,0 +1,9 @@
+NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
+TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
+#Update Constraints
+NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
+NET "U0/iSHIFT_OUT" TIG ;
+TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
+TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
+TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
+TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.xdc
new file mode 100644
index 000000000..903799425
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.xdc
@@ -0,0 +1,7 @@
+# icon XDC
+create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
+create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
+set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
+set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
+set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
+set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.gise b/fpga/usrp3/top/b200/coregen/chipscope_icon.gise
new file mode 100644
index 000000000..a4f878755
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.gise
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="chipscope_icon.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="chipscope_icon.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="chipscope_icon.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.ncf b/fpga/usrp3/top/b200/coregen/chipscope_icon.ncf
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.ngc b/fpga/usrp3/top/b200/coregen/chipscope_icon.ngc
new file mode 100644
index 000000000..58d57c1e1
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/chipscope_icon.ucf
new file mode 100644
index 000000000..b83296f8e
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.ucf
@@ -0,0 +1,9 @@
+NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
+TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
+#Update Constraints
+NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
+NET "U0/iSHIFT_OUT" TIG ;
+TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
+TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
+TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
+TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.v b/fpga/usrp3/top/b200/coregen/chipscope_icon.v
new file mode 100644
index 000000000..2fa3203dd
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.v
@@ -0,0 +1,29 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.4
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : chipscope_icon.v
+// /___/   /\     Timestamp  : Fri Mar 08 11:51:37 PST 2013
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: Verilog Synthesis Wrapper
+///////////////////////////////////////////////////////////////////////////////
+// This wrapper is used to integrate with Project Navigator and PlanAhead
+
+`timescale 1ns/1ps
+
+module chipscope_icon(
+    CONTROL0,
+    CONTROL1) /* synthesis syn_black_box syn_noprune=1 */;
+
+
+inout [35 : 0] CONTROL0;
+inout [35 : 0] CONTROL1;
+
+endmodule
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.veo b/fpga/usrp3/top/b200/coregen/chipscope_icon.veo
new file mode 100644
index 000000000..777580b34
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.veo
@@ -0,0 +1,29 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.4
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : chipscope_icon.veo
+// /___/   /\     Timestamp  : Fri Mar 08 11:51:37 PST 2013
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: ISE Instantiation template
+///////////////////////////////////////////////////////////////////////////////
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+chipscope_icon YourInstanceName (
+    .CONTROL0(CONTROL0), // INOUT BUS [35:0]
+    .CONTROL1(CONTROL1) // INOUT BUS [35:0]
+);
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.xco b/fpga/usrp3/top/b200/coregen/chipscope_icon.xco
new file mode 100644
index 000000000..69906ce4d
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.xco
@@ -0,0 +1,56 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.4
+# Date: Fri Mar  8 19:51:09 2013
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fgg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
+# END Select
+# BEGIN Parameters
+CSET component_name=chipscope_icon
+CSET constraint_type=external
+CSET enable_jtag_bufg=true
+CSET example_design=false
+CSET number_control_ports=2
+CSET use_ext_bscan=false
+CSET use_softbscan=false
+CSET use_unused_bscan=false
+CSET user_scan_chain=USER1
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-12-18T02:47:25Z
+# END Extra information
+GENERATE
+# CRC: 865957ec
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/chipscope_icon.xdc
new file mode 100644
index 000000000..903799425
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.xdc
@@ -0,0 +1,7 @@
+# icon XDC
+create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
+create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
+set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
+set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
+set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
+set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.xise b/fpga/usrp3/top/b200/coregen/chipscope_icon.xise
new file mode 100644
index 000000000..49d561436
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.xise
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="chipscope_icon.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="chipscope_icon.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|chipscope_icon" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="chipscope_icon.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/chipscope_icon" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_icon" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T11:51:40" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BD46AAD29AD5653980780005171DAA9E" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon_flist.txt b/fpga/usrp3/top/b200/coregen/chipscope_icon_flist.txt
new file mode 100644
index 000000000..435dc80e2
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon_flist.txt
@@ -0,0 +1,16 @@
+# Output products list for <chipscope_icon>
+_xmsgs/pn_parser.xmsgs
+chipscope_icon.asy
+chipscope_icon.constraints/chipscope_icon.ucf
+chipscope_icon.constraints/chipscope_icon.xdc
+chipscope_icon.gise
+chipscope_icon.ngc
+chipscope_icon.ucf
+chipscope_icon.v
+chipscope_icon.veo
+chipscope_icon.xco
+chipscope_icon.xdc
+chipscope_icon.xise
+chipscope_icon_flist.txt
+chipscope_icon_readme.txt
+chipscope_icon_xmdf.tcl
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_icon_readme.txt
new file mode 100644
index 000000000..ac93ce5a1
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon_readme.txt
@@ -0,0 +1,46 @@
+The following files were generated for 'chipscope_icon' in directory
+/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/
+
+XCO file generator:
+   Generate an XCO file for compatibility with legacy flows.
+
+   * chipscope_icon.xco
+
+Creates an implementation netlist:
+   Creates an implementation netlist for the IP.
+
+   * chipscope_icon.constraints/chipscope_icon.ucf
+   * chipscope_icon.constraints/chipscope_icon.xdc
+   * chipscope_icon.ngc
+   * chipscope_icon.ucf
+   * chipscope_icon.v
+   * chipscope_icon.veo
+   * chipscope_icon.xdc
+   * chipscope_icon_xmdf.tcl
+
+IP Symbol Generator:
+   Generate an IP symbol based on the current project options'.
+
+   * chipscope_icon.asy
+
+Generate ISE subproject:
+   Create an ISE subproject for use when including this core in ISE designs
+
+   * _xmsgs/pn_parser.xmsgs
+   * chipscope_icon.gise
+   * chipscope_icon.xise
+
+Deliver Readme:
+   Readme file for the IP.
+
+   * chipscope_icon_readme.txt
+
+Generate FLIST file:
+   Text file listing all of the output files produced when a customized core was
+   generated in the CORE Generator.
+
+   * chipscope_icon_flist.txt
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_icon_xmdf.tcl
new file mode 100755
index 000000000..241f4d5ae
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon_xmdf.tcl
@@ -0,0 +1,88 @@
+# The package naming convention is <core_name>_xmdf
+package provide chipscope_icon_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::chipscope_icon_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::chipscope_icon_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_icon
+}
+# ::chipscope_icon_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::chipscope_icon_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ncf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.xdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xcf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_icon
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
+
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.asy b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.asy
new file mode 100644
index 000000000..5342fbe4f
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.asy
@@ -0,0 +1,17 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 chipscope_ila_128
+RECTANGLE Normal 32 32 288 704
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName control[35:0]
+PINATTR Polarity IN
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName clk
+PINATTR Polarity IN
+LINE Wide 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName trig0[127:0]
+PINATTR Polarity IN
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.cdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.cdc
new file mode 100644
index 000000000..be4f8951b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.cdc
@@ -0,0 +1,144 @@
+#ChipScope Core Generator Project File Version 3.0
+#Fri Mar 08 11:53:53 PST 2013
+SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
+SignalExport.bus<0000>.name=TRIG0
+SignalExport.bus<0000>.offset=0.0
+SignalExport.bus<0000>.precision=0
+SignalExport.bus<0000>.radix=Bin
+SignalExport.bus<0000>.scaleFactor=1.0
+SignalExport.clockChannel=CLK
+SignalExport.dataEqualsTrigger=true
+SignalExport.triggerChannel<0000><0000>=TRIG0[0]
+SignalExport.triggerChannel<0000><0001>=TRIG0[1]
+SignalExport.triggerChannel<0000><0002>=TRIG0[2]
+SignalExport.triggerChannel<0000><0003>=TRIG0[3]
+SignalExport.triggerChannel<0000><0004>=TRIG0[4]
+SignalExport.triggerChannel<0000><0005>=TRIG0[5]
+SignalExport.triggerChannel<0000><0006>=TRIG0[6]
+SignalExport.triggerChannel<0000><0007>=TRIG0[7]
+SignalExport.triggerChannel<0000><0008>=TRIG0[8]
+SignalExport.triggerChannel<0000><0009>=TRIG0[9]
+SignalExport.triggerChannel<0000><0010>=TRIG0[10]
+SignalExport.triggerChannel<0000><0011>=TRIG0[11]
+SignalExport.triggerChannel<0000><0012>=TRIG0[12]
+SignalExport.triggerChannel<0000><0013>=TRIG0[13]
+SignalExport.triggerChannel<0000><0014>=TRIG0[14]
+SignalExport.triggerChannel<0000><0015>=TRIG0[15]
+SignalExport.triggerChannel<0000><0016>=TRIG0[16]
+SignalExport.triggerChannel<0000><0017>=TRIG0[17]
+SignalExport.triggerChannel<0000><0018>=TRIG0[18]
+SignalExport.triggerChannel<0000><0019>=TRIG0[19]
+SignalExport.triggerChannel<0000><0020>=TRIG0[20]
+SignalExport.triggerChannel<0000><0021>=TRIG0[21]
+SignalExport.triggerChannel<0000><0022>=TRIG0[22]
+SignalExport.triggerChannel<0000><0023>=TRIG0[23]
+SignalExport.triggerChannel<0000><0024>=TRIG0[24]
+SignalExport.triggerChannel<0000><0025>=TRIG0[25]
+SignalExport.triggerChannel<0000><0026>=TRIG0[26]
+SignalExport.triggerChannel<0000><0027>=TRIG0[27]
+SignalExport.triggerChannel<0000><0028>=TRIG0[28]
+SignalExport.triggerChannel<0000><0029>=TRIG0[29]
+SignalExport.triggerChannel<0000><0030>=TRIG0[30]
+SignalExport.triggerChannel<0000><0031>=TRIG0[31]
+SignalExport.triggerChannel<0000><0032>=TRIG0[32]
+SignalExport.triggerChannel<0000><0033>=TRIG0[33]
+SignalExport.triggerChannel<0000><0034>=TRIG0[34]
+SignalExport.triggerChannel<0000><0035>=TRIG0[35]
+SignalExport.triggerChannel<0000><0036>=TRIG0[36]
+SignalExport.triggerChannel<0000><0037>=TRIG0[37]
+SignalExport.triggerChannel<0000><0038>=TRIG0[38]
+SignalExport.triggerChannel<0000><0039>=TRIG0[39]
+SignalExport.triggerChannel<0000><0040>=TRIG0[40]
+SignalExport.triggerChannel<0000><0041>=TRIG0[41]
+SignalExport.triggerChannel<0000><0042>=TRIG0[42]
+SignalExport.triggerChannel<0000><0043>=TRIG0[43]
+SignalExport.triggerChannel<0000><0044>=TRIG0[44]
+SignalExport.triggerChannel<0000><0045>=TRIG0[45]
+SignalExport.triggerChannel<0000><0046>=TRIG0[46]
+SignalExport.triggerChannel<0000><0047>=TRIG0[47]
+SignalExport.triggerChannel<0000><0048>=TRIG0[48]
+SignalExport.triggerChannel<0000><0049>=TRIG0[49]
+SignalExport.triggerChannel<0000><0050>=TRIG0[50]
+SignalExport.triggerChannel<0000><0051>=TRIG0[51]
+SignalExport.triggerChannel<0000><0052>=TRIG0[52]
+SignalExport.triggerChannel<0000><0053>=TRIG0[53]
+SignalExport.triggerChannel<0000><0054>=TRIG0[54]
+SignalExport.triggerChannel<0000><0055>=TRIG0[55]
+SignalExport.triggerChannel<0000><0056>=TRIG0[56]
+SignalExport.triggerChannel<0000><0057>=TRIG0[57]
+SignalExport.triggerChannel<0000><0058>=TRIG0[58]
+SignalExport.triggerChannel<0000><0059>=TRIG0[59]
+SignalExport.triggerChannel<0000><0060>=TRIG0[60]
+SignalExport.triggerChannel<0000><0061>=TRIG0[61]
+SignalExport.triggerChannel<0000><0062>=TRIG0[62]
+SignalExport.triggerChannel<0000><0063>=TRIG0[63]
+SignalExport.triggerChannel<0000><0064>=TRIG0[64]
+SignalExport.triggerChannel<0000><0065>=TRIG0[65]
+SignalExport.triggerChannel<0000><0066>=TRIG0[66]
+SignalExport.triggerChannel<0000><0067>=TRIG0[67]
+SignalExport.triggerChannel<0000><0068>=TRIG0[68]
+SignalExport.triggerChannel<0000><0069>=TRIG0[69]
+SignalExport.triggerChannel<0000><0070>=TRIG0[70]
+SignalExport.triggerChannel<0000><0071>=TRIG0[71]
+SignalExport.triggerChannel<0000><0072>=TRIG0[72]
+SignalExport.triggerChannel<0000><0073>=TRIG0[73]
+SignalExport.triggerChannel<0000><0074>=TRIG0[74]
+SignalExport.triggerChannel<0000><0075>=TRIG0[75]
+SignalExport.triggerChannel<0000><0076>=TRIG0[76]
+SignalExport.triggerChannel<0000><0077>=TRIG0[77]
+SignalExport.triggerChannel<0000><0078>=TRIG0[78]
+SignalExport.triggerChannel<0000><0079>=TRIG0[79]
+SignalExport.triggerChannel<0000><0080>=TRIG0[80]
+SignalExport.triggerChannel<0000><0081>=TRIG0[81]
+SignalExport.triggerChannel<0000><0082>=TRIG0[82]
+SignalExport.triggerChannel<0000><0083>=TRIG0[83]
+SignalExport.triggerChannel<0000><0084>=TRIG0[84]
+SignalExport.triggerChannel<0000><0085>=TRIG0[85]
+SignalExport.triggerChannel<0000><0086>=TRIG0[86]
+SignalExport.triggerChannel<0000><0087>=TRIG0[87]
+SignalExport.triggerChannel<0000><0088>=TRIG0[88]
+SignalExport.triggerChannel<0000><0089>=TRIG0[89]
+SignalExport.triggerChannel<0000><0090>=TRIG0[90]
+SignalExport.triggerChannel<0000><0091>=TRIG0[91]
+SignalExport.triggerChannel<0000><0092>=TRIG0[92]
+SignalExport.triggerChannel<0000><0093>=TRIG0[93]
+SignalExport.triggerChannel<0000><0094>=TRIG0[94]
+SignalExport.triggerChannel<0000><0095>=TRIG0[95]
+SignalExport.triggerChannel<0000><0096>=TRIG0[96]
+SignalExport.triggerChannel<0000><0097>=TRIG0[97]
+SignalExport.triggerChannel<0000><0098>=TRIG0[98]
+SignalExport.triggerChannel<0000><0099>=TRIG0[99]
+SignalExport.triggerChannel<0000><0100>=TRIG0[100]
+SignalExport.triggerChannel<0000><0101>=TRIG0[101]
+SignalExport.triggerChannel<0000><0102>=TRIG0[102]
+SignalExport.triggerChannel<0000><0103>=TRIG0[103]
+SignalExport.triggerChannel<0000><0104>=TRIG0[104]
+SignalExport.triggerChannel<0000><0105>=TRIG0[105]
+SignalExport.triggerChannel<0000><0106>=TRIG0[106]
+SignalExport.triggerChannel<0000><0107>=TRIG0[107]
+SignalExport.triggerChannel<0000><0108>=TRIG0[108]
+SignalExport.triggerChannel<0000><0109>=TRIG0[109]
+SignalExport.triggerChannel<0000><0110>=TRIG0[110]
+SignalExport.triggerChannel<0000><0111>=TRIG0[111]
+SignalExport.triggerChannel<0000><0112>=TRIG0[112]
+SignalExport.triggerChannel<0000><0113>=TRIG0[113]
+SignalExport.triggerChannel<0000><0114>=TRIG0[114]
+SignalExport.triggerChannel<0000><0115>=TRIG0[115]
+SignalExport.triggerChannel<0000><0116>=TRIG0[116]
+SignalExport.triggerChannel<0000><0117>=TRIG0[117]
+SignalExport.triggerChannel<0000><0118>=TRIG0[118]
+SignalExport.triggerChannel<0000><0119>=TRIG0[119]
+SignalExport.triggerChannel<0000><0120>=TRIG0[120]
+SignalExport.triggerChannel<0000><0121>=TRIG0[121]
+SignalExport.triggerChannel<0000><0122>=TRIG0[122]
+SignalExport.triggerChannel<0000><0123>=TRIG0[123]
+SignalExport.triggerChannel<0000><0124>=TRIG0[124]
+SignalExport.triggerChannel<0000><0125>=TRIG0[125]
+SignalExport.triggerChannel<0000><0126>=TRIG0[126]
+SignalExport.triggerChannel<0000><0127>=TRIG0[127]
+SignalExport.triggerPort<0000>.name=TRIG0
+SignalExport.triggerPortCount=1
+SignalExport.triggerPortIsData<0000>=true
+SignalExport.triggerPortWidth<0000>=128
+SignalExport.type=ila
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.ucf
new file mode 100644
index 000000000..736db76a7
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.ucf
@@ -0,0 +1,15 @@
+#
+# Clock constraints
+#
+NET "CLK" TNM_NET = D_CLK ;
+INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
+TIMESPEC TS_D2_TO_T2_chipscope_ila_128 = FROM D2_CLK TO "FFS" TIG;
+TIMESPEC TS_J2_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J3_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J4_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG;
+
+#
+# Input keep/save net constraints
+#
+NET "TRIG0<*" S;
+NET "TRIG0<*" KEEP;
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.xdc
new file mode 100644
index 000000000..49e2b9e7b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.xdc
@@ -0,0 +1,6 @@
+#
+# Clock constraints
+#
+set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
+set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
+set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise
new file mode 100644
index 000000000..3af396d70
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="chipscope_ila_128.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="chipscope_ila_128.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="chipscope_ila_128.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ncf b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ncf
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ngc b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ngc
new file mode 100644
index 000000000..b5e78e4fd
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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7c22;?i7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j<5<722cij7>5;n070?6=3th8<=4?:683>5}#:l?1>8l4He;7?Mb0j2.9?o4keg9'5`6=:2c887>5;h16>5<<a:<1<75f3983>>o?83:17dli:188k7232900qo<ie;293?6=8r.9i84=5c9K`<2<@m=i7)<<b;ffb>"6m9097d=;:188m63=831b?;4?::k0<?6=3`2;6=44icd94?=h:=>1<75rb3db>5<0290;w)<j5;06f>Nc1=1Ch:l4$31a>aca3-;n<7<4i2694?=n;<0;66g<6;29?l5?2900e5>50;9jfc<722e9894?::a6c>=83=1<7>t$3g6>73e3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f8183>>oen3:17b<;4;29?xd5n?0;6:4?:1y'6`3=:<h0Di7;;If4f>"5;k0oik5+1d296>o4<3:17d=::188m60=831b?54?::k;4?6=3`hm6=44o367>5<<uk8m87>57;294~"5m<099o5Gd868La1e3-88n7jjf:&2a5<53`9?6=44i2794?=n;?0;66g<8;29?l>72900eoh50;9l612=831vn?h=:184>5<7s-8n97<:b:Jg=1=Ol>h0(?=m:ege?!7b8380e>:50;9j70<722c8:7>5;h1;>5<<a1:1<75fbg83>>i5<=0;66sm2g294?1=83:p(?k::37a?Mb><2Bo;o5+22`9```<,8o;6?5f3583>>o4=3:17d=9:188m6>=831b4=4?::kab?6=3f8?87>5;|`1a`<72>0;6=u+2d7960d<@m3?7Ej8b:&17g<cmo1/=h>52:k00?6=3`9>6=44i2494?=n;10;66g70;29?lda2900c?:;:188yg4bk3:1;7>50z&1a0<5=k1Ch4:4He5a?!44j3nnj6*>e181?l532900e>;50;9j73<722c847>5;h:3>5<<akl1<75`25694?=zj;oj6=48:183!4b=38>n6Fk959K`2d<,;9i6iki;%3f4?4<a:>1<75f3483>>o4>3:17d=7:188m=6=831bnk4?::m101<722wi>h650;594?6|,;o>6?;m;If:0>Nc?k1/>>l5ddd8 4c72;1b?94?::k01?6=3`9=6=44i2:94?=n090;66gmf;29?j43<3:17pl<e383>2<729q/>h;524`8La?33An<n6*=3c8gac=#9l:1>6g<4;29?l522900e>850;9j7=<722c3<7>5;h`e>5<<g;>?6=44}c1f4?6=?3:1<v*=e4811g=Ol0>0Di9m;%00f?bbn2.:i=4=;h17>5<<a:?1<75f3783>>o403:17d6?:188mg`=831d>9:50;9~f6bb290<6=4?{%0f1?42j2Bo595Gd6`8 75e2mom7)?j0;08m62=831b?84?::k02?6=3`936=44i9294?=njo0;66a=4583>>{e;mi1<7950;2x 7c22;?i7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j<5<722cij7>5;n070?6=3th8hl4?:683>5}#:l?1>8l4He;7?Mb0j2.9?o4keg9'5`6=:2c887>5;h16>5<<a:<1<75f3983>>o?83:17dli:188k7232900qo=k8;293?6=8r.9i84=5c9K`<2<@m=i7)<<b;ffb>"6m9097d=;:188m63=831b?;4?::k0<?6=3`2;6=44icd94?=h:=>1<75rb2f5>5<0290;w)<j5;06f>Nc1=1Ch:l4$31a>aca3-;n<7<4i2694?=n;<0;66g<6;29?l5?2900e5>50;9jfc<722e9894?::a7a2=83=1<7>t$3g6>73e3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f8183>>oen3:17b<;4;29?xd4l;0;6:4?:1y'6`3=:<h0Di7;;If4f>"5;k0oik5+1d296>o4<3:17d=::188m60=831b?54?::k;4?6=3`hm6=44o367>5<<uk9o<7>57;294~"5m<099o5Gd868La1e3-88n7jjf:&2a5<53`9?6=44i2794?=n;?0;66g<8;29?l>72900eoh50;9l612=831vn>ml:184>5<7s-8n97<:b:Jg=1=Ol>h0(?=m:ege?!7b8380e>:50;9j70<722c8:7>5;h1;>5<<a1:1<75fbg83>>i5<=0;66sm3bc94?1=83:p(?k::37a?Mb><2Bo;o5+22`9```<,8o;6?5f3583>>o4=3:17d=9:188m6>=831b4=4?::kab?6=3f8?87>5;|`0g=<72>0;6=u+2d7960d<@m3?7Ej8b:&17g<cmo1/=h>52:k00?6=3`9>6=44i2494?=n;10;66g70;29?lda2900c?:;:188yg5d>3:1;7>50z&1a0<5=k1Ch4:4He5a?!44j3nnj6*>e181?l532900e>;50;9j73<722c847>5;h:3>5<<akl1<75`25694?=zj:i?6=48:183!4b=38>n6Fk959K`2d<,;9i6iki;%3f4?4<a:>1<75f3483>>o4>3:17d=7:188m=6=831bnk4?::m101<722wi?n<50;594?6|,;o>6?;m;If:0>Nc?k1/>>l5ddd8 4c72;1b?94?::k01?6=3`9=6=44i2:94?=n090;66gmf;29?j43<3:17pl<c183>2<729q/>h;524`8La?33An<n6*=3c8gac=#9l:1>6g<4;29?l522900e>850;9j7=<722c3<7>5;h`e>5<<g;>?6=44}c1aa?6=?3:1<v*=e4811g=Ol0>0Di9m;%00f?bbn2.:i=4=;h17>5<<a:?1<75f3783>>o403:17d6?:188mg`=831d>9:50;9~f6dd290<6=4?{%0f1?42j2Bo595Gd6`8 75e2mom7)?j0;08m62=831b?84?::k02?6=3`936=44i9294?=njo0;66a=4583>>{e;kk1<7950;2x 7c22;?i7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j<5<722cij7>5;n070?6=3th8n;4?:683>5}#:l?1>8l4He;7?Mb0j2.9?o4keg9'5`6=:2c887>5;h16>5<<a:<1<75f3983>>o?83:17dli:188k7232900qo=m4;293?6=8r.9i84=5c9K`<2<@m=i7)<<b;ffb>"6m9097d=;:188m63=831b?;4?::k0<?6=3`2;6=44icd94?=h:=>1<75rb2`1>5<0290;w)<j5;06f>Nc1=1Ch:l4$31a>aca3-;n<7<4i2694?=n;<0;66g<6;29?l5?2900e5>50;9jfc<722e9894?::a7g6=83=1<7>t$3g6>73e3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f8183>>oen3:17b<;4;29?xd4il0;6:4?:1y'6`3=:<h0Di7;;If4f>"5;k0oik5+1d296>o4<3:17d=::188m60=831b?54?::k;4?6=3`hm6=44o367>5<<uk9jo7>57;294~"5m<099o5Gd868La1e3-88n7jjf:&2a5<53`9?6=44i2794?=n;?0;66g<8;29?l>72900eoh50;9l612=831vn>on:184>5<7s-8n97<:b:Jg=1=Ol>h0(?=m:ege?!7b8380e>:50;9j70<722c8:7>5;h1;>5<<a1:1<75fbg83>>i5<=0;66sm3`:94?1=83:p(?k::37a?Mb><2Bo;o5+22`9```<,8o;6?5f3583>>o4=3:17d=9:188m6>=831b4=4?::kab?6=3f8?87>5;|`0e3<72>0;6=u+2d7960d<@m3?7Ej8b:&17g<cmo1/=h>52:k00?6=3`9>6=44i2494?=n;10;66g70;29?lda2900c?:;:188yg5f<3:1;7>50z&1a0<5=k1Ch4:4He5a?!44j3nnj6*>e181?l532900e>;50;9j73<722c847>5;h:3>5<<akl1<75`25694?=zj:k;6=48:183!4b=38>n6Fk959K`2d<,;9i6iki;%3f4?4<a:>1<75f3483>>o4>3:17d=7:188m=6=831bnk4?::m101<722wi?4k50;594?6|,;o>6?;m;If:0>Nc?k1/>>l5ddd8 4c72;1b?94?::k01?6=3`9=6=44i2:94?=n090;66gmf;29?j43<3:17pl<9b83>2<729q/>h;524`8La?33An<n6*=3c8gac=#9l:1>6g<4;29?l522900e>850;9j7=<722c3<7>5;h`e>5<<g;>?6=44}c1:e?6=?3:1<v*=e4811g=Ol0>0Di9m;%00f?bbn2.:i=4=;h17>5<<a:?1<75f3783>>o403:17d6?:188mg`=831d>9:50;9~f6??290<6=4?{%0f1?42j2Bo595Gd6`8 75e2mom7)?j0;08m62=831b?84?::k02?6=3`936=44i9294?=njo0;66a=4583>>{e;0<1<7950;2x 7c22;?i7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j<5<722cij7>5;n070?6=3th8594?:683>5}#:l?1>8l4He;7?Mb0j2.9?o4keg9'5`6=:2c887>5;h16>5<<a:<1<75f3983>>o?83:17dli:188k7232900qo=62;293?6=8r.9i84=5c9K`<2<@m=i7)<<b;ffb>"6m9097d=;:188m63=831b?;4?::k0<?6=3`2;6=44icd94?=h:=>1<75rb2;3>5<0290;w)<j5;06f>Nc1=1Ch:l4$31a>aca3-;n<7<4i2694?=n;<0;66g<6;29?l5?2900e5>50;9jfc<722e9894?::a7=c=83=1<7>t$3g6>73e3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f8183>>oen3:17b<;4;29?xd40h0;6:4?:1y'6`3=:<h0Di7;;If4f>"5;k0oik5+1d296>o4<3:17d=::188m60=831b?54?::k;4?6=3`hm6=44o367>5<<uk9347>57;294~"5m<099o5Gd868La1e3-88n7jjf:&2a5<53`9?6=44i2794?=n;?0;66g<8;29?l>72900eoh50;9l612=831vn>69:184>5<7s-8n97<:b:Jg=1=Ol>h0(?=m:ege?!7b8380e>:50;9j70<722c8:7>5;h1;>5<<a1:1<75fbg83>>i5<=0;66sm39694?1=83:p(?k::37a?Mb><2Bo;o5+22`9```<,8o;6?5f3583>>o4=3:17d=9:188m6>=831b4=4?::kab?6=3f8?87>5;|`0<7<72>0;6=u+2d7960d<@m3?7Ej8b:&17g<cmo1/=h>52:k00?6=3`9>6=44i2494?=n;10;66g70;29?lda2900c?:;:188yg5?83:1;7>50z&1a0<5=k1Ch4:4He5a?!44j3nnj6*>e181?l532900e>;50;9j73<722c847>5;h:3>5<<akl1<75`25694?=zj:=n6=48:183!4b=38>n6Fk959K`2d<,;9i6iki;%3f4?4<a:>1<75f3483>>o4>3:17d=7:188m=6=831bnk4?::m101<722wi?:m50;594?6|,;o>6?;m;If:0>Nc?k1/>>l5ddd8 4c72;1b?94?::k01?6=3`9=6=44i2:94?=n090;66gmf;29?j43<3:17pl<7`83>2<729q/>h;524`8La?33An<n6*=3c8gac=#9l:1>6g<4;29?l522900e>850;9j7=<722c3<7>5;h`e>5<<g;>?6=44}c14<?6=?3:1<v*=e4811g=Ol0>0Di9m;%00f?bbn2.:i=4=;h17>5<<a:?1<75f3783>>o403:17d6?:188mg`=831d>9:50;9~f613290<6=4?{%0f1?42j2Bo595Gd6`8 75e2mom7)?j0;08m62=831b?84?::k02?6=3`936=44i9294?=njo0;66a=4583>>{e;>81<7950;2x 7c22;?i7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j<5<722cij7>5;n070?6=3th8;=4?:683>5}#:l?1>8l4He;7?Mb0j2.9?o4keg9'5`6=:2c887>5;h16>5<<a:<1<75f3983>>o?83:17dli:188k7232900qo=9e;293?6=8r.9i84=5c9K`<2<@m=i7)<<b;ffb>"6m9097d=;:188m63=831b?;4?::k0<?6=3`2;6=44icd94?=h:=>1<75rb24`>5<0290;w)<j5;06f>Nc1=1Ch:l4$31a>aca3-;n<7<4i2694?=n;<0;66g<6;29?l5?2900e5>50;9jfc<722e9894?::a73g=83=1<7>t$3g6>73e3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f8183>>oen3:17b<;4;29?xd4>10;6:4?:1y'6`3=:<h0Di7;;If4f>"5;k0oik5+1d296>o4<3:17d=::188m60=831b?54?::k;4?6=3`hm6=44o367>5<<uk9=:7>57;294~"5m<099o5Gd868La1e3-88n7jjf:&2a5<53`9?6=44i2794?=n;?0;66g<8;29?l>72900eoh50;9l612=831vn>8;:184>5<7s-8n97<:b:Jg=1=Ol>h0(?=m:ege?!7b8380e>:50;9j70<722c8:7>5;h1;>5<<a1:1<75fbg83>>i5<=0;66sm37094?1=83:p(?k::37a?Mb><2Bo;o5+22`9```<,8o;6?5f3583>>o4=3:17d=9:188m6>=831b4=4?::kab?6=3f8?87>5;|`01`<72>0;6=u+2d7960d<@m3?7Ej8b:&17g<cmo1/=h>52:k00?6=3`9>6=44i2494?=n;10;66g70;29?lda2900c?:;:188yg52k3:1;7>50z&1a0<5=k1Ch4:4He5a?!44j3nnj6*>e181?l532900e>;50;9j73<722c847>5;h:3>5<<akl1<75`25694?=zj:?j6=48:183!4b=38>n6Fk959K`2d<,;9i6iki;%3f4?4<a:>1<75f3483>>o4>3:17d=7:188m=6=831bnk4?::m101<722wi?8650;594?6|,;o>6?;m;If:0>Nc?k1/>>l5ddd8 4c72;1b?94?::k01?6=3`9=6=44i2:94?=n090;66gmf;29?j43<3:17pl<5783>2<729q/>h;524`8La?33An<n6*=3c8gac=#9l:1>6g<4;29?l522900e>850;9j7=<722c3<7>5;h`e>5<<g;>?6=44}c160?6=?3:1<v*=e4811g=Ol0>0Di9m;%00f?bbn2.:i=4=;h17>5<<a:?1<75f3783>>o403:17d6?:188mg`=831d>9:50;9~f635290<6=4?{%0f1?42j2Bo595Gd6`8 75e2mom7)?j0;08m62=831b?84?::k02?6=3`936=44i9294?=njo0;66a=4583>>{e;<:1<7950;2x 7c22;?i7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j<5<722cij7>5;n070?6=3th88h4?:683>5}#:l?1>8l4He;7?Mb0j2.9?o4keg9'5`6=:2c887>5;h16>5<<a:<1<75f3983>>o?83:17dli:188k7232900qo=;c;293?6=8r.9i84=5c9K`<2<@m=i7)<<b;ffb>"6m9097d=;:188m63=831b?;4?::k0<?6=3`2;6=44icd94?=h:=>1<75rb26;>5<0290;w)<j5;06f>Nc1=1Ch:l4$31a>aca3-;n<7<4i2694?=n;<0;66g<6;29?l5?2900e5>50;9jfc<722e9894?::a710=83=1<7>t$3g6>73e3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f8183>>oen3:17b<;4;29?xd4<=0;6:4?:1y'6`3=:<h0Di7;;If4f>"5;k0oik5+1d296>o4<3:17d=::188m60=831b?54?::k;4?6=3`hm6=44o367>5<<uk9?>7>57;294~"5m<099o5Gd868La1e3-88n7jjf:&2a5<53`9?6=44i2794?=n;?0;66g<8;29?l>72900eoh50;9l612=831vn>:?:184>5<7s-8n97<:b:Jg=1=Ol>h0(?=m:ege?!7b8380e>:50;9j70<722c8:7>5;h1;>5<<a1:1<75fbg83>>i5<=0;66sm32g94?1=83:p(?k::37a?Mb><2Bo;o5+22`9```<,8o;6?5f3583>>o4=3:17d=9:188m6>=831b4=4?::kab?6=3f8?87>5;|`07f<72>0;6=u+2d7960d<@m3?7Ej8b:&17g<cmo1/=h>52:k00?6=3`9>6=44i2494?=n;10;66g70;29?lda2900c?:;:188yg54i3:1;7>50z&1a0<5=k1Ch4:4He5a?!44j3nnj6*>e181?l532900e>;50;9j73<722c847>5;h:3>5<<akl1<75`25694?=zj:936=48:183!4b=38>n6Fk959K`2d<,;9i6iki;%3f4?4<a:>1<75f3483>>o4>3:17d=7:188m=6=831bnk4?::m101<722wi?>850;594?6|,;o>6?;m;If:0>Nc?k1/>>l5ddd8 4c72;1b?94?::k01?6=3`9=6=44i2:94?=n090;66gmf;29?j43<3:17pl<3383>2<729q/>h;524`8La?33An<n6*=3c8gac=#9l:1>6g<4;29?l522900e>850;9j7=<722c3<7>5;h`e>5<<g;>?6=44}c104?6=?3:1<v*=e4811g=Ol0>0Di9m;%00f?bbn2.:i=4=;h17>5<<a:?1<75f3783>>o403:17d6?:188mg`=831d>9:50;9~f64b290<6=4?{%0f1?42j2Bo595Gd6`8 75e2mom7)?j0;08m62=831b?84?::k02?6=3`936=44i9294?=njo0;66a=4583>>{e;;i1<7950;2x 7c22;?i7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j<5<722cij7>5;n070?6=3th8>l4?:683>5}#:l?1>8l4He;7?Mb0j2.9?o4keg9'5`6=:2c887>5;h16>5<<a:<1<75f3983>>o?83:17dli:188k7232900qo==8;293?6=8r.9i84=5c9K`<2<@m=i7)<<b;ffb>"6m9097d=;:188m63=831b?;4?::k0<?6=3`2;6=44icd94?=h:=>1<75rb205>5<0290;w)<j5;06f>Nc1=1Ch:l4$31a>aca3-;n<7<4i2694?=n;<0;66g<6;29?l5?2900e5>50;9jfc<722e9894?::a772=83=1<7>t$3g6>73e3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f8183>>oen3:17b<;4;29?xd49;0;6:4?:1y'6`3=:<h0Di7;;If4f>"5;k0oik5+1d296>o4<3:17d=::188m60=831b?54?::k;4?6=3`hm6=44o367>5<<uk8mo7>57;294~"5m<099o5Gd868La1e3-88n7jjf:&2a5<53`9?6=44i2794?=n;?0;66g<8;29?l>72900eoh50;9l612=831vn>k;:184>5<7s-8n97<:b:Jg=1=Ol>h0(?=m:ege?!7b8380e>:50;9j70<722c8:7>5;h1;>5<<a1:1<75fbg83>>i5<=0;66sm3bg94?1=83:p(?k::37a?Mb><2Bo;o5+22`9```<,8o;6?5f3583>>o4=3:17d=9:188m6>=831b4=4?::kab?6=3f8?87>5;|`0f=<72>0;6=u+2d7960d<@m3?7Ej8b:&17g<cmo1/=h>52:k00?6=3`9>6=44i2494?=n;10;66g70;29?lda2900c?:;:188yg5f:3:1;7>50z&1a0<5=k1Ch4:4He5a?!44j3nnj6*>e181?l532900e>;50;9j73<722c847>5;h:3>5<<akl1<75`25694?=zj:2h6=48:183!4b=38>n6Fk959K`2d<,;9i6iki;%3f4?4<a:>1<75f3483>>o4>3:17d=7:188m=6=831bnk4?::m101<722wi?:850;594?6|,;o>6?;m;If:0>Nc?k1/>>l5ddd8 4c72;1b?94?::k01?6=3`9=6=44i2:94?=n090;66gmf;29?j43<3:17pl<6183>2<729q/>h;524`8La?33An<n6*=3c8gac=#9l:1>6g<4;29?l522900e>850;9j7=<722c3<7>5;h`e>5<<g;>?6=44}c17e?6=?3:1<v*=e4811g=Ol0>0Di9m;%00f?bbn2.:i=4=;h17>5<<a:?1<75f3783>>o403:17d6?:188mg`=831d>9:50;9~f653290<6=4?{%0f1?42j2Bo595Gd6`8 75e2mom7)?j0;08m62=831b?84?::k02?6=3`936=44i9294?=njo0;66a=4583>>{e:l<1<7950;2x 7c22;?i7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j<5<722cij7>5;n070?6=3th8>>4?:283>5}#:l?1=om4He;7?Mb0j2.9?o4keg9'5`6=92c<n7>5;h`e>5<<g;>?6=44}c115?6=;3:1<v*=e482ff=Ol0>0Di9m;%00f?bbn2.:i=4>;h5a>5<<akl1<75`25694?=zj:;m6=4<:183!4b=3;io6Fk959K`2d<,;9i6iki;%3f4?7<a>h1<75fbg83>>i5<=0;66sm30f94?5=83:p(?k::0``?Mb><2Bo;o5+22`9```<,8o;6<5f7c83>>oen3:17b<;4;29?xd49k0;6>4?:1y'6`3=9ki0Di7;;If4f>"5;k0oik5+1d295>o0j3:17dli:188k7232900qo=>9;297?6=8r.9i84>bb9K`<2<@m=i7)<<b;ffb>"6m90:7d9m:188mg`=831d>9:50;9~f67029086=4?{%0f1?7ek2Bo595Gd6`8 75e2mom7)?j0;38m2d=831bnk4?::m101<722wi?<;50;194?6|,;o>6<ll;If:0>Nc?k1/>>l5ddd8 4c7281b;o4?::kab?6=3f8?87>5;|`054<72:0;6=u+2d795ge<@m3?7Ej8b:&17g<cmo1/=h>51:k4f?6=3`hm6=44o367>5<<uk9;j7>53;294~"5m<0:nn5Gd868La1e3-88n7jjf:&2a5<63`=i6=44icd94?=h:=>1<75rb22g>5<4290;w)<j5;3ag>Nc1=1Ch:l4$31a>aca3-;n<7?4i6`94?=njo0;66a=4583>>{e;9h1<7=50;2x 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7c228i;7Ej64:Jg3g=#::h1hhh4$0g3>4=n?k0;66g8d;29?lda2900c?:;:188yg>4>3:1?7>50z&1a0<c1:1Ch4:4He5a?!44j3nnj6g8f;29?l45>3:17b<<a;29?xd?;:0;694?:1y'6`3=:::0Di7;;If4f>"5;k0oik5f7g83>>od;3:17d<:4;29?j45?3:17pl73`83>6<729q/>h;5d818La?33An<n6*=3c8gac=n?o0;66g=2783>>i5;h0;66sm82594?2=83:p(?k::313?Mb><2Bo;o5+22`9```<a>l1<75fc283>>o5==0;66a=2683>>{e0:o1<7=50;2x 7c22m387Ej64:Jg3g=#::h1hhh4i6d94?=n:;<1<75`22c94?=zj19i6=4;:183!4b=388<6Fk959K`2d<,;9i6iki;h5e>5<<aj91<75f24694?=h:;=1<75rb961>5<4290;w)<j5;f:7>Nc1=1Ch:l4$31a>aca3`=m6=44i305>5<<g;9j6=44}c:0b?6=<3:1<v*=e48175=Ol0>0Di9m;%00f?bbn2c<j7>5;ha0>5<<a;??6=44o304>5<<uk2?:7>53;294~"5m<0o5>5Gd868La1e3-88n7jjf:k4b?6=3`89:7>5;n00e?6=3th38>4?:583>5}#:l?1>>>4He;7?Mb0j2.9?o4keg9j3c<722ch?7>5;h060?6=3f89;7>5;|`;0d<72:0;6=u+2d79`<5<@m3?7Ej8b:&17g<cmo1b;k4?::k163<722e9?l4?::a<11=83>1<7>t$3g6>7573An286Fk7c9'66d=lll0e:h50;9jg6<722c9994?::m162<722wi49k50;194?6|,;o>6i7<;If:0>Nc?k1/>>l5ddd8m2`=831b>?850;9l66g=831vn5:m:187>5<7s-8n97<<0:Jg=1=Ol>h0(?=m:ege?l1a2900en=50;9j602=831d>?950;9~f=3529086=4?{%0f1?b>;2Bo595Gd6`8 75e2mom7d9i:188m7412900c?=n:188yg>3n3:187>50z&1a0<5;91Ch4:4He5a?!44j3nnj6g8f;29?le42900e?;;:188k7402900qo6:6;297?6=8r.9i84k929K`<2<@m=i7)<<b;ffb>o0n3:17d<=6;29?j44i3:17pl75283>1<729q/>h;52228La?33An<n6*=3c8gac=n?o0;66gl3;29?l42<3:17b<=7;29?xd?=00;6>4?:1y'6`3=l090Di7;;If4f>"5;k0oik5f7g83>>o5:?0;66a=3`83>>{e0:?1<7<50;2x 7c22;8j7Ej64:Jg3g=#::h1hhh4$0g3>4e<a8n96=44o31b>5<<uk2857>52;294~"5m<09>l5Gd868La1e3-88n7jjf:&2a5<6k2c:h?4?::m17d<722wi4>j50;094?6|,;o>6?<n;If:0>Nc?k1/>>l5ddd8 4c728i0e<j=:188k75f2900qo6;1;296?6=8r.9i84=2`9K`<2<@m=i7)<<b;ffb>"6m90:o6g>d383>>i5;h0;66sm85794?4=83:p(?k::30b?Mb><2Bo;o5+22`9```<,8o;6<m4i0f1>5<<g;9j6=44}c:7=?6=:3:1<v*=e4816d=Ol0>0Di9m;%00f?bbn2.:i=4>c:k2`7<722e9?l4?::a<1b=8381<7>t$3g6>74f3An286Fk7c9'66d=lll0(<k?:0a8m4b52900c?=n:188yg>293:1>7>50z&1a0<5:h1Ch4:4He5a?!44j3nnj6*>e182g>o6l;0;66a=3`83>>{e0<?1<7<50;2x 7c22;8j7Ej64:Jg3g=#::h1hhh4$0g3>4e<a8n96=44o31b>5<<uk2>47>52;294~"5m<09>l5Gd868La1e3-88n7jjf:&2a5<6k2c:h?4?::m17d<722wi4>:50;794?6|,;o>6<m;;If:0>Nc?k1/>>l5ddd8 4c7281b;o4?::k4`?6=3`hm6=44i364>5<<g;>?6=44}c:0<?6==3:1<v*=e482g1=Ol0>0Di9m;%00f?bbn2.:i=4>;h5a>5<<a>n1<75fbg83>>o5<>0;66a=4583>>{e0:i1<7;50;2x 7c228i?7Ej64:Jg3g=#::h1hhh4$0g3>4=n?k0;66g8d;29?lda2900e?:8:188k7232900qo6;0;291?6=8r.9i84>c59K`<2<@m=i7)<<b;ffb>"6m90:7d9m:188m2b=831bnk4?::k102<722e9894?::a<12=83?1<7>t$3g6>4e33An286Fk7c9'66d=lll0(<k?:09j3g<722c<h7>5;h`e>5<<a;><6=44o367>5<<uk2?47>55;294~"5m<0:o95Gd868La1e3-88n7jjf:&2a5<63`=i6=44i6f94?=njo0;66g=4683>>i5<=0;66sm85a94?3=83:p(?k::0a7?Mb><2Bo;o5+22`9```<,8o;6<5f7c83>>o0l3:17dli:188m7202900c?:;:188yg>283:197>50z&1a0<6k=1Ch4:4He5a?!44j3nnj6*>e182?l1e2900e:j50;9jfc<722c98:4?::m101<722wi48:50;794?6|,;o>6<m;;If:0>Nc?k1/>>l5ddd8 4c7281b;o4?::k4`?6=3`hm6=44i364>5<<g;>?6=44}c:63?6==3:1<v*=e482g1=Ol0>0Di9m;%00f?bbn2.:i=4>;h5a>5<<a>n1<75fbg83>>o5<>0;66a=4583>>{e=;81<7=50;2x 7c22m387Ej64:Jg3g=#::h1hhh4i6d94?=n:;<1<75`22c94?=zj<;m6=4;:183!4b=388<6Fk959K`2d<,;9i6iki;h5e>5<<aj91<75f24694?=h:;=1<75rb405>5<4290;w)<j5;f:7>Nc1=1Ch:l4$31a>aca3`=m6=44i305>5<<g;9j6=44}c717?6=<3:1<v*=e48175=Ol0>0Di9m;%00f?bbn2c<j7>5;ha0>5<<a;??6=44o304>5<<uk?9m7>53;294~"5m<0o5>5Gd868La1e3-88n7jjf:k4b?6=3`89:7>5;n00e?6=3th>>:4?:583>5}#:l?1>>>4He;7?Mb0j2.9?o4keg9j3c<722ch?7>5;h060?6=3f89;7>5;|`66`<72:0;6=u+2d79`<5<@m3?7Ej8b:&17g<cmo1b;k4?::k163<722e9?l4?::a17d=83>1<7>t$3g6>7573An286Fk7c9'66d=lll0e:h50;9jg6<722c9994?::m162<722wi9><50;194?6|,;o>6i7<;If:0>Nc?k1/>>l5ddd8m2`=831b>?850;9l66g=831vn8<i:187>5<7s-8n97<<0:Jg=1=Ol>h0(?=m:ege?l1a2900en=50;9j602=831d>?950;9~f05129086=4?{%0f1?b>;2Bo595Gd6`8 75e2mom7d9i:188m7412900c?=n:188yg34;3:187>50z&1a0<5;91Ch4:4He5a?!44j3nnj6g8f;29?le42900e?;;:188k7402900qo;<a;297?6=8r.9i84k929K`<2<@m=i7)<<b;ffb>o0n3:17d<=6;29?j44i3:17pl:3683>1<729q/>h;52228La?33An<n6*=3c8gac=n?o0;66gl3;29?l42<3:17b<=7;29?xd2;l0;6>4?:1y'6`3=l090Di7;;If4f>"5;k0oik5f7g83>>o5:?0;66a=3`83>>{e=:h1<7:50;2x 7c22;9;7Ej64:Jg3g=#::h1hhh4i6d94?=nk:0;66g=5583>>i5:>0;66sm55094?5=83:p(?k::e;0?Mb><2Bo;o5+22`9```<a>l1<75f23494?=h::k1<75rb41e>5<3290;w)<j5;004>Nc1=1Ch:l4$31a>aca3`=m6=44ib194?=n:<>1<75`23594?=zj<>>6=4<:183!4b=3n2?6Fk959K`2d<,;9i6iki;h5e>5<<a;8=6=44o31b>5<<uk?9=7>52;294~"5m<09>l5Gd868La1e3-88n7jjf:&2a5<6k2c:h?4?::m17d<722wi9?;50;094?6|,;o>6?<n;If:0>Nc?k1/>>l5ddd8 4c728i0e<j=:188k75f2900qo;=9;296?6=8r.9i84=2`9K`<2<@m=i7)<<b;ffb>"6m90:o6g>d383>>i5;h0;66sm53f94?4=83:p(?k::30b?Mb><2Bo;o5+22`9```<,8o;6<m4i0f1>5<<g;9j6=44}c705?6=:3:1<v*=e4816d=Ol0>0Di9m;%00f?bbn2.:i=4>c:k2`7<722e9?l4?::a163=8381<7>t$3g6>74f3An286Fk7c9'66d=lll0(<k?:0a8m4b52900c?=n:188yg3413:1>7>50z&1a0<5:h1Ch4:4He5a?!44j3nnj6*>e182g>o6l;0;66a=3`83>>{e=:n1<7<50;2x 7c22;8j7Ej64:Jg3g=#::h1hhh4$0g3>4e<a8n96=44o31b>5<<uk??=7>52;294~"5m<09>l5Gd868La1e3-88n7jjf:&2a5<6k2c:h?4?::m17d<722wi99:50;094?6|,;o>6?<n;If:0>Nc?k1/>>l5ddd8 4c728i0e<j=:188k75f2900qo;=0;291?6=8r.9i84>c59K`<2<@m=i7)<<b;ffb>"6m90:7d9m:188m2b=831bnk4?::k102<722e9894?::a172=83?1<7>t$3g6>4e33An286Fk7c9'66d=lll0(<k?:09j3g<722c<h7>5;h`e>5<<a;><6=44o367>5<<uk?947>55;294~"5m<0:o95Gd868La1e3-88n7jjf:&2a5<63`=i6=44i6f94?=njo0;66g=4683>>i5<=0;66sm53a94?3=83:p(?k::0a7?Mb><2Bo;o5+22`9```<,8o;6<5f7c83>>o0l3:17dli:188m7202900c?:;:188yg3483:197>50z&1a0<6k=1Ch4:4He5a?!44j3nnj6*>e182?l1e2900e:j50;9jfc<722c98:4?::m101<722wi9>:50;794?6|,;o>6<m;;If:0>Nc?k1/>>l5ddd8 4c7281b;o4?::k4`?6=3`hm6=44i364>5<<g;>?6=44}c70<?6==3:1<v*=e482g1=Ol0>0Di9m;%00f?bbn2.:i=4>;h5a>5<<a>n1<75fbg83>>o5<>0;66a=4583>>{e=:i1<7;50;2x 7c228i?7Ej64:Jg3g=#::h1hhh4$0g3>4=n?k0;66g8d;29?lda2900e?:8:188k7232900qo;;0;291?6=8r.9i84>c59K`<2<@m=i7)<<b;ffb>"6m90:7d9m:188m2b=831bnk4?::k102<722e9894?::a115=83?1<7>t$3g6>4e33An286Fk7c9'66d=lll0(<k?:09j3g<722c<h7>5;h`e>5<<a;><6=44o367>5<<uk=i<7>53;294~"5m<09>o5Gd868La1e3-88n7jjf:&2a5<512c:h?4?::k2`6<722e9?l4?::a3d`=83>1<7>t$3g6>74d3An286Fk7c9'66d=lll0(<k?:0`2?l7c:3:17d?k3;29?l7c<3:17b<<a;29?xd0il0;684?:1y'6`3=:;n0Di7;;If4f>"5;k0oik5+1d295f?<,;>:6io?;h3g6?6=3`;o?7>5;h3g0?6=3`;o97>5;n00e?6=3th<4;4?:583>5}#:l?1=n;4He;7?Mb0j2.9?o4keg9'5`6=981b;o4?::kab?6=3`8>87>5;n070?6=3th<484?:583>5}#:l?1=n;4He;7?Mb0j2.9?o4keg9'5`6=981b;o4?::kab?6=3`8>87>5;n070?6=3th<494?:583>5}#:l?1=n;4He;7?Mb0j2.9?o4keg9'5`6=981b;o4?::kab?6=3`8>87>5;n070?6=3th<4>4?:583>5}#:l?1=n;4He;7?Mb0j2.9?o4keg9'5`6=981b;o4?::kab?6=3`8>87>5;n070?6=3th<4?4?:583>5}#:l?1=n;4He;7?Mb0j2.9?o4keg9'5`6=981b;o4?::kab?6=3`8>87>5;n070?6=3th<4<4?:583>5}#:l?1=n;4He;7?Mb0j2.9?o4keg9'5`6=981b;o4?::kab?6=3`8>87>5;n070?6=3th<4=4?:583>5}#:l?1=n;4He;7?Mb0j2.9?o4keg9'5`6=981b;o4?::kab?6=3`8>87>5;n070?6=3th<;k4?:583>5}#:l?1=n;4He;7?Mb0j2.9?o4keg9'5`6=981b;o4?::kab?6=3`8>87>5;n070?6=3th<5h4?:283>5}#:l?1>?l4He;7?Mb0j2.9?o4keg9'5`6=9j1b=i<50;9j5a5=831d>>o50;9~f2g4290?6=4?{%0f1?7d82Bo595Gd6`8 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7272:n0b?=i:598yg15n3:1m7>50z&1a0<5=l1Ch4:4He5a?_1f28q8>7s+22`9```<,8o;695f8183>>oen3:17d9k:188k7232900c?:9:188m6c=83.98=4<d:l17c<732c8o7>5$363>6b<f;9m6<54i2`94?"5<908h6`=3g81?>o4i3:1(?:?:2f8j75a2:10e>750;&105<4l2d9?k4;;:a366=8331<7>t$3g6>73c3An286Fk7c9'66d=lll0(<k?:39j71<722c897>5;h15>5<<a:21<75f7e83>>o?83:17dli:188k7232900c?:::188yg16<3:187>50z&1a0<5;91Ch4:4He5a?!44j3nnj6g8f;29?le42900e?;;:188k7402900qo9>5;290?6=8r.9i84=319K`<2<@m=i7)<<b;ffb>o0n3:17dm<:188m7332900c?<8:188yg16>3:187>50z&1a0<5;91Ch4:4He5a?!44j3nnj6g8f;29?le42900e?;;:188k7402900qo9>7;290?6=8r.9i84=319K`<2<@m=i7)<<b;ffb>o0n3:17dm<:188m7332900c?<8:188yg1603:187>50z&1a0<5;91Ch4:4He5a?!44j3nnj6g8f;29?le42900e?;;:188k7402900qo9>9;29e?6=8r.9i84=5d9K`<2<@m=i7W9n:0y06?{#::h1hhh4$0g3>1=n090;66gmf;29?l1c2900c?:;:188k7212900e>k50;&105<4l2d9?k4?;:k0g?6=,;>;6>j4n31e>4=<a:h1<7*=4180`>h5;o0976g<a;29 7272:n0b?=i:298m6?=83.98=4<d:l17c<332wi;<o50;c94?6|,;o>6?;j;If:0>Nc?k1Q;l4>{209y!44j3nnj6*>e187?l>72900eoh50;9j3a<722e9894?::m103<722c8i7>5$363>6b<f;9m6=54i2a94?"5<908h6`=3g82?>o4j3:1(?:?:2f8j75a2;10e>o50;&105<4l2d9?k4<;:k0=?6=,;>;6>j4n31e>1=<uk=:n7>5a;294~"5m<099h5Gd868La1e3S=j6<u<2;'66d=lll0(<k?:59j<5<722cij7>5;h5g>5<<g;>?6=44o365>5<<a:o1<7*=4180`>h5;o0;76g<c;29 7272:n0b?=i:098m6d=83.98=4<d:l17c<532c8m7>5$363>6b<f;9m6>54i2;94?"5<908h6`=3g87?>{e?8i1<7750;2x 7c22;?o7Ej64:Jg3g=#::h1hhh4$0g3>7=n;=0;66g<5;29?l512900e>650;9j3a<722c3<7>5;h`e>5<<g;>?6=44o366>5<<uk=;<7>54;294~"5m<09?=5Gd868La1e3-88n7jjf:k4b?6=3`i86=44i377>5<<g;8<6=44}c535?6=<3:1<v*=e48175=Ol0>0Di9m;%00f?bbn2c<j7>5;ha0>5<<a;??6=44o304>5<<uk=;>7>54;294~"5m<09?=5Gd868La1e3-88n7jjf:k4b?6=3`i86=44i377>5<<g;8<6=44}c537?6=<3:1<v*=e48175=Ol0>0Di9m;%00f?bbn2c<j7>5;ha0>5<<a;??6=44o304>5<<uk=;87>54;294~"5m<09?=5Gd868La1e3-88n7jjf:k4b?6=3`i86=44i377>5<<g;8<6=44}c531?6=i3:1<v*=e4811`=Ol0>0Di9m;[5b>4}4:3w/>>l5ddd8 4c72=1b4=4?::kab?6=3`=o6=44o367>5<<g;>=6=44i2g94?"5<908h6`=3g83?>o4k3:1(?:?:2f8j75a2810e>l50;&105<4l2d9?k4=;:k0e?6=,;>;6>j4n31e>6=<a:31<7*=4180`>h5;o0?76sm71494?g=83:p(?k::37f?Mb><2Bo;o5U7`8264=u-88n7jjf:&2a5<33`2;6=44icd94?=n?m0;66a=4583>>i5<?0;66g<e;29 7272:n0b?=i:198m6e=83.98=4<d:l17c<632c8n7>5$363>6b<f;9m6?54i2c94?"5<908h6`=3g80?>o413:1(?:?:2f8j75a2=10qo9?7;29e?6=8r.9i84=5d9K`<2<@m=i7W9n:0y06?{#::h1hhh4$0g3>1=n090;66gmf;29?l1c2900c?:;:188k7212900e>k50;&105<4l2d9?k4?;:k0g?6=,;>;6>j4n31e>4=<a:h1<7*=4180`>h5;o0976g<a;29 7272:n0b?=i:298m6?=83.98=4<d:l17c<332wi;=650;;94?6|,;o>6?;k;If:0>Nc?k1/>>l5ddd8 4c72;1b?94?::k01?6=3`9=6=44i2:94?=n?m0;66g70;29?lda2900c?:;:188k7222900qo:8e;297?6=8r.9i84k929K`<2<@m=i7)<<b;ffb>o0n3:17d<=6;29?j44i3:17pl;7c83>1<729q/>h;52228La?33An<n6*=3c8gac=n?o0;66gl3;29?l42<3:17b<=7;29?xd30;0;6>4?:1y'6`3=l090Di7;;If4f>"5;k0oik5f7g83>>o5:?0;66a=3`83>>{e<>l1<7:50;2x 7c22;9;7Ej64:Jg3g=#::h1hhh4i6d94?=nk:0;66g=5583>>i5:>0;66sm49494?5=83:p(?k::e;0?Mb><2Bo;o5+22`9```<a>l1<75f23494?=h::k1<75rb5:0>5<3290;w)<j5;004>Nc1=1Ch:l4$31a>aca3`=m6=44ib194?=n:<>1<75`23594?=zj=2j6=4<:183!4b=3n2?6Fk959K`2d<,;9i6iki;h5e>5<<a;8=6=44o31b>5<<uk>3;7>54;294~"5m<09?=5Gd868La1e3-88n7jjf:k4b?6=3`i86=44i377>5<<g;8<6=44}c6;a?6=;3:1<v*=e48g=6=Ol0>0Di9m;%00f?bbn2c<j7>5;h012?6=3f88m7>5;|`7<g<72=0;6=u+2d79666<@m3?7Ej8b:&17g<cmo1b;k4?::k`7?6=3`8>87>5;n013?6=3th?5?4?:283>5}#:l?1h4=4He;7?Mb0j2.9?o4keg9j3c<722c9>;4?::m17d<722wi85h50;694?6|,;o>6?=?;If:0>Nc?k1/>>l5ddd8m2`=831bo>4?::k111<722e9>:4?::a0<0=8391<7>t$3g6>a?43An286Fk7c9'66d=lll0e:h50;9j670=831d>>o50;9~f1?4290?6=4?{%0f1?4482Bo595Gd6`8 75e2mom7d9i:188mf5=831b>8:50;9l671=831vn976:180>5<7s-8n97j63:Jg=1=Ol>h0(?=m:ege?l1a2900e?<9:188k75f2900qo:8d;296?6=8r.9i84=2`9K`<2<@m=i7)<<b;ffb>"6m90:o6g>d383>>i5;h0;66sm49394?4=83:p(?k::30b?Mb><2Bo;o5+22`9```<,8o;6<m4i0f1>5<<g;9j6=44}c6;1?6=:3:1<v*=e4816d=Ol0>0Di9m;%00f?bbn2.:i=4>c:k2`7<722e9?l4?::a0=?=8381<7>t$3g6>74f3An286Fk7c9'66d=lll0(<k?:0a8m4b52900c?=n:188yg2?l3:1>7>50z&1a0<5:h1Ch4:4He5a?!44j3nnj6*>e182g>o6l;0;66a=3`83>>{e<0;1<7<50;2x 7c22;8j7Ej64:Jg3g=#::h1hhh4$0g3>4e<a8n96=44o31b>5<<uk>297>52;294~"5m<09>l5Gd868La1e3-88n7jjf:&2a5<6k2c:h?4?::m17d<722wi84650;094?6|,;o>6?<n;If:0>Nc?k1/>>l5ddd8 4c728i0e<j=:188k75f2900qo:8c;291?6=8r.9i84>c59K`<2<@m=i7)<<b;ffb>"6m90:7d9m:188m2b=831bnk4?::k102<722e9894?::a0=6=83?1<7>t$3g6>4e33An286Fk7c9'66d=lll0(<k?:09j3g<722c<h7>5;h`e>5<<a;><6=44o367>5<<uk>387>55;294~"5m<0:o95Gd868La1e3-88n7jjf:&2a5<63`=i6=44i6f94?=njo0;66g=4683>>i5<=0;66sm49:94?3=83:p(?k::0a7?Mb><2Bo;o5+22`9```<,8o;6<5f7c83>>o0l3:17dli:188m7202900c?:;:188yg2?k3:197>50z&1a0<6k=1Ch4:4He5a?!44j3nnj6*>e182?l1e2900e:j50;9jfc<722c98:4?::m101<722wi84>50;794?6|,;o>6<m;;If:0>Nc?k1/>>l5ddd8 4c7281b;o4?::k4`?6=3`hm6=44i364>5<<g;>?6=44}c6:0?6==3:1<v*=e482g1=Ol0>0Di9m;%00f?bbn2.:i=4>;h5a>5<<a>n1<75fbg83>>o5<>0;66a=4583>>{e<0=1<7;50;2x 7c228i?7Ej64:Jg3g=#::h1hhh4$0g3>4=n?k0;66g8d;29?lda2900e?:8:188k7232900qo:n3;291?6=8r.9i84>c59K`<2<@m=i7)<<b;ffb>"6m90:7d9m:188m2b=831bnk4?::k102<722e9894?::a0d2=83?1<7>t$3g6>4e33An286Fk7c9'66d=lll0(<k?:09j3g<722c<h7>5;h`e>5<<a;><6=44o367>5<<uk>j97>55;294~"5m<0:o95Gd868La1e3-88n7jjf:&2a5<63`=i6=44i6f94?=njo0;66g=4683>>i5<=0;66sm4`494?3=83:p(?k::0a7?Mb><2Bo;o5+22`9```<,8o;6<5f7c83>>o0l3:17dli:188m7202900c?:;:188yg2f?3:197>50z&1a0<6k=1Ch4:4He5a?!44j3nnj6*>e182?l1e2900e:j50;9jfc<722c98:4?::m101<722wi8l650;794?6|,;o>6<m;;If:0>Nc?k1/>>l5ddd8 4c7281b;o4?::k4`?6=3`hm6=44i364>5<<g;>?6=44}c6b=?6==3:1<v*=e482g1=Ol0>0Di9m;%00f?bbn2.:i=4>;h5a>5<<a>n1<75fbg83>>o5<>0;66a=4583>>{e<hk1<7;50;2x 7c228i?7Ej64:Jg3g=#::h1hhh4$0g3>4=n?k0;66g8d;29?lda2900e?:8:188k7232900qo9k5;290?6=8r.9i84=2b9K`<2<@m=i7)?j0;3bb>o6l;0;66g>d283>>o6l=0;66a=3`83>>{e=?:1<7850;2x 7c22;8n7Ej64:Jg3g=#9l:146g>d383>>o6l:0;66g>d583>>o6l<0;66g>d783>>i5;h0;66sm57394?3=83:p(?k::30g?Mb><2Bo;o5+1d29`>o6l;0;66g>d283>>o6l=0;66g>d483>>i5;h0;66sm57094?1=83:p(?k::30e?Mb><2Bo;o5+1d29a>o6l;0;66g>d283>>o6l=0;66g>d483>>o6l?0;66g>d683>>i5;h0;66sm57194?1=83:p(?k::30e?Mb><2Bo;o5+1d29a>o6l;0;66g>d283>>o6l=0;66g>d483>>o6l?0;66g>d683>>i5;h0;66sm57694?0=83:p(?k::30f?Mb><2Bo;o5+1d295fg<a8n96=44i0f0>5<<a8n?6=44i0f6>5<<a8n=6=44o31b>5<<uk2;?7>57;294~"5m<09>k5Gd868La1e3-;n<7?l7:k2`7<722c:h>4?::k2`1<722c:h84?::k2`3<722c:h:4?::m17d<722wi4=m50;194?6|,;o>6?<m;If:0>Nc?k1/=h>5109j5a4=831b=i=50;9l66g=831vn5>k:184>5<7s-8n97<=f:Jg=1=Ol>h0(<k?:0`:?l7c:3:17d?k3;29?l7c<3:17d?k5;29?l7c>3:17d?k7;29?j44i3:17pl71383>3<729q/>h;523g8La?33An<n6*>e18`4>o6l;0;66g>d283>>o6l=0;66g>d483>>o6l?0;66a=3`83>>{e0891<7950;2x 7c22;8m7Ej64:Jg3g=#9l:1=nk4i0f1>5<<a8n86=44i0f7>5<<a8n>6=44i0f5>5<<a8n<6=44o31b>5<<uk2:87>57;294~"5m<09>k5Gd868La1e3-;n<7m4i0f1>5<<a8n86=44i0f7>5<<a8n>6=44i0f5>5<<a8n<6=44o31b>5<<uk2;47>57;294~"5m<09>k5Gd868La1e3-;n<7?ld:k2`7<722c:h>4?::k2`1<722c:h84?::k2`3<722c:h:4?::m17d<722wi4=750;694?6|,;o>6?<l;If:0>Nc?k1/=h>51`d8m4b52900e<j<:188m4b32900c?=n:188yg>7j3:1;7>50z&1a0<5:o1Ch4:4He5a?!7b83=27d?k2;29?l7c;3:17d?k4;29?l7c=3:17d?k6;29?l7c?3:17b<<a;29?xd0nl0;694?:1y'6`3=9j90Di7;;If4f>"5;k0oik5+1d295>o0j3:17dli:188m7202900c?:;:188yg>783:187>50z&1a0<6k:1Ch4:4He5a?!44j3nnj6*>e182?l1e2900eoh50;9j611=831d>9:50;9~f=6629086=4?{%0f1?45j2Bo595Gd6`8 4c728kn7)<;1;fb4>o6l;0;66g>d283>>i5;h0;66sm87794?2=83:p(?k::0a0?Mb><2Bo;o5+22`9```<,8o;6<5f7c83>>oen3:17d<;7;29?j43<3:17pl76783>6<729q/>h;523`8La?33An<n6*>e182e`=n9m81<75f1e194?=h::k1<75rb6g6>5<3290;w)<j5;3`7>Nc1=1Ch:l4$31a>aca3-;n<7?4i6`94?=njo0;66g=4683>>i5<=0;66sm7d494?5=83:p(?k::30a?Mb><2Bo;o5+1d295dc<a8n96=44i0f0>5<<g;9j6=44}c:24?6=>3:1<v*=e4816`=Ol0>0Di9m;%3f4?7d92c:h?4?::k2`6<722c:h94?::k2`0<722c:h;4?::m17d<722wi4<?50;794?6|,;o>6?<k;If:0>Nc?k1/=h>51b48m4b52900e<j<:188m4b32900e<j::188k75f2900qo6?f;293?6=8r.9i84=2g9K`<2<@m=i7)?j0;3`g>o6l;0;66g>d283>>o6l=0;66g>d483>>o6l?0;66g>d683>>i5;h0;66smbe394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66smc8;94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek021<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8594?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek0<1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8794?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek0>1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8194?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek081<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8294?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek1l1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc9g94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek1n1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc9a94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek1h1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc9c94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek131<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc9:94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek1=1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc9794?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek1>1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc9194?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek181<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc9394?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek1:1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc6d94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek>o1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc6f94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek>i1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcg;94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{eko21<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcg594?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{eko<1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcg794?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{eko>1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcg194?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{eko81<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcg394?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{eko:1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcdg94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekln1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcda94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{eklh1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcdc94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekl31<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcd:94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekl=1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcd494?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekl?1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcd194?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekl81<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcd394?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekl:1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smced94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekmo1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcef94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekmi1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smce`94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekmk1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smce:94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekm=1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smce494?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekm?1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smce694?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekm91<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smce094?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekm;1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smce294?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekjl1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcbf94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekji1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcb`94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekjk1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcb;94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekj21<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcb594?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekj<1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcb794?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekj>1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcb094?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekj;1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcb294?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekkl1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smccg94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekkn1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcca94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekkh1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smccc94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekk31<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcc594?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekk<1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcc794?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekk>1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcc194?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekk81<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcc394?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekk:1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`d94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekho1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`a94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekhh1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`c94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekh31<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`:94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekh=1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`494?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekh?1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`694?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekh91<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`394?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekh:1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8d94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek0o1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8f94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek0i1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8`94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek0k1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc8394?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek1<1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcgc94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekll1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcd694?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekm31<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcbg94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekj91<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smcc:94?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ekhn1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66smc`094?5=83:p(?k::0``?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66a=4583>>{ek>h1<7=50;2x 7c228hh7Ej64:Jg3g=#9l:1=<5+22`9```<a>h1<75fbg83>>i5<=0;66sm91d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm92d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm95d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm94d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm97d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm96d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm99f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm90d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm93f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm89d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8ba94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8df94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8cc94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8c`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8ca94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8cf94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8cg94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8cd94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8bc94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8b`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8bf94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8bg94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8bd94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8ec94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8e`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8ea94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8ef94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8eg94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8ed94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8dc94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8d`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8da94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8dg94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8dd94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8gc94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8g`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8ga94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8gf94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8gg94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8gd94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm91f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88794?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88`94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88g94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm88d94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`294?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`394?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`094?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`194?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`694?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`494?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`594?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`:94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`;94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`c94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8``94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`a94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm8`f94?2=83:p(?k::0a1?Mb><2Bo;o5+1d2954=#::h1hhh4i6`94?=njo0;66g=4383>>i5<=0;66sm7g294?2=83:p(?k::0`f?Mb><2Bo;o5+1d295>"5;k0oik5f7c83>>o>>3:17dli:188k7232900qo9i1;290?6=8r.9i84>bd9K`<2<@m=i7)?j0;38 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\ No newline at end of file
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ucf
new file mode 100644
index 000000000..736db76a7
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ucf
@@ -0,0 +1,15 @@
+#
+# Clock constraints
+#
+NET "CLK" TNM_NET = D_CLK ;
+INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
+TIMESPEC TS_D2_TO_T2_chipscope_ila_128 = FROM D2_CLK TO "FFS" TIG;
+TIMESPEC TS_J2_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J3_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J4_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG;
+
+#
+# Input keep/save net constraints
+#
+NET "TRIG0<*" S;
+NET "TRIG0<*" KEEP;
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.v b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.v
new file mode 100644
index 000000000..20690c1dd
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.v
@@ -0,0 +1,31 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.4
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : chipscope_ila_128.v
+// /___/   /\     Timestamp  : Fri Mar 08 11:53:53 PST 2013
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: Verilog Synthesis Wrapper
+///////////////////////////////////////////////////////////////////////////////
+// This wrapper is used to integrate with Project Navigator and PlanAhead
+
+`timescale 1ns/1ps
+
+module chipscope_ila_128(
+    CONTROL,
+    CLK,
+    TRIG0) /* synthesis syn_black_box syn_noprune=1 */;
+
+
+inout [35 : 0] CONTROL;
+input CLK;
+input [127 : 0] TRIG0;
+
+endmodule
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.veo b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.veo
new file mode 100644
index 000000000..ba0ec8116
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.veo
@@ -0,0 +1,30 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.4
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : chipscope_ila_128.veo
+// /___/   /\     Timestamp  : Fri Mar 08 11:53:53 PST 2013
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: ISE Instantiation template
+///////////////////////////////////////////////////////////////////////////////
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+chipscope_ila_128 YourInstanceName (
+    .CONTROL(CONTROL), // INOUT BUS [35:0]
+    .CLK(CLK), // IN
+    .TRIG0(TRIG0) // IN BUS [127:0]
+);
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xco b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xco
new file mode 100644
index 000000000..41a6a11be
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xco
@@ -0,0 +1,141 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.4
+# Date: Fri Mar  8 19:52:17 2013
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fgg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
+# END Select
+# BEGIN Parameters
+CSET check_bramcount=false
+CSET component_name=chipscope_ila_128
+CSET constraint_type=external
+CSET counter_width_1=Disabled
+CSET counter_width_10=Disabled
+CSET counter_width_11=Disabled
+CSET counter_width_12=Disabled
+CSET counter_width_13=Disabled
+CSET counter_width_14=Disabled
+CSET counter_width_15=Disabled
+CSET counter_width_16=Disabled
+CSET counter_width_2=Disabled
+CSET counter_width_3=Disabled
+CSET counter_width_4=Disabled
+CSET counter_width_5=Disabled
+CSET counter_width_6=Disabled
+CSET counter_width_7=Disabled
+CSET counter_width_8=Disabled
+CSET counter_width_9=Disabled
+CSET data_port_width=0
+CSET data_same_as_trigger=true
+CSET disable_save_keep=false
+CSET enable_storage_qualification=true
+CSET enable_trigger_output_port=false
+CSET example_design=false
+CSET exclude_from_data_storage_1=false
+CSET exclude_from_data_storage_10=false
+CSET exclude_from_data_storage_11=false
+CSET exclude_from_data_storage_12=false
+CSET exclude_from_data_storage_13=false
+CSET exclude_from_data_storage_14=false
+CSET exclude_from_data_storage_15=false
+CSET exclude_from_data_storage_16=false
+CSET exclude_from_data_storage_2=false
+CSET exclude_from_data_storage_3=false
+CSET exclude_from_data_storage_4=false
+CSET exclude_from_data_storage_5=false
+CSET exclude_from_data_storage_6=false
+CSET exclude_from_data_storage_7=false
+CSET exclude_from_data_storage_8=false
+CSET exclude_from_data_storage_9=false
+CSET match_type_1=basic_with_edges
+CSET match_type_10=basic_with_edges
+CSET match_type_11=basic_with_edges
+CSET match_type_12=basic_with_edges
+CSET match_type_13=basic_with_edges
+CSET match_type_14=basic_with_edges
+CSET match_type_15=basic_with_edges
+CSET match_type_16=basic_with_edges
+CSET match_type_2=basic_with_edges
+CSET match_type_3=basic_with_edges
+CSET match_type_4=basic_with_edges
+CSET match_type_5=basic_with_edges
+CSET match_type_6=basic_with_edges
+CSET match_type_7=basic_with_edges
+CSET match_type_8=basic_with_edges
+CSET match_type_9=basic_with_edges
+CSET match_units_1=1
+CSET match_units_10=1
+CSET match_units_11=1
+CSET match_units_12=1
+CSET match_units_13=1
+CSET match_units_14=1
+CSET match_units_15=1
+CSET match_units_16=1
+CSET match_units_2=1
+CSET match_units_3=1
+CSET match_units_4=1
+CSET match_units_5=1
+CSET match_units_6=1
+CSET match_units_7=1
+CSET match_units_8=1
+CSET match_units_9=1
+CSET max_sequence_levels=1
+CSET number_of_trigger_ports=1
+CSET sample_data_depth=1024
+CSET sample_on=Rising
+CSET trigger_port_width_1=128
+CSET trigger_port_width_10=8
+CSET trigger_port_width_11=8
+CSET trigger_port_width_12=8
+CSET trigger_port_width_13=8
+CSET trigger_port_width_14=8
+CSET trigger_port_width_15=8
+CSET trigger_port_width_16=8
+CSET trigger_port_width_2=8
+CSET trigger_port_width_3=8
+CSET trigger_port_width_4=8
+CSET trigger_port_width_5=8
+CSET trigger_port_width_6=8
+CSET trigger_port_width_7=8
+CSET trigger_port_width_8=8
+CSET trigger_port_width_9=8
+CSET use_rpms=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-12-18T02:47:40Z
+# END Extra information
+GENERATE
+# CRC: 194c140a
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xdc
new file mode 100644
index 000000000..49e2b9e7b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xdc
@@ -0,0 +1,6 @@
+#
+# Clock constraints
+#
+set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
+set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
+set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
new file mode 100644
index 000000000..b5d414354
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="chipscope_ila_128.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="chipscope_ila_128.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|chipscope_ila_128" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="chipscope_ila_128.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/chipscope_ila_128" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_ila_128" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T11:53:54" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9340B6BAD141C451B74411D3998AD5A4" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128_flist.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_flist.txt
new file mode 100644
index 000000000..7ee610500
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_flist.txt
@@ -0,0 +1,18 @@
+# Output products list for <chipscope_ila_128>
+_xmsgs/pn_parser.xmsgs
+chipscope_ila_128.asy
+chipscope_ila_128.cdc
+chipscope_ila_128.constraints/chipscope_ila_128.ucf
+chipscope_ila_128.constraints/chipscope_ila_128.xdc
+chipscope_ila_128.gise
+chipscope_ila_128.ncf
+chipscope_ila_128.ngc
+chipscope_ila_128.ucf
+chipscope_ila_128.v
+chipscope_ila_128.veo
+chipscope_ila_128.xco
+chipscope_ila_128.xdc
+chipscope_ila_128.xise
+chipscope_ila_128_flist.txt
+chipscope_ila_128_readme.txt
+chipscope_ila_128_xmdf.tcl
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_readme.txt
new file mode 100644
index 000000000..395331e42
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_readme.txt
@@ -0,0 +1,48 @@
+The following files were generated for 'chipscope_ila_128' in directory
+/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/
+
+XCO file generator:
+   Generate an XCO file for compatibility with legacy flows.
+
+   * chipscope_ila_128.xco
+
+Creates an implementation netlist:
+   Creates an implementation netlist for the IP.
+
+   * chipscope_ila_128.cdc
+   * chipscope_ila_128.constraints/chipscope_ila_128.ucf
+   * chipscope_ila_128.constraints/chipscope_ila_128.xdc
+   * chipscope_ila_128.ncf
+   * chipscope_ila_128.ngc
+   * chipscope_ila_128.ucf
+   * chipscope_ila_128.v
+   * chipscope_ila_128.veo
+   * chipscope_ila_128.xdc
+   * chipscope_ila_128_xmdf.tcl
+
+IP Symbol Generator:
+   Generate an IP symbol based on the current project options'.
+
+   * chipscope_ila_128.asy
+
+Generate ISE subproject:
+   Create an ISE subproject for use when including this core in ISE designs
+
+   * _xmsgs/pn_parser.xmsgs
+   * chipscope_ila_128.gise
+   * chipscope_ila_128.xise
+
+Deliver Readme:
+   Readme file for the IP.
+
+   * chipscope_ila_128_readme.txt
+
+Generate FLIST file:
+   Text file listing all of the output files produced when a customized core was
+   generated in the CORE Generator.
+
+   * chipscope_ila_128_flist.txt
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_xmdf.tcl
new file mode 100755
index 000000000..e4af2b327
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_xmdf.tcl
@@ -0,0 +1,87 @@
+# The package naming convention is <core_name>_xmdf
+package provide chipscope_ila_128_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::chipscope_ila_128_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::chipscope_ila_128_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila_128
+}
+# ::chipscope_ila_128_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::chipscope_ila_128_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.cdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.constraints/chipscope_ila_128.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
+incr fcount
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.ncf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.constraints/chipscope_ila_128.xdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila_128
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.asy b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.asy
new file mode 100644
index 000000000..3eef48558
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.asy
@@ -0,0 +1,17 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 chipscope_ila_256
+RECTANGLE Normal 32 32 288 704
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName control[35:0]
+PINATTR Polarity IN
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName clk
+PINATTR Polarity IN
+LINE Wide 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName trig0[255:0]
+PINATTR Polarity IN
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.cdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.cdc
new file mode 100644
index 000000000..562f53ff9
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.cdc
@@ -0,0 +1,272 @@
+#ChipScope Core Generator Project File Version 3.0
+#Fri Mar 08 16:13:02 PST 2013
+SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
+SignalExport.bus<0000>.name=TRIG0
+SignalExport.bus<0000>.offset=0.0
+SignalExport.bus<0000>.precision=0
+SignalExport.bus<0000>.radix=Bin
+SignalExport.bus<0000>.scaleFactor=1.0
+SignalExport.clockChannel=CLK
+SignalExport.dataEqualsTrigger=true
+SignalExport.triggerChannel<0000><0000>=TRIG0[0]
+SignalExport.triggerChannel<0000><0001>=TRIG0[1]
+SignalExport.triggerChannel<0000><0002>=TRIG0[2]
+SignalExport.triggerChannel<0000><0003>=TRIG0[3]
+SignalExport.triggerChannel<0000><0004>=TRIG0[4]
+SignalExport.triggerChannel<0000><0005>=TRIG0[5]
+SignalExport.triggerChannel<0000><0006>=TRIG0[6]
+SignalExport.triggerChannel<0000><0007>=TRIG0[7]
+SignalExport.triggerChannel<0000><0008>=TRIG0[8]
+SignalExport.triggerChannel<0000><0009>=TRIG0[9]
+SignalExport.triggerChannel<0000><0010>=TRIG0[10]
+SignalExport.triggerChannel<0000><0011>=TRIG0[11]
+SignalExport.triggerChannel<0000><0012>=TRIG0[12]
+SignalExport.triggerChannel<0000><0013>=TRIG0[13]
+SignalExport.triggerChannel<0000><0014>=TRIG0[14]
+SignalExport.triggerChannel<0000><0015>=TRIG0[15]
+SignalExport.triggerChannel<0000><0016>=TRIG0[16]
+SignalExport.triggerChannel<0000><0017>=TRIG0[17]
+SignalExport.triggerChannel<0000><0018>=TRIG0[18]
+SignalExport.triggerChannel<0000><0019>=TRIG0[19]
+SignalExport.triggerChannel<0000><0020>=TRIG0[20]
+SignalExport.triggerChannel<0000><0021>=TRIG0[21]
+SignalExport.triggerChannel<0000><0022>=TRIG0[22]
+SignalExport.triggerChannel<0000><0023>=TRIG0[23]
+SignalExport.triggerChannel<0000><0024>=TRIG0[24]
+SignalExport.triggerChannel<0000><0025>=TRIG0[25]
+SignalExport.triggerChannel<0000><0026>=TRIG0[26]
+SignalExport.triggerChannel<0000><0027>=TRIG0[27]
+SignalExport.triggerChannel<0000><0028>=TRIG0[28]
+SignalExport.triggerChannel<0000><0029>=TRIG0[29]
+SignalExport.triggerChannel<0000><0030>=TRIG0[30]
+SignalExport.triggerChannel<0000><0031>=TRIG0[31]
+SignalExport.triggerChannel<0000><0032>=TRIG0[32]
+SignalExport.triggerChannel<0000><0033>=TRIG0[33]
+SignalExport.triggerChannel<0000><0034>=TRIG0[34]
+SignalExport.triggerChannel<0000><0035>=TRIG0[35]
+SignalExport.triggerChannel<0000><0036>=TRIG0[36]
+SignalExport.triggerChannel<0000><0037>=TRIG0[37]
+SignalExport.triggerChannel<0000><0038>=TRIG0[38]
+SignalExport.triggerChannel<0000><0039>=TRIG0[39]
+SignalExport.triggerChannel<0000><0040>=TRIG0[40]
+SignalExport.triggerChannel<0000><0041>=TRIG0[41]
+SignalExport.triggerChannel<0000><0042>=TRIG0[42]
+SignalExport.triggerChannel<0000><0043>=TRIG0[43]
+SignalExport.triggerChannel<0000><0044>=TRIG0[44]
+SignalExport.triggerChannel<0000><0045>=TRIG0[45]
+SignalExport.triggerChannel<0000><0046>=TRIG0[46]
+SignalExport.triggerChannel<0000><0047>=TRIG0[47]
+SignalExport.triggerChannel<0000><0048>=TRIG0[48]
+SignalExport.triggerChannel<0000><0049>=TRIG0[49]
+SignalExport.triggerChannel<0000><0050>=TRIG0[50]
+SignalExport.triggerChannel<0000><0051>=TRIG0[51]
+SignalExport.triggerChannel<0000><0052>=TRIG0[52]
+SignalExport.triggerChannel<0000><0053>=TRIG0[53]
+SignalExport.triggerChannel<0000><0054>=TRIG0[54]
+SignalExport.triggerChannel<0000><0055>=TRIG0[55]
+SignalExport.triggerChannel<0000><0056>=TRIG0[56]
+SignalExport.triggerChannel<0000><0057>=TRIG0[57]
+SignalExport.triggerChannel<0000><0058>=TRIG0[58]
+SignalExport.triggerChannel<0000><0059>=TRIG0[59]
+SignalExport.triggerChannel<0000><0060>=TRIG0[60]
+SignalExport.triggerChannel<0000><0061>=TRIG0[61]
+SignalExport.triggerChannel<0000><0062>=TRIG0[62]
+SignalExport.triggerChannel<0000><0063>=TRIG0[63]
+SignalExport.triggerChannel<0000><0064>=TRIG0[64]
+SignalExport.triggerChannel<0000><0065>=TRIG0[65]
+SignalExport.triggerChannel<0000><0066>=TRIG0[66]
+SignalExport.triggerChannel<0000><0067>=TRIG0[67]
+SignalExport.triggerChannel<0000><0068>=TRIG0[68]
+SignalExport.triggerChannel<0000><0069>=TRIG0[69]
+SignalExport.triggerChannel<0000><0070>=TRIG0[70]
+SignalExport.triggerChannel<0000><0071>=TRIG0[71]
+SignalExport.triggerChannel<0000><0072>=TRIG0[72]
+SignalExport.triggerChannel<0000><0073>=TRIG0[73]
+SignalExport.triggerChannel<0000><0074>=TRIG0[74]
+SignalExport.triggerChannel<0000><0075>=TRIG0[75]
+SignalExport.triggerChannel<0000><0076>=TRIG0[76]
+SignalExport.triggerChannel<0000><0077>=TRIG0[77]
+SignalExport.triggerChannel<0000><0078>=TRIG0[78]
+SignalExport.triggerChannel<0000><0079>=TRIG0[79]
+SignalExport.triggerChannel<0000><0080>=TRIG0[80]
+SignalExport.triggerChannel<0000><0081>=TRIG0[81]
+SignalExport.triggerChannel<0000><0082>=TRIG0[82]
+SignalExport.triggerChannel<0000><0083>=TRIG0[83]
+SignalExport.triggerChannel<0000><0084>=TRIG0[84]
+SignalExport.triggerChannel<0000><0085>=TRIG0[85]
+SignalExport.triggerChannel<0000><0086>=TRIG0[86]
+SignalExport.triggerChannel<0000><0087>=TRIG0[87]
+SignalExport.triggerChannel<0000><0088>=TRIG0[88]
+SignalExport.triggerChannel<0000><0089>=TRIG0[89]
+SignalExport.triggerChannel<0000><0090>=TRIG0[90]
+SignalExport.triggerChannel<0000><0091>=TRIG0[91]
+SignalExport.triggerChannel<0000><0092>=TRIG0[92]
+SignalExport.triggerChannel<0000><0093>=TRIG0[93]
+SignalExport.triggerChannel<0000><0094>=TRIG0[94]
+SignalExport.triggerChannel<0000><0095>=TRIG0[95]
+SignalExport.triggerChannel<0000><0096>=TRIG0[96]
+SignalExport.triggerChannel<0000><0097>=TRIG0[97]
+SignalExport.triggerChannel<0000><0098>=TRIG0[98]
+SignalExport.triggerChannel<0000><0099>=TRIG0[99]
+SignalExport.triggerChannel<0000><0100>=TRIG0[100]
+SignalExport.triggerChannel<0000><0101>=TRIG0[101]
+SignalExport.triggerChannel<0000><0102>=TRIG0[102]
+SignalExport.triggerChannel<0000><0103>=TRIG0[103]
+SignalExport.triggerChannel<0000><0104>=TRIG0[104]
+SignalExport.triggerChannel<0000><0105>=TRIG0[105]
+SignalExport.triggerChannel<0000><0106>=TRIG0[106]
+SignalExport.triggerChannel<0000><0107>=TRIG0[107]
+SignalExport.triggerChannel<0000><0108>=TRIG0[108]
+SignalExport.triggerChannel<0000><0109>=TRIG0[109]
+SignalExport.triggerChannel<0000><0110>=TRIG0[110]
+SignalExport.triggerChannel<0000><0111>=TRIG0[111]
+SignalExport.triggerChannel<0000><0112>=TRIG0[112]
+SignalExport.triggerChannel<0000><0113>=TRIG0[113]
+SignalExport.triggerChannel<0000><0114>=TRIG0[114]
+SignalExport.triggerChannel<0000><0115>=TRIG0[115]
+SignalExport.triggerChannel<0000><0116>=TRIG0[116]
+SignalExport.triggerChannel<0000><0117>=TRIG0[117]
+SignalExport.triggerChannel<0000><0118>=TRIG0[118]
+SignalExport.triggerChannel<0000><0119>=TRIG0[119]
+SignalExport.triggerChannel<0000><0120>=TRIG0[120]
+SignalExport.triggerChannel<0000><0121>=TRIG0[121]
+SignalExport.triggerChannel<0000><0122>=TRIG0[122]
+SignalExport.triggerChannel<0000><0123>=TRIG0[123]
+SignalExport.triggerChannel<0000><0124>=TRIG0[124]
+SignalExport.triggerChannel<0000><0125>=TRIG0[125]
+SignalExport.triggerChannel<0000><0126>=TRIG0[126]
+SignalExport.triggerChannel<0000><0127>=TRIG0[127]
+SignalExport.triggerChannel<0000><0128>=TRIG0[128]
+SignalExport.triggerChannel<0000><0129>=TRIG0[129]
+SignalExport.triggerChannel<0000><0130>=TRIG0[130]
+SignalExport.triggerChannel<0000><0131>=TRIG0[131]
+SignalExport.triggerChannel<0000><0132>=TRIG0[132]
+SignalExport.triggerChannel<0000><0133>=TRIG0[133]
+SignalExport.triggerChannel<0000><0134>=TRIG0[134]
+SignalExport.triggerChannel<0000><0135>=TRIG0[135]
+SignalExport.triggerChannel<0000><0136>=TRIG0[136]
+SignalExport.triggerChannel<0000><0137>=TRIG0[137]
+SignalExport.triggerChannel<0000><0138>=TRIG0[138]
+SignalExport.triggerChannel<0000><0139>=TRIG0[139]
+SignalExport.triggerChannel<0000><0140>=TRIG0[140]
+SignalExport.triggerChannel<0000><0141>=TRIG0[141]
+SignalExport.triggerChannel<0000><0142>=TRIG0[142]
+SignalExport.triggerChannel<0000><0143>=TRIG0[143]
+SignalExport.triggerChannel<0000><0144>=TRIG0[144]
+SignalExport.triggerChannel<0000><0145>=TRIG0[145]
+SignalExport.triggerChannel<0000><0146>=TRIG0[146]
+SignalExport.triggerChannel<0000><0147>=TRIG0[147]
+SignalExport.triggerChannel<0000><0148>=TRIG0[148]
+SignalExport.triggerChannel<0000><0149>=TRIG0[149]
+SignalExport.triggerChannel<0000><0150>=TRIG0[150]
+SignalExport.triggerChannel<0000><0151>=TRIG0[151]
+SignalExport.triggerChannel<0000><0152>=TRIG0[152]
+SignalExport.triggerChannel<0000><0153>=TRIG0[153]
+SignalExport.triggerChannel<0000><0154>=TRIG0[154]
+SignalExport.triggerChannel<0000><0155>=TRIG0[155]
+SignalExport.triggerChannel<0000><0156>=TRIG0[156]
+SignalExport.triggerChannel<0000><0157>=TRIG0[157]
+SignalExport.triggerChannel<0000><0158>=TRIG0[158]
+SignalExport.triggerChannel<0000><0159>=TRIG0[159]
+SignalExport.triggerChannel<0000><0160>=TRIG0[160]
+SignalExport.triggerChannel<0000><0161>=TRIG0[161]
+SignalExport.triggerChannel<0000><0162>=TRIG0[162]
+SignalExport.triggerChannel<0000><0163>=TRIG0[163]
+SignalExport.triggerChannel<0000><0164>=TRIG0[164]
+SignalExport.triggerChannel<0000><0165>=TRIG0[165]
+SignalExport.triggerChannel<0000><0166>=TRIG0[166]
+SignalExport.triggerChannel<0000><0167>=TRIG0[167]
+SignalExport.triggerChannel<0000><0168>=TRIG0[168]
+SignalExport.triggerChannel<0000><0169>=TRIG0[169]
+SignalExport.triggerChannel<0000><0170>=TRIG0[170]
+SignalExport.triggerChannel<0000><0171>=TRIG0[171]
+SignalExport.triggerChannel<0000><0172>=TRIG0[172]
+SignalExport.triggerChannel<0000><0173>=TRIG0[173]
+SignalExport.triggerChannel<0000><0174>=TRIG0[174]
+SignalExport.triggerChannel<0000><0175>=TRIG0[175]
+SignalExport.triggerChannel<0000><0176>=TRIG0[176]
+SignalExport.triggerChannel<0000><0177>=TRIG0[177]
+SignalExport.triggerChannel<0000><0178>=TRIG0[178]
+SignalExport.triggerChannel<0000><0179>=TRIG0[179]
+SignalExport.triggerChannel<0000><0180>=TRIG0[180]
+SignalExport.triggerChannel<0000><0181>=TRIG0[181]
+SignalExport.triggerChannel<0000><0182>=TRIG0[182]
+SignalExport.triggerChannel<0000><0183>=TRIG0[183]
+SignalExport.triggerChannel<0000><0184>=TRIG0[184]
+SignalExport.triggerChannel<0000><0185>=TRIG0[185]
+SignalExport.triggerChannel<0000><0186>=TRIG0[186]
+SignalExport.triggerChannel<0000><0187>=TRIG0[187]
+SignalExport.triggerChannel<0000><0188>=TRIG0[188]
+SignalExport.triggerChannel<0000><0189>=TRIG0[189]
+SignalExport.triggerChannel<0000><0190>=TRIG0[190]
+SignalExport.triggerChannel<0000><0191>=TRIG0[191]
+SignalExport.triggerChannel<0000><0192>=TRIG0[192]
+SignalExport.triggerChannel<0000><0193>=TRIG0[193]
+SignalExport.triggerChannel<0000><0194>=TRIG0[194]
+SignalExport.triggerChannel<0000><0195>=TRIG0[195]
+SignalExport.triggerChannel<0000><0196>=TRIG0[196]
+SignalExport.triggerChannel<0000><0197>=TRIG0[197]
+SignalExport.triggerChannel<0000><0198>=TRIG0[198]
+SignalExport.triggerChannel<0000><0199>=TRIG0[199]
+SignalExport.triggerChannel<0000><0200>=TRIG0[200]
+SignalExport.triggerChannel<0000><0201>=TRIG0[201]
+SignalExport.triggerChannel<0000><0202>=TRIG0[202]
+SignalExport.triggerChannel<0000><0203>=TRIG0[203]
+SignalExport.triggerChannel<0000><0204>=TRIG0[204]
+SignalExport.triggerChannel<0000><0205>=TRIG0[205]
+SignalExport.triggerChannel<0000><0206>=TRIG0[206]
+SignalExport.triggerChannel<0000><0207>=TRIG0[207]
+SignalExport.triggerChannel<0000><0208>=TRIG0[208]
+SignalExport.triggerChannel<0000><0209>=TRIG0[209]
+SignalExport.triggerChannel<0000><0210>=TRIG0[210]
+SignalExport.triggerChannel<0000><0211>=TRIG0[211]
+SignalExport.triggerChannel<0000><0212>=TRIG0[212]
+SignalExport.triggerChannel<0000><0213>=TRIG0[213]
+SignalExport.triggerChannel<0000><0214>=TRIG0[214]
+SignalExport.triggerChannel<0000><0215>=TRIG0[215]
+SignalExport.triggerChannel<0000><0216>=TRIG0[216]
+SignalExport.triggerChannel<0000><0217>=TRIG0[217]
+SignalExport.triggerChannel<0000><0218>=TRIG0[218]
+SignalExport.triggerChannel<0000><0219>=TRIG0[219]
+SignalExport.triggerChannel<0000><0220>=TRIG0[220]
+SignalExport.triggerChannel<0000><0221>=TRIG0[221]
+SignalExport.triggerChannel<0000><0222>=TRIG0[222]
+SignalExport.triggerChannel<0000><0223>=TRIG0[223]
+SignalExport.triggerChannel<0000><0224>=TRIG0[224]
+SignalExport.triggerChannel<0000><0225>=TRIG0[225]
+SignalExport.triggerChannel<0000><0226>=TRIG0[226]
+SignalExport.triggerChannel<0000><0227>=TRIG0[227]
+SignalExport.triggerChannel<0000><0228>=TRIG0[228]
+SignalExport.triggerChannel<0000><0229>=TRIG0[229]
+SignalExport.triggerChannel<0000><0230>=TRIG0[230]
+SignalExport.triggerChannel<0000><0231>=TRIG0[231]
+SignalExport.triggerChannel<0000><0232>=TRIG0[232]
+SignalExport.triggerChannel<0000><0233>=TRIG0[233]
+SignalExport.triggerChannel<0000><0234>=TRIG0[234]
+SignalExport.triggerChannel<0000><0235>=TRIG0[235]
+SignalExport.triggerChannel<0000><0236>=TRIG0[236]
+SignalExport.triggerChannel<0000><0237>=TRIG0[237]
+SignalExport.triggerChannel<0000><0238>=TRIG0[238]
+SignalExport.triggerChannel<0000><0239>=TRIG0[239]
+SignalExport.triggerChannel<0000><0240>=TRIG0[240]
+SignalExport.triggerChannel<0000><0241>=TRIG0[241]
+SignalExport.triggerChannel<0000><0242>=TRIG0[242]
+SignalExport.triggerChannel<0000><0243>=TRIG0[243]
+SignalExport.triggerChannel<0000><0244>=TRIG0[244]
+SignalExport.triggerChannel<0000><0245>=TRIG0[245]
+SignalExport.triggerChannel<0000><0246>=TRIG0[246]
+SignalExport.triggerChannel<0000><0247>=TRIG0[247]
+SignalExport.triggerChannel<0000><0248>=TRIG0[248]
+SignalExport.triggerChannel<0000><0249>=TRIG0[249]
+SignalExport.triggerChannel<0000><0250>=TRIG0[250]
+SignalExport.triggerChannel<0000><0251>=TRIG0[251]
+SignalExport.triggerChannel<0000><0252>=TRIG0[252]
+SignalExport.triggerChannel<0000><0253>=TRIG0[253]
+SignalExport.triggerChannel<0000><0254>=TRIG0[254]
+SignalExport.triggerChannel<0000><0255>=TRIG0[255]
+SignalExport.triggerPort<0000>.name=TRIG0
+SignalExport.triggerPortCount=1
+SignalExport.triggerPortIsData<0000>=true
+SignalExport.triggerPortWidth<0000>=256
+SignalExport.type=ila
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.ucf
new file mode 100644
index 000000000..b458eed9c
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.ucf
@@ -0,0 +1,15 @@
+#
+# Clock constraints
+#
+NET "CLK" TNM_NET = D_CLK ;
+INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
+TIMESPEC TS_D2_TO_T2_chipscope_ila_256 = FROM D2_CLK TO "FFS" TIG;
+TIMESPEC TS_J2_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J3_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J4_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG;
+
+#
+# Input keep/save net constraints
+#
+NET "TRIG0<*" S;
+NET "TRIG0<*" KEEP;
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.xdc
new file mode 100644
index 000000000..49e2b9e7b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.xdc
@@ -0,0 +1,6 @@
+#
+# Clock constraints
+#
+set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
+set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
+set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise
new file mode 100644
index 000000000..6305e6288
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="chipscope_ila_256.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="chipscope_ila_256.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="chipscope_ila_256.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ncf b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ncf
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ngc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ngc
new file mode 100644
index 000000000..e6dfef4e8
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ucf
new file mode 100644
index 000000000..b458eed9c
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ucf
@@ -0,0 +1,15 @@
+#
+# Clock constraints
+#
+NET "CLK" TNM_NET = D_CLK ;
+INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
+TIMESPEC TS_D2_TO_T2_chipscope_ila_256 = FROM D2_CLK TO "FFS" TIG;
+TIMESPEC TS_J2_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J3_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J4_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG;
+
+#
+# Input keep/save net constraints
+#
+NET "TRIG0<*" S;
+NET "TRIG0<*" KEEP;
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.v b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.v
new file mode 100644
index 000000000..2f0ec9349
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.v
@@ -0,0 +1,31 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.4
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : chipscope_ila_256.v
+// /___/   /\     Timestamp  : Fri Mar 08 16:13:02 PST 2013
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: Verilog Synthesis Wrapper
+///////////////////////////////////////////////////////////////////////////////
+// This wrapper is used to integrate with Project Navigator and PlanAhead
+
+`timescale 1ns/1ps
+
+module chipscope_ila_256(
+    CONTROL,
+    CLK,
+    TRIG0) /* synthesis syn_black_box syn_noprune=1 */;
+
+
+inout [35 : 0] CONTROL;
+input CLK;
+input [255 : 0] TRIG0;
+
+endmodule
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.veo b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.veo
new file mode 100644
index 000000000..201512ffb
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.veo
@@ -0,0 +1,30 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.4
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : chipscope_ila_256.veo
+// /___/   /\     Timestamp  : Fri Mar 08 16:13:02 PST 2013
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: ISE Instantiation template
+///////////////////////////////////////////////////////////////////////////////
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+chipscope_ila_256 YourInstanceName (
+    .CONTROL(CONTROL), // INOUT BUS [35:0]
+    .CLK(CLK), // IN
+    .TRIG0(TRIG0) // IN BUS [255:0]
+);
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xco b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xco
new file mode 100644
index 000000000..4272296fc
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xco
@@ -0,0 +1,141 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.4
+# Date: Sat Mar  9 00:11:24 2013
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fgg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
+# END Select
+# BEGIN Parameters
+CSET check_bramcount=false
+CSET component_name=chipscope_ila_256
+CSET constraint_type=external
+CSET counter_width_1=Disabled
+CSET counter_width_10=Disabled
+CSET counter_width_11=Disabled
+CSET counter_width_12=Disabled
+CSET counter_width_13=Disabled
+CSET counter_width_14=Disabled
+CSET counter_width_15=Disabled
+CSET counter_width_16=Disabled
+CSET counter_width_2=Disabled
+CSET counter_width_3=Disabled
+CSET counter_width_4=Disabled
+CSET counter_width_5=Disabled
+CSET counter_width_6=Disabled
+CSET counter_width_7=Disabled
+CSET counter_width_8=Disabled
+CSET counter_width_9=Disabled
+CSET data_port_width=0
+CSET data_same_as_trigger=true
+CSET disable_save_keep=false
+CSET enable_storage_qualification=true
+CSET enable_trigger_output_port=false
+CSET example_design=false
+CSET exclude_from_data_storage_1=false
+CSET exclude_from_data_storage_10=false
+CSET exclude_from_data_storage_11=false
+CSET exclude_from_data_storage_12=false
+CSET exclude_from_data_storage_13=false
+CSET exclude_from_data_storage_14=false
+CSET exclude_from_data_storage_15=false
+CSET exclude_from_data_storage_16=false
+CSET exclude_from_data_storage_2=false
+CSET exclude_from_data_storage_3=false
+CSET exclude_from_data_storage_4=false
+CSET exclude_from_data_storage_5=false
+CSET exclude_from_data_storage_6=false
+CSET exclude_from_data_storage_7=false
+CSET exclude_from_data_storage_8=false
+CSET exclude_from_data_storage_9=false
+CSET match_type_1=basic_with_edges
+CSET match_type_10=basic_with_edges
+CSET match_type_11=basic_with_edges
+CSET match_type_12=basic_with_edges
+CSET match_type_13=basic_with_edges
+CSET match_type_14=basic_with_edges
+CSET match_type_15=basic_with_edges
+CSET match_type_16=basic_with_edges
+CSET match_type_2=basic_with_edges
+CSET match_type_3=basic_with_edges
+CSET match_type_4=basic_with_edges
+CSET match_type_5=basic_with_edges
+CSET match_type_6=basic_with_edges
+CSET match_type_7=basic_with_edges
+CSET match_type_8=basic_with_edges
+CSET match_type_9=basic_with_edges
+CSET match_units_1=1
+CSET match_units_10=1
+CSET match_units_11=1
+CSET match_units_12=1
+CSET match_units_13=1
+CSET match_units_14=1
+CSET match_units_15=1
+CSET match_units_16=1
+CSET match_units_2=1
+CSET match_units_3=1
+CSET match_units_4=1
+CSET match_units_5=1
+CSET match_units_6=1
+CSET match_units_7=1
+CSET match_units_8=1
+CSET match_units_9=1
+CSET max_sequence_levels=1
+CSET number_of_trigger_ports=1
+CSET sample_data_depth=1024
+CSET sample_on=Rising
+CSET trigger_port_width_1=256
+CSET trigger_port_width_10=8
+CSET trigger_port_width_11=8
+CSET trigger_port_width_12=8
+CSET trigger_port_width_13=8
+CSET trigger_port_width_14=8
+CSET trigger_port_width_15=8
+CSET trigger_port_width_16=8
+CSET trigger_port_width_2=8
+CSET trigger_port_width_3=8
+CSET trigger_port_width_4=8
+CSET trigger_port_width_5=8
+CSET trigger_port_width_6=8
+CSET trigger_port_width_7=8
+CSET trigger_port_width_8=8
+CSET trigger_port_width_9=8
+CSET use_rpms=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-12-18T02:47:40Z
+# END Extra information
+GENERATE
+# CRC: b8a8f4bd
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xdc
new file mode 100644
index 000000000..49e2b9e7b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xdc
@@ -0,0 +1,6 @@
+#
+# Clock constraints
+#
+set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
+set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
+set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise
new file mode 100644
index 000000000..f8c51bac1
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="chipscope_ila_256.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="chipscope_ila_256.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|chipscope_ila_256" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="chipscope_ila_256.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/chipscope_ila_256" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_ila_256" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T16:13:04" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2F48FC702B99E05DB4E13DA9BB134584" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256_flist.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_flist.txt
new file mode 100644
index 000000000..da4f99bbe
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_flist.txt
@@ -0,0 +1,18 @@
+# Output products list for <chipscope_ila_256>
+_xmsgs/pn_parser.xmsgs
+chipscope_ila_256.asy
+chipscope_ila_256.cdc
+chipscope_ila_256.constraints/chipscope_ila_256.ucf
+chipscope_ila_256.constraints/chipscope_ila_256.xdc
+chipscope_ila_256.gise
+chipscope_ila_256.ncf
+chipscope_ila_256.ngc
+chipscope_ila_256.ucf
+chipscope_ila_256.v
+chipscope_ila_256.veo
+chipscope_ila_256.xco
+chipscope_ila_256.xdc
+chipscope_ila_256.xise
+chipscope_ila_256_flist.txt
+chipscope_ila_256_readme.txt
+chipscope_ila_256_xmdf.tcl
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_readme.txt
new file mode 100644
index 000000000..764247d3b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_readme.txt
@@ -0,0 +1,53 @@
+The following files were generated for 'chipscope_ila_256' in directory
+/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/
+
+ISE file generator:
+   Add description here...
+
+   * chipscope_ila_32_flist.txt
+
+XCO file generator:
+   Generate an XCO file for compatibility with legacy flows.
+
+   * chipscope_ila_256.xco
+
+Creates an implementation netlist:
+   Creates an implementation netlist for the IP.
+
+   * chipscope_ila_256.cdc
+   * chipscope_ila_256.constraints/chipscope_ila_256.ucf
+   * chipscope_ila_256.constraints/chipscope_ila_256.xdc
+   * chipscope_ila_256.ncf
+   * chipscope_ila_256.ngc
+   * chipscope_ila_256.ucf
+   * chipscope_ila_256.v
+   * chipscope_ila_256.veo
+   * chipscope_ila_256.xdc
+   * chipscope_ila_256_xmdf.tcl
+
+IP Symbol Generator:
+   Generate an IP symbol based on the current project options'.
+
+   * chipscope_ila_256.asy
+
+Generate ISE subproject:
+   Create an ISE subproject for use when including this core in ISE designs
+
+   * _xmsgs/pn_parser.xmsgs
+   * chipscope_ila_256.gise
+   * chipscope_ila_256.xise
+
+Deliver Readme:
+   Readme file for the IP.
+
+   * chipscope_ila_256_readme.txt
+
+Generate FLIST file:
+   Text file listing all of the output files produced when a customized core was
+   generated in the CORE Generator.
+
+   * chipscope_ila_256_flist.txt
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_xmdf.tcl
new file mode 100755
index 000000000..1fb67dd98
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_xmdf.tcl
@@ -0,0 +1,87 @@
+# The package naming convention is <core_name>_xmdf
+package provide chipscope_ila_256_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::chipscope_ila_256_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::chipscope_ila_256_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila_256
+}
+# ::chipscope_ila_256_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::chipscope_ila_256_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.cdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.constraints/chipscope_ila_256.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
+incr fcount
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.ncf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.constraints/chipscope_ila_256.xdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila_256
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.asy b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.asy
new file mode 100644
index 000000000..69e989c04
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.asy
@@ -0,0 +1,17 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 chipscope_ila_32
+RECTANGLE Normal 32 32 288 704
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName control[35:0]
+PINATTR Polarity IN
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName clk
+PINATTR Polarity IN
+LINE Wide 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName trig0[31:0]
+PINATTR Polarity IN
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.cdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.cdc
new file mode 100644
index 000000000..d0ba2170c
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.cdc
@@ -0,0 +1,48 @@
+#ChipScope Core Generator Project File Version 3.0
+#Fri Mar 08 11:59:29 PST 2013
+SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+SignalExport.bus<0000>.name=TRIG0
+SignalExport.bus<0000>.offset=0.0
+SignalExport.bus<0000>.precision=0
+SignalExport.bus<0000>.radix=Bin
+SignalExport.bus<0000>.scaleFactor=1.0
+SignalExport.clockChannel=CLK
+SignalExport.dataEqualsTrigger=true
+SignalExport.triggerChannel<0000><0000>=TRIG0[0]
+SignalExport.triggerChannel<0000><0001>=TRIG0[1]
+SignalExport.triggerChannel<0000><0002>=TRIG0[2]
+SignalExport.triggerChannel<0000><0003>=TRIG0[3]
+SignalExport.triggerChannel<0000><0004>=TRIG0[4]
+SignalExport.triggerChannel<0000><0005>=TRIG0[5]
+SignalExport.triggerChannel<0000><0006>=TRIG0[6]
+SignalExport.triggerChannel<0000><0007>=TRIG0[7]
+SignalExport.triggerChannel<0000><0008>=TRIG0[8]
+SignalExport.triggerChannel<0000><0009>=TRIG0[9]
+SignalExport.triggerChannel<0000><0010>=TRIG0[10]
+SignalExport.triggerChannel<0000><0011>=TRIG0[11]
+SignalExport.triggerChannel<0000><0012>=TRIG0[12]
+SignalExport.triggerChannel<0000><0013>=TRIG0[13]
+SignalExport.triggerChannel<0000><0014>=TRIG0[14]
+SignalExport.triggerChannel<0000><0015>=TRIG0[15]
+SignalExport.triggerChannel<0000><0016>=TRIG0[16]
+SignalExport.triggerChannel<0000><0017>=TRIG0[17]
+SignalExport.triggerChannel<0000><0018>=TRIG0[18]
+SignalExport.triggerChannel<0000><0019>=TRIG0[19]
+SignalExport.triggerChannel<0000><0020>=TRIG0[20]
+SignalExport.triggerChannel<0000><0021>=TRIG0[21]
+SignalExport.triggerChannel<0000><0022>=TRIG0[22]
+SignalExport.triggerChannel<0000><0023>=TRIG0[23]
+SignalExport.triggerChannel<0000><0024>=TRIG0[24]
+SignalExport.triggerChannel<0000><0025>=TRIG0[25]
+SignalExport.triggerChannel<0000><0026>=TRIG0[26]
+SignalExport.triggerChannel<0000><0027>=TRIG0[27]
+SignalExport.triggerChannel<0000><0028>=TRIG0[28]
+SignalExport.triggerChannel<0000><0029>=TRIG0[29]
+SignalExport.triggerChannel<0000><0030>=TRIG0[30]
+SignalExport.triggerChannel<0000><0031>=TRIG0[31]
+SignalExport.triggerPort<0000>.name=TRIG0
+SignalExport.triggerPortCount=1
+SignalExport.triggerPortIsData<0000>=true
+SignalExport.triggerPortWidth<0000>=32
+SignalExport.type=ila
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.ucf
new file mode 100644
index 000000000..228071c37
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.ucf
@@ -0,0 +1,15 @@
+#
+# Clock constraints
+#
+NET "CLK" TNM_NET = D_CLK ;
+INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
+TIMESPEC TS_D2_TO_T2_chipscope_ila_32 = FROM D2_CLK TO "FFS" TIG;
+TIMESPEC TS_J2_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J3_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J4_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG;
+
+#
+# Input keep/save net constraints
+#
+NET "TRIG0<*" S;
+NET "TRIG0<*" KEEP;
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.xdc
new file mode 100644
index 000000000..49e2b9e7b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.xdc
@@ -0,0 +1,6 @@
+#
+# Clock constraints
+#
+set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
+set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
+set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise
new file mode 100644
index 000000000..4bc01d034
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="chipscope_ila_32.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="chipscope_ila_32.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="chipscope_ila_32.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ncf b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ncf
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ngc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ngc
new file mode 100644
index 000000000..29677d942
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ucf
new file mode 100644
index 000000000..228071c37
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ucf
@@ -0,0 +1,15 @@
+#
+# Clock constraints
+#
+NET "CLK" TNM_NET = D_CLK ;
+INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
+TIMESPEC TS_D2_TO_T2_chipscope_ila_32 = FROM D2_CLK TO "FFS" TIG;
+TIMESPEC TS_J2_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J3_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG;
+TIMESPEC TS_J4_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG;
+
+#
+# Input keep/save net constraints
+#
+NET "TRIG0<*" S;
+NET "TRIG0<*" KEEP;
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.v b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.v
new file mode 100644
index 000000000..5c409080b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.v
@@ -0,0 +1,31 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.4
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : chipscope_ila_32.v
+// /___/   /\     Timestamp  : Fri Mar 08 11:59:29 PST 2013
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: Verilog Synthesis Wrapper
+///////////////////////////////////////////////////////////////////////////////
+// This wrapper is used to integrate with Project Navigator and PlanAhead
+
+`timescale 1ns/1ps
+
+module chipscope_ila_32(
+    CONTROL,
+    CLK,
+    TRIG0) /* synthesis syn_black_box syn_noprune=1 */;
+
+
+inout [35 : 0] CONTROL;
+input CLK;
+input [31 : 0] TRIG0;
+
+endmodule
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.veo b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.veo
new file mode 100644
index 000000000..c949fbe7f
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.veo
@@ -0,0 +1,30 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.4
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : chipscope_ila_32.veo
+// /___/   /\     Timestamp  : Fri Mar 08 11:59:29 PST 2013
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: ISE Instantiation template
+///////////////////////////////////////////////////////////////////////////////
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+chipscope_ila_32 YourInstanceName (
+    .CONTROL(CONTROL), // INOUT BUS [35:0]
+    .CLK(CLK), // IN
+    .TRIG0(TRIG0) // IN BUS [31:0]
+);
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xco b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xco
new file mode 100644
index 000000000..15047431b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xco
@@ -0,0 +1,141 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.4
+# Date: Fri Mar  8 19:57:57 2013
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fgg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
+# END Select
+# BEGIN Parameters
+CSET check_bramcount=false
+CSET component_name=chipscope_ila_32
+CSET constraint_type=external
+CSET counter_width_1=Disabled
+CSET counter_width_10=Disabled
+CSET counter_width_11=Disabled
+CSET counter_width_12=Disabled
+CSET counter_width_13=Disabled
+CSET counter_width_14=Disabled
+CSET counter_width_15=Disabled
+CSET counter_width_16=Disabled
+CSET counter_width_2=Disabled
+CSET counter_width_3=Disabled
+CSET counter_width_4=Disabled
+CSET counter_width_5=Disabled
+CSET counter_width_6=Disabled
+CSET counter_width_7=Disabled
+CSET counter_width_8=Disabled
+CSET counter_width_9=Disabled
+CSET data_port_width=0
+CSET data_same_as_trigger=true
+CSET disable_save_keep=false
+CSET enable_storage_qualification=true
+CSET enable_trigger_output_port=false
+CSET example_design=false
+CSET exclude_from_data_storage_1=false
+CSET exclude_from_data_storage_10=false
+CSET exclude_from_data_storage_11=false
+CSET exclude_from_data_storage_12=false
+CSET exclude_from_data_storage_13=false
+CSET exclude_from_data_storage_14=false
+CSET exclude_from_data_storage_15=false
+CSET exclude_from_data_storage_16=false
+CSET exclude_from_data_storage_2=false
+CSET exclude_from_data_storage_3=false
+CSET exclude_from_data_storage_4=false
+CSET exclude_from_data_storage_5=false
+CSET exclude_from_data_storage_6=false
+CSET exclude_from_data_storage_7=false
+CSET exclude_from_data_storage_8=false
+CSET exclude_from_data_storage_9=false
+CSET match_type_1=basic_with_edges
+CSET match_type_10=basic_with_edges
+CSET match_type_11=basic_with_edges
+CSET match_type_12=basic_with_edges
+CSET match_type_13=basic_with_edges
+CSET match_type_14=basic_with_edges
+CSET match_type_15=basic_with_edges
+CSET match_type_16=basic_with_edges
+CSET match_type_2=basic_with_edges
+CSET match_type_3=basic_with_edges
+CSET match_type_4=basic_with_edges
+CSET match_type_5=basic_with_edges
+CSET match_type_6=basic_with_edges
+CSET match_type_7=basic_with_edges
+CSET match_type_8=basic_with_edges
+CSET match_type_9=basic_with_edges
+CSET match_units_1=1
+CSET match_units_10=1
+CSET match_units_11=1
+CSET match_units_12=1
+CSET match_units_13=1
+CSET match_units_14=1
+CSET match_units_15=1
+CSET match_units_16=1
+CSET match_units_2=1
+CSET match_units_3=1
+CSET match_units_4=1
+CSET match_units_5=1
+CSET match_units_6=1
+CSET match_units_7=1
+CSET match_units_8=1
+CSET match_units_9=1
+CSET max_sequence_levels=1
+CSET number_of_trigger_ports=1
+CSET sample_data_depth=1024
+CSET sample_on=Rising
+CSET trigger_port_width_1=32
+CSET trigger_port_width_10=8
+CSET trigger_port_width_11=8
+CSET trigger_port_width_12=8
+CSET trigger_port_width_13=8
+CSET trigger_port_width_14=8
+CSET trigger_port_width_15=8
+CSET trigger_port_width_16=8
+CSET trigger_port_width_2=8
+CSET trigger_port_width_3=8
+CSET trigger_port_width_4=8
+CSET trigger_port_width_5=8
+CSET trigger_port_width_6=8
+CSET trigger_port_width_7=8
+CSET trigger_port_width_8=8
+CSET trigger_port_width_9=8
+CSET use_rpms=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-12-18T02:47:40Z
+# END Extra information
+GENERATE
+# CRC: aad58d16
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xdc
new file mode 100644
index 000000000..49e2b9e7b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xdc
@@ -0,0 +1,6 @@
+#
+# Clock constraints
+#
+set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
+set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
+set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise
new file mode 100644
index 000000000..9a9fb9459
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="chipscope_ila_32.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="chipscope_ila_32.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|chipscope_ila_32" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="chipscope_ila_32.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/chipscope_ila_32" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_ila_32" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T11:59:31" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="99488C9B3579739424DA923B35D96093" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32_flist.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_flist.txt
new file mode 100644
index 000000000..0a88237f8
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_flist.txt
@@ -0,0 +1,18 @@
+# Output products list for <chipscope_ila_32>
+_xmsgs/pn_parser.xmsgs
+chipscope_ila_32.asy
+chipscope_ila_32.cdc
+chipscope_ila_32.constraints/chipscope_ila_32.ucf
+chipscope_ila_32.constraints/chipscope_ila_32.xdc
+chipscope_ila_32.gise
+chipscope_ila_32.ncf
+chipscope_ila_32.ngc
+chipscope_ila_32.ucf
+chipscope_ila_32.v
+chipscope_ila_32.veo
+chipscope_ila_32.xco
+chipscope_ila_32.xdc
+chipscope_ila_32.xise
+chipscope_ila_32_flist.txt
+chipscope_ila_32_readme.txt
+chipscope_ila_32_xmdf.tcl
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_readme.txt
new file mode 100644
index 000000000..231b5d1ad
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_readme.txt
@@ -0,0 +1,48 @@
+The following files were generated for 'chipscope_ila_32' in directory
+/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/
+
+XCO file generator:
+   Generate an XCO file for compatibility with legacy flows.
+
+   * chipscope_ila_32.xco
+
+Creates an implementation netlist:
+   Creates an implementation netlist for the IP.
+
+   * chipscope_ila_32.cdc
+   * chipscope_ila_32.constraints/chipscope_ila_32.ucf
+   * chipscope_ila_32.constraints/chipscope_ila_32.xdc
+   * chipscope_ila_32.ncf
+   * chipscope_ila_32.ngc
+   * chipscope_ila_32.ucf
+   * chipscope_ila_32.v
+   * chipscope_ila_32.veo
+   * chipscope_ila_32.xdc
+   * chipscope_ila_32_xmdf.tcl
+
+IP Symbol Generator:
+   Generate an IP symbol based on the current project options'.
+
+   * chipscope_ila_32.asy
+
+Generate ISE subproject:
+   Create an ISE subproject for use when including this core in ISE designs
+
+   * _xmsgs/pn_parser.xmsgs
+   * chipscope_ila_32.gise
+   * chipscope_ila_32.xise
+
+Deliver Readme:
+   Readme file for the IP.
+
+   * chipscope_ila_32_readme.txt
+
+Generate FLIST file:
+   Text file listing all of the output files produced when a customized core was
+   generated in the CORE Generator.
+
+   * chipscope_ila_32_flist.txt
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_xmdf.tcl
new file mode 100755
index 000000000..f3617c66c
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_xmdf.tcl
@@ -0,0 +1,87 @@
+# The package naming convention is <core_name>_xmdf
+package provide chipscope_ila_32_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::chipscope_ila_32_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::chipscope_ila_32_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila_32
+}
+# ::chipscope_ila_32_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::chipscope_ila_32_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.cdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.constraints/chipscope_ila_32.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
+incr fcount
+
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.ncf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.constraints/chipscope_ila_32.xdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila_32
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
+
diff --git a/fpga/usrp3/top/b200/coregen/coregen.cgp b/fpga/usrp3/top/b200/coregen/coregen.cgp
new file mode 100644
index 000000000..de5a5aaeb
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/coregen.cgp
@@ -0,0 +1,10 @@
+SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET package = fgg484
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.asy b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.asy
new file mode 100644
index 000000000..fd6eef6f7
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.asy
@@ -0,0 +1,49 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 fifo_4k_2clk
+RECTANGLE Normal 32 32 800 4064
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Normal 0 208 32 208
+PIN 0 208 LEFT 36
+PINATTR PinName wr_clk
+PINATTR Polarity IN
+LINE Wide 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName din[71:0]
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 464 32 464
+PIN 0 464 LEFT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Wide 0 624 32 624
+PIN 0 624 LEFT 36
+PINATTR PinName wr_data_count[9:0]
+PINATTR Polarity OUT
+LINE Normal 832 240 800 240
+PIN 832 240 RIGHT 36
+PINATTR PinName rd_clk
+PINATTR Polarity IN
+LINE Wide 832 272 800 272
+PIN 832 272 RIGHT 36
+PINATTR PinName dout[71:0]
+PINATTR Polarity OUT
+LINE Normal 832 304 800 304
+PIN 832 304 RIGHT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 832 496 800 496
+PIN 832 496 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+LINE Wide 832 656 800 656
+PIN 832 656 RIGHT 36
+PINATTR PinName rd_data_count[9:0]
+PINATTR Polarity OUT
+
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise
new file mode 100644
index 000000000..c631a4815
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_4k_2clk.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_4k_2clk.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_4k_2clk.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ncf b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ncf
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ngc b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ngc
new file mode 100644
index 000000000..b379066c6
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.v b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.v
new file mode 100644
index 000000000..5724dd553
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.v
@@ -0,0 +1,491 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
+*                                                                              *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
+*                                                                              *
+*     (c) Copyright 1995-2013 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// You must compile the wrapper file fifo_4k_2clk.v when simulating
+// the core, fifo_4k_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+`timescale 1ns/1ps
+
+module fifo_4k_2clk(
+  rst,
+  wr_clk,
+  rd_clk,
+  din,
+  wr_en,
+  rd_en,
+  dout,
+  full,
+  empty,
+  rd_data_count,
+  wr_data_count
+);
+
+input rst;
+input wr_clk;
+input rd_clk;
+input [71 : 0] din;
+input wr_en;
+input rd_en;
+output [71 : 0] dout;
+output full;
+output empty;
+output [9 : 0] rd_data_count;
+output [9 : 0] wr_data_count;
+
+// synthesis translate_off
+
+  FIFO_GENERATOR_V9_3 #(
+    .C_ADD_NGC_CONSTRAINT(0),
+    .C_APPLICATION_TYPE_AXIS(0),
+    .C_APPLICATION_TYPE_RACH(0),
+    .C_APPLICATION_TYPE_RDCH(0),
+    .C_APPLICATION_TYPE_WACH(0),
+    .C_APPLICATION_TYPE_WDCH(0),
+    .C_APPLICATION_TYPE_WRCH(0),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_AXI_DATA_WIDTH(64),
+    .C_AXI_ID_WIDTH(4),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_TYPE(0),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXIS_TDATA_WIDTH(64),
+    .C_AXIS_TDEST_WIDTH(4),
+    .C_AXIS_TID_WIDTH(8),
+    .C_AXIS_TKEEP_WIDTH(4),
+    .C_AXIS_TSTRB_WIDTH(4),
+    .C_AXIS_TUSER_WIDTH(4),
+    .C_AXIS_TYPE(0),
+    .C_COMMON_CLOCK(0),
+    .C_COUNT_TYPE(0),
+    .C_DATA_COUNT_WIDTH(9),
+    .C_DEFAULT_VALUE("BlankString"),
+    .C_DIN_WIDTH(72),
+    .C_DIN_WIDTH_AXIS(1),
+    .C_DIN_WIDTH_RACH(32),
+    .C_DIN_WIDTH_RDCH(64),
+    .C_DIN_WIDTH_WACH(32),
+    .C_DIN_WIDTH_WDCH(64),
+    .C_DIN_WIDTH_WRCH(2),
+    .C_DOUT_RST_VAL("0"),
+    .C_DOUT_WIDTH(72),
+    .C_ENABLE_RLOCS(0),
+    .C_ENABLE_RST_SYNC(1),
+    .C_ERROR_INJECTION_TYPE(0),
+    .C_ERROR_INJECTION_TYPE_AXIS(0),
+    .C_ERROR_INJECTION_TYPE_RACH(0),
+    .C_ERROR_INJECTION_TYPE_RDCH(0),
+    .C_ERROR_INJECTION_TYPE_WACH(0),
+    .C_ERROR_INJECTION_TYPE_WDCH(0),
+    .C_ERROR_INJECTION_TYPE_WRCH(0),
+    .C_FAMILY("spartan6"),
+    .C_FULL_FLAGS_RST_VAL(1),
+    .C_HAS_ALMOST_EMPTY(0),
+    .C_HAS_ALMOST_FULL(0),
+    .C_HAS_AXI_ARUSER(0),
+    .C_HAS_AXI_AWUSER(0),
+    .C_HAS_AXI_BUSER(0),
+    .C_HAS_AXI_RD_CHANNEL(0),
+    .C_HAS_AXI_RUSER(0),
+    .C_HAS_AXI_WR_CHANNEL(0),
+    .C_HAS_AXI_WUSER(0),
+    .C_HAS_AXIS_TDATA(0),
+    .C_HAS_AXIS_TDEST(0),
+    .C_HAS_AXIS_TID(0),
+    .C_HAS_AXIS_TKEEP(0),
+    .C_HAS_AXIS_TLAST(0),
+    .C_HAS_AXIS_TREADY(1),
+    .C_HAS_AXIS_TSTRB(0),
+    .C_HAS_AXIS_TUSER(0),
+    .C_HAS_BACKUP(0),
+    .C_HAS_DATA_COUNT(0),
+    .C_HAS_DATA_COUNTS_AXIS(0),
+    .C_HAS_DATA_COUNTS_RACH(0),
+    .C_HAS_DATA_COUNTS_RDCH(0),
+    .C_HAS_DATA_COUNTS_WACH(0),
+    .C_HAS_DATA_COUNTS_WDCH(0),
+    .C_HAS_DATA_COUNTS_WRCH(0),
+    .C_HAS_INT_CLK(0),
+    .C_HAS_MASTER_CE(0),
+    .C_HAS_MEMINIT_FILE(0),
+    .C_HAS_OVERFLOW(0),
+    .C_HAS_PROG_FLAGS_AXIS(0),
+    .C_HAS_PROG_FLAGS_RACH(0),
+    .C_HAS_PROG_FLAGS_RDCH(0),
+    .C_HAS_PROG_FLAGS_WACH(0),
+    .C_HAS_PROG_FLAGS_WDCH(0),
+    .C_HAS_PROG_FLAGS_WRCH(0),
+    .C_HAS_RD_DATA_COUNT(1),
+    .C_HAS_RD_RST(0),
+    .C_HAS_RST(1),
+    .C_HAS_SLAVE_CE(0),
+    .C_HAS_SRST(0),
+    .C_HAS_UNDERFLOW(0),
+    .C_HAS_VALID(0),
+    .C_HAS_WR_ACK(0),
+    .C_HAS_WR_DATA_COUNT(1),
+    .C_HAS_WR_RST(0),
+    .C_IMPLEMENTATION_TYPE(2),
+    .C_IMPLEMENTATION_TYPE_AXIS(1),
+    .C_IMPLEMENTATION_TYPE_RACH(1),
+    .C_IMPLEMENTATION_TYPE_RDCH(1),
+    .C_IMPLEMENTATION_TYPE_WACH(1),
+    .C_IMPLEMENTATION_TYPE_WDCH(1),
+    .C_IMPLEMENTATION_TYPE_WRCH(1),
+    .C_INIT_WR_PNTR_VAL(0),
+    .C_INTERFACE_TYPE(0),
+    .C_MEMORY_TYPE(1),
+    .C_MIF_FILE_NAME("BlankString"),
+    .C_MSGON_VAL(1),
+    .C_OPTIMIZATION_MODE(0),
+    .C_OVERFLOW_LOW(0),
+    .C_PRELOAD_LATENCY(0),
+    .C_PRELOAD_REGS(1),
+    .C_PRIM_FIFO_TYPE("512x72"),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
+    .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+    .C_PROG_EMPTY_TYPE(0),
+    .C_PROG_EMPTY_TYPE_AXIS(0),
+    .C_PROG_EMPTY_TYPE_RACH(0),
+    .C_PROG_EMPTY_TYPE_RDCH(0),
+    .C_PROG_EMPTY_TYPE_WACH(0),
+    .C_PROG_EMPTY_TYPE_WDCH(0),
+    .C_PROG_EMPTY_TYPE_WRCH(0),
+    .C_PROG_FULL_THRESH_ASSERT_VAL(511),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
+    .C_PROG_FULL_THRESH_NEGATE_VAL(510),
+    .C_PROG_FULL_TYPE(0),
+    .C_PROG_FULL_TYPE_AXIS(0),
+    .C_PROG_FULL_TYPE_RACH(0),
+    .C_PROG_FULL_TYPE_RDCH(0),
+    .C_PROG_FULL_TYPE_WACH(0),
+    .C_PROG_FULL_TYPE_WDCH(0),
+    .C_PROG_FULL_TYPE_WRCH(0),
+    .C_RACH_TYPE(0),
+    .C_RD_DATA_COUNT_WIDTH(10),
+    .C_RD_DEPTH(512),
+    .C_RD_FREQ(1),
+    .C_RD_PNTR_WIDTH(9),
+    .C_RDCH_TYPE(0),
+    .C_REG_SLICE_MODE_AXIS(0),
+    .C_REG_SLICE_MODE_RACH(0),
+    .C_REG_SLICE_MODE_RDCH(0),
+    .C_REG_SLICE_MODE_WACH(0),
+    .C_REG_SLICE_MODE_WDCH(0),
+    .C_REG_SLICE_MODE_WRCH(0),
+    .C_SYNCHRONIZER_STAGE(2),
+    .C_UNDERFLOW_LOW(0),
+    .C_USE_COMMON_OVERFLOW(0),
+    .C_USE_COMMON_UNDERFLOW(0),
+    .C_USE_DEFAULT_SETTINGS(0),
+    .C_USE_DOUT_RST(1),
+    .C_USE_ECC(0),
+    .C_USE_ECC_AXIS(0),
+    .C_USE_ECC_RACH(0),
+    .C_USE_ECC_RDCH(0),
+    .C_USE_ECC_WACH(0),
+    .C_USE_ECC_WDCH(0),
+    .C_USE_ECC_WRCH(0),
+    .C_USE_EMBEDDED_REG(0),
+    .C_USE_FIFO16_FLAGS(0),
+    .C_USE_FWFT_DATA_COUNT(1),
+    .C_VALID_LOW(0),
+    .C_WACH_TYPE(0),
+    .C_WDCH_TYPE(0),
+    .C_WR_ACK_LOW(0),
+    .C_WR_DATA_COUNT_WIDTH(10),
+    .C_WR_DEPTH(512),
+    .C_WR_DEPTH_AXIS(1024),
+    .C_WR_DEPTH_RACH(16),
+    .C_WR_DEPTH_RDCH(1024),
+    .C_WR_DEPTH_WACH(16),
+    .C_WR_DEPTH_WDCH(1024),
+    .C_WR_DEPTH_WRCH(16),
+    .C_WR_FREQ(1),
+    .C_WR_PNTR_WIDTH(9),
+    .C_WR_PNTR_WIDTH_AXIS(10),
+    .C_WR_PNTR_WIDTH_RACH(4),
+    .C_WR_PNTR_WIDTH_RDCH(10),
+    .C_WR_PNTR_WIDTH_WACH(4),
+    .C_WR_PNTR_WIDTH_WDCH(10),
+    .C_WR_PNTR_WIDTH_WRCH(4),
+    .C_WR_RESPONSE_LATENCY(1),
+    .C_WRCH_TYPE(0)
+  )
+  inst (
+    .RST(rst),
+    .WR_CLK(wr_clk),
+    .RD_CLK(rd_clk),
+    .DIN(din),
+    .WR_EN(wr_en),
+    .RD_EN(rd_en),
+    .DOUT(dout),
+    .FULL(full),
+    .EMPTY(empty),
+    .RD_DATA_COUNT(rd_data_count),
+    .WR_DATA_COUNT(wr_data_count),
+    .BACKUP(),
+    .BACKUP_MARKER(),
+    .CLK(),
+    .SRST(),
+    .WR_RST(),
+    .RD_RST(),
+    .PROG_EMPTY_THRESH(),
+    .PROG_EMPTY_THRESH_ASSERT(),
+    .PROG_EMPTY_THRESH_NEGATE(),
+    .PROG_FULL_THRESH(),
+    .PROG_FULL_THRESH_ASSERT(),
+    .PROG_FULL_THRESH_NEGATE(),
+    .INT_CLK(),
+    .INJECTDBITERR(),
+    .INJECTSBITERR(),
+    .ALMOST_FULL(),
+    .WR_ACK(),
+    .OVERFLOW(),
+    .ALMOST_EMPTY(),
+    .VALID(),
+    .UNDERFLOW(),
+    .DATA_COUNT(),
+    .PROG_FULL(),
+    .PROG_EMPTY(),
+    .SBITERR(),
+    .DBITERR(),
+    .M_ACLK(),
+    .S_ACLK(),
+    .S_ARESETN(),
+    .M_ACLK_EN(),
+    .S_ACLK_EN(),
+    .S_AXI_AWID(),
+    .S_AXI_AWADDR(),
+    .S_AXI_AWLEN(),
+    .S_AXI_AWSIZE(),
+    .S_AXI_AWBURST(),
+    .S_AXI_AWLOCK(),
+    .S_AXI_AWCACHE(),
+    .S_AXI_AWPROT(),
+    .S_AXI_AWQOS(),
+    .S_AXI_AWREGION(),
+    .S_AXI_AWUSER(),
+    .S_AXI_AWVALID(),
+    .S_AXI_AWREADY(),
+    .S_AXI_WID(),
+    .S_AXI_WDATA(),
+    .S_AXI_WSTRB(),
+    .S_AXI_WLAST(),
+    .S_AXI_WUSER(),
+    .S_AXI_WVALID(),
+    .S_AXI_WREADY(),
+    .S_AXI_BID(),
+    .S_AXI_BRESP(),
+    .S_AXI_BUSER(),
+    .S_AXI_BVALID(),
+    .S_AXI_BREADY(),
+    .M_AXI_AWID(),
+    .M_AXI_AWADDR(),
+    .M_AXI_AWLEN(),
+    .M_AXI_AWSIZE(),
+    .M_AXI_AWBURST(),
+    .M_AXI_AWLOCK(),
+    .M_AXI_AWCACHE(),
+    .M_AXI_AWPROT(),
+    .M_AXI_AWQOS(),
+    .M_AXI_AWREGION(),
+    .M_AXI_AWUSER(),
+    .M_AXI_AWVALID(),
+    .M_AXI_AWREADY(),
+    .M_AXI_WID(),
+    .M_AXI_WDATA(),
+    .M_AXI_WSTRB(),
+    .M_AXI_WLAST(),
+    .M_AXI_WUSER(),
+    .M_AXI_WVALID(),
+    .M_AXI_WREADY(),
+    .M_AXI_BID(),
+    .M_AXI_BRESP(),
+    .M_AXI_BUSER(),
+    .M_AXI_BVALID(),
+    .M_AXI_BREADY(),
+    .S_AXI_ARID(),
+    .S_AXI_ARADDR(),
+    .S_AXI_ARLEN(),
+    .S_AXI_ARSIZE(),
+    .S_AXI_ARBURST(),
+    .S_AXI_ARLOCK(),
+    .S_AXI_ARCACHE(),
+    .S_AXI_ARPROT(),
+    .S_AXI_ARQOS(),
+    .S_AXI_ARREGION(),
+    .S_AXI_ARUSER(),
+    .S_AXI_ARVALID(),
+    .S_AXI_ARREADY(),
+    .S_AXI_RID(),
+    .S_AXI_RDATA(),
+    .S_AXI_RRESP(),
+    .S_AXI_RLAST(),
+    .S_AXI_RUSER(),
+    .S_AXI_RVALID(),
+    .S_AXI_RREADY(),
+    .M_AXI_ARID(),
+    .M_AXI_ARADDR(),
+    .M_AXI_ARLEN(),
+    .M_AXI_ARSIZE(),
+    .M_AXI_ARBURST(),
+    .M_AXI_ARLOCK(),
+    .M_AXI_ARCACHE(),
+    .M_AXI_ARPROT(),
+    .M_AXI_ARQOS(),
+    .M_AXI_ARREGION(),
+    .M_AXI_ARUSER(),
+    .M_AXI_ARVALID(),
+    .M_AXI_ARREADY(),
+    .M_AXI_RID(),
+    .M_AXI_RDATA(),
+    .M_AXI_RRESP(),
+    .M_AXI_RLAST(),
+    .M_AXI_RUSER(),
+    .M_AXI_RVALID(),
+    .M_AXI_RREADY(),
+    .S_AXIS_TVALID(),
+    .S_AXIS_TREADY(),
+    .S_AXIS_TDATA(),
+    .S_AXIS_TSTRB(),
+    .S_AXIS_TKEEP(),
+    .S_AXIS_TLAST(),
+    .S_AXIS_TID(),
+    .S_AXIS_TDEST(),
+    .S_AXIS_TUSER(),
+    .M_AXIS_TVALID(),
+    .M_AXIS_TREADY(),
+    .M_AXIS_TDATA(),
+    .M_AXIS_TSTRB(),
+    .M_AXIS_TKEEP(),
+    .M_AXIS_TLAST(),
+    .M_AXIS_TID(),
+    .M_AXIS_TDEST(),
+    .M_AXIS_TUSER(),
+    .AXI_AW_INJECTSBITERR(),
+    .AXI_AW_INJECTDBITERR(),
+    .AXI_AW_PROG_FULL_THRESH(),
+    .AXI_AW_PROG_EMPTY_THRESH(),
+    .AXI_AW_DATA_COUNT(),
+    .AXI_AW_WR_DATA_COUNT(),
+    .AXI_AW_RD_DATA_COUNT(),
+    .AXI_AW_SBITERR(),
+    .AXI_AW_DBITERR(),
+    .AXI_AW_OVERFLOW(),
+    .AXI_AW_UNDERFLOW(),
+    .AXI_AW_PROG_FULL(),
+    .AXI_AW_PROG_EMPTY(),
+    .AXI_W_INJECTSBITERR(),
+    .AXI_W_INJECTDBITERR(),
+    .AXI_W_PROG_FULL_THRESH(),
+    .AXI_W_PROG_EMPTY_THRESH(),
+    .AXI_W_DATA_COUNT(),
+    .AXI_W_WR_DATA_COUNT(),
+    .AXI_W_RD_DATA_COUNT(),
+    .AXI_W_SBITERR(),
+    .AXI_W_DBITERR(),
+    .AXI_W_OVERFLOW(),
+    .AXI_W_UNDERFLOW(),
+    .AXI_B_INJECTSBITERR(),
+    .AXI_W_PROG_FULL(),
+    .AXI_W_PROG_EMPTY(),
+    .AXI_B_INJECTDBITERR(),
+    .AXI_B_PROG_FULL_THRESH(),
+    .AXI_B_PROG_EMPTY_THRESH(),
+    .AXI_B_DATA_COUNT(),
+    .AXI_B_WR_DATA_COUNT(),
+    .AXI_B_RD_DATA_COUNT(),
+    .AXI_B_SBITERR(),
+    .AXI_B_DBITERR(),
+    .AXI_B_OVERFLOW(),
+    .AXI_B_UNDERFLOW(),
+    .AXI_AR_INJECTSBITERR(),
+    .AXI_B_PROG_FULL(),
+    .AXI_B_PROG_EMPTY(),
+    .AXI_AR_INJECTDBITERR(),
+    .AXI_AR_PROG_FULL_THRESH(),
+    .AXI_AR_PROG_EMPTY_THRESH(),
+    .AXI_AR_DATA_COUNT(),
+    .AXI_AR_WR_DATA_COUNT(),
+    .AXI_AR_RD_DATA_COUNT(),
+    .AXI_AR_SBITERR(),
+    .AXI_AR_DBITERR(),
+    .AXI_AR_OVERFLOW(),
+    .AXI_AR_UNDERFLOW(),
+    .AXI_AR_PROG_FULL(),
+    .AXI_AR_PROG_EMPTY(),
+    .AXI_R_INJECTSBITERR(),
+    .AXI_R_INJECTDBITERR(),
+    .AXI_R_PROG_FULL_THRESH(),
+    .AXI_R_PROG_EMPTY_THRESH(),
+    .AXI_R_DATA_COUNT(),
+    .AXI_R_WR_DATA_COUNT(),
+    .AXI_R_RD_DATA_COUNT(),
+    .AXI_R_SBITERR(),
+    .AXI_R_DBITERR(),
+    .AXI_R_OVERFLOW(),
+    .AXI_R_UNDERFLOW(),
+    .AXIS_INJECTSBITERR(),
+    .AXI_R_PROG_FULL(),
+    .AXI_R_PROG_EMPTY(),
+    .AXIS_INJECTDBITERR(),
+    .AXIS_PROG_FULL_THRESH(),
+    .AXIS_PROG_EMPTY_THRESH(),
+    .AXIS_DATA_COUNT(),
+    .AXIS_WR_DATA_COUNT(),
+    .AXIS_RD_DATA_COUNT(),
+    .AXIS_SBITERR(),
+    .AXIS_DBITERR(),
+    .AXIS_OVERFLOW(),
+    .AXIS_UNDERFLOW(),
+    .AXIS_PROG_FULL(),
+    .AXIS_PROG_EMPTY()
+  );
+
+// synthesis translate_on
+
+endmodule
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.veo b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.veo
new file mode 100644
index 000000000..12c025d5d
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.veo
@@ -0,0 +1,79 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
+*                                                                              *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
+*                                                                              *
+*     (c) Copyright 1995-2013 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+
+/*******************************************************************************
+*     Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3    *
+*                                                                              *
+*     Rev 1. The FIFO Generator is a parameterizable first-in/first-out        *
+*     memory queue generator. Use it to generate resource and performance      *
+*     optimized FIFOs with common or independent read/write clock domains,     *
+*     and optional fixed or programmable full and empty flags and              *
+*     handshaking signals.  Choose from a selection of memory resource         *
+*     types for implementation.  Optional Hamming code based error             *
+*     detection and correction as well as error injection capability for       *
+*     system test help to insure data integrity.  FIFO width and depth are     *
+*     parameterizable, and for native interface FIFOs, asymmetric read and     *
+*     write port widths are also supported.                                    *
+*******************************************************************************/
+
+// Interfaces:
+//    AXI4Stream_MASTER_M_AXIS
+//    AXI4Stream_SLAVE_S_AXIS
+//    AXI4_MASTER_M_AXI
+//    AXI4_SLAVE_S_AXI
+//    AXI4Lite_MASTER_M_AXI
+//    AXI4Lite_SLAVE_S_AXI
+//    master_aclk
+//    slave_aclk
+//    slave_aresetn
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_4k_2clk your_instance_name (
+  .rst(rst), // input rst
+  .wr_clk(wr_clk), // input wr_clk
+  .rd_clk(rd_clk), // input rd_clk
+  .din(din), // input [71 : 0] din
+  .wr_en(wr_en), // input wr_en
+  .rd_en(rd_en), // input rd_en
+  .dout(dout), // output [71 : 0] dout
+  .full(full), // output full
+  .empty(empty), // output empty
+  .rd_data_count(rd_data_count), // output [9 : 0] rd_data_count
+  .wr_data_count(wr_data_count) // output [9 : 0] wr_data_count
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_4k_2clk.v when simulating
+// the core, fifo_4k_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xco b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xco
new file mode 100644
index 000000000..f617ee440
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xco
@@ -0,0 +1,213 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.4
+# Date: Fri Jan 25 19:58:19 2013
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:fifo_generator:9.3
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
+# END Select
+# BEGIN Parameters
+CSET add_ngc_constraint_axi=false
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET aruser_width=1
+CSET awuser_width=1
+CSET axi_address_width=32
+CSET axi_data_width=64
+CSET axi_type=AXI4_Stream
+CSET axis_type=FIFO
+CSET buser_width=1
+CSET clock_enable_type=Slave_Interface_Clock_Enable
+CSET clock_type_axi=Common_Clock
+CSET component_name=fifo_4k_2clk
+CSET data_count=false
+CSET data_count_width=9
+CSET disable_timing_violations=false
+CSET disable_timing_violations_axi=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_assert_value_axis=1022
+CSET empty_threshold_assert_value_rach=1022
+CSET empty_threshold_assert_value_rdch=1022
+CSET empty_threshold_assert_value_wach=1022
+CSET empty_threshold_assert_value_wdch=1022
+CSET empty_threshold_assert_value_wrch=1022
+CSET empty_threshold_negate_value=5
+CSET enable_aruser=false
+CSET enable_awuser=false
+CSET enable_buser=false
+CSET enable_common_overflow=false
+CSET enable_common_underflow=false
+CSET enable_data_counts_axis=false
+CSET enable_data_counts_rach=false
+CSET enable_data_counts_rdch=false
+CSET enable_data_counts_wach=false
+CSET enable_data_counts_wdch=false
+CSET enable_data_counts_wrch=false
+CSET enable_ecc=false
+CSET enable_ecc_axis=false
+CSET enable_ecc_rach=false
+CSET enable_ecc_rdch=false
+CSET enable_ecc_wach=false
+CSET enable_ecc_wdch=false
+CSET enable_ecc_wrch=false
+CSET enable_read_channel=false
+CSET enable_read_pointer_increment_by2=false
+CSET enable_reset_synchronization=true
+CSET enable_ruser=false
+CSET enable_tdata=false
+CSET enable_tdest=false
+CSET enable_tid=false
+CSET enable_tkeep=false
+CSET enable_tlast=false
+CSET enable_tready=true
+CSET enable_tstrobe=false
+CSET enable_tuser=false
+CSET enable_write_channel=false
+CSET enable_wuser=false
+CSET fifo_application_type_axis=Data_FIFO
+CSET fifo_application_type_rach=Data_FIFO
+CSET fifo_application_type_rdch=Data_FIFO
+CSET fifo_application_type_wach=Data_FIFO
+CSET fifo_application_type_wdch=Data_FIFO
+CSET fifo_application_type_wrch=Data_FIFO
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET fifo_implementation_axis=Common_Clock_Block_RAM
+CSET fifo_implementation_rach=Common_Clock_Block_RAM
+CSET fifo_implementation_rdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wach=Common_Clock_Block_RAM
+CSET fifo_implementation_wdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wrch=Common_Clock_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=511
+CSET full_threshold_assert_value_axis=1023
+CSET full_threshold_assert_value_rach=1023
+CSET full_threshold_assert_value_rdch=1023
+CSET full_threshold_assert_value_wach=1023
+CSET full_threshold_assert_value_wdch=1023
+CSET full_threshold_assert_value_wrch=1023
+CSET full_threshold_negate_value=510
+CSET id_width=4
+CSET inject_dbit_error=false
+CSET inject_dbit_error_axis=false
+CSET inject_dbit_error_rach=false
+CSET inject_dbit_error_rdch=false
+CSET inject_dbit_error_wach=false
+CSET inject_dbit_error_wdch=false
+CSET inject_dbit_error_wrch=false
+CSET inject_sbit_error=false
+CSET inject_sbit_error_axis=false
+CSET inject_sbit_error_rach=false
+CSET inject_sbit_error_rdch=false
+CSET inject_sbit_error_wach=false
+CSET inject_sbit_error_wdch=false
+CSET inject_sbit_error_wrch=false
+CSET input_data_width=72
+CSET input_depth=512
+CSET input_depth_axis=1024
+CSET input_depth_rach=16
+CSET input_depth_rdch=1024
+CSET input_depth_wach=16
+CSET input_depth_wdch=1024
+CSET input_depth_wrch=16
+CSET interface_type=Native
+CSET output_data_width=72
+CSET output_depth=512
+CSET overflow_flag=false
+CSET overflow_flag_axi=false
+CSET overflow_sense=Active_High
+CSET overflow_sense_axi=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET programmable_full_type_axis=No_Programmable_Full_Threshold
+CSET programmable_full_type_rach=No_Programmable_Full_Threshold
+CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
+CSET programmable_full_type_wach=No_Programmable_Full_Threshold
+CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
+CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
+CSET rach_type=FIFO
+CSET rdch_type=FIFO
+CSET read_clock_frequency=1
+CSET read_data_count=true
+CSET read_data_count_width=10
+CSET register_slice_mode_axis=Fully_Registered
+CSET register_slice_mode_rach=Fully_Registered
+CSET register_slice_mode_rdch=Fully_Registered
+CSET register_slice_mode_wach=Fully_Registered
+CSET register_slice_mode_wdch=Fully_Registered
+CSET register_slice_mode_wrch=Fully_Registered
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET ruser_width=1
+CSET synchronization_stages=2
+CSET synchronization_stages_axi=2
+CSET tdata_width=64
+CSET tdest_width=4
+CSET tid_width=8
+CSET tkeep_width=4
+CSET tstrb_width=4
+CSET tuser_width=4
+CSET underflow_flag=false
+CSET underflow_flag_axi=false
+CSET underflow_sense=Active_High
+CSET underflow_sense_axi=Active_High
+CSET use_clock_enable=false
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=true
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET wach_type=FIFO
+CSET wdch_type=FIFO
+CSET wrch_type=FIFO
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=true
+CSET write_data_count_width=10
+CSET wuser_width=1
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-19T12:39:56Z
+# END Extra information
+GENERATE
+# CRC: 372c204f
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise
new file mode 100644
index 000000000..2d8132c10
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="fifo_4k_2clk.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="fifo_4k_2clk.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_4k_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_4k_2clk.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_4k_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_4k_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-25T11:59:33" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A74B340026B44B356C1780B6C6FE45BC" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt
new file mode 100644
index 000000000..7853ebde8
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt
@@ -0,0 +1,236 @@
+CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
+
+                    Release Date: December 18, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------  
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
+solution. For the latest core updates, see the product page at:
+ 
+   http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+    The following device families are supported by the core for this release.
+    
+    
+    All 7 Series devices
+    Zynq-7000 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Spartan-3 devices
+    All Virtex-4 devices
+  
+  
+  2.2 Vivado 
+  
+    All 7 Series devices
+    Zynq-7000 devices
+
+................................................................................
+
+
+3. NEW FEATURE HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+  
+  3.2 Vivado
+  
+    - 2012.4 software support
+    - IP level constraint for Built-in FIFO reset synchronizer
+
+................................................................................
+
+
+4. RESOLVED ISSUES 
+
+
+  4.1 ISE 
+
+    - N/A
+
+
+  4.2 Vivado 
+
+    - N/A
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+
+  5.1 ISE 
+  
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+  
+    1. Importing an XCO file alters the XCO configurations
+  
+       Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+       into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
+       page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+    
+       CR 467240
+       AR 31379
+  
+    2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
+  
+       Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
+       correct behavior of the FIFO status flags cannot be guaranteed after the first write.
+    
+       Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
+       For more information and additional workaround see Answer Record 41099.
+  
+  5.2 Vivado 
+
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+     
+    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen 
+       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
+      
+       CR 665836
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes User Guide
+located at 
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.  
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+................................................................................
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/18/2012  Xilinx, Inc.  9.3 Rev 1    ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
+10/16/2012  Xilinx, Inc.  9.3          ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
+07/25/2012  Xilinx, Inc.  9.2          ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
+04/24/2012  Xilinx, Inc.  9.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+                                       AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
+01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
+10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
+06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
+03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
+10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
+09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
+07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
+06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
+08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
+05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
+04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
+================================================================================
+
+................................................................................
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html
new file mode 100644
index 000000000..fefce62a3
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html
@@ -0,0 +1,247 @@
+<HTML>
+<HEAD>
+<TITLE>fifo_generator_v9_3_vinfo</TITLE>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
+</HEAD>
+<BODY>
+<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
+CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
+
+                    Release Date: December 18, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------  
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+   <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
+
+For system requirements:
+
+   <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
+solution. For the latest core updates, see the product page at:
+ 
+   <A HREF="http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm">www.xilinx.com/products/ipcenter/FIFO_Generator.htm</A>
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+    The following device families are supported by the core for this release.
+    
+    
+    All 7 Series devices
+    Zynq-7000 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Spartan-3 devices
+    All Virtex-4 devices
+  
+  
+  2.2 Vivado 
+  
+    All 7 Series devices
+    Zynq-7000 devices
+
+................................................................................
+
+
+3. NEW FEATURE HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+  
+  3.2 Vivado
+  
+    - 2012.4 software support
+    - IP level constraint for Built-in FIFO reset synchronizer
+
+................................................................................
+
+
+4. RESOLVED ISSUES 
+
+
+  4.1 ISE 
+
+    - N/A
+
+
+  4.2 Vivado 
+
+    - N/A
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+
+  5.1 ISE 
+  
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+  
+    1. Importing an XCO file alters the XCO configurations
+  
+       Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+       into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
+       page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+    
+       CR 467240
+       AR 31379
+  
+    2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
+  
+       Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
+       correct behavior of the FIFO status flags cannot be guaranteed after the first write.
+    
+       Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
+       For more information and additional workaround see Answer Record 41099.
+  
+  5.2 Vivado 
+
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+     
+    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen 
+       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
+      
+       CR 665836
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes User Guide
+located at 
+
+   <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A> 
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
+Questions are routed to a team with expertise using this product.  
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+................................................................................
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/18/2012  Xilinx, Inc.  9.3 Rev 1    ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
+10/16/2012  Xilinx, Inc.  9.3          ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
+07/25/2012  Xilinx, Inc.  9.2          ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
+04/24/2012  Xilinx, Inc.  9.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+                                       AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
+01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
+10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
+06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
+03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
+10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
+09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
+07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
+06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
+08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
+05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
+04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
+================================================================================
+
+................................................................................
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+</FONT>
+</PRE>
+</BODY>
+</HTML>
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf
new file mode 100644
index 000000000..5ec45fbcb
Binary files /dev/null and b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf differ
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf
new file mode 100755
index 000000000..62e5058ab
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf
@@ -0,0 +1,56 @@
+################################################################################
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+  NET "RD_CLK"  TNM_NET     = "RD_CLK";
+  NET "WR_CLK"  TNM_NET     = "WR_CLK";
+  TIMESPEC "TS_RD_CLK"      = PERIOD "RD_CLK" 50 MHZ;
+  TIMESPEC "TS_WR_CLK"      = PERIOD "WR_CLK" 50 MHZ;
+################################################################################
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd
new file mode 100755
index 000000000..2674443c8
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd
@@ -0,0 +1,145 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core - core top file for implementation
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_4k_2clk_exdes.vhd
+--
+-- Description:
+--   This is the FIFO core wrapper with BUFG instances for clock connections.
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+entity fifo_4k_2clk_exdes is
+   PORT (
+           WR_CLK                    : IN  std_logic;
+     	   RD_CLK                    : IN  std_logic;
+     	   WR_DATA_COUNT             : OUT std_logic_vector(10-1 DOWNTO 0);
+           RD_DATA_COUNT             : OUT std_logic_vector(10-1 DOWNTO 0);
+           RST                       : IN  std_logic;
+           WR_EN 		     : IN  std_logic;
+           RD_EN                     : IN  std_logic;
+           DIN                       : IN  std_logic_vector(72-1 DOWNTO 0);
+           DOUT                      : OUT std_logic_vector(72-1 DOWNTO 0);
+           FULL                      : OUT std_logic;
+           EMPTY                     : OUT std_logic);
+
+end fifo_4k_2clk_exdes;
+
+
+
+architecture xilinx of fifo_4k_2clk_exdes is
+
+  signal wr_clk_i : std_logic;
+  signal rd_clk_i : std_logic;
+
+
+
+  component fifo_4k_2clk is
+   PORT (
+           WR_CLK                    : IN  std_logic;
+     	   RD_CLK                    : IN  std_logic;
+     	   WR_DATA_COUNT             : OUT std_logic_vector(10-1 DOWNTO 0);
+           RD_DATA_COUNT             : OUT std_logic_vector(10-1 DOWNTO 0);
+           RST                       : IN  std_logic;
+           WR_EN 		     : IN  std_logic;
+           RD_EN                     : IN  std_logic;
+           DIN                       : IN  std_logic_vector(72-1 DOWNTO 0);
+           DOUT                      : OUT std_logic_vector(72-1 DOWNTO 0);
+           FULL                      : OUT std_logic;
+           EMPTY                     : OUT std_logic);
+
+  end component;
+
+
+begin
+
+  wr_clk_buf: bufg
+    PORT map(
+      i => WR_CLK,
+      o => wr_clk_i
+      );
+
+  rd_clk_buf: bufg
+    PORT map(
+      i => RD_CLK,
+      o => rd_clk_i
+      );
+
+
+  exdes_inst : fifo_4k_2clk 
+    PORT MAP (
+           WR_CLK                    => wr_clk_i,
+           RD_CLK                    => rd_clk_i,
+           WR_DATA_COUNT             => wr_data_count,
+           RD_DATA_COUNT             => rd_data_count,
+           RST                       => rst,
+           WR_EN 		     => wr_en,
+           RD_EN                     => rd_en,
+           DIN                       => din,
+           DOUT                      => dout,
+           FULL                      => full,
+           EMPTY                     => empty);
+
+end xilinx;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt
new file mode 100644
index 000000000..7853ebde8
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt
@@ -0,0 +1,236 @@
+CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
+
+                    Release Date: December 18, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------  
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
+solution. For the latest core updates, see the product page at:
+ 
+   http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+    The following device families are supported by the core for this release.
+    
+    
+    All 7 Series devices
+    Zynq-7000 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Spartan-3 devices
+    All Virtex-4 devices
+  
+  
+  2.2 Vivado 
+  
+    All 7 Series devices
+    Zynq-7000 devices
+
+................................................................................
+
+
+3. NEW FEATURE HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+  
+  3.2 Vivado
+  
+    - 2012.4 software support
+    - IP level constraint for Built-in FIFO reset synchronizer
+
+................................................................................
+
+
+4. RESOLVED ISSUES 
+
+
+  4.1 ISE 
+
+    - N/A
+
+
+  4.2 Vivado 
+
+    - N/A
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+
+  5.1 ISE 
+  
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+  
+    1. Importing an XCO file alters the XCO configurations
+  
+       Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+       into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
+       page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+    
+       CR 467240
+       AR 31379
+  
+    2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
+  
+       Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
+       correct behavior of the FIFO status flags cannot be guaranteed after the first write.
+    
+       Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
+       For more information and additional workaround see Answer Record 41099.
+  
+  5.2 Vivado 
+
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+     
+    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen 
+       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
+      
+       CR 665836
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes User Guide
+located at 
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.  
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+................................................................................
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/18/2012  Xilinx, Inc.  9.3 Rev 1    ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
+10/16/2012  Xilinx, Inc.  9.3          ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
+07/25/2012  Xilinx, Inc.  9.2          ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
+04/24/2012  Xilinx, Inc.  9.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+                                       AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
+01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
+10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
+06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
+03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
+10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
+09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
+07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
+06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
+08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
+05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
+04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
+================================================================================
+
+................................................................................
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.bat
new file mode 100755
index 000000000..f5fcf0a2b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.bat
@@ -0,0 +1,88 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+
+rem Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+rem Synthesize the VHDL Wrapper Files
+
+#Synthesize the Wrapper Files
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+copy fifo_4k_2clk_exdes.ngc .\results\
+
+
+rem Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+copy ..\..\fifo_4k_2clk.ngc results\
+
+
+rem  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\fifo_4k_2clk_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+
+ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes
+
+echo 'Running map'
+map fifo_4k_2clk_exdes -o mapped.ncd
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.sh
new file mode 100755
index 000000000..9cb53f5c7
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.sh
@@ -0,0 +1,87 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+#Synthesize the Wrapper Files
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+cp fifo_4k_2clk_exdes.ngc ./results/
+
+
+# Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+cp ../../fifo_4k_2clk.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/fifo_4k_2clk_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+
+ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes
+
+echo 'Running map'
+map fifo_4k_2clk_exdes -o mapped.ncd
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
+
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.bat
new file mode 100755
index 000000000..9d99aaa5c
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.bat
@@ -0,0 +1,87 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+
+rem Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+rem Synthesize the VHDL Wrapper Files
+
+#Synthesize the Wrapper Files
+
+echo 'Synthesizing example design with Synplify'
+synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
+
+
+rem Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+copy ..\..\fifo_4k_2clk.ngc results\
+
+
+rem  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\fifo_4k_2clk_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+
+ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes
+
+echo 'Running map'
+map fifo_4k_2clk_exdes -o mapped.ncd
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.sh
new file mode 100755
index 000000000..db245edbb
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.sh
@@ -0,0 +1,86 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+#Synthesize the Wrapper Files
+
+echo 'Synthesizing example design with Synplify'
+synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
+
+
+# Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+cp ../../fifo_4k_2clk.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/fifo_4k_2clk_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+
+ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes
+
+echo 'Running map'
+map fifo_4k_2clk_exdes -o mapped.ncd
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
+
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.bat
new file mode 100755
index 000000000..a48fea790
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.bat
@@ -0,0 +1,54 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+
+rem -----------------------------------------------------------------------------
+rem  Script to synthesize and implement the Coregen FIFO Generator
+rem -----------------------------------------------------------------------------
+rmdir /S /Q results
+mkdir results
+cd results
+copy ..\..\..\fifo_4k_2clk.ngc .
+planAhead -mode batch -source ..\planAhead_ise.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.sh
new file mode 100755
index 000000000..7171a0e5e
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.sh
@@ -0,0 +1,55 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+#-----------------------------------------------------------------------------
+#  Script to synthesize and implement the Coregen FIFO Generator
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+cp ../../../fifo_4k_2clk.ngc .
+planAhead -mode batch -source ../planAhead_ise.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.tcl
new file mode 100755
index 000000000..6af923b85
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.tcl
@@ -0,0 +1,67 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+set device xc6slx75csg484-2
+set projName fifo_4k_2clk
+set design fifo_4k_2clk
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module fifo_4k_2clk_exdes
+add_files -norecurse {../../example_design/fifo_4k_2clk_exdes.vhd}
+add_files -norecurse {./fifo_4k_2clk.ngc}
+import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/fifo_4k_2clk_exdes.xdc}
+set_property top fifo_4k_2clk_exdes [get_property srcset [current_run]]
+synth_design
+opt_design 
+place_design 
+route_design 
+write_sdf -rename_top_module fifo_4k_2clk_exdes -file routed.sdf 
+write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module fifo_4k_2clk_exdes routed.v
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.prj b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.prj
new file mode 100755
index 000000000..573a1716f
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.prj
@@ -0,0 +1 @@
+work ../example_design/fifo_4k_2clk_exdes.vhd
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.scr b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.scr
new file mode 100755
index 000000000..bff287f78
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.scr
@@ -0,0 +1,13 @@
+run
+-ifmt VHDL
+-ent fifo_4k_2clk_exdes 
+-p xc6slx75-csg484-2
+-ifn xst.prj
+-write_timing_constraints No
+-iobuf YES
+-max_fanout 100
+-ofn fifo_4k_2clk_exdes 
+-ofmt NGC
+-bus_delimiter ()
+-hierarchy_separator /
+-case Maintain
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd
new file mode 100755
index 000000000..d14bb7a51
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd
@@ -0,0 +1,123 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_4k_2clk_dgen.vhd
+--
+-- Description:
+--   Used for write interface stimulus generation
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE IEEE.std_logic_arith.all;
+USE IEEE.std_logic_misc.all;
+
+LIBRARY work;
+USE work.fifo_4k_2clk_pkg.ALL;
+
+ENTITY fifo_4k_2clk_dgen IS
+  GENERIC (
+	    C_DIN_WIDTH   : INTEGER := 32;
+	    C_DOUT_WIDTH  : INTEGER := 32;
+	    C_CH_TYPE     : INTEGER := 0;
+	    TB_SEED       : INTEGER := 2
+	 );
+  PORT (
+        RESET     : IN STD_LOGIC;
+        WR_CLK    : IN STD_LOGIC;
+        PRC_WR_EN : IN STD_LOGIC;
+        FULL      : IN STD_LOGIC;  
+        WR_EN     : OUT STD_LOGIC;      
+        WR_DATA   : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
+       );
+END ENTITY;
+
+
+ARCHITECTURE fg_dg_arch OF fifo_4k_2clk_dgen IS
+ 
+  CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
+  CONSTANT LOOP_COUNT   : INTEGER := divroundup(C_DATA_WIDTH,8);
+  
+  SIGNAL pr_w_en        : STD_LOGIC := '0';
+  SIGNAL rand_num       : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
+  SIGNAL wr_data_i      : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
+ BEGIN
+  
+   WR_EN   <= PRC_WR_EN ;
+   WR_DATA <= wr_data_i AFTER 100 ns;
+
+  ----------------------------------------------
+  -- Generation of DATA
+  ----------------------------------------------
+  gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
+    rd_gen_inst1:fifo_4k_2clk_rng
+    GENERIC MAP(
+    	       WIDTH => 8,
+               SEED  => TB_SEED+N
+               )
+    PORT MAP(
+              CLK        => WR_CLK,
+	      RESET      => RESET,
+              RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
+              ENABLE     => pr_w_en
+            );
+  END GENERATE; 
+
+     pr_w_en <= PRC_WR_EN AND NOT FULL;
+     wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
+
+
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd
new file mode 100755
index 000000000..0a7c2aa87
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd
@@ -0,0 +1,150 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_4k_2clk_dverif.vhd
+--
+-- Description:
+--   Used for FIFO read interface stimulus generation and data checking
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE IEEE.std_logic_arith.all;
+USE IEEE.std_logic_misc.all;
+
+LIBRARY work;
+USE work.fifo_4k_2clk_pkg.ALL;
+
+ENTITY fifo_4k_2clk_dverif IS
+  GENERIC(
+   C_DIN_WIDTH        : INTEGER := 0;
+   C_DOUT_WIDTH       : INTEGER := 0;
+   C_USE_EMBEDDED_REG : INTEGER := 0;
+   C_CH_TYPE          : INTEGER := 0;
+   TB_SEED            : INTEGER := 2
+  );
+  PORT(
+       RESET          : IN STD_LOGIC;
+       RD_CLK         : IN STD_LOGIC;
+       PRC_RD_EN      : IN STD_LOGIC;
+       EMPTY          : IN STD_LOGIC;
+       DATA_OUT       : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
+       RD_EN          : OUT STD_LOGIC;
+       DOUT_CHK       : OUT STD_LOGIC
+      );
+END ENTITY;
+
+
+ARCHITECTURE fg_dv_arch OF fifo_4k_2clk_dverif IS
+ 
+ CONSTANT C_DATA_WIDTH    : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
+ CONSTANT EXTRA_WIDTH     : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
+ CONSTANT LOOP_COUNT      : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
+
+ SIGNAL expected_dout     : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL data_chk          : STD_LOGIC := '1';
+ SIGNAL rand_num          : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
+ SIGNAL rd_en_i           : STD_LOGIC := '0';
+ SIGNAL pr_r_en           : STD_LOGIC := '0';
+ SIGNAL rd_en_d1          : STD_LOGIC := '1';
+BEGIN
+
+ 
+  DOUT_CHK <= data_chk;
+  RD_EN    <= rd_en_i;
+  rd_en_i  <= PRC_RD_EN;
+  rd_en_d1 <= '1';
+  
+ 
+  data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE 
+  -------------------------------------------------------
+  -- Expected data generation and checking for data_fifo
+  -------------------------------------------------------
+   
+      pr_r_en       <= rd_en_i AND NOT EMPTY AND rd_en_d1;
+      expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
+
+    gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
+      rd_gen_inst2:fifo_4k_2clk_rng
+      GENERIC MAP(
+      	        WIDTH => 8,
+                SEED  => TB_SEED+N
+                 )
+      PORT MAP(
+                CLK        => RD_CLK,
+	        RESET      => RESET,
+                RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
+                ENABLE     => pr_r_en 	    
+              );
+    END GENERATE;    
+    
+      PROCESS (RD_CLK,RESET)
+      BEGIN
+        IF(RESET = '1') THEN
+          data_chk <= '0';
+        ELSIF (RD_CLK'event AND RD_CLK='1') THEN
+          IF(EMPTY = '0') THEN
+            IF(DATA_OUT = expected_dout) THEN
+              data_chk <= '0';
+            ELSE
+              data_chk <= '1';
+            END IF;
+          END IF;
+        END IF;
+      END PROCESS;
+  END GENERATE data_fifo_chk;
+
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd
new file mode 100755
index 000000000..fa32e4781
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd
@@ -0,0 +1,541 @@
+
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_4k_2clk_pctrl.vhd
+--
+-- Description:
+--   Used for protocol control on write and read interface stimulus and status generation
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE IEEE.std_logic_arith.all;
+USE IEEE.std_logic_misc.all;
+
+LIBRARY work;
+USE work.fifo_4k_2clk_pkg.ALL;
+
+ENTITY fifo_4k_2clk_pctrl IS
+  GENERIC(
+   AXI_CHANNEL         : STRING  :="NONE";
+   C_APPLICATION_TYPE  : INTEGER := 0;
+   C_DIN_WIDTH         : INTEGER := 0;
+   C_DOUT_WIDTH        : INTEGER := 0;
+   C_WR_PNTR_WIDTH     : INTEGER := 0;
+   C_RD_PNTR_WIDTH     : INTEGER := 0;
+   C_CH_TYPE           : INTEGER := 0;
+   FREEZEON_ERROR      : INTEGER := 0;
+   TB_STOP_CNT         : INTEGER := 2;
+   TB_SEED             : INTEGER := 2
+  );
+  PORT(
+       RESET_WR        : IN STD_LOGIC;
+       RESET_RD        : IN STD_LOGIC;
+       WR_CLK          : IN STD_LOGIC;
+       RD_CLK          : IN STD_LOGIC;
+       FULL            : IN STD_LOGIC;
+       EMPTY           : IN STD_LOGIC;
+       ALMOST_FULL     : IN STD_LOGIC;
+       ALMOST_EMPTY    : IN STD_LOGIC;
+       DATA_IN         : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
+       DATA_OUT        : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
+       DOUT_CHK        : IN STD_LOGIC;
+       PRC_WR_EN       : OUT STD_LOGIC;
+       PRC_RD_EN       : OUT STD_LOGIC;
+       RESET_EN        : OUT STD_LOGIC;
+       SIM_DONE        : OUT STD_LOGIC;
+       STATUS          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+      );
+END ENTITY;
+
+
+ARCHITECTURE fg_pc_arch OF fifo_4k_2clk_pctrl IS
+ 
+ CONSTANT C_DATA_WIDTH   : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
+ CONSTANT LOOP_COUNT     : INTEGER := divroundup(C_DATA_WIDTH,8);
+ CONSTANT D_WIDTH_DIFF   :   INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
+
+ SIGNAL data_chk_i       : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
+ SIGNAL full_chk_i       : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
+ SIGNAL empty_chk_i      : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
+ SIGNAL status_i         : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
+ SIGNAL status_d1_i      : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
+ SIGNAL wr_en_gen        : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
+ SIGNAL rd_en_gen        : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
+ SIGNAL wr_cntr          : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0)   := (OTHERS => '0');
+ SIGNAL full_as_timeout  : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0)   := (OTHERS => '0');
+ SIGNAL full_ds_timeout  : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
+ SIGNAL rd_cntr          : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0)   := (OTHERS => '0'); 
+ SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0)  := (OTHERS => '0'); 
+ SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0'); 
+ SIGNAL wr_en_i          : STD_LOGIC := '0';
+ SIGNAL rd_en_i          : STD_LOGIC := '0';
+ SIGNAL state            : STD_LOGIC := '0';
+ SIGNAL wr_control       : STD_LOGIC := '0';
+ SIGNAL rd_control       : STD_LOGIC := '0';
+ SIGNAL stop_on_err      : STD_LOGIC := '0';
+ SIGNAL sim_stop_cntr    : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
+ SIGNAL sim_done_i       : STD_LOGIC := '0';
+ SIGNAL rdw_gt_wrw       : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
+ SIGNAL wrw_gt_rdw       : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
+ SIGNAL rd_activ_cont    : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
+ SIGNAL prc_we_i         : STD_LOGIC := '0';
+ SIGNAL prc_re_i         : STD_LOGIC := '0';
+ SIGNAL reset_en_i       : STD_LOGIC := '0';
+ SIGNAL sim_done_d1      : STD_LOGIC := '0';
+ SIGNAL sim_done_wr1     : STD_LOGIC := '0';
+ SIGNAL sim_done_wr2     : STD_LOGIC := '0'; 
+ SIGNAL empty_d1         : STD_LOGIC := '0';
+ SIGNAL empty_wr_dom1    : STD_LOGIC := '0';
+ SIGNAL state_d1         : STD_LOGIC := '0';
+ SIGNAL state_rd_dom1    : STD_LOGIC := '0';
+ SIGNAL rd_en_d1         : STD_LOGIC := '0';
+ SIGNAL rd_en_wr1        : STD_LOGIC := '0';
+ SIGNAL wr_en_d1         : STD_LOGIC := '0';
+ SIGNAL wr_en_rd1        : STD_LOGIC := '0';
+ SIGNAL full_chk_d1      : STD_LOGIC := '0';
+ SIGNAL full_chk_rd1     : STD_LOGIC := '0';
+ SIGNAL empty_wr_dom2    : STD_LOGIC := '0';
+
+ SIGNAL state_rd_dom2    : STD_LOGIC := '0';
+ SIGNAL state_rd_dom3    : STD_LOGIC := '0';
+ SIGNAL rd_en_wr2        : STD_LOGIC := '0';
+ SIGNAL wr_en_rd2        : STD_LOGIC := '0';
+ SIGNAL full_chk_rd2     : STD_LOGIC := '0';
+ SIGNAL reset_en_d1      : STD_LOGIC := '0';
+ SIGNAL reset_en_rd1     : STD_LOGIC := '0';
+ SIGNAL reset_en_rd2     : STD_LOGIC := '0';
+
+ SIGNAL data_chk_wr_d1   : STD_LOGIC := '0';
+ SIGNAL data_chk_rd1     : STD_LOGIC := '0';
+ SIGNAL data_chk_rd2     : STD_LOGIC := '0';
+ SIGNAL post_rst_dly_wr  : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
+ SIGNAL post_rst_dly_rd  : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
+BEGIN
+ status_i  <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
+ STATUS    <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
+
+ prc_we_i <= wr_en_i  WHEN sim_done_wr2 = '0' ELSE '0';
+ prc_re_i <= rd_en_i  WHEN sim_done_i   = '0' ELSE '0';
+
+ SIM_DONE   <= sim_done_i;
+ rdw_gt_wrw <= (OTHERS => '1');
+ wrw_gt_rdw <= (OTHERS => '1');
+
+ PROCESS(RD_CLK)
+ BEGIN
+   IF (RD_CLK'event AND RD_CLK='1') THEN
+     IF(prc_re_i = '1') THEN
+       rd_activ_cont <= rd_activ_cont + "1";
+     END IF;
+   END IF;
+ END PROCESS;
+
+
+ PROCESS(sim_done_i)
+ BEGIN
+    assert sim_done_i = '0'
+    report "Simulation Complete for:" & AXI_CHANNEL
+    severity note;
+ END PROCESS;
+
+-----------------------------------------------------
+-- SIM_DONE SIGNAL GENERATION
+-----------------------------------------------------
+PROCESS (RD_CLK,RESET_RD)
+BEGIN
+    IF(RESET_RD = '1') THEN
+      --sim_done_i <= '0';
+    ELSIF(RD_CLK'event AND RD_CLK='1') THEN
+      IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
+     	sim_done_i <= '1';
+      END IF;
+    END IF;
+END PROCESS;
+
+ -- TB Timeout/Stop
+ fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
+   PROCESS (RD_CLK)
+   BEGIN
+       IF (RD_CLK'event AND RD_CLK='1') THEN
+         IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
+           sim_stop_cntr <= sim_stop_cntr - "1";
+         END IF;
+       END IF;
+   END PROCESS;
+ END GENERATE fifo_tb_stop_run;
+
+
+  -- Stop when error found
+  PROCESS (RD_CLK)
+  BEGIN
+    IF (RD_CLK'event AND RD_CLK='1') THEN
+      IF(sim_done_i = '0') THEN
+        status_d1_i <= status_i OR status_d1_i;
+      END IF;
+      IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
+        stop_on_err <= '1';
+      END IF;
+    END IF;
+  END PROCESS;
+  -----------------------------------------------------
+
+  -----------------------------------------------------
+  -- CHECKS FOR FIFO
+  -----------------------------------------------------
+
+
+  PROCESS(RD_CLK,RESET_RD)
+  BEGIN
+    IF(RESET_RD = '1') THEN
+      post_rst_dly_rd <= (OTHERS => '1');
+    ELSIF (RD_CLK'event AND RD_CLK='1') THEN
+      post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
+    END IF;
+  END PROCESS;
+  
+  PROCESS(WR_CLK,RESET_WR)
+  BEGIN
+    IF(RESET_WR = '1') THEN
+      post_rst_dly_wr <= (OTHERS => '1');
+    ELSIF (WR_CLK'event AND WR_CLK='1') THEN
+      post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
+    END IF;
+  END PROCESS;
+
+
+  -- FULL de-assert Counter
+  PROCESS(WR_CLK,RESET_WR) 
+  BEGIN
+    IF(RESET_WR = '1') THEN
+      full_ds_timeout <= (OTHERS => '0');
+    ELSIF(WR_CLK'event AND WR_CLK='1') THEN
+      IF(state = '1') THEN
+        IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
+          full_ds_timeout <= full_ds_timeout + '1';
+        END IF;
+      ELSE
+  	full_ds_timeout <= (OTHERS => '0');
+      END IF;
+    END IF;
+  END PROCESS;
+   
+ 
+ -- EMPTY deassert counter
+  PROCESS(RD_CLK,RESET_RD) 
+  BEGIN
+    IF(RESET_RD = '1') THEN
+      empty_ds_timeout <= (OTHERS => '0');
+    ELSIF(RD_CLK'event AND RD_CLK='1') THEN
+      IF(state = '0') THEN
+        IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
+          empty_ds_timeout <= empty_ds_timeout + '1';
+        END IF;
+      ELSE
+  	empty_ds_timeout <= (OTHERS => '0');
+      END IF;
+    END IF;
+  END PROCESS;
+
+  -- Full check signal generation
+  PROCESS(WR_CLK,RESET_WR) 
+  BEGIN
+    IF(RESET_WR = '1') THEN
+      full_chk_i <= '0';
+    ELSIF(WR_CLK'event AND WR_CLK='1') THEN
+      IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
+        full_chk_i <= '0';
+      ELSE
+        full_chk_i <= AND_REDUCE(full_as_timeout) OR 
+		      AND_REDUCE(full_ds_timeout);
+      END IF;
+    END IF;
+  END PROCESS;
+
+  -- Empty checks
+  PROCESS(RD_CLK,RESET_RD) 
+  BEGIN
+    IF(RESET_RD = '1') THEN
+      empty_chk_i <= '0';
+    ELSIF(RD_CLK'event AND RD_CLK='1') THEN
+      IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
+        empty_chk_i <= '0';
+      ELSE
+        empty_chk_i <= AND_REDUCE(empty_as_timeout) OR 
+		       AND_REDUCE(empty_ds_timeout);
+      END IF;
+    END IF;
+  END PROCESS;
+
+  fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
+    PRC_WR_EN  <= prc_we_i  AFTER 100 ns;
+    PRC_RD_EN  <= prc_re_i  AFTER 50 ns;
+    data_chk_i <= dout_chk;
+  END GENERATE fifo_d_chk;
+  -----------------------------------------------------
+ 
+
+ -----------------------------------------------------
+ -- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
+ -----------------------------------------------------
+   PROCESS(WR_CLK,RESET_WR)
+   BEGIN
+     IF(RESET_WR = '1') THEN
+       empty_wr_dom1  <= '1';
+       empty_wr_dom2  <= '1';
+       state_d1       <= '0';
+       wr_en_d1       <= '0';
+       rd_en_wr1      <= '0';
+       rd_en_wr2      <= '0';
+       full_chk_d1    <= '0';
+       reset_en_d1    <= '0';
+       sim_done_wr1   <= '0';
+       sim_done_wr2   <= '0';
+     ELSIF (WR_CLK'event AND WR_CLK='1') THEN
+       sim_done_wr1   <= sim_done_d1;
+       sim_done_wr2   <= sim_done_wr1;
+       reset_en_d1    <= reset_en_i;
+       state_d1       <= state;
+       empty_wr_dom1  <= empty_d1;
+       empty_wr_dom2  <= empty_wr_dom1;
+       wr_en_d1       <= wr_en_i;
+       rd_en_wr1      <= rd_en_d1;
+       rd_en_wr2      <= rd_en_wr1;
+       full_chk_d1    <= full_chk_i;
+     END IF;
+   END PROCESS;
+
+   PROCESS(RD_CLK,RESET_RD)
+   BEGIN
+     IF(RESET_RD = '1') THEN
+         empty_d1       <= '1';
+         state_rd_dom1  <= '0';
+         state_rd_dom2  <= '0';
+         state_rd_dom3  <= '0';
+         wr_en_rd1      <= '0';
+         wr_en_rd2      <= '0';
+         rd_en_d1       <= '0';
+         full_chk_rd1   <= '0';
+         full_chk_rd2   <= '0';
+         reset_en_rd1   <= '0';
+         reset_en_rd2   <= '0';
+         sim_done_d1    <= '0';
+     ELSIF (RD_CLK'event AND RD_CLK='1') THEN
+         sim_done_d1    <= sim_done_i;
+         reset_en_rd1   <= reset_en_d1;
+         reset_en_rd2   <= reset_en_rd1;
+         empty_d1       <= EMPTY;
+         rd_en_d1       <= rd_en_i;
+         state_rd_dom1  <= state_d1;
+         state_rd_dom2  <= state_rd_dom1;
+         state_rd_dom3  <= state_rd_dom2;
+         wr_en_rd1      <= wr_en_d1;
+         wr_en_rd2      <= wr_en_rd1;
+         full_chk_rd1   <= full_chk_d1;
+         full_chk_rd2   <= full_chk_rd1;
+     END IF;
+   END PROCESS;
+   
+   RESET_EN   <= reset_en_rd2;
+ 
+
+   data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE  
+    -----------------------------------------------------
+    -- WR_EN GENERATION
+    -----------------------------------------------------
+    gen_rand_wr_en:fifo_4k_2clk_rng
+    GENERIC MAP(
+    	         WIDTH => 8,
+                 SEED  => TB_SEED+1
+               )
+    PORT MAP(
+              CLK        => WR_CLK,
+              RESET      => RESET_WR,
+              RANDOM_NUM => wr_en_gen,
+              ENABLE     => '1'
+            );
+
+    PROCESS(WR_CLK,RESET_WR)
+    BEGIN
+      IF(RESET_WR = '1') THEN
+        wr_en_i   <=  '0';
+      ELSIF(WR_CLK'event AND WR_CLK='1') THEN
+        IF(state = '1') THEN
+          wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
+        ELSE
+          wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4)); 
+        END IF;
+      END IF;
+    END PROCESS;
+    
+    -----------------------------------------------------
+    -- WR_EN CONTROL
+    -----------------------------------------------------
+    PROCESS(WR_CLK,RESET_WR)
+    BEGIN
+      IF(RESET_WR = '1') THEN
+        wr_cntr         <= (OTHERS => '0');
+	wr_control      <= '1';
+	full_as_timeout <= (OTHERS => '0');
+      ELSIF(WR_CLK'event AND WR_CLK='1') THEN
+	IF(state = '1') THEN
+	  IF(wr_en_i = '1') THEN
+	    wr_cntr <= wr_cntr + "1";
+	  END IF;
+	  full_as_timeout <= (OTHERS => '0');
+	ELSE
+	  wr_cntr <= (OTHERS => '0');
+	  IF(rd_en_wr2 = '0') THEN
+	    IF(wr_en_i = '1') THEN
+  	      full_as_timeout <= full_as_timeout + "1";
+  	    END IF;
+	  ELSE 
+	    full_as_timeout <= (OTHERS => '0');
+	  END IF;
+	END IF;
+
+	wr_control <= NOT wr_cntr(wr_cntr'high);
+
+      END IF;
+    END PROCESS;
+
+    -----------------------------------------------------
+    -- RD_EN GENERATION
+    -----------------------------------------------------
+    gen_rand_rd_en:fifo_4k_2clk_rng
+    GENERIC MAP(
+    	         WIDTH => 8,
+                 SEED  => TB_SEED
+               )
+    PORT MAP(
+              CLK        => RD_CLK,
+              RESET      => RESET_RD,
+              RANDOM_NUM => rd_en_gen,
+              ENABLE     => '1'
+            );
+
+    PROCESS(RD_CLK,RESET_RD)
+    BEGIN
+      IF(RESET_RD = '1') THEN
+	rd_en_i    <= '0';
+      ELSIF(RD_CLK'event AND RD_CLK='1') THEN
+        IF(state_rd_dom2 = '0') THEN
+  	    rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
+        ELSE
+          rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
+        END IF;
+      END IF;
+    END PROCESS;
+
+    -----------------------------------------------------
+    -- RD_EN CONTROL
+    -----------------------------------------------------
+    PROCESS(RD_CLK,RESET_RD)
+    BEGIN
+      IF(RESET_RD = '1') THEN
+        rd_cntr    <= (OTHERS => '0');
+	rd_control <= '1';
+	empty_as_timeout <= (OTHERS => '0');
+      ELSIF(RD_CLK'event AND RD_CLK='1') THEN
+	IF(state_rd_dom2 = '0') THEN
+	  IF(rd_en_i = '1') THEN
+	    rd_cntr <= rd_cntr + "1";
+	  END IF;
+	  empty_as_timeout <= (OTHERS => '0');
+	ELSE
+	  rd_cntr <= (OTHERS => '0');
+	  IF(wr_en_rd2 = '0') THEN
+	    IF(rd_en_i = '1') THEN
+  	      empty_as_timeout <= empty_as_timeout + "1";
+  	    END IF;
+	  ELSE 
+	    empty_as_timeout <= (OTHERS => '0');
+	  END IF;
+	END IF;
+	
+	rd_control <= NOT rd_cntr(rd_cntr'high);
+
+      END IF;
+    END PROCESS;
+
+    -----------------------------------------------------
+    -- STIMULUS CONTROL
+    -----------------------------------------------------
+    PROCESS(WR_CLK,RESET_WR)
+    BEGIN
+      IF(RESET_WR = '1') THEN
+        state      <= '0';
+	reset_en_i <= '0';
+      ELSIF(WR_CLK'event AND WR_CLK='1') THEN
+        CASE state IS
+          WHEN '0' => 
+            IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
+              state      <= '1';
+	      reset_en_i <= '0';
+    	    END IF;
+          WHEN '1' => 
+            IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
+              state    	 <= '0';
+	      reset_en_i <= '1';
+    	    END IF;
+          WHEN OTHERS => state <= state;
+	END CASE;
+      END IF;
+    END PROCESS;
+  END GENERATE data_fifo_en;
+
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd
new file mode 100755
index 000000000..46d4ac9cf
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd
@@ -0,0 +1,350 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_4k_2clk_pkg.vhd
+--
+-- Description:
+--   This is the demo testbench package file for FIFO Generator core.
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE ieee.std_logic_arith.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+PACKAGE fifo_4k_2clk_pkg IS
+
+ FUNCTION divroundup (
+    data_value : INTEGER;
+    divisor : INTEGER)
+ RETURN INTEGER;
+ ------------------------
+ FUNCTION if_then_else (
+   condition : BOOLEAN;
+   true_case : INTEGER;
+   false_case : INTEGER)
+ RETURN INTEGER;
+ ------------------------
+ FUNCTION if_then_else (
+   condition : BOOLEAN;
+   true_case : STD_LOGIC;
+   false_case : STD_LOGIC)
+ RETURN STD_LOGIC;
+  ------------------------
+ FUNCTION if_then_else (
+   condition : BOOLEAN;
+   true_case : TIME;
+   false_case : TIME)
+ RETURN TIME;
+ ------------------------ 
+ FUNCTION log2roundup (
+      data_value : INTEGER)
+ RETURN INTEGER; 
+ ------------------------ 
+ FUNCTION hexstr_to_std_logic_vec(
+   arg1 : string;
+   size : integer )
+ RETURN std_logic_vector;
+ ------------------------
+ COMPONENT fifo_4k_2clk_rng IS
+    GENERIC (WIDTH : integer :=  8;
+             SEED  : integer := 3);
+    PORT (
+      CLK : IN STD_LOGIC;
+      RESET : IN STD_LOGIC;
+      ENABLE : IN STD_LOGIC;
+      RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)         
+     );
+ END COMPONENT; 
+ ------------------------ 
+ 
+ COMPONENT fifo_4k_2clk_dgen IS
+  GENERIC (
+	    C_DIN_WIDTH   : INTEGER := 32;
+	    C_DOUT_WIDTH  : INTEGER := 32;
+	    C_CH_TYPE     : INTEGER := 0;
+	    TB_SEED       : INTEGER := 2
+	 );
+  PORT (
+        RESET     : IN STD_LOGIC;
+        WR_CLK    : IN STD_LOGIC;
+        PRC_WR_EN : IN STD_LOGIC;
+        FULL      : IN STD_LOGIC;  
+        WR_EN     : OUT STD_LOGIC;      
+        WR_DATA   : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
+       );
+ END COMPONENT;
+ ------------------------ 
+
+ COMPONENT fifo_4k_2clk_dverif IS
+  GENERIC(
+   C_DIN_WIDTH        : INTEGER := 0;
+   C_DOUT_WIDTH       : INTEGER := 0;
+   C_USE_EMBEDDED_REG : INTEGER := 0;
+   C_CH_TYPE          : INTEGER := 0;
+   TB_SEED            : INTEGER := 2
+  );
+  PORT(
+       RESET       : IN STD_LOGIC;
+       RD_CLK      : IN STD_LOGIC;
+       PRC_RD_EN   : IN STD_LOGIC;
+       EMPTY       : IN STD_LOGIC;
+       DATA_OUT    : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
+       RD_EN       : OUT STD_LOGIC;
+       DOUT_CHK    : OUT STD_LOGIC
+      );
+ END COMPONENT; 
+ ------------------------ 
+
+ COMPONENT fifo_4k_2clk_pctrl IS
+   GENERIC(
+     AXI_CHANNEL         : STRING  := "NONE";
+     C_APPLICATION_TYPE  : INTEGER := 0;
+     C_DIN_WIDTH         : INTEGER := 0;
+     C_DOUT_WIDTH        : INTEGER := 0;
+     C_WR_PNTR_WIDTH     : INTEGER := 0;
+     C_RD_PNTR_WIDTH     : INTEGER := 0;
+     C_CH_TYPE           : INTEGER := 0;
+     FREEZEON_ERROR      : INTEGER := 0;
+     TB_STOP_CNT         : INTEGER := 2;
+     TB_SEED             : INTEGER := 2
+   );
+   PORT(
+       RESET_WR        : IN STD_LOGIC;
+       RESET_RD        : IN STD_LOGIC;
+       WR_CLK          : IN STD_LOGIC;
+       RD_CLK          : IN STD_LOGIC;
+       FULL            : IN STD_LOGIC;
+       EMPTY           : IN STD_LOGIC;
+       ALMOST_FULL     : IN STD_LOGIC;
+       ALMOST_EMPTY    : IN STD_LOGIC;
+       DATA_IN         : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
+       DATA_OUT        : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
+       DOUT_CHK        : IN STD_LOGIC;
+       PRC_WR_EN       : OUT STD_LOGIC;
+       PRC_RD_EN       : OUT STD_LOGIC;
+       RESET_EN        : OUT STD_LOGIC;
+       SIM_DONE        : OUT STD_LOGIC;
+       STATUS          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+      );
+ END COMPONENT;
+ ------------------------
+ COMPONENT fifo_4k_2clk_synth IS
+  GENERIC(
+  	   FREEZEON_ERROR : INTEGER := 0;
+	   TB_STOP_CNT    : INTEGER := 0;
+	   TB_SEED        : INTEGER := 1
+	 );
+  PORT(
+	WR_CLK     :  IN  STD_LOGIC;
+	RD_CLK     :  IN  STD_LOGIC;
+        RESET      :  IN  STD_LOGIC;
+        SIM_DONE   :  OUT STD_LOGIC;
+        STATUS     :  OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+      );
+ END COMPONENT;
+ ------------------------
+ COMPONENT fifo_4k_2clk_exdes IS
+   PORT (
+           WR_CLK                    : IN  std_logic;
+     	   RD_CLK                    : IN  std_logic;
+     	   WR_DATA_COUNT             : OUT std_logic_vector(10-1 DOWNTO 0);
+           RD_DATA_COUNT             : OUT std_logic_vector(10-1 DOWNTO 0);
+           RST                       : IN  std_logic;
+           WR_EN 		     : IN  std_logic;
+           RD_EN                     : IN  std_logic;
+           DIN                       : IN  std_logic_vector(72-1 DOWNTO 0);
+           DOUT                      : OUT std_logic_vector(72-1 DOWNTO 0);
+           FULL                      : OUT std_logic;
+           EMPTY                     : OUT std_logic);
+
+ END COMPONENT;
+ ------------------------ 
+
+
+END fifo_4k_2clk_pkg;
+
+
+
+PACKAGE BODY fifo_4k_2clk_pkg IS
+
+ FUNCTION divroundup (
+    data_value : INTEGER;
+    divisor : INTEGER)
+  RETURN INTEGER IS
+    VARIABLE div                   : INTEGER;
+  BEGIN
+    div   := data_value/divisor;
+    IF ( (data_value MOD divisor) /= 0) THEN
+      div := div+1;
+    END IF;
+    RETURN div;
+  END divroundup;
+  ---------------------------------
+  FUNCTION if_then_else (
+    condition : BOOLEAN;
+    true_case : INTEGER;
+    false_case : INTEGER)
+  RETURN INTEGER IS
+    VARIABLE retval : INTEGER := 0;
+  BEGIN
+    IF condition=false THEN
+      retval:=false_case;
+    ELSE
+      retval:=true_case;
+    END IF;
+    RETURN retval;
+  END if_then_else;
+    ---------------------------------
+  FUNCTION if_then_else (
+    condition : BOOLEAN;
+    true_case : STD_LOGIC;
+    false_case : STD_LOGIC)
+  RETURN STD_LOGIC IS
+    VARIABLE retval : STD_LOGIC := '0';
+  BEGIN
+    IF condition=false THEN
+      retval:=false_case;
+    ELSE
+      retval:=true_case;
+    END IF;
+    RETURN retval;
+  END if_then_else;
+  ---------------------------------
+  FUNCTION if_then_else (
+    condition : BOOLEAN;
+    true_case : TIME;
+    false_case : TIME)
+  RETURN TIME IS
+    VARIABLE retval : TIME := 0 ps;
+  BEGIN
+    IF condition=false THEN
+      retval:=false_case;
+    ELSE
+      retval:=true_case;
+    END IF;
+    RETURN retval;
+  END if_then_else;
+  ------------------------------- 
+  FUNCTION log2roundup (
+      data_value : INTEGER)
+    RETURN INTEGER IS
+
+      VARIABLE width       : INTEGER := 0;
+      VARIABLE cnt         : INTEGER := 1;
+    BEGIN
+      IF (data_value <= 1) THEN
+        width   := 1;
+      ELSE
+        WHILE (cnt < data_value) LOOP
+          width := width + 1;
+          cnt   := cnt *2;
+        END LOOP;
+      END IF;
+
+      RETURN width;
+    END log2roundup;
+  ------------------------------------------------------------------------------
+  -- hexstr_to_std_logic_vec
+  --  This function converts a hex string to a std_logic_vector
+  ------------------------------------------------------------------------------
+  FUNCTION hexstr_to_std_logic_vec( 
+    arg1 : string; 
+    size : integer ) 
+  RETURN std_logic_vector IS
+    VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
+    VARIABLE bin    : std_logic_vector(3 DOWNTO 0);
+    VARIABLE index  : integer                           := 0;
+  BEGIN
+    FOR i IN arg1'reverse_range LOOP
+      CASE arg1(i) IS
+        WHEN '0' => bin := (OTHERS => '0');
+        WHEN '1' => bin := (0 => '1', OTHERS => '0');
+        WHEN '2' => bin := (1 => '1', OTHERS => '0');
+        WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
+        WHEN '4' => bin := (2 => '1', OTHERS => '0');
+        WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
+        WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
+        WHEN '7' => bin := (3 => '0', OTHERS => '1');
+        WHEN '8' => bin := (3 => '1', OTHERS => '0');
+        WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
+        WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
+        WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
+        WHEN 'B' => bin := (2 => '0', OTHERS => '1');
+        WHEN 'b' => bin := (2 => '0', OTHERS => '1');
+        WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
+        WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
+        WHEN 'D' => bin := (1 => '0', OTHERS => '1');
+        WHEN 'd' => bin := (1 => '0', OTHERS => '1');
+        WHEN 'E' => bin := (0 => '0', OTHERS => '1');
+        WHEN 'e' => bin := (0 => '0', OTHERS => '1');
+        WHEN 'F' => bin := (OTHERS => '1');
+        WHEN 'f' => bin := (OTHERS => '1');
+        WHEN OTHERS =>
+          FOR j IN 0 TO 3 LOOP
+            bin(j) := 'X';
+          END LOOP;
+      END CASE;
+      FOR j IN 0 TO 3 LOOP
+        IF (index*4)+j < size THEN
+          result((index*4)+j) := bin(j);
+        END IF;
+      END LOOP;
+      index := index + 1;
+    END LOOP;
+    RETURN result;
+  END hexstr_to_std_logic_vec;
+
+END fifo_4k_2clk_pkg;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd
new file mode 100755
index 000000000..bed58d88e
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd
@@ -0,0 +1,100 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_4k_2clk_rng.vhd
+--
+-- Description:
+--   Used for generation of pseudo random numbers
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE IEEE.std_logic_arith.all;
+USE IEEE.std_logic_misc.all;
+
+ENTITY fifo_4k_2clk_rng IS
+    GENERIC (
+      WIDTH        : integer :=  8;
+      SEED         : integer :=  3);
+    PORT (
+      CLK         : IN STD_LOGIC;
+      RESET       : IN STD_LOGIC;
+      ENABLE      : IN STD_LOGIC;
+      RANDOM_NUM  : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
+END ENTITY;
+
+ARCHITECTURE rg_arch OF fifo_4k_2clk_rng IS
+BEGIN
+PROCESS (CLK,RESET)
+  VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
+  VARIABLE temp      : STD_LOGIC := '0';
+BEGIN
+  IF(RESET = '1') THEN
+    rand_temp := conv_std_logic_vector(SEED,width);
+    temp      := '0';
+  ELSIF (CLK'event AND CLK = '1') THEN
+    IF (ENABLE = '1') THEN
+      temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
+      rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
+      rand_temp(0) := temp;
+    END IF;
+  END IF;
+
+  RANDOM_NUM <= rand_temp;
+
+END PROCESS;
+
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd
new file mode 100755
index 000000000..4149735c5
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd
@@ -0,0 +1,300 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_4k_2clk_synth.vhd
+--
+-- Description:
+--   This is the demo testbench for fifo_generator core.
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+LIBRARY ieee;
+USE ieee.STD_LOGIC_1164.ALL;
+USE ieee.STD_LOGIC_unsigned.ALL;
+USE IEEE.STD_LOGIC_arith.ALL;
+USE ieee.numeric_std.ALL;
+USE ieee.STD_LOGIC_misc.ALL;
+
+LIBRARY std;
+USE std.textio.ALL;
+
+LIBRARY work;
+USE work.fifo_4k_2clk_pkg.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY fifo_4k_2clk_synth IS
+  GENERIC(
+  	   FREEZEON_ERROR : INTEGER := 0;
+	   TB_STOP_CNT    : INTEGER := 0;
+	   TB_SEED        : INTEGER := 1
+	 );
+  PORT(
+	WR_CLK     :  IN  STD_LOGIC;
+	RD_CLK     :  IN  STD_LOGIC;
+        RESET      :  IN  STD_LOGIC;
+        SIM_DONE   :  OUT STD_LOGIC;
+        STATUS     :  OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+      );
+END ENTITY;
+
+ARCHITECTURE simulation_arch OF fifo_4k_2clk_synth IS
+
+    -- FIFO interface signal declarations
+    SIGNAL wr_clk_i                       :   STD_LOGIC;
+    SIGNAL rd_clk_i                       :   STD_LOGIC;
+    SIGNAL wr_data_count                  :   STD_LOGIC_VECTOR(10-1 DOWNTO 0);
+    SIGNAL rd_data_count                  :   STD_LOGIC_VECTOR(10-1 DOWNTO 0);
+    SIGNAL rst	                          :   STD_LOGIC;
+    SIGNAL wr_en                          :   STD_LOGIC;
+    SIGNAL rd_en                          :   STD_LOGIC;
+    SIGNAL din                            :   STD_LOGIC_VECTOR(72-1 DOWNTO 0);
+    SIGNAL dout                           :   STD_LOGIC_VECTOR(72-1 DOWNTO 0);
+    SIGNAL full                           :   STD_LOGIC;
+    SIGNAL empty                          :   STD_LOGIC;
+   -- TB Signals
+    SIGNAL wr_data                        :   STD_LOGIC_VECTOR(72-1 DOWNTO 0);
+    SIGNAL dout_i                         :   STD_LOGIC_VECTOR(72-1 DOWNTO 0);
+    SIGNAL wr_en_i                        :   STD_LOGIC := '0';
+    SIGNAL rd_en_i                        :   STD_LOGIC := '0';
+    SIGNAL full_i                         :   STD_LOGIC := '0';
+    SIGNAL empty_i                        :   STD_LOGIC := '0';
+    SIGNAL almost_full_i                  :   STD_LOGIC := '0';
+    SIGNAL almost_empty_i                 :   STD_LOGIC := '0';
+    SIGNAL prc_we_i                       :   STD_LOGIC := '0';
+    SIGNAL prc_re_i                       :   STD_LOGIC := '0';
+    SIGNAL dout_chk_i                     :   STD_LOGIC := '0';
+    SIGNAL rst_int_rd                     :   STD_LOGIC := '0';
+    SIGNAL rst_int_wr                     :   STD_LOGIC := '0';
+    SIGNAL rst_s_wr1                      :   STD_LOGIC := '0';
+    SIGNAL rst_s_wr2                      :   STD_LOGIC := '0';
+    SIGNAL rst_gen_rd                     :   STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL rst_s_wr3                      :   STD_LOGIC := '0';
+    SIGNAL rst_s_rd                       :   STD_LOGIC := '0';
+    SIGNAL reset_en                       :   STD_LOGIC := '0';
+    SIGNAL rst_async_wr1                  :   STD_LOGIC := '0'; 
+    SIGNAL rst_async_wr2                  :   STD_LOGIC := '0'; 
+    SIGNAL rst_async_wr3                  :   STD_LOGIC := '0'; 
+    SIGNAL rst_async_rd1                  :   STD_LOGIC := '0'; 
+    SIGNAL rst_async_rd2                  :   STD_LOGIC := '0'; 
+    SIGNAL rst_async_rd3                  :   STD_LOGIC := '0'; 
+
+
+ BEGIN  
+
+   ---- Reset generation logic -----
+   rst_int_wr          <= rst_async_wr3 OR rst_s_wr3;
+   rst_int_rd          <= rst_async_rd3 OR rst_s_rd;
+
+   --Testbench reset synchronization
+   PROCESS(rd_clk_i,RESET)
+   BEGIN
+     IF(RESET = '1') THEN
+       rst_async_rd1    <= '1';
+       rst_async_rd2    <= '1';
+       rst_async_rd3    <= '1';
+     ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
+       rst_async_rd1    <= RESET;
+       rst_async_rd2    <= rst_async_rd1;
+       rst_async_rd3    <= rst_async_rd2;
+     END IF;
+   END PROCESS;
+
+   PROCESS(wr_clk_i,RESET)
+   BEGIN
+     IF(RESET = '1') THEN
+       rst_async_wr1  <= '1';
+       rst_async_wr2  <= '1';
+       rst_async_wr3  <= '1';
+     ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
+       rst_async_wr1  <= RESET;
+       rst_async_wr2  <= rst_async_wr1;
+       rst_async_wr3  <= rst_async_wr2;
+     END IF;
+   END PROCESS;
+
+   --Soft reset for core and testbench
+   PROCESS(rd_clk_i)
+   BEGIN 
+     IF(rd_clk_i'event AND rd_clk_i='1') THEN
+       rst_gen_rd      <= rst_gen_rd + "1";
+       IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
+         rst_s_rd      <= '1';
+         assert false
+         report "Reset applied..Memory Collision checks are not valid"
+         severity note;
+       ELSE
+         IF(AND_REDUCE(rst_gen_rd)  = '1' AND rst_s_rd = '1') THEN
+           rst_s_rd    <= '0';
+         END IF;
+       END IF;
+     END IF;
+   END PROCESS;
+   
+   PROCESS(wr_clk_i)
+   BEGIN 
+       IF(wr_clk_i'event AND wr_clk_i='1') THEN
+         rst_s_wr1   <= rst_s_rd; 
+         rst_s_wr2   <= rst_s_wr1; 
+         rst_s_wr3   <= rst_s_wr2;
+         IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
+           assert false
+           report "Reset removed..Memory Collision checks are valid"
+           severity note;
+         END IF;
+       END IF;
+   END PROCESS;
+   ------------------
+   
+   ---- Clock buffers for testbench ----
+  wr_clk_i <= WR_CLK;
+  rd_clk_i <= RD_CLK;
+   ------------------
+     
+    rst                       <=   RESET OR rst_s_rd AFTER 12 ns;
+    din                       <=   wr_data;
+    dout_i                    <=   dout;
+    wr_en                     <=   wr_en_i;
+    rd_en                     <=   rd_en_i;
+    full_i                    <=   full;
+    empty_i                   <=   empty;
+
+    fg_dg_nv: fifo_4k_2clk_dgen
+      GENERIC MAP (
+          	C_DIN_WIDTH       => 72,
+		C_DOUT_WIDTH      => 72,
+		TB_SEED           => TB_SEED, 
+ 		C_CH_TYPE         => 0	
+                 )
+      PORT MAP (  -- Write Port
+                RESET             => rst_int_wr,
+                WR_CLK            => wr_clk_i,
+		PRC_WR_EN         => prc_we_i,
+                FULL              => full_i,
+                WR_EN             => wr_en_i,
+                WR_DATA           => wr_data
+	       );
+
+   fg_dv_nv: fifo_4k_2clk_dverif
+    GENERIC MAP (  
+	       C_DOUT_WIDTH       => 72,
+	       C_DIN_WIDTH        => 72,
+	       C_USE_EMBEDDED_REG => 0,
+	       TB_SEED            => TB_SEED, 
+ 	       C_CH_TYPE          => 0
+	        )
+     PORT MAP(
+              RESET               => rst_int_rd,
+              RD_CLK              => rd_clk_i,
+	      PRC_RD_EN           => prc_re_i,
+              RD_EN               => rd_en_i,
+	      EMPTY               => empty_i,
+	      DATA_OUT            => dout_i,
+	      DOUT_CHK            => dout_chk_i
+	    );
+
+    fg_pc_nv: fifo_4k_2clk_pctrl
+    GENERIC MAP ( 
+              AXI_CHANNEL         => "Native",
+              C_APPLICATION_TYPE  => 0,
+	      C_DOUT_WIDTH        => 72,
+	      C_DIN_WIDTH         => 72,
+	      C_WR_PNTR_WIDTH     => 9,
+    	      C_RD_PNTR_WIDTH     => 9,
+ 	      C_CH_TYPE           => 0,
+              FREEZEON_ERROR      => FREEZEON_ERROR,
+	      TB_SEED             => TB_SEED, 
+              TB_STOP_CNT         => TB_STOP_CNT
+	        )
+     PORT MAP(
+              RESET_WR            => rst_int_wr,
+              RESET_RD            => rst_int_rd,
+	      RESET_EN            => reset_en,
+              WR_CLK              => wr_clk_i,
+              RD_CLK              => rd_clk_i,
+              PRC_WR_EN           => prc_we_i,
+              PRC_RD_EN           => prc_re_i,
+	      FULL                => full_i,
+              ALMOST_FULL         => almost_full_i,
+              ALMOST_EMPTY        => almost_empty_i,
+	      DOUT_CHK            => dout_chk_i,
+	      EMPTY               => empty_i,
+	      DATA_IN             => wr_data,
+	      DATA_OUT            => dout,
+	      SIM_DONE            => SIM_DONE,
+	      STATUS              => STATUS
+	    );
+
+
+
+
+
+  fifo_4k_2clk_inst : fifo_4k_2clk_exdes 
+    PORT MAP (
+           WR_CLK                    => wr_clk_i,
+           RD_CLK                    => rd_clk_i,
+           WR_DATA_COUNT             => wr_data_count,
+           RD_DATA_COUNT             => rd_data_count,
+           RST                       => rst,
+           WR_EN 		     => wr_en,
+           RD_EN                     => rd_en,
+           DIN                       => din,
+           DOUT                      => dout,
+           FULL                      => full,
+           EMPTY                     => empty);
+
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd
new file mode 100755
index 000000000..51d699e21
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd
@@ -0,0 +1,208 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_4k_2clk_tb.vhd
+--
+-- Description:
+--   This is the demo testbench top file for fifo_generator core.
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+LIBRARY std;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+USE IEEE.std_logic_arith.ALL;
+USE IEEE.std_logic_misc.ALL;
+USE ieee.numeric_std.ALL;
+USE ieee.std_logic_textio.ALL;
+USE std.textio.ALL;
+
+LIBRARY work;
+USE work.fifo_4k_2clk_pkg.ALL;
+
+ENTITY fifo_4k_2clk_tb IS
+END ENTITY;
+
+
+ARCHITECTURE fifo_4k_2clk_arch OF fifo_4k_2clk_tb IS
+ SIGNAL  status              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ SIGNAL  wr_clk              : STD_LOGIC;
+ SIGNAL  rd_clk              : STD_LOGIC;
+ SIGNAL  reset 	             : STD_LOGIC;
+ SIGNAL  sim_done            : STD_LOGIC := '0';
+ SIGNAL  end_of_sim          : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
+ -- Write and Read clock periods
+ CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
+ CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
+ -- Procedures to display strings
+ PROCEDURE disp_str(CONSTANT str:IN STRING) IS
+    variable dp_l : line := null;   
+ BEGIN
+  write(dp_l,str);
+  writeline(output,dp_l);
+ END PROCEDURE;
+ 
+ PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
+    variable dp_lx : line := null;   
+ BEGIN
+  hwrite(dp_lx,hex);
+  writeline(output,dp_lx);
+ END PROCEDURE;
+
+BEGIN
+  
+  -- Generation of clock
+
+  PROCESS BEGIN
+    WAIT FOR 400 ns; -- Wait for global reset
+    WHILE 1 = 1 LOOP
+      wr_clk <= '0';
+      WAIT FOR wr_clk_period_by_2;
+      wr_clk <= '1'; 
+      WAIT FOR wr_clk_period_by_2;
+    END LOOP;
+  END PROCESS;
+
+  PROCESS BEGIN
+    WAIT FOR 200 ns;-- Wait for global reset
+    WHILE 1 = 1 LOOP
+      rd_clk <= '0';
+      WAIT FOR rd_clk_period_by_2;
+      rd_clk <= '1'; 
+      WAIT FOR rd_clk_period_by_2;
+    END LOOP;
+  END PROCESS;
+  
+  -- Generation of Reset
+  
+  PROCESS BEGIN
+    reset <= '1';
+    WAIT FOR 4200 ns;
+    reset <= '0';
+    WAIT;
+  END PROCESS;
+  
+  
+  -- Error message printing based on STATUS signal from fifo_4k_2clk_synth
+
+  PROCESS(status)
+  BEGIN
+    IF(status /= "0" AND status /= "1") THEN
+      disp_str("STATUS:");
+      disp_hex(status);
+    END IF;
+
+    IF(status(7) = '1') THEN
+      assert false
+       report "Data mismatch found"
+       severity error;
+    END IF;
+
+    IF(status(1) = '1') THEN
+    END IF;
+    
+    IF(status(5) = '1') THEN
+      assert false
+       report "Empty flag Mismatch/timeout"
+       severity error;
+    END IF;
+
+    IF(status(6) = '1') THEN
+      assert false
+       report "Full Flag Mismatch/timeout"
+       severity error;
+    END IF;
+  END PROCESS;
+
+
+  PROCESS 
+  BEGIN
+    wait until sim_done = '1';
+    IF(status /= "0" AND status /= "1") THEN
+      assert false
+      report "Simulation failed"
+      severity failure;
+    ELSE
+      assert false
+      report "Test Completed Successfully"
+      severity failure;
+    END IF;
+  END PROCESS;
+  
+  PROCESS
+  BEGIN
+    wait for 400 ms;
+    assert false
+    report "Test bench timed out"
+    severity failure;
+  END PROCESS;
+
+  -- Instance of fifo_4k_2clk_synth
+  
+  fifo_4k_2clk_synth_inst:fifo_4k_2clk_synth
+   GENERIC MAP(
+              FREEZEON_ERROR => 0,
+ 	      TB_STOP_CNT    => 2,
+ 	      TB_SEED        => 76 
+ 	      )
+  PORT MAP(
+	   WR_CLK        => wr_clk,
+	   RD_CLK        => rd_clk,
+	   RESET         => reset,
+	   SIM_DONE      => sim_done,
+           STATUS        => status
+	  );
+
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat
new file mode 100755
index 000000000..3d0783055
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat
@@ -0,0 +1,63 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogcomp -work work ..\\..\\..\\fifo_4k_2clk.v
+vhpcomp -work work ..\\..\\example_design\\fifo_4k_2clk_exdes.vhd
+
+echo "Compiling Test Bench Files"
+vhpcomp -work work ..\\fifo_4k_2clk_pkg.vhd
+vhpcomp -work work ..\\fifo_4k_2clk_rng.vhd 
+vhpcomp -work work ..\\fifo_4k_2clk_dgen.vhd
+vhpcomp -work work ..\\fifo_4k_2clk_dverif.vhd
+vhpcomp -work work ..\\fifo_4k_2clk_pctrl.vhd 
+vhpcomp -work work ..\\fifo_4k_2clk_synth.vhd 
+vhpcomp -work work ..\\fifo_4k_2clk_tb.vhd
+
+vlogcomp -work work $XILINX\\verilog\\src\\glbl.v
+fuse work.fifo_4k_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_4k_2clk_tb.exe
+
+.\\fifo_4k_2clk_tb.exe -gui -tclbatch .\\wave_isim.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.sh
new file mode 100755
index 000000000..c3abd5a51
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.sh
@@ -0,0 +1,65 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogcomp -work work ../../../fifo_4k_2clk.v
+vhpcomp -work work ../../example_design/fifo_4k_2clk_exdes.vhd
+
+echo "Compiling Test Bench Files"
+vhpcomp -work work ../fifo_4k_2clk_pkg.vhd
+vhpcomp -work work ../fifo_4k_2clk_rng.vhd 
+vhpcomp -work work ../fifo_4k_2clk_dgen.vhd
+vhpcomp -work work ../fifo_4k_2clk_dverif.vhd
+vhpcomp -work work ../fifo_4k_2clk_pctrl.vhd 
+vhpcomp -work work ../fifo_4k_2clk_synth.vhd 
+vhpcomp -work work ../fifo_4k_2clk_tb.vhd
+
+vlogcomp -work work $XILINX/verilog/src/glbl.v
+fuse work.fifo_4k_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_4k_2clk_tb.exe
+
+./fifo_4k_2clk_tb.exe -gui -tclbatch ./wave_isim.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat
new file mode 100755
index 000000000..35375ce20
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat
@@ -0,0 +1,47 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+
+vsim -c -do simulate_mti.do
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.do
new file mode 100755
index 000000000..af53abefb
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.do
@@ -0,0 +1,74 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+vlib work 
+vmap work work 
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlog -work work ../../../fifo_4k_2clk.v
+vcom -work work ../../example_design/fifo_4k_2clk_exdes.vhd
+
+echo "Compiling Test Bench Files"
+vcom -work work ../fifo_4k_2clk_pkg.vhd
+vcom -work work ../fifo_4k_2clk_rng.vhd 
+vcom -work work ../fifo_4k_2clk_dgen.vhd
+vcom -work work ../fifo_4k_2clk_dverif.vhd
+vcom -work work ../fifo_4k_2clk_pctrl.vhd 
+vcom -work work ../fifo_4k_2clk_synth.vhd 
+vcom -work work ../fifo_4k_2clk_tb.vhd
+
+vlog -work work $env(XILINX)/verilog/src/glbl.v
+vsim  -t ps -voptargs="+acc" -L XilinxCoreLib_ver -L unisims_ver glbl work.fifo_4k_2clk_tb
+
+add log -r /*
+do wave_mti.do
+#Ignore integer warnings at time 0
+set StdArithNoWarnings 1
+run 0
+set StdArithNoWarnings 0
+
+run -all
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.sh
new file mode 100755
index 000000000..edb1b0dd9
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.sh
@@ -0,0 +1,49 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_ncsim.sh
new file mode 100755
index 000000000..0d3376452
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_ncsim.sh
@@ -0,0 +1,69 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+mkdir work
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+ncvlog -work work ../../../fifo_4k_2clk.v
+ncvhdl -v93 -work work ../../example_design/fifo_4k_2clk_exdes.vhd
+
+echo "Compiling Test Bench Files"
+ncvhdl -v93 -work work ../fifo_4k_2clk_pkg.vhd
+ncvhdl -v93 -work work ../fifo_4k_2clk_rng.vhd 
+ncvhdl -v93 -work work ../fifo_4k_2clk_dgen.vhd
+ncvhdl -v93 -work work ../fifo_4k_2clk_dverif.vhd
+ncvhdl -v93 -work work ../fifo_4k_2clk_pctrl.vhd 
+ncvhdl -v93 -work work ../fifo_4k_2clk_synth.vhd 
+ncvhdl -v93 -work work ../fifo_4k_2clk_tb.vhd
+
+echo "Elaborating Design"
+ncvlog -work work $XILINX/verilog/src/glbl.v
+ncelab -access +rwc glbl work.fifo_4k_2clk_tb
+
+echo "Simulating Design"
+ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_4k_2clk_tb
+
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_vcs.sh
new file mode 100755
index 000000000..8c26af20c
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_vcs.sh
@@ -0,0 +1,69 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+rm -rf simv* csrc DVEfiles AN.DB
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogan +v2k  ../../../fifo_4k_2clk.v
+vhdlan  ../../example_design/fifo_4k_2clk_exdes.vhd
+
+echo "Compiling Test Bench Files"
+vhdlan   ../fifo_4k_2clk_pkg.vhd
+vhdlan   ../fifo_4k_2clk_rng.vhd 
+vhdlan   ../fifo_4k_2clk_dgen.vhd
+vhdlan   ../fifo_4k_2clk_dverif.vhd
+vhdlan   ../fifo_4k_2clk_pctrl.vhd 
+vhdlan   ../fifo_4k_2clk_synth.vhd 
+vhdlan   ../fifo_4k_2clk_tb.vhd
+
+echo "Elaborating Design"
+vlogan +v2k $XILINX/verilog/src/glbl.v
+vcs -time_res 1ps +vcs+lic+wait -debug fifo_4k_2clk_tb glbl
+
+echo "Simulating Design"
+./simv -ucli -i ucli_commands.key
+dve -session vcs_session.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key
new file mode 100755
index 000000000..9c95a2ade
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key
@@ -0,0 +1,4 @@
+dump -file fifo_4k_2clk.vpd -type VPD
+dump -add fifo_4k_2clk_tb
+run 
+quit
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl
new file mode 100755
index 000000000..b9ef9837a
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl
@@ -0,0 +1,77 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: vcs_session.tcl
+#
+# Description:
+#   This is the VCS wave form file.
+#
+#--------------------------------------------------------------------------------
+if { ![gui_is_db_opened -db {fifo_4k_2clk.vpd}] } {
+	gui_open_db -design V1 -file fifo_4k_2clk.vpd -nosource
+}
+gui_set_precision 1ps
+gui_set_time_units 1ps
+
+
+gui_open_window Wave
+gui_sg_create fifo_4k_2clk_Group
+gui_list_add_group -id Wave.1 {fifo_4k_2clk_Group}
+
+gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST
+gui_sg_addsignal -group fifo_4k_2clk_Group  WRITE -divider
+gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK
+gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN
+gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL
+gui_sg_addsignal -group fifo_4k_2clk_Group  READ -divider
+gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK
+gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN
+gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY
+gui_zoom -window Wave.1 -full
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl
new file mode 100755
index 000000000..10be1a965
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl
@@ -0,0 +1,68 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: wave_isim.tcl
+#
+# Description:
+#   This is the ISIM wave form file.
+#
+#--------------------------------------------------------------------------------
+wcfg new
+isim set radix hex
+wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST
+wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK
+wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN
+wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL
+wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK
+wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN
+wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY
+run all
+quit
+
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do
new file mode 100755
index 000000000..adc4cb8d7
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do
@@ -0,0 +1,88 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+# Filename: wave_mti.do
+#
+# Description:
+#   This is the modelsim wave form file.
+#
+#--------------------------------------------------------------------------------
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST
+add wave -noupdate -divider WRITE
+add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK
+add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN
+add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL
+add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DIN
+add wave -noupdate -divider READ
+add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK
+add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN
+add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY
+add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DOUT
+
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {2164886 ps} 0}
+configure wave -namecolwidth 197
+configure wave -valuecolwidth 106
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {9464063 ps}
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_ncsim.sv
new file mode 100755
index 000000000..51819bad9
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_ncsim.sv
@@ -0,0 +1,70 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: wave_ncsim.sv
+#
+# Description:
+#   This is the IUS wave form file.
+#
+#--------------------------------------------------------------------------------
+
+window new WaveWindow  -name  "Waves for FIFO Generator Example Design"
+waveform  using  "Waves for FIFO Generator Example Design"
+
+waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST
+waveform add -label WRITE
+waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK
+waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN
+waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL
+waveform add -label READ
+waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK
+waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN
+waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY
+console submit -using simulator -wait no "run"
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat
new file mode 100755
index 000000000..a6f8ce91f
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat
@@ -0,0 +1,61 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogcomp -work work ..\\..\\implement\\results\\routed.v
+
+echo "Compiling Test Bench Files"
+vhpcomp -work work ..\\fifo_4k_2clk_pkg.vhd
+vhpcomp -work work ..\\fifo_4k_2clk_rng.vhd 
+vhpcomp -work work ..\\fifo_4k_2clk_dgen.vhd
+vhpcomp -work work ..\\fifo_4k_2clk_dverif.vhd
+vhpcomp -work work ..\\fifo_4k_2clk_pctrl.vhd 
+vhpcomp -work work ..\\fifo_4k_2clk_synth.vhd 
+vhpcomp -work work ..\\fifo_4k_2clk_tb.vhd
+
+fuse work.fifo_4k_2clk_tb work.glbl -L simprims_ver -o fifo_4k_2clk_tb.exe
+
+.\\fifo_4k_2clk_tb.exe -sdfmax /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst=..\\..\\implement\\results\\routed.sdf -gui -tclbatch .\\wave_isim.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.sh
new file mode 100755
index 000000000..f5ad36b7e
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.sh
@@ -0,0 +1,63 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogcomp -work work ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+vhpcomp -work work ../fifo_4k_2clk_pkg.vhd
+vhpcomp -work work ../fifo_4k_2clk_rng.vhd 
+vhpcomp -work work ../fifo_4k_2clk_dgen.vhd
+vhpcomp -work work ../fifo_4k_2clk_dverif.vhd
+vhpcomp -work work ../fifo_4k_2clk_pctrl.vhd 
+vhpcomp -work work ../fifo_4k_2clk_synth.vhd 
+vhpcomp -work work ../fifo_4k_2clk_tb.vhd
+
+fuse work.fifo_4k_2clk_tb work.glbl -L simprims_ver -o fifo_4k_2clk_tb.exe
+
+./fifo_4k_2clk_tb.exe -sdfmax /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst=../../implement/results/routed.sdf -gui -tclbatch ./wave_isim.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat
new file mode 100755
index 000000000..35375ce20
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat
@@ -0,0 +1,47 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+
+vsim -c -do simulate_mti.do
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.do
new file mode 100755
index 000000000..74e930a13
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.do
@@ -0,0 +1,72 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+vlib work 
+vmap work work 
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlog -work work ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+vcom -work work ../fifo_4k_2clk_pkg.vhd  
+vcom -work work ../fifo_4k_2clk_rng.vhd 
+vcom -work work ../fifo_4k_2clk_dgen.vhd
+vcom -work work ../fifo_4k_2clk_dverif.vhd
+vcom -work work ../fifo_4k_2clk_pctrl.vhd 
+vcom -work work ../fifo_4k_2clk_synth.vhd 
+vcom -work work ../fifo_4k_2clk_tb.vhd
+
+vsim  -t ps -voptargs="+acc" +transport_int_delays -L simprims_ver glbl -sdfmax /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst=../../implement/results/routed.sdf work.fifo_4k_2clk_tb
+
+add log -r /*
+do wave_mti.do
+#Ignore integer warnings at time 0
+set StdArithNoWarnings 1
+run 0
+set StdArithNoWarnings 0
+
+run -all
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.sh
new file mode 100755
index 000000000..edb1b0dd9
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.sh
@@ -0,0 +1,49 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_ncsim.sh
new file mode 100755
index 000000000..a1967adcf
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_ncsim.sh
@@ -0,0 +1,73 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+mkdir work
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+ncvlog -work work ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+ncvhdl -v93 -work work ../fifo_4k_2clk_pkg.vhd
+ncvhdl -v93 -work work ../fifo_4k_2clk_rng.vhd 
+ncvhdl -v93 -work work ../fifo_4k_2clk_dgen.vhd
+ncvhdl -v93 -work work ../fifo_4k_2clk_dverif.vhd
+ncvhdl -v93 -work work ../fifo_4k_2clk_pctrl.vhd 
+ncvhdl -v93 -work work ../fifo_4k_2clk_synth.vhd 
+ncvhdl -v93 -work work ../fifo_4k_2clk_tb.vhd
+
+echo "Compiling SDF file"
+ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X
+
+echo "Generating SDF command file"
+echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd
+echo 'SCOPE = :fifo_4k_2clk_synth_inst:fifo_4k_2clk_inst,' >> sdf.cmd
+echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd
+
+echo "Elaborating Design"
+ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd work.fifo_4k_2clk_tb
+
+echo "Simulating Design"
+ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_4k_2clk_tb
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_vcs.sh
new file mode 100755
index 000000000..f62f540be
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_vcs.sh
@@ -0,0 +1,67 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+rm -rf simv* csrc DVEfiles AN.DB
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogan +v2k  ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+vhdlan   ../fifo_4k_2clk_pkg.vhd
+vhdlan   ../fifo_4k_2clk_rng.vhd
+vhdlan   ../fifo_4k_2clk_dgen.vhd
+vhdlan   ../fifo_4k_2clk_dverif.vhd
+vhdlan   ../fifo_4k_2clk_pctrl.vhd
+vhdlan   ../fifo_4k_2clk_synth.vhd
+vhdlan   ../fifo_4k_2clk_tb.vhd
+
+echo "Elaborating Design"
+vcs -time_res 1ps +neg_tchk -sdf max:/fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst:../../implement/results/routed.sdf +vcs+lic+wait -debug fifo_4k_2clk_tb glbl
+
+echo "Simulating Design"
+./simv -ucli -i ucli_commands.key
+dve -session vcs_session.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key
new file mode 100755
index 000000000..9c95a2ade
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key
@@ -0,0 +1,4 @@
+dump -file fifo_4k_2clk.vpd -type VPD
+dump -add fifo_4k_2clk_tb
+run 
+quit
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/vcs_session.tcl
new file mode 100755
index 000000000..28ebc1163
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/vcs_session.tcl
@@ -0,0 +1,76 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: vcs_session.tcl
+#
+# Description:
+#   This is the VCS wave form file.
+#
+#--------------------------------------------------------------------------------
+if { ![gui_is_db_opened -db {fifo_4k_2clk.vpd}] } {
+	gui_open_db -design V1 -file fifo_4k_2clk.vpd -nosource
+}
+gui_set_precision 1ps
+gui_set_time_units 1ps
+
+gui_open_window Wave
+gui_sg_create fifo_4k_2clk_Group
+gui_list_add_group -id Wave.1 {fifo_4k_2clk_Group}
+
+gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST
+gui_sg_addsignal -group fifo_4k_2clk_Group  WRITE -divider
+gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK
+gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN
+gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL
+gui_sg_addsignal -group fifo_4k_2clk_Group  READ -divider
+gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK
+gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN
+gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY
+gui_zoom -window Wave.1 -full
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_isim.tcl
new file mode 100755
index 000000000..10be1a965
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_isim.tcl
@@ -0,0 +1,68 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: wave_isim.tcl
+#
+# Description:
+#   This is the ISIM wave form file.
+#
+#--------------------------------------------------------------------------------
+wcfg new
+isim set radix hex
+wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST
+wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK
+wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN
+wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL
+wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK
+wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN
+wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY
+run all
+quit
+
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do
new file mode 100755
index 000000000..adc4cb8d7
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do
@@ -0,0 +1,88 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+# Filename: wave_mti.do
+#
+# Description:
+#   This is the modelsim wave form file.
+#
+#--------------------------------------------------------------------------------
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST
+add wave -noupdate -divider WRITE
+add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK
+add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN
+add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL
+add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DIN
+add wave -noupdate -divider READ
+add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK
+add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN
+add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY
+add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DOUT
+
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {2164886 ps} 0}
+configure wave -namecolwidth 197
+configure wave -valuecolwidth 106
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {9464063 ps}
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_ncsim.sv
new file mode 100755
index 000000000..51819bad9
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_ncsim.sv
@@ -0,0 +1,70 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: wave_ncsim.sv
+#
+# Description:
+#   This is the IUS wave form file.
+#
+#--------------------------------------------------------------------------------
+
+window new WaveWindow  -name  "Waves for FIFO Generator Example Design"
+waveform  using  "Waves for FIFO Generator Example Design"
+
+waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST
+waveform add -label WRITE
+waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK
+waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN
+waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL
+waveform add -label READ
+waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK
+waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN
+waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY
+console submit -using simulator -wait no "run"
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_flist.txt b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_flist.txt
new file mode 100644
index 000000000..e33a4de1c
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_flist.txt
@@ -0,0 +1,56 @@
+# Output products list for <fifo_4k_2clk>
+fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt
+fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html
+fifo_4k_2clk/doc/pg057-fifo-generator.pdf
+fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf
+fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd
+fifo_4k_2clk/fifo_generator_v9_3_readme.txt
+fifo_4k_2clk/implement/implement.bat
+fifo_4k_2clk/implement/implement.sh
+fifo_4k_2clk/implement/implement_synplify.bat
+fifo_4k_2clk/implement/implement_synplify.sh
+fifo_4k_2clk/implement/planAhead_ise.bat
+fifo_4k_2clk/implement/planAhead_ise.sh
+fifo_4k_2clk/implement/planAhead_ise.tcl
+fifo_4k_2clk/implement/xst.prj
+fifo_4k_2clk/implement/xst.scr
+fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd
+fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd
+fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd
+fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd
+fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd
+fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd
+fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd
+fifo_4k_2clk/simulation/functional/simulate_isim.bat
+fifo_4k_2clk/simulation/functional/simulate_isim.sh
+fifo_4k_2clk/simulation/functional/simulate_mti.bat
+fifo_4k_2clk/simulation/functional/simulate_mti.do
+fifo_4k_2clk/simulation/functional/simulate_mti.sh
+fifo_4k_2clk/simulation/functional/simulate_ncsim.sh
+fifo_4k_2clk/simulation/functional/simulate_vcs.sh
+fifo_4k_2clk/simulation/functional/ucli_commands.key
+fifo_4k_2clk/simulation/functional/vcs_session.tcl
+fifo_4k_2clk/simulation/functional/wave_isim.tcl
+fifo_4k_2clk/simulation/functional/wave_mti.do
+fifo_4k_2clk/simulation/functional/wave_ncsim.sv
+fifo_4k_2clk/simulation/timing/simulate_isim.bat
+fifo_4k_2clk/simulation/timing/simulate_isim.sh
+fifo_4k_2clk/simulation/timing/simulate_mti.bat
+fifo_4k_2clk/simulation/timing/simulate_mti.do
+fifo_4k_2clk/simulation/timing/simulate_mti.sh
+fifo_4k_2clk/simulation/timing/simulate_ncsim.sh
+fifo_4k_2clk/simulation/timing/simulate_vcs.sh
+fifo_4k_2clk/simulation/timing/ucli_commands.key
+fifo_4k_2clk/simulation/timing/vcs_session.tcl
+fifo_4k_2clk/simulation/timing/wave_isim.tcl
+fifo_4k_2clk/simulation/timing/wave_mti.do
+fifo_4k_2clk/simulation/timing/wave_ncsim.sv
+fifo_4k_2clk.asy
+fifo_4k_2clk.gise
+fifo_4k_2clk.ngc
+fifo_4k_2clk.v
+fifo_4k_2clk.veo
+fifo_4k_2clk.xco
+fifo_4k_2clk.xise
+fifo_4k_2clk_flist.txt
+fifo_4k_2clk_xmdf.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_xmdf.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_xmdf.tcl
new file mode 100644
index 000000000..bdc5c355d
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_xmdf.tcl
@@ -0,0 +1,251 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_4k_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_4k_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_4k_2clk_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_4k_2clk
+}
+# ::fifo_4k_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_4k_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/doc/pg057-fifo-generator.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/fifo_generator_v9_3_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement_synplify.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement_synplify.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/planAhead_ise.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/planAhead_ise.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/planAhead_ise.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/xst.prj
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/xst.scr
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_isim.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_isim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_mti.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_mti.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_vcs.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/ucli_commands.key
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/vcs_session.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/wave_isim.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/wave_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/wave_ncsim.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_isim.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_isim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_mti.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_mti.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_vcs.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/ucli_commands.key
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/vcs_session.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/wave_isim.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/wave_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/wave_ncsim.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_4k_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.asy b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.asy
new file mode 100644
index 000000000..1c03599f3
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.asy
@@ -0,0 +1,49 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 fifo_short_2clk
+RECTANGLE Normal 32 32 800 4064
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Normal 0 208 32 208
+PIN 0 208 LEFT 36
+PINATTR PinName wr_clk
+PINATTR Polarity IN
+LINE Wide 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName din[71:0]
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 464 32 464
+PIN 0 464 LEFT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Wide 0 624 32 624
+PIN 0 624 LEFT 36
+PINATTR PinName wr_data_count[5:0]
+PINATTR Polarity OUT
+LINE Normal 832 240 800 240
+PIN 832 240 RIGHT 36
+PINATTR PinName rd_clk
+PINATTR Polarity IN
+LINE Wide 832 272 800 272
+PIN 832 272 RIGHT 36
+PINATTR PinName dout[71:0]
+PINATTR Polarity OUT
+LINE Normal 832 304 800 304
+PIN 832 304 RIGHT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 832 496 800 496
+PIN 832 496 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+LINE Wide 832 656 800 656
+PIN 832 656 RIGHT 36
+PINATTR PinName rd_data_count[5:0]
+PINATTR Polarity OUT
+
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise
new file mode 100644
index 000000000..ea47d0f4b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_short_2clk.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_short_2clk.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_short_2clk.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ncf b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ncf
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ngc b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ngc
new file mode 100644
index 000000000..ec6b0ff10
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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a5=111C?ik4H2f:?!g32>1b9h4?::k43?6=3`i26=44ob`94?=zj:ii6=4;:183!b42020D>jj;I1g=>"f<3=0e8k50;9j32<722ch57>5;naa>5<<uk9o97>53;294~"c;33>7E=ke:J0`<=O=h1/n?4k2:&b0?4<a<o1<75f7683>>idj3:17pl<c183>1<729q/h>468:J0``=O;m30D8o4$c09`7=#i=0<7d;j:188m21=831bo44?::m`f?6=3th94o4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<d<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9454?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<2<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94;4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<0<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9494?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<6<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94?4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<4<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94=4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;i4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13f<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;o4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13d<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;44?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;:4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`133<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;84?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`131<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;?4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`134<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;=4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:h4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12a<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:n4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:l4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9::4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`123<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:84?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`121<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:>4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`127<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:<4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`125<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99k4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`11`<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99n4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`11g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99l4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`11<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9954?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`112<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99;4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`110<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9994?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`116<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99<4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`115<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th98k4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10`<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th98i4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10f<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th98o4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10d<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9844?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94i4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<f<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9444?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13`<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;: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d8?:188m25=831b;:4?::m`f?6=3th88o4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`00<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88:4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`000<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88>4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`07c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?i4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`07g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?44?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`072<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?84?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`076<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?<4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`06c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8>i4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0f=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8n;4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0f5<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th85l4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0<1<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8:h4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`01=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88?4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`06f<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8>l4?:483>5}#l:02;6F<dd9K7a?<,h>1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`234<72=0;6=u+d28:2>N4ll1C?i74$`696>o2m3:17d9<:188m21=831doo4?::a526=83>1<7>t$e19=3=O;mo0D>j6;%c7>7=n=l0;66g83;29?l102900cnl50;9~f40a290?6=4?{%f0><0<@:nn7E=k9:&b0?4<a<o1<75f7283>>o0?3:17bmm:188yg71m3:187>50z&g7??13A9oi6F<d89'e1<53`?n6=44i6194?=n?>0;66alb;29?xd6>m0;694?:1y'`6<>>2B8hh5G3e;8 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\ No newline at end of file
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.v b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.v
new file mode 100644
index 000000000..82200a502
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.v
@@ -0,0 +1,491 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
+*                                                                              *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
+*                                                                              *
+*     (c) Copyright 1995-2013 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// You must compile the wrapper file fifo_short_2clk.v when simulating
+// the core, fifo_short_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+`timescale 1ns/1ps
+
+module fifo_short_2clk(
+  rst,
+  wr_clk,
+  rd_clk,
+  din,
+  wr_en,
+  rd_en,
+  dout,
+  full,
+  empty,
+  rd_data_count,
+  wr_data_count
+);
+
+input rst;
+input wr_clk;
+input rd_clk;
+input [71 : 0] din;
+input wr_en;
+input rd_en;
+output [71 : 0] dout;
+output full;
+output empty;
+output [5 : 0] rd_data_count;
+output [5 : 0] wr_data_count;
+
+// synthesis translate_off
+
+  FIFO_GENERATOR_V9_3 #(
+    .C_ADD_NGC_CONSTRAINT(0),
+    .C_APPLICATION_TYPE_AXIS(0),
+    .C_APPLICATION_TYPE_RACH(0),
+    .C_APPLICATION_TYPE_RDCH(0),
+    .C_APPLICATION_TYPE_WACH(0),
+    .C_APPLICATION_TYPE_WDCH(0),
+    .C_APPLICATION_TYPE_WRCH(0),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_AXI_DATA_WIDTH(64),
+    .C_AXI_ID_WIDTH(4),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_TYPE(0),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXIS_TDATA_WIDTH(64),
+    .C_AXIS_TDEST_WIDTH(4),
+    .C_AXIS_TID_WIDTH(8),
+    .C_AXIS_TKEEP_WIDTH(4),
+    .C_AXIS_TSTRB_WIDTH(4),
+    .C_AXIS_TUSER_WIDTH(4),
+    .C_AXIS_TYPE(0),
+    .C_COMMON_CLOCK(0),
+    .C_COUNT_TYPE(0),
+    .C_DATA_COUNT_WIDTH(5),
+    .C_DEFAULT_VALUE("BlankString"),
+    .C_DIN_WIDTH(72),
+    .C_DIN_WIDTH_AXIS(1),
+    .C_DIN_WIDTH_RACH(32),
+    .C_DIN_WIDTH_RDCH(64),
+    .C_DIN_WIDTH_WACH(32),
+    .C_DIN_WIDTH_WDCH(64),
+    .C_DIN_WIDTH_WRCH(2),
+    .C_DOUT_RST_VAL("0"),
+    .C_DOUT_WIDTH(72),
+    .C_ENABLE_RLOCS(0),
+    .C_ENABLE_RST_SYNC(1),
+    .C_ERROR_INJECTION_TYPE(0),
+    .C_ERROR_INJECTION_TYPE_AXIS(0),
+    .C_ERROR_INJECTION_TYPE_RACH(0),
+    .C_ERROR_INJECTION_TYPE_RDCH(0),
+    .C_ERROR_INJECTION_TYPE_WACH(0),
+    .C_ERROR_INJECTION_TYPE_WDCH(0),
+    .C_ERROR_INJECTION_TYPE_WRCH(0),
+    .C_FAMILY("spartan6"),
+    .C_FULL_FLAGS_RST_VAL(1),
+    .C_HAS_ALMOST_EMPTY(0),
+    .C_HAS_ALMOST_FULL(0),
+    .C_HAS_AXI_ARUSER(0),
+    .C_HAS_AXI_AWUSER(0),
+    .C_HAS_AXI_BUSER(0),
+    .C_HAS_AXI_RD_CHANNEL(0),
+    .C_HAS_AXI_RUSER(0),
+    .C_HAS_AXI_WR_CHANNEL(0),
+    .C_HAS_AXI_WUSER(0),
+    .C_HAS_AXIS_TDATA(0),
+    .C_HAS_AXIS_TDEST(0),
+    .C_HAS_AXIS_TID(0),
+    .C_HAS_AXIS_TKEEP(0),
+    .C_HAS_AXIS_TLAST(0),
+    .C_HAS_AXIS_TREADY(1),
+    .C_HAS_AXIS_TSTRB(0),
+    .C_HAS_AXIS_TUSER(0),
+    .C_HAS_BACKUP(0),
+    .C_HAS_DATA_COUNT(0),
+    .C_HAS_DATA_COUNTS_AXIS(0),
+    .C_HAS_DATA_COUNTS_RACH(0),
+    .C_HAS_DATA_COUNTS_RDCH(0),
+    .C_HAS_DATA_COUNTS_WACH(0),
+    .C_HAS_DATA_COUNTS_WDCH(0),
+    .C_HAS_DATA_COUNTS_WRCH(0),
+    .C_HAS_INT_CLK(0),
+    .C_HAS_MASTER_CE(0),
+    .C_HAS_MEMINIT_FILE(0),
+    .C_HAS_OVERFLOW(0),
+    .C_HAS_PROG_FLAGS_AXIS(0),
+    .C_HAS_PROG_FLAGS_RACH(0),
+    .C_HAS_PROG_FLAGS_RDCH(0),
+    .C_HAS_PROG_FLAGS_WACH(0),
+    .C_HAS_PROG_FLAGS_WDCH(0),
+    .C_HAS_PROG_FLAGS_WRCH(0),
+    .C_HAS_RD_DATA_COUNT(1),
+    .C_HAS_RD_RST(0),
+    .C_HAS_RST(1),
+    .C_HAS_SLAVE_CE(0),
+    .C_HAS_SRST(0),
+    .C_HAS_UNDERFLOW(0),
+    .C_HAS_VALID(0),
+    .C_HAS_WR_ACK(0),
+    .C_HAS_WR_DATA_COUNT(1),
+    .C_HAS_WR_RST(0),
+    .C_IMPLEMENTATION_TYPE(2),
+    .C_IMPLEMENTATION_TYPE_AXIS(1),
+    .C_IMPLEMENTATION_TYPE_RACH(1),
+    .C_IMPLEMENTATION_TYPE_RDCH(1),
+    .C_IMPLEMENTATION_TYPE_WACH(1),
+    .C_IMPLEMENTATION_TYPE_WDCH(1),
+    .C_IMPLEMENTATION_TYPE_WRCH(1),
+    .C_INIT_WR_PNTR_VAL(0),
+    .C_INTERFACE_TYPE(0),
+    .C_MEMORY_TYPE(2),
+    .C_MIF_FILE_NAME("BlankString"),
+    .C_MSGON_VAL(1),
+    .C_OPTIMIZATION_MODE(0),
+    .C_OVERFLOW_LOW(0),
+    .C_PRELOAD_LATENCY(0),
+    .C_PRELOAD_REGS(1),
+    .C_PRIM_FIFO_TYPE("512x72"),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
+    .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+    .C_PROG_EMPTY_TYPE(0),
+    .C_PROG_EMPTY_TYPE_AXIS(0),
+    .C_PROG_EMPTY_TYPE_RACH(0),
+    .C_PROG_EMPTY_TYPE_RDCH(0),
+    .C_PROG_EMPTY_TYPE_WACH(0),
+    .C_PROG_EMPTY_TYPE_WDCH(0),
+    .C_PROG_EMPTY_TYPE_WRCH(0),
+    .C_PROG_FULL_THRESH_ASSERT_VAL(31),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
+    .C_PROG_FULL_THRESH_NEGATE_VAL(30),
+    .C_PROG_FULL_TYPE(0),
+    .C_PROG_FULL_TYPE_AXIS(0),
+    .C_PROG_FULL_TYPE_RACH(0),
+    .C_PROG_FULL_TYPE_RDCH(0),
+    .C_PROG_FULL_TYPE_WACH(0),
+    .C_PROG_FULL_TYPE_WDCH(0),
+    .C_PROG_FULL_TYPE_WRCH(0),
+    .C_RACH_TYPE(0),
+    .C_RD_DATA_COUNT_WIDTH(6),
+    .C_RD_DEPTH(32),
+    .C_RD_FREQ(1),
+    .C_RD_PNTR_WIDTH(5),
+    .C_RDCH_TYPE(0),
+    .C_REG_SLICE_MODE_AXIS(0),
+    .C_REG_SLICE_MODE_RACH(0),
+    .C_REG_SLICE_MODE_RDCH(0),
+    .C_REG_SLICE_MODE_WACH(0),
+    .C_REG_SLICE_MODE_WDCH(0),
+    .C_REG_SLICE_MODE_WRCH(0),
+    .C_SYNCHRONIZER_STAGE(2),
+    .C_UNDERFLOW_LOW(0),
+    .C_USE_COMMON_OVERFLOW(0),
+    .C_USE_COMMON_UNDERFLOW(0),
+    .C_USE_DEFAULT_SETTINGS(0),
+    .C_USE_DOUT_RST(1),
+    .C_USE_ECC(0),
+    .C_USE_ECC_AXIS(0),
+    .C_USE_ECC_RACH(0),
+    .C_USE_ECC_RDCH(0),
+    .C_USE_ECC_WACH(0),
+    .C_USE_ECC_WDCH(0),
+    .C_USE_ECC_WRCH(0),
+    .C_USE_EMBEDDED_REG(0),
+    .C_USE_FIFO16_FLAGS(0),
+    .C_USE_FWFT_DATA_COUNT(1),
+    .C_VALID_LOW(0),
+    .C_WACH_TYPE(0),
+    .C_WDCH_TYPE(0),
+    .C_WR_ACK_LOW(0),
+    .C_WR_DATA_COUNT_WIDTH(6),
+    .C_WR_DEPTH(32),
+    .C_WR_DEPTH_AXIS(1024),
+    .C_WR_DEPTH_RACH(16),
+    .C_WR_DEPTH_RDCH(1024),
+    .C_WR_DEPTH_WACH(16),
+    .C_WR_DEPTH_WDCH(1024),
+    .C_WR_DEPTH_WRCH(16),
+    .C_WR_FREQ(1),
+    .C_WR_PNTR_WIDTH(5),
+    .C_WR_PNTR_WIDTH_AXIS(10),
+    .C_WR_PNTR_WIDTH_RACH(4),
+    .C_WR_PNTR_WIDTH_RDCH(10),
+    .C_WR_PNTR_WIDTH_WACH(4),
+    .C_WR_PNTR_WIDTH_WDCH(10),
+    .C_WR_PNTR_WIDTH_WRCH(4),
+    .C_WR_RESPONSE_LATENCY(1),
+    .C_WRCH_TYPE(0)
+  )
+  inst (
+    .RST(rst),
+    .WR_CLK(wr_clk),
+    .RD_CLK(rd_clk),
+    .DIN(din),
+    .WR_EN(wr_en),
+    .RD_EN(rd_en),
+    .DOUT(dout),
+    .FULL(full),
+    .EMPTY(empty),
+    .RD_DATA_COUNT(rd_data_count),
+    .WR_DATA_COUNT(wr_data_count),
+    .BACKUP(),
+    .BACKUP_MARKER(),
+    .CLK(),
+    .SRST(),
+    .WR_RST(),
+    .RD_RST(),
+    .PROG_EMPTY_THRESH(),
+    .PROG_EMPTY_THRESH_ASSERT(),
+    .PROG_EMPTY_THRESH_NEGATE(),
+    .PROG_FULL_THRESH(),
+    .PROG_FULL_THRESH_ASSERT(),
+    .PROG_FULL_THRESH_NEGATE(),
+    .INT_CLK(),
+    .INJECTDBITERR(),
+    .INJECTSBITERR(),
+    .ALMOST_FULL(),
+    .WR_ACK(),
+    .OVERFLOW(),
+    .ALMOST_EMPTY(),
+    .VALID(),
+    .UNDERFLOW(),
+    .DATA_COUNT(),
+    .PROG_FULL(),
+    .PROG_EMPTY(),
+    .SBITERR(),
+    .DBITERR(),
+    .M_ACLK(),
+    .S_ACLK(),
+    .S_ARESETN(),
+    .M_ACLK_EN(),
+    .S_ACLK_EN(),
+    .S_AXI_AWID(),
+    .S_AXI_AWADDR(),
+    .S_AXI_AWLEN(),
+    .S_AXI_AWSIZE(),
+    .S_AXI_AWBURST(),
+    .S_AXI_AWLOCK(),
+    .S_AXI_AWCACHE(),
+    .S_AXI_AWPROT(),
+    .S_AXI_AWQOS(),
+    .S_AXI_AWREGION(),
+    .S_AXI_AWUSER(),
+    .S_AXI_AWVALID(),
+    .S_AXI_AWREADY(),
+    .S_AXI_WID(),
+    .S_AXI_WDATA(),
+    .S_AXI_WSTRB(),
+    .S_AXI_WLAST(),
+    .S_AXI_WUSER(),
+    .S_AXI_WVALID(),
+    .S_AXI_WREADY(),
+    .S_AXI_BID(),
+    .S_AXI_BRESP(),
+    .S_AXI_BUSER(),
+    .S_AXI_BVALID(),
+    .S_AXI_BREADY(),
+    .M_AXI_AWID(),
+    .M_AXI_AWADDR(),
+    .M_AXI_AWLEN(),
+    .M_AXI_AWSIZE(),
+    .M_AXI_AWBURST(),
+    .M_AXI_AWLOCK(),
+    .M_AXI_AWCACHE(),
+    .M_AXI_AWPROT(),
+    .M_AXI_AWQOS(),
+    .M_AXI_AWREGION(),
+    .M_AXI_AWUSER(),
+    .M_AXI_AWVALID(),
+    .M_AXI_AWREADY(),
+    .M_AXI_WID(),
+    .M_AXI_WDATA(),
+    .M_AXI_WSTRB(),
+    .M_AXI_WLAST(),
+    .M_AXI_WUSER(),
+    .M_AXI_WVALID(),
+    .M_AXI_WREADY(),
+    .M_AXI_BID(),
+    .M_AXI_BRESP(),
+    .M_AXI_BUSER(),
+    .M_AXI_BVALID(),
+    .M_AXI_BREADY(),
+    .S_AXI_ARID(),
+    .S_AXI_ARADDR(),
+    .S_AXI_ARLEN(),
+    .S_AXI_ARSIZE(),
+    .S_AXI_ARBURST(),
+    .S_AXI_ARLOCK(),
+    .S_AXI_ARCACHE(),
+    .S_AXI_ARPROT(),
+    .S_AXI_ARQOS(),
+    .S_AXI_ARREGION(),
+    .S_AXI_ARUSER(),
+    .S_AXI_ARVALID(),
+    .S_AXI_ARREADY(),
+    .S_AXI_RID(),
+    .S_AXI_RDATA(),
+    .S_AXI_RRESP(),
+    .S_AXI_RLAST(),
+    .S_AXI_RUSER(),
+    .S_AXI_RVALID(),
+    .S_AXI_RREADY(),
+    .M_AXI_ARID(),
+    .M_AXI_ARADDR(),
+    .M_AXI_ARLEN(),
+    .M_AXI_ARSIZE(),
+    .M_AXI_ARBURST(),
+    .M_AXI_ARLOCK(),
+    .M_AXI_ARCACHE(),
+    .M_AXI_ARPROT(),
+    .M_AXI_ARQOS(),
+    .M_AXI_ARREGION(),
+    .M_AXI_ARUSER(),
+    .M_AXI_ARVALID(),
+    .M_AXI_ARREADY(),
+    .M_AXI_RID(),
+    .M_AXI_RDATA(),
+    .M_AXI_RRESP(),
+    .M_AXI_RLAST(),
+    .M_AXI_RUSER(),
+    .M_AXI_RVALID(),
+    .M_AXI_RREADY(),
+    .S_AXIS_TVALID(),
+    .S_AXIS_TREADY(),
+    .S_AXIS_TDATA(),
+    .S_AXIS_TSTRB(),
+    .S_AXIS_TKEEP(),
+    .S_AXIS_TLAST(),
+    .S_AXIS_TID(),
+    .S_AXIS_TDEST(),
+    .S_AXIS_TUSER(),
+    .M_AXIS_TVALID(),
+    .M_AXIS_TREADY(),
+    .M_AXIS_TDATA(),
+    .M_AXIS_TSTRB(),
+    .M_AXIS_TKEEP(),
+    .M_AXIS_TLAST(),
+    .M_AXIS_TID(),
+    .M_AXIS_TDEST(),
+    .M_AXIS_TUSER(),
+    .AXI_AW_INJECTSBITERR(),
+    .AXI_AW_INJECTDBITERR(),
+    .AXI_AW_PROG_FULL_THRESH(),
+    .AXI_AW_PROG_EMPTY_THRESH(),
+    .AXI_AW_DATA_COUNT(),
+    .AXI_AW_WR_DATA_COUNT(),
+    .AXI_AW_RD_DATA_COUNT(),
+    .AXI_AW_SBITERR(),
+    .AXI_AW_DBITERR(),
+    .AXI_AW_OVERFLOW(),
+    .AXI_AW_UNDERFLOW(),
+    .AXI_AW_PROG_FULL(),
+    .AXI_AW_PROG_EMPTY(),
+    .AXI_W_INJECTSBITERR(),
+    .AXI_W_INJECTDBITERR(),
+    .AXI_W_PROG_FULL_THRESH(),
+    .AXI_W_PROG_EMPTY_THRESH(),
+    .AXI_W_DATA_COUNT(),
+    .AXI_W_WR_DATA_COUNT(),
+    .AXI_W_RD_DATA_COUNT(),
+    .AXI_W_SBITERR(),
+    .AXI_W_DBITERR(),
+    .AXI_W_OVERFLOW(),
+    .AXI_W_UNDERFLOW(),
+    .AXI_B_INJECTSBITERR(),
+    .AXI_W_PROG_FULL(),
+    .AXI_W_PROG_EMPTY(),
+    .AXI_B_INJECTDBITERR(),
+    .AXI_B_PROG_FULL_THRESH(),
+    .AXI_B_PROG_EMPTY_THRESH(),
+    .AXI_B_DATA_COUNT(),
+    .AXI_B_WR_DATA_COUNT(),
+    .AXI_B_RD_DATA_COUNT(),
+    .AXI_B_SBITERR(),
+    .AXI_B_DBITERR(),
+    .AXI_B_OVERFLOW(),
+    .AXI_B_UNDERFLOW(),
+    .AXI_AR_INJECTSBITERR(),
+    .AXI_B_PROG_FULL(),
+    .AXI_B_PROG_EMPTY(),
+    .AXI_AR_INJECTDBITERR(),
+    .AXI_AR_PROG_FULL_THRESH(),
+    .AXI_AR_PROG_EMPTY_THRESH(),
+    .AXI_AR_DATA_COUNT(),
+    .AXI_AR_WR_DATA_COUNT(),
+    .AXI_AR_RD_DATA_COUNT(),
+    .AXI_AR_SBITERR(),
+    .AXI_AR_DBITERR(),
+    .AXI_AR_OVERFLOW(),
+    .AXI_AR_UNDERFLOW(),
+    .AXI_AR_PROG_FULL(),
+    .AXI_AR_PROG_EMPTY(),
+    .AXI_R_INJECTSBITERR(),
+    .AXI_R_INJECTDBITERR(),
+    .AXI_R_PROG_FULL_THRESH(),
+    .AXI_R_PROG_EMPTY_THRESH(),
+    .AXI_R_DATA_COUNT(),
+    .AXI_R_WR_DATA_COUNT(),
+    .AXI_R_RD_DATA_COUNT(),
+    .AXI_R_SBITERR(),
+    .AXI_R_DBITERR(),
+    .AXI_R_OVERFLOW(),
+    .AXI_R_UNDERFLOW(),
+    .AXIS_INJECTSBITERR(),
+    .AXI_R_PROG_FULL(),
+    .AXI_R_PROG_EMPTY(),
+    .AXIS_INJECTDBITERR(),
+    .AXIS_PROG_FULL_THRESH(),
+    .AXIS_PROG_EMPTY_THRESH(),
+    .AXIS_DATA_COUNT(),
+    .AXIS_WR_DATA_COUNT(),
+    .AXIS_RD_DATA_COUNT(),
+    .AXIS_SBITERR(),
+    .AXIS_DBITERR(),
+    .AXIS_OVERFLOW(),
+    .AXIS_UNDERFLOW(),
+    .AXIS_PROG_FULL(),
+    .AXIS_PROG_EMPTY()
+  );
+
+// synthesis translate_on
+
+endmodule
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.veo b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.veo
new file mode 100644
index 000000000..06d74a77c
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.veo
@@ -0,0 +1,79 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
+*                                                                              *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
+*                                                                              *
+*     (c) Copyright 1995-2013 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+
+/*******************************************************************************
+*     Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3    *
+*                                                                              *
+*     Rev 1. The FIFO Generator is a parameterizable first-in/first-out        *
+*     memory queue generator. Use it to generate resource and performance      *
+*     optimized FIFOs with common or independent read/write clock domains,     *
+*     and optional fixed or programmable full and empty flags and              *
+*     handshaking signals.  Choose from a selection of memory resource         *
+*     types for implementation.  Optional Hamming code based error             *
+*     detection and correction as well as error injection capability for       *
+*     system test help to insure data integrity.  FIFO width and depth are     *
+*     parameterizable, and for native interface FIFOs, asymmetric read and     *
+*     write port widths are also supported.                                    *
+*******************************************************************************/
+
+// Interfaces:
+//    AXI4Stream_MASTER_M_AXIS
+//    AXI4Stream_SLAVE_S_AXIS
+//    AXI4_MASTER_M_AXI
+//    AXI4_SLAVE_S_AXI
+//    AXI4Lite_MASTER_M_AXI
+//    AXI4Lite_SLAVE_S_AXI
+//    master_aclk
+//    slave_aclk
+//    slave_aresetn
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_short_2clk your_instance_name (
+  .rst(rst), // input rst
+  .wr_clk(wr_clk), // input wr_clk
+  .rd_clk(rd_clk), // input rd_clk
+  .din(din), // input [71 : 0] din
+  .wr_en(wr_en), // input wr_en
+  .rd_en(rd_en), // input rd_en
+  .dout(dout), // output [71 : 0] dout
+  .full(full), // output full
+  .empty(empty), // output empty
+  .rd_data_count(rd_data_count), // output [5 : 0] rd_data_count
+  .wr_data_count(wr_data_count) // output [5 : 0] wr_data_count
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_short_2clk.v when simulating
+// the core, fifo_short_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xco b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xco
new file mode 100644
index 000000000..0f256d496
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xco
@@ -0,0 +1,213 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.4
+# Date: Fri Mar  8 18:15:07 2013
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:fifo_generator:9.3
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fgg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
+# END Select
+# BEGIN Parameters
+CSET add_ngc_constraint_axi=false
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET aruser_width=1
+CSET awuser_width=1
+CSET axi_address_width=32
+CSET axi_data_width=64
+CSET axi_type=AXI4_Stream
+CSET axis_type=FIFO
+CSET buser_width=1
+CSET clock_enable_type=Slave_Interface_Clock_Enable
+CSET clock_type_axi=Common_Clock
+CSET component_name=fifo_short_2clk
+CSET data_count=false
+CSET data_count_width=5
+CSET disable_timing_violations=false
+CSET disable_timing_violations_axi=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_assert_value_axis=1022
+CSET empty_threshold_assert_value_rach=1022
+CSET empty_threshold_assert_value_rdch=1022
+CSET empty_threshold_assert_value_wach=1022
+CSET empty_threshold_assert_value_wdch=1022
+CSET empty_threshold_assert_value_wrch=1022
+CSET empty_threshold_negate_value=5
+CSET enable_aruser=false
+CSET enable_awuser=false
+CSET enable_buser=false
+CSET enable_common_overflow=false
+CSET enable_common_underflow=false
+CSET enable_data_counts_axis=false
+CSET enable_data_counts_rach=false
+CSET enable_data_counts_rdch=false
+CSET enable_data_counts_wach=false
+CSET enable_data_counts_wdch=false
+CSET enable_data_counts_wrch=false
+CSET enable_ecc=false
+CSET enable_ecc_axis=false
+CSET enable_ecc_rach=false
+CSET enable_ecc_rdch=false
+CSET enable_ecc_wach=false
+CSET enable_ecc_wdch=false
+CSET enable_ecc_wrch=false
+CSET enable_read_channel=false
+CSET enable_read_pointer_increment_by2=false
+CSET enable_reset_synchronization=true
+CSET enable_ruser=false
+CSET enable_tdata=false
+CSET enable_tdest=false
+CSET enable_tid=false
+CSET enable_tkeep=false
+CSET enable_tlast=false
+CSET enable_tready=true
+CSET enable_tstrobe=false
+CSET enable_tuser=false
+CSET enable_write_channel=false
+CSET enable_wuser=false
+CSET fifo_application_type_axis=Data_FIFO
+CSET fifo_application_type_rach=Data_FIFO
+CSET fifo_application_type_rdch=Data_FIFO
+CSET fifo_application_type_wach=Data_FIFO
+CSET fifo_application_type_wdch=Data_FIFO
+CSET fifo_application_type_wrch=Data_FIFO
+CSET fifo_implementation=Independent_Clocks_Distributed_RAM
+CSET fifo_implementation_axis=Common_Clock_Block_RAM
+CSET fifo_implementation_rach=Common_Clock_Block_RAM
+CSET fifo_implementation_rdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wach=Common_Clock_Block_RAM
+CSET fifo_implementation_wdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wrch=Common_Clock_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=31
+CSET full_threshold_assert_value_axis=1023
+CSET full_threshold_assert_value_rach=1023
+CSET full_threshold_assert_value_rdch=1023
+CSET full_threshold_assert_value_wach=1023
+CSET full_threshold_assert_value_wdch=1023
+CSET full_threshold_assert_value_wrch=1023
+CSET full_threshold_negate_value=30
+CSET id_width=4
+CSET inject_dbit_error=false
+CSET inject_dbit_error_axis=false
+CSET inject_dbit_error_rach=false
+CSET inject_dbit_error_rdch=false
+CSET inject_dbit_error_wach=false
+CSET inject_dbit_error_wdch=false
+CSET inject_dbit_error_wrch=false
+CSET inject_sbit_error=false
+CSET inject_sbit_error_axis=false
+CSET inject_sbit_error_rach=false
+CSET inject_sbit_error_rdch=false
+CSET inject_sbit_error_wach=false
+CSET inject_sbit_error_wdch=false
+CSET inject_sbit_error_wrch=false
+CSET input_data_width=72
+CSET input_depth=32
+CSET input_depth_axis=1024
+CSET input_depth_rach=16
+CSET input_depth_rdch=1024
+CSET input_depth_wach=16
+CSET input_depth_wdch=1024
+CSET input_depth_wrch=16
+CSET interface_type=Native
+CSET output_data_width=72
+CSET output_depth=32
+CSET overflow_flag=false
+CSET overflow_flag_axi=false
+CSET overflow_sense=Active_High
+CSET overflow_sense_axi=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET programmable_full_type_axis=No_Programmable_Full_Threshold
+CSET programmable_full_type_rach=No_Programmable_Full_Threshold
+CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
+CSET programmable_full_type_wach=No_Programmable_Full_Threshold
+CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
+CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
+CSET rach_type=FIFO
+CSET rdch_type=FIFO
+CSET read_clock_frequency=1
+CSET read_data_count=true
+CSET read_data_count_width=6
+CSET register_slice_mode_axis=Fully_Registered
+CSET register_slice_mode_rach=Fully_Registered
+CSET register_slice_mode_rdch=Fully_Registered
+CSET register_slice_mode_wach=Fully_Registered
+CSET register_slice_mode_wdch=Fully_Registered
+CSET register_slice_mode_wrch=Fully_Registered
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET ruser_width=1
+CSET synchronization_stages=2
+CSET synchronization_stages_axi=2
+CSET tdata_width=64
+CSET tdest_width=4
+CSET tid_width=8
+CSET tkeep_width=4
+CSET tstrb_width=4
+CSET tuser_width=4
+CSET underflow_flag=false
+CSET underflow_flag_axi=false
+CSET underflow_sense=Active_High
+CSET underflow_sense_axi=Active_High
+CSET use_clock_enable=false
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=true
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET wach_type=FIFO
+CSET wdch_type=FIFO
+CSET wrch_type=FIFO
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=true
+CSET write_data_count_width=6
+CSET wuser_width=1
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-19T12:39:56Z
+# END Extra information
+GENERATE
+# CRC: 8cc2c19d
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise
new file mode 100644
index 000000000..1ca7d35ee
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="fifo_short_2clk.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="fifo_short_2clk.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_short_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_short_2clk.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_short_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_short_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T10:16:13" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="164C88B0B983B3E77A86A61EAC6C8697" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt
new file mode 100644
index 000000000..7853ebde8
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt
@@ -0,0 +1,236 @@
+CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
+
+                    Release Date: December 18, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------  
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
+solution. For the latest core updates, see the product page at:
+ 
+   http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+    The following device families are supported by the core for this release.
+    
+    
+    All 7 Series devices
+    Zynq-7000 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Spartan-3 devices
+    All Virtex-4 devices
+  
+  
+  2.2 Vivado 
+  
+    All 7 Series devices
+    Zynq-7000 devices
+
+................................................................................
+
+
+3. NEW FEATURE HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+  
+  3.2 Vivado
+  
+    - 2012.4 software support
+    - IP level constraint for Built-in FIFO reset synchronizer
+
+................................................................................
+
+
+4. RESOLVED ISSUES 
+
+
+  4.1 ISE 
+
+    - N/A
+
+
+  4.2 Vivado 
+
+    - N/A
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+
+  5.1 ISE 
+  
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+  
+    1. Importing an XCO file alters the XCO configurations
+  
+       Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+       into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
+       page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+    
+       CR 467240
+       AR 31379
+  
+    2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
+  
+       Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
+       correct behavior of the FIFO status flags cannot be guaranteed after the first write.
+    
+       Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
+       For more information and additional workaround see Answer Record 41099.
+  
+  5.2 Vivado 
+
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+     
+    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen 
+       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
+      
+       CR 665836
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes User Guide
+located at 
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.  
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+................................................................................
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/18/2012  Xilinx, Inc.  9.3 Rev 1    ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
+10/16/2012  Xilinx, Inc.  9.3          ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
+07/25/2012  Xilinx, Inc.  9.2          ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
+04/24/2012  Xilinx, Inc.  9.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+                                       AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
+01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
+10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
+06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
+03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
+10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
+09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
+07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
+06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
+08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
+05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
+04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
+================================================================================
+
+................................................................................
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html
new file mode 100644
index 000000000..fefce62a3
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html
@@ -0,0 +1,247 @@
+<HTML>
+<HEAD>
+<TITLE>fifo_generator_v9_3_vinfo</TITLE>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
+</HEAD>
+<BODY>
+<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
+CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
+
+                    Release Date: December 18, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------  
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+   <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
+
+For system requirements:
+
+   <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
+solution. For the latest core updates, see the product page at:
+ 
+   <A HREF="http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm">www.xilinx.com/products/ipcenter/FIFO_Generator.htm</A>
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+    The following device families are supported by the core for this release.
+    
+    
+    All 7 Series devices
+    Zynq-7000 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Spartan-3 devices
+    All Virtex-4 devices
+  
+  
+  2.2 Vivado 
+  
+    All 7 Series devices
+    Zynq-7000 devices
+
+................................................................................
+
+
+3. NEW FEATURE HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+  
+  3.2 Vivado
+  
+    - 2012.4 software support
+    - IP level constraint for Built-in FIFO reset synchronizer
+
+................................................................................
+
+
+4. RESOLVED ISSUES 
+
+
+  4.1 ISE 
+
+    - N/A
+
+
+  4.2 Vivado 
+
+    - N/A
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+
+  5.1 ISE 
+  
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+  
+    1. Importing an XCO file alters the XCO configurations
+  
+       Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+       into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
+       page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+    
+       CR 467240
+       AR 31379
+  
+    2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
+  
+       Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
+       correct behavior of the FIFO status flags cannot be guaranteed after the first write.
+    
+       Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
+       For more information and additional workaround see Answer Record 41099.
+  
+  5.2 Vivado 
+
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+     
+    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen 
+       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
+      
+       CR 665836
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes User Guide
+located at 
+
+   <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A> 
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
+Questions are routed to a team with expertise using this product.  
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+................................................................................
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/18/2012  Xilinx, Inc.  9.3 Rev 1    ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
+10/16/2012  Xilinx, Inc.  9.3          ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
+07/25/2012  Xilinx, Inc.  9.2          ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
+04/24/2012  Xilinx, Inc.  9.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+                                       AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
+01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
+10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
+06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
+03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
+10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
+09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
+07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
+06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
+08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
+05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
+04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
+================================================================================
+
+................................................................................
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+</FONT>
+</PRE>
+</BODY>
+</HTML>
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf
new file mode 100644
index 000000000..5ec45fbcb
Binary files /dev/null and b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf differ
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf
new file mode 100755
index 000000000..62e5058ab
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf
@@ -0,0 +1,56 @@
+################################################################################
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+  NET "RD_CLK"  TNM_NET     = "RD_CLK";
+  NET "WR_CLK"  TNM_NET     = "WR_CLK";
+  TIMESPEC "TS_RD_CLK"      = PERIOD "RD_CLK" 50 MHZ;
+  TIMESPEC "TS_WR_CLK"      = PERIOD "WR_CLK" 50 MHZ;
+################################################################################
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd
new file mode 100755
index 000000000..9e38bcb7c
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd
@@ -0,0 +1,145 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core - core top file for implementation
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_short_2clk_exdes.vhd
+--
+-- Description:
+--   This is the FIFO core wrapper with BUFG instances for clock connections.
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+entity fifo_short_2clk_exdes is
+   PORT (
+           WR_CLK                    : IN  std_logic;
+     	   RD_CLK                    : IN  std_logic;
+     	   WR_DATA_COUNT             : OUT std_logic_vector(6-1 DOWNTO 0);
+           RD_DATA_COUNT             : OUT std_logic_vector(6-1 DOWNTO 0);
+           RST                       : IN  std_logic;
+           WR_EN 		     : IN  std_logic;
+           RD_EN                     : IN  std_logic;
+           DIN                       : IN  std_logic_vector(72-1 DOWNTO 0);
+           DOUT                      : OUT std_logic_vector(72-1 DOWNTO 0);
+           FULL                      : OUT std_logic;
+           EMPTY                     : OUT std_logic);
+
+end fifo_short_2clk_exdes;
+
+
+
+architecture xilinx of fifo_short_2clk_exdes is
+
+  signal wr_clk_i : std_logic;
+  signal rd_clk_i : std_logic;
+
+
+
+  component fifo_short_2clk is
+   PORT (
+           WR_CLK                    : IN  std_logic;
+     	   RD_CLK                    : IN  std_logic;
+     	   WR_DATA_COUNT             : OUT std_logic_vector(6-1 DOWNTO 0);
+           RD_DATA_COUNT             : OUT std_logic_vector(6-1 DOWNTO 0);
+           RST                       : IN  std_logic;
+           WR_EN 		     : IN  std_logic;
+           RD_EN                     : IN  std_logic;
+           DIN                       : IN  std_logic_vector(72-1 DOWNTO 0);
+           DOUT                      : OUT std_logic_vector(72-1 DOWNTO 0);
+           FULL                      : OUT std_logic;
+           EMPTY                     : OUT std_logic);
+
+  end component;
+
+
+begin
+
+  wr_clk_buf: bufg
+    PORT map(
+      i => WR_CLK,
+      o => wr_clk_i
+      );
+
+  rd_clk_buf: bufg
+    PORT map(
+      i => RD_CLK,
+      o => rd_clk_i
+      );
+
+
+  exdes_inst : fifo_short_2clk 
+    PORT MAP (
+           WR_CLK                    => wr_clk_i,
+           RD_CLK                    => rd_clk_i,
+           WR_DATA_COUNT             => wr_data_count,
+           RD_DATA_COUNT             => rd_data_count,
+           RST                       => rst,
+           WR_EN 		     => wr_en,
+           RD_EN                     => rd_en,
+           DIN                       => din,
+           DOUT                      => dout,
+           FULL                      => full,
+           EMPTY                     => empty);
+
+end xilinx;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/fifo_generator_v9_3_readme.txt
new file mode 100644
index 000000000..7853ebde8
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/fifo_generator_v9_3_readme.txt
@@ -0,0 +1,236 @@
+CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
+
+                    Release Date: December 18, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------  
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
+solution. For the latest core updates, see the product page at:
+ 
+   http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+    The following device families are supported by the core for this release.
+    
+    
+    All 7 Series devices
+    Zynq-7000 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Spartan-3 devices
+    All Virtex-4 devices
+  
+  
+  2.2 Vivado 
+  
+    All 7 Series devices
+    Zynq-7000 devices
+
+................................................................................
+
+
+3. NEW FEATURE HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+  
+  3.2 Vivado
+  
+    - 2012.4 software support
+    - IP level constraint for Built-in FIFO reset synchronizer
+
+................................................................................
+
+
+4. RESOLVED ISSUES 
+
+
+  4.1 ISE 
+
+    - N/A
+
+
+  4.2 Vivado 
+
+    - N/A
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+
+  5.1 ISE 
+  
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+  
+    1. Importing an XCO file alters the XCO configurations
+  
+       Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+       into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
+       page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+    
+       CR 467240
+       AR 31379
+  
+    2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
+  
+       Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
+       correct behavior of the FIFO status flags cannot be guaranteed after the first write.
+    
+       Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
+       For more information and additional workaround see Answer Record 41099.
+  
+  5.2 Vivado 
+
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+     
+    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen 
+       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
+      
+       CR 665836
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes User Guide
+located at 
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.  
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+................................................................................
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/18/2012  Xilinx, Inc.  9.3 Rev 1    ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
+10/16/2012  Xilinx, Inc.  9.3          ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
+07/25/2012  Xilinx, Inc.  9.2          ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
+04/24/2012  Xilinx, Inc.  9.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+                                       AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
+01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
+10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
+06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
+03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
+10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
+09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
+07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
+06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
+08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
+05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
+04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
+================================================================================
+
+................................................................................
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.bat
new file mode 100755
index 000000000..f846d4485
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.bat
@@ -0,0 +1,88 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+
+rem Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+rem Synthesize the VHDL Wrapper Files
+
+#Synthesize the Wrapper Files
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+copy fifo_short_2clk_exdes.ngc .\results\
+
+
+rem Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+copy ..\..\fifo_short_2clk.ngc results\
+
+
+rem  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\fifo_short_2clk_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+
+ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes
+
+echo 'Running map'
+map fifo_short_2clk_exdes -o mapped.ncd
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.sh
new file mode 100755
index 000000000..e2453c4a1
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.sh
@@ -0,0 +1,87 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+#Synthesize the Wrapper Files
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+cp fifo_short_2clk_exdes.ngc ./results/
+
+
+# Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+cp ../../fifo_short_2clk.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/fifo_short_2clk_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+
+ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes
+
+echo 'Running map'
+map fifo_short_2clk_exdes -o mapped.ncd
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
+
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.bat
new file mode 100755
index 000000000..4fe498bff
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.bat
@@ -0,0 +1,87 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+
+rem Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+rem Synthesize the VHDL Wrapper Files
+
+#Synthesize the Wrapper Files
+
+echo 'Synthesizing example design with Synplify'
+synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
+
+
+rem Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+copy ..\..\fifo_short_2clk.ngc results\
+
+
+rem  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\fifo_short_2clk_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+
+ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes
+
+echo 'Running map'
+map fifo_short_2clk_exdes -o mapped.ncd
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.sh
new file mode 100755
index 000000000..882036474
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.sh
@@ -0,0 +1,86 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+#Synthesize the Wrapper Files
+
+echo 'Synthesizing example design with Synplify'
+synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
+
+
+# Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+cp ../../fifo_short_2clk.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/fifo_short_2clk_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+
+ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes
+
+echo 'Running map'
+map fifo_short_2clk_exdes -o mapped.ncd
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
+
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.bat
new file mode 100755
index 000000000..49053fd63
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.bat
@@ -0,0 +1,54 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+
+rem -----------------------------------------------------------------------------
+rem  Script to synthesize and implement the Coregen FIFO Generator
+rem -----------------------------------------------------------------------------
+rmdir /S /Q results
+mkdir results
+cd results
+copy ..\..\..\fifo_short_2clk.ngc .
+planAhead -mode batch -source ..\planAhead_ise.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.sh
new file mode 100755
index 000000000..42916c2bc
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.sh
@@ -0,0 +1,55 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+#-----------------------------------------------------------------------------
+#  Script to synthesize and implement the Coregen FIFO Generator
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+cp ../../../fifo_short_2clk.ngc .
+planAhead -mode batch -source ../planAhead_ise.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.tcl
new file mode 100755
index 000000000..9f39b3e13
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.tcl
@@ -0,0 +1,67 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+set device xc6slx75fgg484-3
+set projName fifo_short_2clk
+set design fifo_short_2clk
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module fifo_short_2clk_exdes
+add_files -norecurse {../../example_design/fifo_short_2clk_exdes.vhd}
+add_files -norecurse {./fifo_short_2clk.ngc}
+import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/fifo_short_2clk_exdes.xdc}
+set_property top fifo_short_2clk_exdes [get_property srcset [current_run]]
+synth_design
+opt_design 
+place_design 
+route_design 
+write_sdf -rename_top_module fifo_short_2clk_exdes -file routed.sdf 
+write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module fifo_short_2clk_exdes routed.v
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.prj b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.prj
new file mode 100755
index 000000000..f16af4308
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.prj
@@ -0,0 +1 @@
+work ../example_design/fifo_short_2clk_exdes.vhd
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.scr b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.scr
new file mode 100755
index 000000000..b5a9091c7
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.scr
@@ -0,0 +1,13 @@
+run
+-ifmt VHDL
+-ent fifo_short_2clk_exdes 
+-p xc6slx75-fgg484-3
+-ifn xst.prj
+-write_timing_constraints No
+-iobuf YES
+-max_fanout 100
+-ofn fifo_short_2clk_exdes 
+-ofmt NGC
+-bus_delimiter ()
+-hierarchy_separator /
+-case Maintain
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd
new file mode 100755
index 000000000..bc7a1b525
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd
@@ -0,0 +1,123 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_short_2clk_dgen.vhd
+--
+-- Description:
+--   Used for write interface stimulus generation
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE IEEE.std_logic_arith.all;
+USE IEEE.std_logic_misc.all;
+
+LIBRARY work;
+USE work.fifo_short_2clk_pkg.ALL;
+
+ENTITY fifo_short_2clk_dgen IS
+  GENERIC (
+	    C_DIN_WIDTH   : INTEGER := 32;
+	    C_DOUT_WIDTH  : INTEGER := 32;
+	    C_CH_TYPE     : INTEGER := 0;
+	    TB_SEED       : INTEGER := 2
+	 );
+  PORT (
+        RESET     : IN STD_LOGIC;
+        WR_CLK    : IN STD_LOGIC;
+        PRC_WR_EN : IN STD_LOGIC;
+        FULL      : IN STD_LOGIC;  
+        WR_EN     : OUT STD_LOGIC;      
+        WR_DATA   : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
+       );
+END ENTITY;
+
+
+ARCHITECTURE fg_dg_arch OF fifo_short_2clk_dgen IS
+ 
+  CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
+  CONSTANT LOOP_COUNT   : INTEGER := divroundup(C_DATA_WIDTH,8);
+  
+  SIGNAL pr_w_en        : STD_LOGIC := '0';
+  SIGNAL rand_num       : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
+  SIGNAL wr_data_i      : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
+ BEGIN
+  
+   WR_EN   <= PRC_WR_EN ;
+   WR_DATA <= wr_data_i AFTER 100 ns;
+
+  ----------------------------------------------
+  -- Generation of DATA
+  ----------------------------------------------
+  gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
+    rd_gen_inst1:fifo_short_2clk_rng
+    GENERIC MAP(
+    	       WIDTH => 8,
+               SEED  => TB_SEED+N
+               )
+    PORT MAP(
+              CLK        => WR_CLK,
+	      RESET      => RESET,
+              RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
+              ENABLE     => pr_w_en
+            );
+  END GENERATE; 
+
+     pr_w_en <= PRC_WR_EN AND NOT FULL;
+     wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
+
+
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd
new file mode 100755
index 000000000..b0465d84f
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd
@@ -0,0 +1,150 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_short_2clk_dverif.vhd
+--
+-- Description:
+--   Used for FIFO read interface stimulus generation and data checking
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE IEEE.std_logic_arith.all;
+USE IEEE.std_logic_misc.all;
+
+LIBRARY work;
+USE work.fifo_short_2clk_pkg.ALL;
+
+ENTITY fifo_short_2clk_dverif IS
+  GENERIC(
+   C_DIN_WIDTH        : INTEGER := 0;
+   C_DOUT_WIDTH       : INTEGER := 0;
+   C_USE_EMBEDDED_REG : INTEGER := 0;
+   C_CH_TYPE          : INTEGER := 0;
+   TB_SEED            : INTEGER := 2
+  );
+  PORT(
+       RESET          : IN STD_LOGIC;
+       RD_CLK         : IN STD_LOGIC;
+       PRC_RD_EN      : IN STD_LOGIC;
+       EMPTY          : IN STD_LOGIC;
+       DATA_OUT       : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
+       RD_EN          : OUT STD_LOGIC;
+       DOUT_CHK       : OUT STD_LOGIC
+      );
+END ENTITY;
+
+
+ARCHITECTURE fg_dv_arch OF fifo_short_2clk_dverif IS
+ 
+ CONSTANT C_DATA_WIDTH    : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
+ CONSTANT EXTRA_WIDTH     : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
+ CONSTANT LOOP_COUNT      : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
+
+ SIGNAL expected_dout     : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL data_chk          : STD_LOGIC := '1';
+ SIGNAL rand_num          : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
+ SIGNAL rd_en_i           : STD_LOGIC := '0';
+ SIGNAL pr_r_en           : STD_LOGIC := '0';
+ SIGNAL rd_en_d1          : STD_LOGIC := '1';
+BEGIN
+
+ 
+  DOUT_CHK <= data_chk;
+  RD_EN    <= rd_en_i;
+  rd_en_i  <= PRC_RD_EN;
+  rd_en_d1 <= '1';
+  
+ 
+  data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE 
+  -------------------------------------------------------
+  -- Expected data generation and checking for data_fifo
+  -------------------------------------------------------
+   
+      pr_r_en       <= rd_en_i AND NOT EMPTY AND rd_en_d1;
+      expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
+
+    gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
+      rd_gen_inst2:fifo_short_2clk_rng
+      GENERIC MAP(
+      	        WIDTH => 8,
+                SEED  => TB_SEED+N
+                 )
+      PORT MAP(
+                CLK        => RD_CLK,
+	        RESET      => RESET,
+                RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
+                ENABLE     => pr_r_en 	    
+              );
+    END GENERATE;    
+    
+      PROCESS (RD_CLK,RESET)
+      BEGIN
+        IF(RESET = '1') THEN
+          data_chk <= '0';
+        ELSIF (RD_CLK'event AND RD_CLK='1') THEN
+          IF(EMPTY = '0') THEN
+            IF(DATA_OUT = expected_dout) THEN
+              data_chk <= '0';
+            ELSE
+              data_chk <= '1';
+            END IF;
+          END IF;
+        END IF;
+      END PROCESS;
+  END GENERATE data_fifo_chk;
+
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd
new file mode 100755
index 000000000..5d6506398
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd
@@ -0,0 +1,541 @@
+
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_short_2clk_pctrl.vhd
+--
+-- Description:
+--   Used for protocol control on write and read interface stimulus and status generation
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE IEEE.std_logic_arith.all;
+USE IEEE.std_logic_misc.all;
+
+LIBRARY work;
+USE work.fifo_short_2clk_pkg.ALL;
+
+ENTITY fifo_short_2clk_pctrl IS
+  GENERIC(
+   AXI_CHANNEL         : STRING  :="NONE";
+   C_APPLICATION_TYPE  : INTEGER := 0;
+   C_DIN_WIDTH         : INTEGER := 0;
+   C_DOUT_WIDTH        : INTEGER := 0;
+   C_WR_PNTR_WIDTH     : INTEGER := 0;
+   C_RD_PNTR_WIDTH     : INTEGER := 0;
+   C_CH_TYPE           : INTEGER := 0;
+   FREEZEON_ERROR      : INTEGER := 0;
+   TB_STOP_CNT         : INTEGER := 2;
+   TB_SEED             : INTEGER := 2
+  );
+  PORT(
+       RESET_WR        : IN STD_LOGIC;
+       RESET_RD        : IN STD_LOGIC;
+       WR_CLK          : IN STD_LOGIC;
+       RD_CLK          : IN STD_LOGIC;
+       FULL            : IN STD_LOGIC;
+       EMPTY           : IN STD_LOGIC;
+       ALMOST_FULL     : IN STD_LOGIC;
+       ALMOST_EMPTY    : IN STD_LOGIC;
+       DATA_IN         : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
+       DATA_OUT        : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
+       DOUT_CHK        : IN STD_LOGIC;
+       PRC_WR_EN       : OUT STD_LOGIC;
+       PRC_RD_EN       : OUT STD_LOGIC;
+       RESET_EN        : OUT STD_LOGIC;
+       SIM_DONE        : OUT STD_LOGIC;
+       STATUS          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+      );
+END ENTITY;
+
+
+ARCHITECTURE fg_pc_arch OF fifo_short_2clk_pctrl IS
+ 
+ CONSTANT C_DATA_WIDTH   : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
+ CONSTANT LOOP_COUNT     : INTEGER := divroundup(C_DATA_WIDTH,8);
+ CONSTANT D_WIDTH_DIFF   :   INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
+
+ SIGNAL data_chk_i       : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
+ SIGNAL full_chk_i       : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
+ SIGNAL empty_chk_i      : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
+ SIGNAL status_i         : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
+ SIGNAL status_d1_i      : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
+ SIGNAL wr_en_gen        : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
+ SIGNAL rd_en_gen        : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
+ SIGNAL wr_cntr          : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0)   := (OTHERS => '0');
+ SIGNAL full_as_timeout  : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0)   := (OTHERS => '0');
+ SIGNAL full_ds_timeout  : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
+ SIGNAL rd_cntr          : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0)   := (OTHERS => '0'); 
+ SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0)  := (OTHERS => '0'); 
+ SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0'); 
+ SIGNAL wr_en_i          : STD_LOGIC := '0';
+ SIGNAL rd_en_i          : STD_LOGIC := '0';
+ SIGNAL state            : STD_LOGIC := '0';
+ SIGNAL wr_control       : STD_LOGIC := '0';
+ SIGNAL rd_control       : STD_LOGIC := '0';
+ SIGNAL stop_on_err      : STD_LOGIC := '0';
+ SIGNAL sim_stop_cntr    : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
+ SIGNAL sim_done_i       : STD_LOGIC := '0';
+ SIGNAL rdw_gt_wrw       : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
+ SIGNAL wrw_gt_rdw       : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
+ SIGNAL rd_activ_cont    : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
+ SIGNAL prc_we_i         : STD_LOGIC := '0';
+ SIGNAL prc_re_i         : STD_LOGIC := '0';
+ SIGNAL reset_en_i       : STD_LOGIC := '0';
+ SIGNAL sim_done_d1      : STD_LOGIC := '0';
+ SIGNAL sim_done_wr1     : STD_LOGIC := '0';
+ SIGNAL sim_done_wr2     : STD_LOGIC := '0'; 
+ SIGNAL empty_d1         : STD_LOGIC := '0';
+ SIGNAL empty_wr_dom1    : STD_LOGIC := '0';
+ SIGNAL state_d1         : STD_LOGIC := '0';
+ SIGNAL state_rd_dom1    : STD_LOGIC := '0';
+ SIGNAL rd_en_d1         : STD_LOGIC := '0';
+ SIGNAL rd_en_wr1        : STD_LOGIC := '0';
+ SIGNAL wr_en_d1         : STD_LOGIC := '0';
+ SIGNAL wr_en_rd1        : STD_LOGIC := '0';
+ SIGNAL full_chk_d1      : STD_LOGIC := '0';
+ SIGNAL full_chk_rd1     : STD_LOGIC := '0';
+ SIGNAL empty_wr_dom2    : STD_LOGIC := '0';
+
+ SIGNAL state_rd_dom2    : STD_LOGIC := '0';
+ SIGNAL state_rd_dom3    : STD_LOGIC := '0';
+ SIGNAL rd_en_wr2        : STD_LOGIC := '0';
+ SIGNAL wr_en_rd2        : STD_LOGIC := '0';
+ SIGNAL full_chk_rd2     : STD_LOGIC := '0';
+ SIGNAL reset_en_d1      : STD_LOGIC := '0';
+ SIGNAL reset_en_rd1     : STD_LOGIC := '0';
+ SIGNAL reset_en_rd2     : STD_LOGIC := '0';
+
+ SIGNAL data_chk_wr_d1   : STD_LOGIC := '0';
+ SIGNAL data_chk_rd1     : STD_LOGIC := '0';
+ SIGNAL data_chk_rd2     : STD_LOGIC := '0';
+ SIGNAL post_rst_dly_wr  : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
+ SIGNAL post_rst_dly_rd  : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
+BEGIN
+ status_i  <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
+ STATUS    <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
+
+ prc_we_i <= wr_en_i  WHEN sim_done_wr2 = '0' ELSE '0';
+ prc_re_i <= rd_en_i  WHEN sim_done_i   = '0' ELSE '0';
+
+ SIM_DONE   <= sim_done_i;
+ rdw_gt_wrw <= (OTHERS => '1');
+ wrw_gt_rdw <= (OTHERS => '1');
+
+ PROCESS(RD_CLK)
+ BEGIN
+   IF (RD_CLK'event AND RD_CLK='1') THEN
+     IF(prc_re_i = '1') THEN
+       rd_activ_cont <= rd_activ_cont + "1";
+     END IF;
+   END IF;
+ END PROCESS;
+
+
+ PROCESS(sim_done_i)
+ BEGIN
+    assert sim_done_i = '0'
+    report "Simulation Complete for:" & AXI_CHANNEL
+    severity note;
+ END PROCESS;
+
+-----------------------------------------------------
+-- SIM_DONE SIGNAL GENERATION
+-----------------------------------------------------
+PROCESS (RD_CLK,RESET_RD)
+BEGIN
+    IF(RESET_RD = '1') THEN
+      --sim_done_i <= '0';
+    ELSIF(RD_CLK'event AND RD_CLK='1') THEN
+      IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
+     	sim_done_i <= '1';
+      END IF;
+    END IF;
+END PROCESS;
+
+ -- TB Timeout/Stop
+ fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
+   PROCESS (RD_CLK)
+   BEGIN
+       IF (RD_CLK'event AND RD_CLK='1') THEN
+         IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
+           sim_stop_cntr <= sim_stop_cntr - "1";
+         END IF;
+       END IF;
+   END PROCESS;
+ END GENERATE fifo_tb_stop_run;
+
+
+  -- Stop when error found
+  PROCESS (RD_CLK)
+  BEGIN
+    IF (RD_CLK'event AND RD_CLK='1') THEN
+      IF(sim_done_i = '0') THEN
+        status_d1_i <= status_i OR status_d1_i;
+      END IF;
+      IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
+        stop_on_err <= '1';
+      END IF;
+    END IF;
+  END PROCESS;
+  -----------------------------------------------------
+
+  -----------------------------------------------------
+  -- CHECKS FOR FIFO
+  -----------------------------------------------------
+
+
+  PROCESS(RD_CLK,RESET_RD)
+  BEGIN
+    IF(RESET_RD = '1') THEN
+      post_rst_dly_rd <= (OTHERS => '1');
+    ELSIF (RD_CLK'event AND RD_CLK='1') THEN
+      post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
+    END IF;
+  END PROCESS;
+  
+  PROCESS(WR_CLK,RESET_WR)
+  BEGIN
+    IF(RESET_WR = '1') THEN
+      post_rst_dly_wr <= (OTHERS => '1');
+    ELSIF (WR_CLK'event AND WR_CLK='1') THEN
+      post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
+    END IF;
+  END PROCESS;
+
+
+  -- FULL de-assert Counter
+  PROCESS(WR_CLK,RESET_WR) 
+  BEGIN
+    IF(RESET_WR = '1') THEN
+      full_ds_timeout <= (OTHERS => '0');
+    ELSIF(WR_CLK'event AND WR_CLK='1') THEN
+      IF(state = '1') THEN
+        IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
+          full_ds_timeout <= full_ds_timeout + '1';
+        END IF;
+      ELSE
+  	full_ds_timeout <= (OTHERS => '0');
+      END IF;
+    END IF;
+  END PROCESS;
+   
+ 
+ -- EMPTY deassert counter
+  PROCESS(RD_CLK,RESET_RD) 
+  BEGIN
+    IF(RESET_RD = '1') THEN
+      empty_ds_timeout <= (OTHERS => '0');
+    ELSIF(RD_CLK'event AND RD_CLK='1') THEN
+      IF(state = '0') THEN
+        IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
+          empty_ds_timeout <= empty_ds_timeout + '1';
+        END IF;
+      ELSE
+  	empty_ds_timeout <= (OTHERS => '0');
+      END IF;
+    END IF;
+  END PROCESS;
+
+  -- Full check signal generation
+  PROCESS(WR_CLK,RESET_WR) 
+  BEGIN
+    IF(RESET_WR = '1') THEN
+      full_chk_i <= '0';
+    ELSIF(WR_CLK'event AND WR_CLK='1') THEN
+      IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
+        full_chk_i <= '0';
+      ELSE
+        full_chk_i <= AND_REDUCE(full_as_timeout) OR 
+		      AND_REDUCE(full_ds_timeout);
+      END IF;
+    END IF;
+  END PROCESS;
+
+  -- Empty checks
+  PROCESS(RD_CLK,RESET_RD) 
+  BEGIN
+    IF(RESET_RD = '1') THEN
+      empty_chk_i <= '0';
+    ELSIF(RD_CLK'event AND RD_CLK='1') THEN
+      IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
+        empty_chk_i <= '0';
+      ELSE
+        empty_chk_i <= AND_REDUCE(empty_as_timeout) OR 
+		       AND_REDUCE(empty_ds_timeout);
+      END IF;
+    END IF;
+  END PROCESS;
+
+  fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
+    PRC_WR_EN  <= prc_we_i  AFTER 100 ns;
+    PRC_RD_EN  <= prc_re_i  AFTER 50 ns;
+    data_chk_i <= dout_chk;
+  END GENERATE fifo_d_chk;
+  -----------------------------------------------------
+ 
+
+ -----------------------------------------------------
+ -- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
+ -----------------------------------------------------
+   PROCESS(WR_CLK,RESET_WR)
+   BEGIN
+     IF(RESET_WR = '1') THEN
+       empty_wr_dom1  <= '1';
+       empty_wr_dom2  <= '1';
+       state_d1       <= '0';
+       wr_en_d1       <= '0';
+       rd_en_wr1      <= '0';
+       rd_en_wr2      <= '0';
+       full_chk_d1    <= '0';
+       reset_en_d1    <= '0';
+       sim_done_wr1   <= '0';
+       sim_done_wr2   <= '0';
+     ELSIF (WR_CLK'event AND WR_CLK='1') THEN
+       sim_done_wr1   <= sim_done_d1;
+       sim_done_wr2   <= sim_done_wr1;
+       reset_en_d1    <= reset_en_i;
+       state_d1       <= state;
+       empty_wr_dom1  <= empty_d1;
+       empty_wr_dom2  <= empty_wr_dom1;
+       wr_en_d1       <= wr_en_i;
+       rd_en_wr1      <= rd_en_d1;
+       rd_en_wr2      <= rd_en_wr1;
+       full_chk_d1    <= full_chk_i;
+     END IF;
+   END PROCESS;
+
+   PROCESS(RD_CLK,RESET_RD)
+   BEGIN
+     IF(RESET_RD = '1') THEN
+         empty_d1       <= '1';
+         state_rd_dom1  <= '0';
+         state_rd_dom2  <= '0';
+         state_rd_dom3  <= '0';
+         wr_en_rd1      <= '0';
+         wr_en_rd2      <= '0';
+         rd_en_d1       <= '0';
+         full_chk_rd1   <= '0';
+         full_chk_rd2   <= '0';
+         reset_en_rd1   <= '0';
+         reset_en_rd2   <= '0';
+         sim_done_d1    <= '0';
+     ELSIF (RD_CLK'event AND RD_CLK='1') THEN
+         sim_done_d1    <= sim_done_i;
+         reset_en_rd1   <= reset_en_d1;
+         reset_en_rd2   <= reset_en_rd1;
+         empty_d1       <= EMPTY;
+         rd_en_d1       <= rd_en_i;
+         state_rd_dom1  <= state_d1;
+         state_rd_dom2  <= state_rd_dom1;
+         state_rd_dom3  <= state_rd_dom2;
+         wr_en_rd1      <= wr_en_d1;
+         wr_en_rd2      <= wr_en_rd1;
+         full_chk_rd1   <= full_chk_d1;
+         full_chk_rd2   <= full_chk_rd1;
+     END IF;
+   END PROCESS;
+   
+   RESET_EN   <= reset_en_rd2;
+ 
+
+   data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE  
+    -----------------------------------------------------
+    -- WR_EN GENERATION
+    -----------------------------------------------------
+    gen_rand_wr_en:fifo_short_2clk_rng
+    GENERIC MAP(
+    	         WIDTH => 8,
+                 SEED  => TB_SEED+1
+               )
+    PORT MAP(
+              CLK        => WR_CLK,
+              RESET      => RESET_WR,
+              RANDOM_NUM => wr_en_gen,
+              ENABLE     => '1'
+            );
+
+    PROCESS(WR_CLK,RESET_WR)
+    BEGIN
+      IF(RESET_WR = '1') THEN
+        wr_en_i   <=  '0';
+      ELSIF(WR_CLK'event AND WR_CLK='1') THEN
+        IF(state = '1') THEN
+          wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
+        ELSE
+          wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4)); 
+        END IF;
+      END IF;
+    END PROCESS;
+    
+    -----------------------------------------------------
+    -- WR_EN CONTROL
+    -----------------------------------------------------
+    PROCESS(WR_CLK,RESET_WR)
+    BEGIN
+      IF(RESET_WR = '1') THEN
+        wr_cntr         <= (OTHERS => '0');
+	wr_control      <= '1';
+	full_as_timeout <= (OTHERS => '0');
+      ELSIF(WR_CLK'event AND WR_CLK='1') THEN
+	IF(state = '1') THEN
+	  IF(wr_en_i = '1') THEN
+	    wr_cntr <= wr_cntr + "1";
+	  END IF;
+	  full_as_timeout <= (OTHERS => '0');
+	ELSE
+	  wr_cntr <= (OTHERS => '0');
+	  IF(rd_en_wr2 = '0') THEN
+	    IF(wr_en_i = '1') THEN
+  	      full_as_timeout <= full_as_timeout + "1";
+  	    END IF;
+	  ELSE 
+	    full_as_timeout <= (OTHERS => '0');
+	  END IF;
+	END IF;
+
+	wr_control <= NOT wr_cntr(wr_cntr'high);
+
+      END IF;
+    END PROCESS;
+
+    -----------------------------------------------------
+    -- RD_EN GENERATION
+    -----------------------------------------------------
+    gen_rand_rd_en:fifo_short_2clk_rng
+    GENERIC MAP(
+    	         WIDTH => 8,
+                 SEED  => TB_SEED
+               )
+    PORT MAP(
+              CLK        => RD_CLK,
+              RESET      => RESET_RD,
+              RANDOM_NUM => rd_en_gen,
+              ENABLE     => '1'
+            );
+
+    PROCESS(RD_CLK,RESET_RD)
+    BEGIN
+      IF(RESET_RD = '1') THEN
+	rd_en_i    <= '0';
+      ELSIF(RD_CLK'event AND RD_CLK='1') THEN
+        IF(state_rd_dom2 = '0') THEN
+  	    rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
+        ELSE
+          rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
+        END IF;
+      END IF;
+    END PROCESS;
+
+    -----------------------------------------------------
+    -- RD_EN CONTROL
+    -----------------------------------------------------
+    PROCESS(RD_CLK,RESET_RD)
+    BEGIN
+      IF(RESET_RD = '1') THEN
+        rd_cntr    <= (OTHERS => '0');
+	rd_control <= '1';
+	empty_as_timeout <= (OTHERS => '0');
+      ELSIF(RD_CLK'event AND RD_CLK='1') THEN
+	IF(state_rd_dom2 = '0') THEN
+	  IF(rd_en_i = '1') THEN
+	    rd_cntr <= rd_cntr + "1";
+	  END IF;
+	  empty_as_timeout <= (OTHERS => '0');
+	ELSE
+	  rd_cntr <= (OTHERS => '0');
+	  IF(wr_en_rd2 = '0') THEN
+	    IF(rd_en_i = '1') THEN
+  	      empty_as_timeout <= empty_as_timeout + "1";
+  	    END IF;
+	  ELSE 
+	    empty_as_timeout <= (OTHERS => '0');
+	  END IF;
+	END IF;
+	
+	rd_control <= NOT rd_cntr(rd_cntr'high);
+
+      END IF;
+    END PROCESS;
+
+    -----------------------------------------------------
+    -- STIMULUS CONTROL
+    -----------------------------------------------------
+    PROCESS(WR_CLK,RESET_WR)
+    BEGIN
+      IF(RESET_WR = '1') THEN
+        state      <= '0';
+	reset_en_i <= '0';
+      ELSIF(WR_CLK'event AND WR_CLK='1') THEN
+        CASE state IS
+          WHEN '0' => 
+            IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
+              state      <= '1';
+	      reset_en_i <= '0';
+    	    END IF;
+          WHEN '1' => 
+            IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
+              state    	 <= '0';
+	      reset_en_i <= '1';
+    	    END IF;
+          WHEN OTHERS => state <= state;
+	END CASE;
+      END IF;
+    END PROCESS;
+  END GENERATE data_fifo_en;
+
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd
new file mode 100755
index 000000000..4c0e4035b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd
@@ -0,0 +1,350 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_short_2clk_pkg.vhd
+--
+-- Description:
+--   This is the demo testbench package file for FIFO Generator core.
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE ieee.std_logic_arith.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+PACKAGE fifo_short_2clk_pkg IS
+
+ FUNCTION divroundup (
+    data_value : INTEGER;
+    divisor : INTEGER)
+ RETURN INTEGER;
+ ------------------------
+ FUNCTION if_then_else (
+   condition : BOOLEAN;
+   true_case : INTEGER;
+   false_case : INTEGER)
+ RETURN INTEGER;
+ ------------------------
+ FUNCTION if_then_else (
+   condition : BOOLEAN;
+   true_case : STD_LOGIC;
+   false_case : STD_LOGIC)
+ RETURN STD_LOGIC;
+  ------------------------
+ FUNCTION if_then_else (
+   condition : BOOLEAN;
+   true_case : TIME;
+   false_case : TIME)
+ RETURN TIME;
+ ------------------------ 
+ FUNCTION log2roundup (
+      data_value : INTEGER)
+ RETURN INTEGER; 
+ ------------------------ 
+ FUNCTION hexstr_to_std_logic_vec(
+   arg1 : string;
+   size : integer )
+ RETURN std_logic_vector;
+ ------------------------
+ COMPONENT fifo_short_2clk_rng IS
+    GENERIC (WIDTH : integer :=  8;
+             SEED  : integer := 3);
+    PORT (
+      CLK : IN STD_LOGIC;
+      RESET : IN STD_LOGIC;
+      ENABLE : IN STD_LOGIC;
+      RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)         
+     );
+ END COMPONENT; 
+ ------------------------ 
+ 
+ COMPONENT fifo_short_2clk_dgen IS
+  GENERIC (
+	    C_DIN_WIDTH   : INTEGER := 32;
+	    C_DOUT_WIDTH  : INTEGER := 32;
+	    C_CH_TYPE     : INTEGER := 0;
+	    TB_SEED       : INTEGER := 2
+	 );
+  PORT (
+        RESET     : IN STD_LOGIC;
+        WR_CLK    : IN STD_LOGIC;
+        PRC_WR_EN : IN STD_LOGIC;
+        FULL      : IN STD_LOGIC;  
+        WR_EN     : OUT STD_LOGIC;      
+        WR_DATA   : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
+       );
+ END COMPONENT;
+ ------------------------ 
+
+ COMPONENT fifo_short_2clk_dverif IS
+  GENERIC(
+   C_DIN_WIDTH        : INTEGER := 0;
+   C_DOUT_WIDTH       : INTEGER := 0;
+   C_USE_EMBEDDED_REG : INTEGER := 0;
+   C_CH_TYPE          : INTEGER := 0;
+   TB_SEED            : INTEGER := 2
+  );
+  PORT(
+       RESET       : IN STD_LOGIC;
+       RD_CLK      : IN STD_LOGIC;
+       PRC_RD_EN   : IN STD_LOGIC;
+       EMPTY       : IN STD_LOGIC;
+       DATA_OUT    : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
+       RD_EN       : OUT STD_LOGIC;
+       DOUT_CHK    : OUT STD_LOGIC
+      );
+ END COMPONENT; 
+ ------------------------ 
+
+ COMPONENT fifo_short_2clk_pctrl IS
+   GENERIC(
+     AXI_CHANNEL         : STRING  := "NONE";
+     C_APPLICATION_TYPE  : INTEGER := 0;
+     C_DIN_WIDTH         : INTEGER := 0;
+     C_DOUT_WIDTH        : INTEGER := 0;
+     C_WR_PNTR_WIDTH     : INTEGER := 0;
+     C_RD_PNTR_WIDTH     : INTEGER := 0;
+     C_CH_TYPE           : INTEGER := 0;
+     FREEZEON_ERROR      : INTEGER := 0;
+     TB_STOP_CNT         : INTEGER := 2;
+     TB_SEED             : INTEGER := 2
+   );
+   PORT(
+       RESET_WR        : IN STD_LOGIC;
+       RESET_RD        : IN STD_LOGIC;
+       WR_CLK          : IN STD_LOGIC;
+       RD_CLK          : IN STD_LOGIC;
+       FULL            : IN STD_LOGIC;
+       EMPTY           : IN STD_LOGIC;
+       ALMOST_FULL     : IN STD_LOGIC;
+       ALMOST_EMPTY    : IN STD_LOGIC;
+       DATA_IN         : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
+       DATA_OUT        : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
+       DOUT_CHK        : IN STD_LOGIC;
+       PRC_WR_EN       : OUT STD_LOGIC;
+       PRC_RD_EN       : OUT STD_LOGIC;
+       RESET_EN        : OUT STD_LOGIC;
+       SIM_DONE        : OUT STD_LOGIC;
+       STATUS          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+      );
+ END COMPONENT;
+ ------------------------
+ COMPONENT fifo_short_2clk_synth IS
+  GENERIC(
+  	   FREEZEON_ERROR : INTEGER := 0;
+	   TB_STOP_CNT    : INTEGER := 0;
+	   TB_SEED        : INTEGER := 1
+	 );
+  PORT(
+	WR_CLK     :  IN  STD_LOGIC;
+	RD_CLK     :  IN  STD_LOGIC;
+        RESET      :  IN  STD_LOGIC;
+        SIM_DONE   :  OUT STD_LOGIC;
+        STATUS     :  OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+      );
+ END COMPONENT;
+ ------------------------
+ COMPONENT fifo_short_2clk_exdes IS
+   PORT (
+           WR_CLK                    : IN  std_logic;
+     	   RD_CLK                    : IN  std_logic;
+     	   WR_DATA_COUNT             : OUT std_logic_vector(6-1 DOWNTO 0);
+           RD_DATA_COUNT             : OUT std_logic_vector(6-1 DOWNTO 0);
+           RST                       : IN  std_logic;
+           WR_EN 		     : IN  std_logic;
+           RD_EN                     : IN  std_logic;
+           DIN                       : IN  std_logic_vector(72-1 DOWNTO 0);
+           DOUT                      : OUT std_logic_vector(72-1 DOWNTO 0);
+           FULL                      : OUT std_logic;
+           EMPTY                     : OUT std_logic);
+
+ END COMPONENT;
+ ------------------------ 
+
+
+END fifo_short_2clk_pkg;
+
+
+
+PACKAGE BODY fifo_short_2clk_pkg IS
+
+ FUNCTION divroundup (
+    data_value : INTEGER;
+    divisor : INTEGER)
+  RETURN INTEGER IS
+    VARIABLE div                   : INTEGER;
+  BEGIN
+    div   := data_value/divisor;
+    IF ( (data_value MOD divisor) /= 0) THEN
+      div := div+1;
+    END IF;
+    RETURN div;
+  END divroundup;
+  ---------------------------------
+  FUNCTION if_then_else (
+    condition : BOOLEAN;
+    true_case : INTEGER;
+    false_case : INTEGER)
+  RETURN INTEGER IS
+    VARIABLE retval : INTEGER := 0;
+  BEGIN
+    IF condition=false THEN
+      retval:=false_case;
+    ELSE
+      retval:=true_case;
+    END IF;
+    RETURN retval;
+  END if_then_else;
+    ---------------------------------
+  FUNCTION if_then_else (
+    condition : BOOLEAN;
+    true_case : STD_LOGIC;
+    false_case : STD_LOGIC)
+  RETURN STD_LOGIC IS
+    VARIABLE retval : STD_LOGIC := '0';
+  BEGIN
+    IF condition=false THEN
+      retval:=false_case;
+    ELSE
+      retval:=true_case;
+    END IF;
+    RETURN retval;
+  END if_then_else;
+  ---------------------------------
+  FUNCTION if_then_else (
+    condition : BOOLEAN;
+    true_case : TIME;
+    false_case : TIME)
+  RETURN TIME IS
+    VARIABLE retval : TIME := 0 ps;
+  BEGIN
+    IF condition=false THEN
+      retval:=false_case;
+    ELSE
+      retval:=true_case;
+    END IF;
+    RETURN retval;
+  END if_then_else;
+  ------------------------------- 
+  FUNCTION log2roundup (
+      data_value : INTEGER)
+    RETURN INTEGER IS
+
+      VARIABLE width       : INTEGER := 0;
+      VARIABLE cnt         : INTEGER := 1;
+    BEGIN
+      IF (data_value <= 1) THEN
+        width   := 1;
+      ELSE
+        WHILE (cnt < data_value) LOOP
+          width := width + 1;
+          cnt   := cnt *2;
+        END LOOP;
+      END IF;
+
+      RETURN width;
+    END log2roundup;
+  ------------------------------------------------------------------------------
+  -- hexstr_to_std_logic_vec
+  --  This function converts a hex string to a std_logic_vector
+  ------------------------------------------------------------------------------
+  FUNCTION hexstr_to_std_logic_vec( 
+    arg1 : string; 
+    size : integer ) 
+  RETURN std_logic_vector IS
+    VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
+    VARIABLE bin    : std_logic_vector(3 DOWNTO 0);
+    VARIABLE index  : integer                           := 0;
+  BEGIN
+    FOR i IN arg1'reverse_range LOOP
+      CASE arg1(i) IS
+        WHEN '0' => bin := (OTHERS => '0');
+        WHEN '1' => bin := (0 => '1', OTHERS => '0');
+        WHEN '2' => bin := (1 => '1', OTHERS => '0');
+        WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
+        WHEN '4' => bin := (2 => '1', OTHERS => '0');
+        WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
+        WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
+        WHEN '7' => bin := (3 => '0', OTHERS => '1');
+        WHEN '8' => bin := (3 => '1', OTHERS => '0');
+        WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
+        WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
+        WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
+        WHEN 'B' => bin := (2 => '0', OTHERS => '1');
+        WHEN 'b' => bin := (2 => '0', OTHERS => '1');
+        WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
+        WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
+        WHEN 'D' => bin := (1 => '0', OTHERS => '1');
+        WHEN 'd' => bin := (1 => '0', OTHERS => '1');
+        WHEN 'E' => bin := (0 => '0', OTHERS => '1');
+        WHEN 'e' => bin := (0 => '0', OTHERS => '1');
+        WHEN 'F' => bin := (OTHERS => '1');
+        WHEN 'f' => bin := (OTHERS => '1');
+        WHEN OTHERS =>
+          FOR j IN 0 TO 3 LOOP
+            bin(j) := 'X';
+          END LOOP;
+      END CASE;
+      FOR j IN 0 TO 3 LOOP
+        IF (index*4)+j < size THEN
+          result((index*4)+j) := bin(j);
+        END IF;
+      END LOOP;
+      index := index + 1;
+    END LOOP;
+    RETURN result;
+  END hexstr_to_std_logic_vec;
+
+END fifo_short_2clk_pkg;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd
new file mode 100755
index 000000000..80c201c3b
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd
@@ -0,0 +1,100 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_short_2clk_rng.vhd
+--
+-- Description:
+--   Used for generation of pseudo random numbers
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE IEEE.std_logic_arith.all;
+USE IEEE.std_logic_misc.all;
+
+ENTITY fifo_short_2clk_rng IS
+    GENERIC (
+      WIDTH        : integer :=  8;
+      SEED         : integer :=  3);
+    PORT (
+      CLK         : IN STD_LOGIC;
+      RESET       : IN STD_LOGIC;
+      ENABLE      : IN STD_LOGIC;
+      RANDOM_NUM  : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
+END ENTITY;
+
+ARCHITECTURE rg_arch OF fifo_short_2clk_rng IS
+BEGIN
+PROCESS (CLK,RESET)
+  VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
+  VARIABLE temp      : STD_LOGIC := '0';
+BEGIN
+  IF(RESET = '1') THEN
+    rand_temp := conv_std_logic_vector(SEED,width);
+    temp      := '0';
+  ELSIF (CLK'event AND CLK = '1') THEN
+    IF (ENABLE = '1') THEN
+      temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
+      rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
+      rand_temp(0) := temp;
+    END IF;
+  END IF;
+
+  RANDOM_NUM <= rand_temp;
+
+END PROCESS;
+
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd
new file mode 100755
index 000000000..e9139fc96
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd
@@ -0,0 +1,300 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_short_2clk_synth.vhd
+--
+-- Description:
+--   This is the demo testbench for fifo_generator core.
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+LIBRARY ieee;
+USE ieee.STD_LOGIC_1164.ALL;
+USE ieee.STD_LOGIC_unsigned.ALL;
+USE IEEE.STD_LOGIC_arith.ALL;
+USE ieee.numeric_std.ALL;
+USE ieee.STD_LOGIC_misc.ALL;
+
+LIBRARY std;
+USE std.textio.ALL;
+
+LIBRARY work;
+USE work.fifo_short_2clk_pkg.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY fifo_short_2clk_synth IS
+  GENERIC(
+  	   FREEZEON_ERROR : INTEGER := 0;
+	   TB_STOP_CNT    : INTEGER := 0;
+	   TB_SEED        : INTEGER := 1
+	 );
+  PORT(
+	WR_CLK     :  IN  STD_LOGIC;
+	RD_CLK     :  IN  STD_LOGIC;
+        RESET      :  IN  STD_LOGIC;
+        SIM_DONE   :  OUT STD_LOGIC;
+        STATUS     :  OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+      );
+END ENTITY;
+
+ARCHITECTURE simulation_arch OF fifo_short_2clk_synth IS
+
+    -- FIFO interface signal declarations
+    SIGNAL wr_clk_i                       :   STD_LOGIC;
+    SIGNAL rd_clk_i                       :   STD_LOGIC;
+    SIGNAL wr_data_count                  :   STD_LOGIC_VECTOR(6-1 DOWNTO 0);
+    SIGNAL rd_data_count                  :   STD_LOGIC_VECTOR(6-1 DOWNTO 0);
+    SIGNAL rst	                          :   STD_LOGIC;
+    SIGNAL wr_en                          :   STD_LOGIC;
+    SIGNAL rd_en                          :   STD_LOGIC;
+    SIGNAL din                            :   STD_LOGIC_VECTOR(72-1 DOWNTO 0);
+    SIGNAL dout                           :   STD_LOGIC_VECTOR(72-1 DOWNTO 0);
+    SIGNAL full                           :   STD_LOGIC;
+    SIGNAL empty                          :   STD_LOGIC;
+   -- TB Signals
+    SIGNAL wr_data                        :   STD_LOGIC_VECTOR(72-1 DOWNTO 0);
+    SIGNAL dout_i                         :   STD_LOGIC_VECTOR(72-1 DOWNTO 0);
+    SIGNAL wr_en_i                        :   STD_LOGIC := '0';
+    SIGNAL rd_en_i                        :   STD_LOGIC := '0';
+    SIGNAL full_i                         :   STD_LOGIC := '0';
+    SIGNAL empty_i                        :   STD_LOGIC := '0';
+    SIGNAL almost_full_i                  :   STD_LOGIC := '0';
+    SIGNAL almost_empty_i                 :   STD_LOGIC := '0';
+    SIGNAL prc_we_i                       :   STD_LOGIC := '0';
+    SIGNAL prc_re_i                       :   STD_LOGIC := '0';
+    SIGNAL dout_chk_i                     :   STD_LOGIC := '0';
+    SIGNAL rst_int_rd                     :   STD_LOGIC := '0';
+    SIGNAL rst_int_wr                     :   STD_LOGIC := '0';
+    SIGNAL rst_s_wr1                      :   STD_LOGIC := '0';
+    SIGNAL rst_s_wr2                      :   STD_LOGIC := '0';
+    SIGNAL rst_gen_rd                     :   STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL rst_s_wr3                      :   STD_LOGIC := '0';
+    SIGNAL rst_s_rd                       :   STD_LOGIC := '0';
+    SIGNAL reset_en                       :   STD_LOGIC := '0';
+    SIGNAL rst_async_wr1                  :   STD_LOGIC := '0'; 
+    SIGNAL rst_async_wr2                  :   STD_LOGIC := '0'; 
+    SIGNAL rst_async_wr3                  :   STD_LOGIC := '0'; 
+    SIGNAL rst_async_rd1                  :   STD_LOGIC := '0'; 
+    SIGNAL rst_async_rd2                  :   STD_LOGIC := '0'; 
+    SIGNAL rst_async_rd3                  :   STD_LOGIC := '0'; 
+
+
+ BEGIN  
+
+   ---- Reset generation logic -----
+   rst_int_wr          <= rst_async_wr3 OR rst_s_wr3;
+   rst_int_rd          <= rst_async_rd3 OR rst_s_rd;
+
+   --Testbench reset synchronization
+   PROCESS(rd_clk_i,RESET)
+   BEGIN
+     IF(RESET = '1') THEN
+       rst_async_rd1    <= '1';
+       rst_async_rd2    <= '1';
+       rst_async_rd3    <= '1';
+     ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
+       rst_async_rd1    <= RESET;
+       rst_async_rd2    <= rst_async_rd1;
+       rst_async_rd3    <= rst_async_rd2;
+     END IF;
+   END PROCESS;
+
+   PROCESS(wr_clk_i,RESET)
+   BEGIN
+     IF(RESET = '1') THEN
+       rst_async_wr1  <= '1';
+       rst_async_wr2  <= '1';
+       rst_async_wr3  <= '1';
+     ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
+       rst_async_wr1  <= RESET;
+       rst_async_wr2  <= rst_async_wr1;
+       rst_async_wr3  <= rst_async_wr2;
+     END IF;
+   END PROCESS;
+
+   --Soft reset for core and testbench
+   PROCESS(rd_clk_i)
+   BEGIN 
+     IF(rd_clk_i'event AND rd_clk_i='1') THEN
+       rst_gen_rd      <= rst_gen_rd + "1";
+       IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
+         rst_s_rd      <= '1';
+         assert false
+         report "Reset applied..Memory Collision checks are not valid"
+         severity note;
+       ELSE
+         IF(AND_REDUCE(rst_gen_rd)  = '1' AND rst_s_rd = '1') THEN
+           rst_s_rd    <= '0';
+         END IF;
+       END IF;
+     END IF;
+   END PROCESS;
+   
+   PROCESS(wr_clk_i)
+   BEGIN 
+       IF(wr_clk_i'event AND wr_clk_i='1') THEN
+         rst_s_wr1   <= rst_s_rd; 
+         rst_s_wr2   <= rst_s_wr1; 
+         rst_s_wr3   <= rst_s_wr2;
+         IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
+           assert false
+           report "Reset removed..Memory Collision checks are valid"
+           severity note;
+         END IF;
+       END IF;
+   END PROCESS;
+   ------------------
+   
+   ---- Clock buffers for testbench ----
+  wr_clk_i <= WR_CLK;
+  rd_clk_i <= RD_CLK;
+   ------------------
+     
+    rst                       <=   RESET OR rst_s_rd AFTER 12 ns;
+    din                       <=   wr_data;
+    dout_i                    <=   dout;
+    wr_en                     <=   wr_en_i;
+    rd_en                     <=   rd_en_i;
+    full_i                    <=   full;
+    empty_i                   <=   empty;
+
+    fg_dg_nv: fifo_short_2clk_dgen
+      GENERIC MAP (
+          	C_DIN_WIDTH       => 72,
+		C_DOUT_WIDTH      => 72,
+		TB_SEED           => TB_SEED, 
+ 		C_CH_TYPE         => 0	
+                 )
+      PORT MAP (  -- Write Port
+                RESET             => rst_int_wr,
+                WR_CLK            => wr_clk_i,
+		PRC_WR_EN         => prc_we_i,
+                FULL              => full_i,
+                WR_EN             => wr_en_i,
+                WR_DATA           => wr_data
+	       );
+
+   fg_dv_nv: fifo_short_2clk_dverif
+    GENERIC MAP (  
+	       C_DOUT_WIDTH       => 72,
+	       C_DIN_WIDTH        => 72,
+	       C_USE_EMBEDDED_REG => 0,
+	       TB_SEED            => TB_SEED, 
+ 	       C_CH_TYPE          => 0
+	        )
+     PORT MAP(
+              RESET               => rst_int_rd,
+              RD_CLK              => rd_clk_i,
+	      PRC_RD_EN           => prc_re_i,
+              RD_EN               => rd_en_i,
+	      EMPTY               => empty_i,
+	      DATA_OUT            => dout_i,
+	      DOUT_CHK            => dout_chk_i
+	    );
+
+    fg_pc_nv: fifo_short_2clk_pctrl
+    GENERIC MAP ( 
+              AXI_CHANNEL         => "Native",
+              C_APPLICATION_TYPE  => 0,
+	      C_DOUT_WIDTH        => 72,
+	      C_DIN_WIDTH         => 72,
+	      C_WR_PNTR_WIDTH     => 5,
+    	      C_RD_PNTR_WIDTH     => 5,
+ 	      C_CH_TYPE           => 0,
+              FREEZEON_ERROR      => FREEZEON_ERROR,
+	      TB_SEED             => TB_SEED, 
+              TB_STOP_CNT         => TB_STOP_CNT
+	        )
+     PORT MAP(
+              RESET_WR            => rst_int_wr,
+              RESET_RD            => rst_int_rd,
+	      RESET_EN            => reset_en,
+              WR_CLK              => wr_clk_i,
+              RD_CLK              => rd_clk_i,
+              PRC_WR_EN           => prc_we_i,
+              PRC_RD_EN           => prc_re_i,
+	      FULL                => full_i,
+              ALMOST_FULL         => almost_full_i,
+              ALMOST_EMPTY        => almost_empty_i,
+	      DOUT_CHK            => dout_chk_i,
+	      EMPTY               => empty_i,
+	      DATA_IN             => wr_data,
+	      DATA_OUT            => dout,
+	      SIM_DONE            => SIM_DONE,
+	      STATUS              => STATUS
+	    );
+
+
+
+
+
+  fifo_short_2clk_inst : fifo_short_2clk_exdes 
+    PORT MAP (
+           WR_CLK                    => wr_clk_i,
+           RD_CLK                    => rd_clk_i,
+           WR_DATA_COUNT             => wr_data_count,
+           RD_DATA_COUNT             => rd_data_count,
+           RST                       => rst,
+           WR_EN 		     => wr_en,
+           RD_EN                     => rd_en,
+           DIN                       => din,
+           DOUT                      => dout,
+           FULL                      => full,
+           EMPTY                     => empty);
+
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd
new file mode 100755
index 000000000..6d86157db
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd
@@ -0,0 +1,208 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: fifo_short_2clk_tb.vhd
+--
+-- Description:
+--   This is the demo testbench top file for fifo_generator core.
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+LIBRARY std;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+USE IEEE.std_logic_arith.ALL;
+USE IEEE.std_logic_misc.ALL;
+USE ieee.numeric_std.ALL;
+USE ieee.std_logic_textio.ALL;
+USE std.textio.ALL;
+
+LIBRARY work;
+USE work.fifo_short_2clk_pkg.ALL;
+
+ENTITY fifo_short_2clk_tb IS
+END ENTITY;
+
+
+ARCHITECTURE fifo_short_2clk_arch OF fifo_short_2clk_tb IS
+ SIGNAL  status              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ SIGNAL  wr_clk              : STD_LOGIC;
+ SIGNAL  rd_clk              : STD_LOGIC;
+ SIGNAL  reset 	             : STD_LOGIC;
+ SIGNAL  sim_done            : STD_LOGIC := '0';
+ SIGNAL  end_of_sim          : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
+ -- Write and Read clock periods
+ CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
+ CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
+ -- Procedures to display strings
+ PROCEDURE disp_str(CONSTANT str:IN STRING) IS
+    variable dp_l : line := null;   
+ BEGIN
+  write(dp_l,str);
+  writeline(output,dp_l);
+ END PROCEDURE;
+ 
+ PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
+    variable dp_lx : line := null;   
+ BEGIN
+  hwrite(dp_lx,hex);
+  writeline(output,dp_lx);
+ END PROCEDURE;
+
+BEGIN
+  
+  -- Generation of clock
+
+  PROCESS BEGIN
+    WAIT FOR 400 ns; -- Wait for global reset
+    WHILE 1 = 1 LOOP
+      wr_clk <= '0';
+      WAIT FOR wr_clk_period_by_2;
+      wr_clk <= '1'; 
+      WAIT FOR wr_clk_period_by_2;
+    END LOOP;
+  END PROCESS;
+
+  PROCESS BEGIN
+    WAIT FOR 200 ns;-- Wait for global reset
+    WHILE 1 = 1 LOOP
+      rd_clk <= '0';
+      WAIT FOR rd_clk_period_by_2;
+      rd_clk <= '1'; 
+      WAIT FOR rd_clk_period_by_2;
+    END LOOP;
+  END PROCESS;
+  
+  -- Generation of Reset
+  
+  PROCESS BEGIN
+    reset <= '1';
+    WAIT FOR 4200 ns;
+    reset <= '0';
+    WAIT;
+  END PROCESS;
+  
+  
+  -- Error message printing based on STATUS signal from fifo_short_2clk_synth
+
+  PROCESS(status)
+  BEGIN
+    IF(status /= "0" AND status /= "1") THEN
+      disp_str("STATUS:");
+      disp_hex(status);
+    END IF;
+
+    IF(status(7) = '1') THEN
+      assert false
+       report "Data mismatch found"
+       severity error;
+    END IF;
+
+    IF(status(1) = '1') THEN
+    END IF;
+    
+    IF(status(5) = '1') THEN
+      assert false
+       report "Empty flag Mismatch/timeout"
+       severity error;
+    END IF;
+
+    IF(status(6) = '1') THEN
+      assert false
+       report "Full Flag Mismatch/timeout"
+       severity error;
+    END IF;
+  END PROCESS;
+
+
+  PROCESS 
+  BEGIN
+    wait until sim_done = '1';
+    IF(status /= "0" AND status /= "1") THEN
+      assert false
+      report "Simulation failed"
+      severity failure;
+    ELSE
+      assert false
+      report "Test Completed Successfully"
+      severity failure;
+    END IF;
+  END PROCESS;
+  
+  PROCESS
+  BEGIN
+    wait for 400 ms;
+    assert false
+    report "Test bench timed out"
+    severity failure;
+  END PROCESS;
+
+  -- Instance of fifo_short_2clk_synth
+  
+  fifo_short_2clk_synth_inst:fifo_short_2clk_synth
+   GENERIC MAP(
+              FREEZEON_ERROR => 0,
+ 	      TB_STOP_CNT    => 2,
+ 	      TB_SEED        => 108 
+ 	      )
+  PORT MAP(
+	   WR_CLK        => wr_clk,
+	   RD_CLK        => rd_clk,
+	   RESET         => reset,
+	   SIM_DONE      => sim_done,
+           STATUS        => status
+	  );
+
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat
new file mode 100755
index 000000000..d40cb85cf
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat
@@ -0,0 +1,63 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogcomp -work work ..\\..\\..\\fifo_short_2clk.v
+vhpcomp -work work ..\\..\\example_design\\fifo_short_2clk_exdes.vhd
+
+echo "Compiling Test Bench Files"
+vhpcomp -work work ..\\fifo_short_2clk_pkg.vhd
+vhpcomp -work work ..\\fifo_short_2clk_rng.vhd 
+vhpcomp -work work ..\\fifo_short_2clk_dgen.vhd
+vhpcomp -work work ..\\fifo_short_2clk_dverif.vhd
+vhpcomp -work work ..\\fifo_short_2clk_pctrl.vhd 
+vhpcomp -work work ..\\fifo_short_2clk_synth.vhd 
+vhpcomp -work work ..\\fifo_short_2clk_tb.vhd
+
+vlogcomp -work work $XILINX\\verilog\\src\\glbl.v
+fuse work.fifo_short_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_short_2clk_tb.exe
+
+.\\fifo_short_2clk_tb.exe -gui -tclbatch .\\wave_isim.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.sh
new file mode 100755
index 000000000..78f9ce588
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.sh
@@ -0,0 +1,65 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogcomp -work work ../../../fifo_short_2clk.v
+vhpcomp -work work ../../example_design/fifo_short_2clk_exdes.vhd
+
+echo "Compiling Test Bench Files"
+vhpcomp -work work ../fifo_short_2clk_pkg.vhd
+vhpcomp -work work ../fifo_short_2clk_rng.vhd 
+vhpcomp -work work ../fifo_short_2clk_dgen.vhd
+vhpcomp -work work ../fifo_short_2clk_dverif.vhd
+vhpcomp -work work ../fifo_short_2clk_pctrl.vhd 
+vhpcomp -work work ../fifo_short_2clk_synth.vhd 
+vhpcomp -work work ../fifo_short_2clk_tb.vhd
+
+vlogcomp -work work $XILINX/verilog/src/glbl.v
+fuse work.fifo_short_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_short_2clk_tb.exe
+
+./fifo_short_2clk_tb.exe -gui -tclbatch ./wave_isim.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.bat
new file mode 100755
index 000000000..35375ce20
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.bat
@@ -0,0 +1,47 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+
+vsim -c -do simulate_mti.do
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.do
new file mode 100755
index 000000000..8deb52187
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.do
@@ -0,0 +1,74 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+vlib work 
+vmap work work 
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlog -work work ../../../fifo_short_2clk.v
+vcom -work work ../../example_design/fifo_short_2clk_exdes.vhd
+
+echo "Compiling Test Bench Files"
+vcom -work work ../fifo_short_2clk_pkg.vhd
+vcom -work work ../fifo_short_2clk_rng.vhd 
+vcom -work work ../fifo_short_2clk_dgen.vhd
+vcom -work work ../fifo_short_2clk_dverif.vhd
+vcom -work work ../fifo_short_2clk_pctrl.vhd 
+vcom -work work ../fifo_short_2clk_synth.vhd 
+vcom -work work ../fifo_short_2clk_tb.vhd
+
+vlog -work work $env(XILINX)/verilog/src/glbl.v
+vsim  -t ps -voptargs="+acc" -L XilinxCoreLib_ver -L unisims_ver glbl work.fifo_short_2clk_tb
+
+add log -r /*
+do wave_mti.do
+#Ignore integer warnings at time 0
+set StdArithNoWarnings 1
+run 0
+set StdArithNoWarnings 0
+
+run -all
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.sh
new file mode 100755
index 000000000..edb1b0dd9
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.sh
@@ -0,0 +1,49 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_ncsim.sh
new file mode 100755
index 000000000..749f9db06
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_ncsim.sh
@@ -0,0 +1,69 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+mkdir work
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+ncvlog -work work ../../../fifo_short_2clk.v
+ncvhdl -v93 -work work ../../example_design/fifo_short_2clk_exdes.vhd
+
+echo "Compiling Test Bench Files"
+ncvhdl -v93 -work work ../fifo_short_2clk_pkg.vhd
+ncvhdl -v93 -work work ../fifo_short_2clk_rng.vhd 
+ncvhdl -v93 -work work ../fifo_short_2clk_dgen.vhd
+ncvhdl -v93 -work work ../fifo_short_2clk_dverif.vhd
+ncvhdl -v93 -work work ../fifo_short_2clk_pctrl.vhd 
+ncvhdl -v93 -work work ../fifo_short_2clk_synth.vhd 
+ncvhdl -v93 -work work ../fifo_short_2clk_tb.vhd
+
+echo "Elaborating Design"
+ncvlog -work work $XILINX/verilog/src/glbl.v
+ncelab -access +rwc glbl work.fifo_short_2clk_tb
+
+echo "Simulating Design"
+ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_short_2clk_tb
+
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_vcs.sh
new file mode 100755
index 000000000..71a568e24
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_vcs.sh
@@ -0,0 +1,69 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+rm -rf simv* csrc DVEfiles AN.DB
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogan +v2k  ../../../fifo_short_2clk.v
+vhdlan  ../../example_design/fifo_short_2clk_exdes.vhd
+
+echo "Compiling Test Bench Files"
+vhdlan   ../fifo_short_2clk_pkg.vhd
+vhdlan   ../fifo_short_2clk_rng.vhd 
+vhdlan   ../fifo_short_2clk_dgen.vhd
+vhdlan   ../fifo_short_2clk_dverif.vhd
+vhdlan   ../fifo_short_2clk_pctrl.vhd 
+vhdlan   ../fifo_short_2clk_synth.vhd 
+vhdlan   ../fifo_short_2clk_tb.vhd
+
+echo "Elaborating Design"
+vlogan +v2k $XILINX/verilog/src/glbl.v
+vcs -time_res 1ps +vcs+lic+wait -debug fifo_short_2clk_tb glbl
+
+echo "Simulating Design"
+./simv -ucli -i ucli_commands.key
+dve -session vcs_session.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key
new file mode 100755
index 000000000..f90cccb67
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key
@@ -0,0 +1,4 @@
+dump -file fifo_short_2clk.vpd -type VPD
+dump -add fifo_short_2clk_tb
+run 
+quit
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl
new file mode 100755
index 000000000..7f3170d74
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl
@@ -0,0 +1,77 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: vcs_session.tcl
+#
+# Description:
+#   This is the VCS wave form file.
+#
+#--------------------------------------------------------------------------------
+if { ![gui_is_db_opened -db {fifo_short_2clk.vpd}] } {
+	gui_open_db -design V1 -file fifo_short_2clk.vpd -nosource
+}
+gui_set_precision 1ps
+gui_set_time_units 1ps
+
+
+gui_open_window Wave
+gui_sg_create fifo_short_2clk_Group
+gui_list_add_group -id Wave.1 {fifo_short_2clk_Group}
+
+gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST
+gui_sg_addsignal -group fifo_short_2clk_Group  WRITE -divider
+gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK
+gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN
+gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL
+gui_sg_addsignal -group fifo_short_2clk_Group  READ -divider
+gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK
+gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN
+gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY
+gui_zoom -window Wave.1 -full
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_isim.tcl
new file mode 100755
index 000000000..156aad172
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_isim.tcl
@@ -0,0 +1,68 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: wave_isim.tcl
+#
+# Description:
+#   This is the ISIM wave form file.
+#
+#--------------------------------------------------------------------------------
+wcfg new
+isim set radix hex
+wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST
+wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK
+wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN
+wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL
+wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK
+wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN
+wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY
+run all
+quit
+
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_mti.do
new file mode 100755
index 000000000..eafc64cf2
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_mti.do
@@ -0,0 +1,88 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+# Filename: wave_mti.do
+#
+# Description:
+#   This is the modelsim wave form file.
+#
+#--------------------------------------------------------------------------------
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST
+add wave -noupdate -divider WRITE
+add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK
+add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN
+add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL
+add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DIN
+add wave -noupdate -divider READ
+add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK
+add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN
+add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY
+add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DOUT
+
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {2164886 ps} 0}
+configure wave -namecolwidth 197
+configure wave -valuecolwidth 106
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {9464063 ps}
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_ncsim.sv
new file mode 100755
index 000000000..655d5c65a
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_ncsim.sv
@@ -0,0 +1,70 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: wave_ncsim.sv
+#
+# Description:
+#   This is the IUS wave form file.
+#
+#--------------------------------------------------------------------------------
+
+window new WaveWindow  -name  "Waves for FIFO Generator Example Design"
+waveform  using  "Waves for FIFO Generator Example Design"
+
+waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST
+waveform add -label WRITE
+waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK
+waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN
+waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL
+waveform add -label READ
+waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK
+waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN
+waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY
+console submit -using simulator -wait no "run"
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.bat
new file mode 100755
index 000000000..536a7cfee
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.bat
@@ -0,0 +1,61 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogcomp -work work ..\\..\\implement\\results\\routed.v
+
+echo "Compiling Test Bench Files"
+vhpcomp -work work ..\\fifo_short_2clk_pkg.vhd
+vhpcomp -work work ..\\fifo_short_2clk_rng.vhd 
+vhpcomp -work work ..\\fifo_short_2clk_dgen.vhd
+vhpcomp -work work ..\\fifo_short_2clk_dverif.vhd
+vhpcomp -work work ..\\fifo_short_2clk_pctrl.vhd 
+vhpcomp -work work ..\\fifo_short_2clk_synth.vhd 
+vhpcomp -work work ..\\fifo_short_2clk_tb.vhd
+
+fuse work.fifo_short_2clk_tb work.glbl -L simprims_ver -o fifo_short_2clk_tb.exe
+
+.\\fifo_short_2clk_tb.exe -sdfmax /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst=..\\..\\implement\\results\\routed.sdf -gui -tclbatch .\\wave_isim.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.sh
new file mode 100755
index 000000000..2d9404294
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.sh
@@ -0,0 +1,63 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogcomp -work work ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+vhpcomp -work work ../fifo_short_2clk_pkg.vhd
+vhpcomp -work work ../fifo_short_2clk_rng.vhd 
+vhpcomp -work work ../fifo_short_2clk_dgen.vhd
+vhpcomp -work work ../fifo_short_2clk_dverif.vhd
+vhpcomp -work work ../fifo_short_2clk_pctrl.vhd 
+vhpcomp -work work ../fifo_short_2clk_synth.vhd 
+vhpcomp -work work ../fifo_short_2clk_tb.vhd
+
+fuse work.fifo_short_2clk_tb work.glbl -L simprims_ver -o fifo_short_2clk_tb.exe
+
+./fifo_short_2clk_tb.exe -sdfmax /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst=../../implement/results/routed.sdf -gui -tclbatch ./wave_isim.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.bat
new file mode 100755
index 000000000..35375ce20
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.bat
@@ -0,0 +1,47 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+
+vsim -c -do simulate_mti.do
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.do
new file mode 100755
index 000000000..7ec785533
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.do
@@ -0,0 +1,72 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+vlib work 
+vmap work work 
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlog -work work ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+vcom -work work ../fifo_short_2clk_pkg.vhd  
+vcom -work work ../fifo_short_2clk_rng.vhd 
+vcom -work work ../fifo_short_2clk_dgen.vhd
+vcom -work work ../fifo_short_2clk_dverif.vhd
+vcom -work work ../fifo_short_2clk_pctrl.vhd 
+vcom -work work ../fifo_short_2clk_synth.vhd 
+vcom -work work ../fifo_short_2clk_tb.vhd
+
+vsim  -t ps -voptargs="+acc" +transport_int_delays -L simprims_ver glbl -sdfmax /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst=../../implement/results/routed.sdf work.fifo_short_2clk_tb
+
+add log -r /*
+do wave_mti.do
+#Ignore integer warnings at time 0
+set StdArithNoWarnings 1
+run 0
+set StdArithNoWarnings 0
+
+run -all
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.sh
new file mode 100755
index 000000000..edb1b0dd9
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.sh
@@ -0,0 +1,49 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_ncsim.sh
new file mode 100755
index 000000000..e9dc952cf
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_ncsim.sh
@@ -0,0 +1,73 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+mkdir work
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+ncvlog -work work ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+ncvhdl -v93 -work work ../fifo_short_2clk_pkg.vhd
+ncvhdl -v93 -work work ../fifo_short_2clk_rng.vhd 
+ncvhdl -v93 -work work ../fifo_short_2clk_dgen.vhd
+ncvhdl -v93 -work work ../fifo_short_2clk_dverif.vhd
+ncvhdl -v93 -work work ../fifo_short_2clk_pctrl.vhd 
+ncvhdl -v93 -work work ../fifo_short_2clk_synth.vhd 
+ncvhdl -v93 -work work ../fifo_short_2clk_tb.vhd
+
+echo "Compiling SDF file"
+ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X
+
+echo "Generating SDF command file"
+echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd
+echo 'SCOPE = :fifo_short_2clk_synth_inst:fifo_short_2clk_inst,' >> sdf.cmd
+echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd
+
+echo "Elaborating Design"
+ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd work.fifo_short_2clk_tb
+
+echo "Simulating Design"
+ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_short_2clk_tb
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_vcs.sh
new file mode 100755
index 000000000..bbd548a74
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_vcs.sh
@@ -0,0 +1,67 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+rm -rf simv* csrc DVEfiles AN.DB
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogan +v2k  ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+vhdlan   ../fifo_short_2clk_pkg.vhd
+vhdlan   ../fifo_short_2clk_rng.vhd
+vhdlan   ../fifo_short_2clk_dgen.vhd
+vhdlan   ../fifo_short_2clk_dverif.vhd
+vhdlan   ../fifo_short_2clk_pctrl.vhd
+vhdlan   ../fifo_short_2clk_synth.vhd
+vhdlan   ../fifo_short_2clk_tb.vhd
+
+echo "Elaborating Design"
+vcs -time_res 1ps +neg_tchk -sdf max:/fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst:../../implement/results/routed.sdf +vcs+lic+wait -debug fifo_short_2clk_tb glbl
+
+echo "Simulating Design"
+./simv -ucli -i ucli_commands.key
+dve -session vcs_session.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key
new file mode 100755
index 000000000..f90cccb67
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key
@@ -0,0 +1,4 @@
+dump -file fifo_short_2clk.vpd -type VPD
+dump -add fifo_short_2clk_tb
+run 
+quit
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl
new file mode 100755
index 000000000..e27baa9d8
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl
@@ -0,0 +1,76 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: vcs_session.tcl
+#
+# Description:
+#   This is the VCS wave form file.
+#
+#--------------------------------------------------------------------------------
+if { ![gui_is_db_opened -db {fifo_short_2clk.vpd}] } {
+	gui_open_db -design V1 -file fifo_short_2clk.vpd -nosource
+}
+gui_set_precision 1ps
+gui_set_time_units 1ps
+
+gui_open_window Wave
+gui_sg_create fifo_short_2clk_Group
+gui_list_add_group -id Wave.1 {fifo_short_2clk_Group}
+
+gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST
+gui_sg_addsignal -group fifo_short_2clk_Group  WRITE -divider
+gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK
+gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN
+gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL
+gui_sg_addsignal -group fifo_short_2clk_Group  READ -divider
+gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK
+gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN
+gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY
+gui_zoom -window Wave.1 -full
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_isim.tcl
new file mode 100755
index 000000000..156aad172
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_isim.tcl
@@ -0,0 +1,68 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: wave_isim.tcl
+#
+# Description:
+#   This is the ISIM wave form file.
+#
+#--------------------------------------------------------------------------------
+wcfg new
+isim set radix hex
+wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST
+wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK
+wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN
+wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL
+wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK
+wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN
+wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY
+run all
+quit
+
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_mti.do
new file mode 100755
index 000000000..eafc64cf2
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_mti.do
@@ -0,0 +1,88 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+# Filename: wave_mti.do
+#
+# Description:
+#   This is the modelsim wave form file.
+#
+#--------------------------------------------------------------------------------
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST
+add wave -noupdate -divider WRITE
+add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK
+add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN
+add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL
+add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DIN
+add wave -noupdate -divider READ
+add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK
+add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN
+add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY
+add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DOUT
+
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {2164886 ps} 0}
+configure wave -namecolwidth 197
+configure wave -valuecolwidth 106
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {9464063 ps}
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_ncsim.sv
new file mode 100755
index 000000000..655d5c65a
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_ncsim.sv
@@ -0,0 +1,70 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: wave_ncsim.sv
+#
+# Description:
+#   This is the IUS wave form file.
+#
+#--------------------------------------------------------------------------------
+
+window new WaveWindow  -name  "Waves for FIFO Generator Example Design"
+waveform  using  "Waves for FIFO Generator Example Design"
+
+waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST
+waveform add -label WRITE
+waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK
+waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN
+waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL
+waveform add -label READ
+waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK
+waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN
+waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY
+console submit -using simulator -wait no "run"
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk_flist.txt b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_flist.txt
new file mode 100644
index 000000000..4ab119a52
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_flist.txt
@@ -0,0 +1,57 @@
+# Output products list for <fifo_short_2clk>
+_xmsgs/pn_parser.xmsgs
+fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt
+fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html
+fifo_short_2clk/doc/pg057-fifo-generator.pdf
+fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf
+fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd
+fifo_short_2clk/fifo_generator_v9_3_readme.txt
+fifo_short_2clk/implement/implement.bat
+fifo_short_2clk/implement/implement.sh
+fifo_short_2clk/implement/implement_synplify.bat
+fifo_short_2clk/implement/implement_synplify.sh
+fifo_short_2clk/implement/planAhead_ise.bat
+fifo_short_2clk/implement/planAhead_ise.sh
+fifo_short_2clk/implement/planAhead_ise.tcl
+fifo_short_2clk/implement/xst.prj
+fifo_short_2clk/implement/xst.scr
+fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd
+fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd
+fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd
+fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd
+fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd
+fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd
+fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd
+fifo_short_2clk/simulation/functional/simulate_isim.bat
+fifo_short_2clk/simulation/functional/simulate_isim.sh
+fifo_short_2clk/simulation/functional/simulate_mti.bat
+fifo_short_2clk/simulation/functional/simulate_mti.do
+fifo_short_2clk/simulation/functional/simulate_mti.sh
+fifo_short_2clk/simulation/functional/simulate_ncsim.sh
+fifo_short_2clk/simulation/functional/simulate_vcs.sh
+fifo_short_2clk/simulation/functional/ucli_commands.key
+fifo_short_2clk/simulation/functional/vcs_session.tcl
+fifo_short_2clk/simulation/functional/wave_isim.tcl
+fifo_short_2clk/simulation/functional/wave_mti.do
+fifo_short_2clk/simulation/functional/wave_ncsim.sv
+fifo_short_2clk/simulation/timing/simulate_isim.bat
+fifo_short_2clk/simulation/timing/simulate_isim.sh
+fifo_short_2clk/simulation/timing/simulate_mti.bat
+fifo_short_2clk/simulation/timing/simulate_mti.do
+fifo_short_2clk/simulation/timing/simulate_mti.sh
+fifo_short_2clk/simulation/timing/simulate_ncsim.sh
+fifo_short_2clk/simulation/timing/simulate_vcs.sh
+fifo_short_2clk/simulation/timing/ucli_commands.key
+fifo_short_2clk/simulation/timing/vcs_session.tcl
+fifo_short_2clk/simulation/timing/wave_isim.tcl
+fifo_short_2clk/simulation/timing/wave_mti.do
+fifo_short_2clk/simulation/timing/wave_ncsim.sv
+fifo_short_2clk.asy
+fifo_short_2clk.gise
+fifo_short_2clk.ngc
+fifo_short_2clk.v
+fifo_short_2clk.veo
+fifo_short_2clk.xco
+fifo_short_2clk.xise
+fifo_short_2clk_flist.txt
+fifo_short_2clk_xmdf.tcl
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk_xmdf.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_xmdf.tcl
new file mode 100644
index 000000000..0abe2bb7c
--- /dev/null
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_xmdf.tcl
@@ -0,0 +1,251 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_short_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_short_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_short_2clk_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_short_2clk
+}
+# ::fifo_short_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_short_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/doc/pg057-fifo-generator.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/fifo_generator_v9_3_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement_synplify.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement_synplify.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/planAhead_ise.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/planAhead_ise.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/planAhead_ise.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/xst.prj
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/xst.scr
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_isim.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_isim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_mti.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_mti.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_vcs.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/ucli_commands.key
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/vcs_session.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/wave_isim.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/wave_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/wave_ncsim.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_isim.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_isim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_mti.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_mti.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_vcs.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/ucli_commands.key
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/vcs_session.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/wave_isim.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/wave_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/wave_ncsim.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_short_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/cache/b200_ngc_d1c0f267.edif b/fpga/usrp3/top/b200/planahead/planahead.data/cache/b200_ngc_d1c0f267.edif
new file mode 100644
index 000000000..897eebbf3
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.data/cache/b200_ngc_d1c0f267.edif
@@ -0,0 +1,59025 @@
+(edif b200
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2013 1 29 17 25 52)
+      (program "Xilinx ngc2edif" (version "P.49d"))
+      (author "Xilinx. Inc ")
+      (comment "This EDIF netlist is to be used within supported synthesis tools")
+      (comment "for determining resource/timing estimates of the design component")
+      (comment "represented by this netlist.")
+      (comment "Command line: -mdp2sp -w -secure b200.ngc b200.edif ")))
+  (external UNISIMS
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell GND
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port G
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell VCC
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port P
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDP
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port PRE
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell IBUFG
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell ODDR2
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port D0
+              (direction INPUT)
+            )
+            (port D1
+              (direction INPUT)
+            )
+            (port C0
+              (direction INPUT)
+            )
+            (port C1
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port R
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell BUFG
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port O
+              (direction OUTPUT)
+            )
+            (port I
+              (direction INPUT)
+            )
+          )
+      )
+    )
+    (cell DCM_SP
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CLK2X180
+              (direction OUTPUT)
+            )
+            (port PSCLK
+              (direction INPUT)
+            )
+            (port CLK2X
+              (direction OUTPUT)
+            )
+            (port CLKFX
+              (direction OUTPUT)
+            )
+            (port CLK180
+              (direction OUTPUT)
+            )
+            (port CLK270
+              (direction OUTPUT)
+            )
+            (port RST
+              (direction INPUT)
+            )
+            (port PSINCDEC
+              (direction INPUT)
+            )
+            (port CLKIN
+              (direction INPUT)
+            )
+            (port CLKFB
+              (direction INPUT)
+            )
+            (port PSEN
+              (direction INPUT)
+            )
+            (port CLK0
+              (direction OUTPUT)
+            )
+            (port CLKFX180
+              (direction OUTPUT)
+            )
+            (port CLKDV
+              (direction OUTPUT)
+            )
+            (port PSDONE
+              (direction OUTPUT)
+            )
+            (port CLK90
+              (direction OUTPUT)
+            )
+            (port LOCKED
+              (direction OUTPUT)
+            )
+            (port DSSEN
+              (direction INPUT)
+            )
+            (port (rename STATUS_7_ "STATUS<7>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 0) (owner "Xilinx"))
+            )
+            (port (rename STATUS_6_ "STATUS<6>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 1) (owner "Xilinx"))
+            )
+            (port (rename STATUS_5_ "STATUS<5>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 2) (owner "Xilinx"))
+            )
+            (port (rename STATUS_4_ "STATUS<4>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 3) (owner "Xilinx"))
+            )
+            (port (rename STATUS_3_ "STATUS<3>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 4) (owner "Xilinx"))
+            )
+            (port (rename STATUS_2_ "STATUS<2>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 5) (owner "Xilinx"))
+            )
+            (port (rename STATUS_1_ "STATUS<1>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 6) (owner "Xilinx"))
+            )
+            (port (rename STATUS_0_ "STATUS<0>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 7) (owner "Xilinx"))
+            )
+          )
+      )
+    )
+    (cell IBUFGDS
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port IB
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDRE
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port R
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDR
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port R
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FD
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDSE
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell SRLC32E
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CLK
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+            (port Q31
+              (direction OUTPUT)
+            )
+            (port (array (rename A "A<4:0>") 5)
+              (direction INPUT))
+          )
+      )
+    )
+    (cell MUXCY
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CI
+              (direction INPUT)
+            )
+            (port DI
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT2
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT6
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port I3
+              (direction INPUT)
+            )
+            (port I4
+              (direction INPUT)
+            )
+            (port I5
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell XORCY
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CI
+              (direction INPUT)
+            )
+            (port LI
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDE
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT3
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT4
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port I3
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT5
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port I3
+              (direction INPUT)
+            )
+            (port I4
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell IBUF
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell OBUF
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDS
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT1
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell MUXF7
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell INV
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell IOBUF
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port T
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+            (port IO
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell RAMB8BWER
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port RSTBRST
+              (direction INPUT)
+            )
+            (port ENBRDEN
+              (direction INPUT)
+            )
+            (port REGCEA
+              (direction INPUT)
+            )
+            (port ENAWREN
+              (direction INPUT)
+            )
+            (port CLKAWRCLK
+              (direction INPUT)
+            )
+            (port CLKBRDCLK
+              (direction INPUT)
+            )
+            (port REGCEBREGCE
+              (direction INPUT)
+            )
+            (port RSTA
+              (direction INPUT)
+            )
+            (port (array (rename WEAWEL "WEAWEL<1:0>") 2)
+              (direction INPUT))
+            (port (array (rename DOADO "DOADO<15:0>") 16)
+              (direction OUTPUT))
+            (port (array (rename DOPADOP "DOPADOP<1:0>") 2)
+              (direction OUTPUT))
+            (port (array (rename DOPBDOP "DOPBDOP<1:0>") 2)
+              (direction OUTPUT))
+            (port (array (rename WEBWEU "WEBWEU<1:0>") 2)
+              (direction INPUT))
+            (port (array (rename ADDRAWRADDR "ADDRAWRADDR<12:0>") 13)
+              (direction INPUT))
+            (port (array (rename DIPBDIP "DIPBDIP<1:0>") 2)
+              (direction INPUT))
+            (port (array (rename DIBDI "DIBDI<15:0>") 16)
+              (direction INPUT))
+            (port (array (rename DIADI "DIADI<15:0>") 16)
+              (direction INPUT))
+            (port (array (rename ADDRBRDADDR "ADDRBRDADDR<12:0>") 13)
+              (direction INPUT))
+            (port (array (rename DOBDO "DOBDO<15:0>") 16)
+              (direction OUTPUT))
+            (port (array (rename DIPADIP "DIPADIP<1:0>") 2)
+              (direction INPUT))
+          )
+      )
+    )
+    (cell RAMB16BWER
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port REGCEA
+              (direction INPUT)
+            )
+            (port CLKA
+              (direction INPUT)
+            )
+            (port ENB
+              (direction INPUT)
+            )
+            (port RSTB
+              (direction INPUT)
+            )
+            (port CLKB
+              (direction INPUT)
+            )
+            (port REGCEB
+              (direction INPUT)
+            )
+            (port RSTA
+              (direction INPUT)
+            )
+            (port ENA
+              (direction INPUT)
+            )
+            (port (array (rename DIPA "DIPA<3:0>") 4)
+              (direction INPUT))
+            (port (array (rename WEA "WEA<3:0>") 4)
+              (direction INPUT))
+            (port (array (rename DOA "DOA<31:0>") 32)
+              (direction OUTPUT))
+            (port (array (rename ADDRA "ADDRA<13:0>") 14)
+              (direction INPUT))
+            (port (array (rename ADDRB "ADDRB<13:0>") 14)
+              (direction INPUT))
+            (port (array (rename DIB "DIB<31:0>") 32)
+              (direction INPUT))
+            (port (array (rename DOPA "DOPA<3:0>") 4)
+              (direction OUTPUT))
+            (port (array (rename DIPB "DIPB<3:0>") 4)
+              (direction INPUT))
+            (port (array (rename DOPB "DOPB<3:0>") 4)
+              (direction OUTPUT))
+            (port (array (rename DOB "DOB<31:0>") 32)
+              (direction OUTPUT))
+            (port (array (rename WEB "WEB<3:0>") 4)
+              (direction INPUT))
+            (port (array (rename DIA "DIA<31:0>") 32)
+              (direction INPUT))
+          )
+      )
+    )
+  )
+
+  (library b200_lib
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell fifo_4k_2clk
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port rst
+              (direction INPUT)
+            )
+            (port wr_clk
+              (direction INPUT)
+            )
+            (port rd_clk
+              (direction INPUT)
+            )
+            (port wr_en
+              (direction INPUT)
+            )
+            (port rd_en
+              (direction INPUT)
+            )
+            (port full
+              (direction OUTPUT)
+            )
+            (port empty
+              (direction OUTPUT)
+            )
+            (port (array (rename din "din<71:0>") 72)
+              (direction INPUT))
+            (port (array (rename dout "dout<71:0>") 72)
+              (direction OUTPUT))
+            (port (array (rename rd_data_count "rd_data_count<9:0>") 10)
+              (direction OUTPUT))
+            (port (array (rename wr_data_count "wr_data_count<9:0>") 10)
+              (direction OUTPUT))
+          )
+      )
+    )
+    (cell b200
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port cat_miso
+              (direction INPUT)
+            )
+            (port fx3_ce
+              (direction INPUT)
+            )
+            (port fx3_mosi
+              (direction INPUT)
+            )
+            (port fx3_sclk
+              (direction INPUT)
+            )
+            (port FPGA_RXD0
+              (direction INPUT)
+            )
+            (port FPGA_TXD0
+              (direction INPUT)
+            )
+            (port SCL_FPGA
+              (direction INPUT)
+            )
+            (port SDA_FPGA
+              (direction INPUT)
+            )
+            (port codec_data_clk_p
+              (direction INPUT)
+            )
+            (port rx_frame_p
+              (direction INPUT)
+            )
+            (port cat_clkout_fpga
+              (direction INPUT)
+            )
+            (port codec_main_clk_p
+              (direction INPUT)
+            )
+            (port codec_main_clk_n
+              (direction INPUT)
+            )
+            (port GPIF_CTL4
+              (direction INPUT)
+            )
+            (port GPIF_CTL5
+              (direction INPUT)
+            )
+            (port GPIF_CTL6
+              (direction INPUT)
+            )
+            (port GPIF_CTL8
+              (direction INPUT)
+            )
+            (port GPIF_CTL9
+              (direction INPUT)
+            )
+            (port gps_lock
+              (direction INPUT)
+            )
+            (port gps_rxd
+              (direction INPUT)
+            )
+            (port gps_txd
+              (direction INPUT)
+            )
+            (port gps_txd_nmea
+              (direction INPUT)
+            )
+            (port pll_lock
+              (direction INPUT)
+            )
+            (port FPGA_CFG_CS
+              (direction INPUT)
+            )
+            (port AUX_PWR_ON
+              (direction INPUT)
+            )
+            (port PPS_IN_EXT
+              (direction INPUT)
+            )
+            (port PPS_IN_INT
+              (direction INPUT)
+            )
+            (port pps_out
+              (direction INPUT)
+            )
+            (port cat_ce
+              (direction OUTPUT)
+            )
+            (port cat_mosi
+              (direction OUTPUT)
+            )
+            (port cat_sclk
+              (direction OUTPUT)
+            )
+            (port fx3_miso
+              (direction OUTPUT)
+            )
+            (port pll_ce
+              (direction OUTPUT)
+            )
+            (port pll_mosi
+              (direction OUTPUT)
+            )
+            (port pll_sclk
+              (direction OUTPUT)
+            )
+            (port codec_enable
+              (direction OUTPUT)
+            )
+            (port codec_en_agc
+              (direction OUTPUT)
+            )
+            (port codec_reset
+              (direction OUTPUT)
+            )
+            (port codec_sync
+              (direction OUTPUT)
+            )
+            (port codec_txrx
+              (direction OUTPUT)
+            )
+            (port codec_fb_clk_p
+              (direction OUTPUT)
+            )
+            (port tx_frame_p
+              (direction OUTPUT)
+            )
+            (port IFCLK
+              (direction OUTPUT)
+            )
+            (port FX3_EXTINT
+              (direction OUTPUT)
+            )
+            (port GPIF_CTL0
+              (direction OUTPUT)
+            )
+            (port GPIF_CTL1
+              (direction OUTPUT)
+            )
+            (port GPIF_CTL2
+              (direction OUTPUT)
+            )
+            (port GPIF_CTL3
+              (direction OUTPUT)
+            )
+            (port GPIF_CTL7
+              (direction OUTPUT)
+            )
+            (port GPIF_CTL11
+              (direction OUTPUT)
+            )
+            (port GPIF_CTL12
+              (direction OUTPUT)
+            )
+            (port gps_out_enable
+              (direction OUTPUT)
+            )
+            (port gps_ref_enable
+              (direction OUTPUT)
+            )
+            (port LED_RX1
+              (direction OUTPUT)
+            )
+            (port LED_RX2
+              (direction OUTPUT)
+            )
+            (port LED_TXRX1_RX
+              (direction OUTPUT)
+            )
+            (port LED_TXRX1_TX
+              (direction OUTPUT)
+            )
+            (port LED_TXRX2_RX
+              (direction OUTPUT)
+            )
+            (port LED_TXRX2_TX
+              (direction OUTPUT)
+            )
+            (port ext_ref_enable
+              (direction OUTPUT)
+            )
+            (port pps_fpga_out_enable
+              (direction OUTPUT)
+            )
+            (port SFDX1_RX
+              (direction OUTPUT)
+            )
+            (port SFDX1_TX
+              (direction OUTPUT)
+            )
+            (port SFDX2_RX
+              (direction OUTPUT)
+            )
+            (port SFDX2_TX
+              (direction OUTPUT)
+            )
+            (port SRX1_RX
+              (direction OUTPUT)
+            )
+            (port SRX1_TX
+              (direction OUTPUT)
+            )
+            (port SRX2_RX
+              (direction OUTPUT)
+            )
+            (port SRX2_TX
+              (direction OUTPUT)
+            )
+            (port tx_bandsel_a
+              (direction OUTPUT)
+            )
+            (port tx_bandsel_b
+              (direction OUTPUT)
+            )
+            (port tx_enable1
+              (direction OUTPUT)
+            )
+            (port tx_enable2
+              (direction OUTPUT)
+            )
+            (port rx_bandsel_a
+              (direction OUTPUT)
+            )
+            (port rx_bandsel_b
+              (direction OUTPUT)
+            )
+            (port rx_bandsel_c
+              (direction OUTPUT)
+            )
+            (port (array (rename codec_ctrl_out "codec_ctrl_out<7:0>") 8)
+              (direction INPUT))
+            (port (array (rename rx_codec_d "rx_codec_d<11:0>") 12)
+              (direction INPUT))
+            (port (array (rename codec_ctrl_in "codec_ctrl_in<3:0>") 4)
+              (direction OUTPUT))
+            (port (array (rename tx_codec_d "tx_codec_d<11:0>") 12)
+              (direction OUTPUT))
+            (port (array (rename debug "debug<31:0>") 32)
+              (direction OUTPUT))
+            (port (array (rename debug_clk "debug_clk<1:0>") 2)
+              (direction OUTPUT))
+            (port (array (rename GPIF_D "GPIF_D<31:0>") 32)
+              (direction INOUT))
+            (designator "xc6slx75-3-fgg484")
+            (property TYPE (string "b200") (owner "Xilinx"))
+            (property BUS_INFO (string "8:INPUT:codec_ctrl_out<7:0>") (owner "Xilinx"))
+            (property BUS_INFO (string "12:INPUT:rx_codec_d<11:0>") (owner "Xilinx"))
+            (property BUS_INFO (string "4:OUTPUT:codec_ctrl_in<3:0>") (owner "Xilinx"))
+            (property BUS_INFO (string "12:OUTPUT:tx_codec_d<11:0>") (owner "Xilinx"))
+            (property BUS_INFO (string "32:OUTPUT:debug<31:0>") (owner "Xilinx"))
+            (property BUS_INFO (string "2:OUTPUT:debug_clk<1:0>") (owner "Xilinx"))
+            (property BUS_INFO (string "32:INOUT:GPIF_D<31:0>") (owner "Xilinx"))
+            (property SHREG_MIN_SIZE (string "2") (owner "Xilinx"))
+            (property X_CORE_INFO (string "fifo_generator_v9_3, Xilinx CORE Generator 14.4") (owner "Xilinx"))
+            (property CORE_GENERATION_INFO (string "b200_clk_gen,clk_wiz_v3_6,{component_name=b200_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}") (owner "Xilinx"))
+            (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx"))
+            (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_TAG (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_ALIAS (string "b200_b200") (owner "Xilinx"))
+          )
+          (contents
+            (instance XST_GND
+              (viewRef view_1 (cellRef GND (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance XST_VCC
+              (viewRef view_1 (cellRef VCC (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename bus_sync_reset_out_renamed_0 "bus_sync/reset_out")
+              (viewRef view_1 (cellRef FDP (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename bus_sync_reset_int_renamed_1 "bus_sync/reset_int")
+              (viewRef view_1 (cellRef FDP (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename gpif_sync_reset_out_renamed_2 "gpif_sync/reset_out")
+              (viewRef view_1 (cellRef FDP (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename gpif_sync_reset_int_renamed_3 "gpif_sync/reset_int")
+              (viewRef view_1 (cellRef FDP (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance codec_data_clk_bufg
+              (viewRef view_1 (cellRef IBUFG (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property CAPACITANCE (string "DONT_CARE") (owner "Xilinx"))
+              (property IBUF_DELAY_VALUE (string "0") (owner "Xilinx"))
+              (property IBUF_LOW_PWR (string "TRUE") (owner "Xilinx"))
+              (property IOSTANDARD (string "DEFAULT") (owner "Xilinx"))
+            )
+            (instance ODDR2_ifclk
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "NONE") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance ODDR2_ifclk_dbg
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "NONE") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename gen_clks_clkout3_buf "gen_clks/clkout3_buf")
+              (viewRef view_1 (cellRef BUFG (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename gen_clks_clkout2_buf "gen_clks/clkout2_buf")
+              (viewRef view_1 (cellRef BUFG (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename gen_clks_clkout1_buf "gen_clks/clkout1_buf")
+              (viewRef view_1 (cellRef BUFG (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename gen_clks_dcm_sp_inst "gen_clks/dcm_sp_inst")
+              (viewRef view_1 (cellRef DCM_SP (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "8:OUTPUT:STATUS<7:0>") (owner "Xilinx"))
+              (property CLKIN_DIVIDE_BY_2 (string "FALSE") (owner "Xilinx"))
+              (property CLKOUT_PHASE_SHIFT (string "NONE") (owner "Xilinx"))
+              (property CLK_FEEDBACK (string "1X") (owner "Xilinx"))
+              (property DESKEW_ADJUST (string "SYSTEM_SYNCHRONOUS") (owner "Xilinx"))
+              (property DFS_FREQUENCY_MODE (string "LOW") (owner "Xilinx"))
+              (property DLL_FREQUENCY_MODE (string "LOW") (owner "Xilinx"))
+              (property DSS_MODE (string "NONE") (owner "Xilinx"))
+              (property DUTY_CYCLE_CORRECTION (string "TRUE") (owner "Xilinx"))
+              (property FACTORY_JF (string "16'B1100000010000000") (owner "Xilinx"))
+              (property STARTUP_WAIT (string "FALSE") (owner "Xilinx"))
+              (property CLKFX_DIVIDE (integer 2) (owner "Xilinx"))
+              (property CLKFX_MULTIPLY (integer 5) (owner "Xilinx"))
+              (property PHASE_SHIFT (integer 0) (owner "Xilinx"))
+              (property CLKDV_DIVIDE (number (e 2 0)) (owner "Xilinx"))
+              (property CLKIN_PERIOD (string "25.000000") (owner "Xilinx"))
+              (property VERY_HIGH_FREQUENCY (string "FALSE") (owner "Xilinx"))
+            )
+            (instance (rename gen_clks_clkin1_buf "gen_clks/clkin1_buf")
+              (viewRef view_1 (cellRef IBUFGDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property CAPACITANCE (string "DONT_CARE") (owner "Xilinx"))
+              (property DIFF_TERM (string "FALSE") (owner "Xilinx"))
+              (property IBUF_DELAY_VALUE (string "0") (owner "Xilinx"))
+              (property IBUF_LOW_PWR (string "TRUE") (owner "Xilinx"))
+              (property IOSTANDARD (string "DEFAULT") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_idle_cycles_2 "slave_fifo32/idle_cycles_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_idle_cycles_1 "slave_fifo32/idle_cycles_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_idle_cycles_0 "slave_fifo32/idle_cycles_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifoadr_1 "slave_fifo32/fifoadr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifoadr_0 "slave_fifo32/fifoadr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_state_FSM_FFd1_renamed_4 "slave_fifo32/state_FSM_FFd1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_state_FSM_FFd2_renamed_5 "slave_fifo32/state_FSM_FFd2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_31 "slave_fifo32/debug2_31")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_29 "slave_fifo32/debug2_29")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_28 "slave_fifo32/debug2_28")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_27 "slave_fifo32/debug2_27")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_26 "slave_fifo32/debug2_26")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_23 "slave_fifo32/debug2_23")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_22 "slave_fifo32/debug2_22")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_21 "slave_fifo32/debug2_21")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_19 "slave_fifo32/debug2_19")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_18 "slave_fifo32/debug2_18")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_17 "slave_fifo32/debug2_17")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_16 "slave_fifo32/debug2_16")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_15 "slave_fifo32/debug2_15")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_14 "slave_fifo32/debug2_14")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_13 "slave_fifo32/debug2_13")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_12 "slave_fifo32/debug2_12")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_11 "slave_fifo32/debug2_11")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_10 "slave_fifo32/debug2_10")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_9 "slave_fifo32/debug2_9")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_8 "slave_fifo32/debug2_8")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_7 "slave_fifo32/debug2_7")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_6 "slave_fifo32/debug2_6")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_5 "slave_fifo32/debug2_5")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_4 "slave_fifo32/debug2_4")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_3 "slave_fifo32/debug2_3")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_2 "slave_fifo32/debug2_2")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_1 "slave_fifo32/debug2_1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug2_0 "slave_fifo32/debug2_0")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_31 "slave_fifo32/debug1_31")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_29 "slave_fifo32/debug1_29")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_28 "slave_fifo32/debug1_28")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_27 "slave_fifo32/debug1_27")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_26 "slave_fifo32/debug1_26")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_23 "slave_fifo32/debug1_23")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_22 "slave_fifo32/debug1_22")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_21 "slave_fifo32/debug1_21")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_19 "slave_fifo32/debug1_19")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_18 "slave_fifo32/debug1_18")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_15 "slave_fifo32/debug1_15")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_14 "slave_fifo32/debug1_14")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_13 "slave_fifo32/debug1_13")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_12 "slave_fifo32/debug1_12")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_11 "slave_fifo32/debug1_11")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_10 "slave_fifo32/debug1_10")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_9 "slave_fifo32/debug1_9")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_8 "slave_fifo32/debug1_8")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_7 "slave_fifo32/debug1_7")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_6 "slave_fifo32/debug1_6")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_5 "slave_fifo32/debug1_5")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_4 "slave_fifo32/debug1_4")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_3 "slave_fifo32/debug1_3")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_2 "slave_fifo32/debug1_2")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_1 "slave_fifo32/debug1_1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_0 "slave_fifo32/debug1_0")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_31 "slave_fifo32/gpif_data_in_31")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_30 "slave_fifo32/gpif_data_in_30")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_29 "slave_fifo32/gpif_data_in_29")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_28 "slave_fifo32/gpif_data_in_28")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_27 "slave_fifo32/gpif_data_in_27")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_26 "slave_fifo32/gpif_data_in_26")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_25 "slave_fifo32/gpif_data_in_25")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_24 "slave_fifo32/gpif_data_in_24")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_23 "slave_fifo32/gpif_data_in_23")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_22 "slave_fifo32/gpif_data_in_22")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_21 "slave_fifo32/gpif_data_in_21")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_20 "slave_fifo32/gpif_data_in_20")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_19 "slave_fifo32/gpif_data_in_19")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_18 "slave_fifo32/gpif_data_in_18")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_17 "slave_fifo32/gpif_data_in_17")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_16 "slave_fifo32/gpif_data_in_16")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_15 "slave_fifo32/gpif_data_in_15")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_14 "slave_fifo32/gpif_data_in_14")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_13 "slave_fifo32/gpif_data_in_13")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_12 "slave_fifo32/gpif_data_in_12")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_11 "slave_fifo32/gpif_data_in_11")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_10 "slave_fifo32/gpif_data_in_10")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_9 "slave_fifo32/gpif_data_in_9")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_8 "slave_fifo32/gpif_data_in_8")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_7 "slave_fifo32/gpif_data_in_7")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_6 "slave_fifo32/gpif_data_in_6")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_5 "slave_fifo32/gpif_data_in_5")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_4 "slave_fifo32/gpif_data_in_4")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_3 "slave_fifo32/gpif_data_in_3")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_2 "slave_fifo32/gpif_data_in_2")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_1 "slave_fifo32/gpif_data_in_1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_in_0 "slave_fifo32/gpif_data_in_0")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_pktend_renamed_6 "slave_fifo32/pktend")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_slwr_renamed_7 "slave_fifo32/slwr")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_slrd3_renamed_8 "slave_fifo32/slrd3")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_slrd2_renamed_9 "slave_fifo32/slrd2")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_slrd1_renamed_10 "slave_fifo32/slrd1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_EP_WMARK1_renamed_11 "slave_fifo32/EP_WMARK1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_EP_READY1_renamed_12 "slave_fifo32/EP_READY1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_EP_READY_renamed_13 "slave_fifo32/EP_READY")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_write_ready_go_renamed_14 "slave_fifo32/write_ready_go")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_read_ready_go_renamed_15 "slave_fifo32/read_ready_go")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_EP_WMARK_renamed_16 "slave_fifo32/EP_WMARK")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename catgen_oddr2_clk "catgen/oddr2_clk")
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "C0") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename catgen_oddr2_frame "catgen/oddr2_frame")
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "C0") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename catgen_gen_pins_11__oddr2 "catgen/gen_pins[11].oddr2")
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "C0") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename catgen_gen_pins_10__oddr2 "catgen/gen_pins[10].oddr2")
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "C0") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename catgen_gen_pins_9__oddr2 "catgen/gen_pins[9].oddr2")
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "C0") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename catgen_gen_pins_8__oddr2 "catgen/gen_pins[8].oddr2")
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "C0") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename catgen_gen_pins_7__oddr2 "catgen/gen_pins[7].oddr2")
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "C0") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename catgen_gen_pins_6__oddr2 "catgen/gen_pins[6].oddr2")
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "C0") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename catgen_gen_pins_5__oddr2 "catgen/gen_pins[5].oddr2")
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "C0") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename catgen_gen_pins_4__oddr2 "catgen/gen_pins[4].oddr2")
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "C0") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename catgen_gen_pins_3__oddr2 "catgen/gen_pins[3].oddr2")
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "C0") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename catgen_gen_pins_2__oddr2 "catgen/gen_pins[2].oddr2")
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "C0") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename catgen_gen_pins_1__oddr2 "catgen/gen_pins[1].oddr2")
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "C0") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename catgen_gen_pins_0__oddr2 "catgen/gen_pins[0].oddr2")
+              (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property DDR_ALIGNMENT (string "C0") (owner "Xilinx"))
+              (property SRTYPE (string "ASYNC") (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[64].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[63].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[62].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[61].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[60].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[59].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[58].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[57].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[56].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[55].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[54].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[53].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[52].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[51].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[50].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[49].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[48].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[47].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[46].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[45].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[44].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[43].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[42].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[41].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[40].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[39].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[38].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[37].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[36].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[35].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[34].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[33].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[32].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[31].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[30].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[29].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[28].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[27].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[26].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[25].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[24].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[23].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[22].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[21].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[20].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[19].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[18].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[17].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[16].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[15].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[14].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[13].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[12].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[11].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[10].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[9].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[8].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[7].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[6].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[5].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[4].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[3].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[2].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[1].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[0].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[64].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[63].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[62].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[61].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[60].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[59].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[58].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[57].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[56].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[55].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[54].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[53].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[52].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[51].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[50].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[49].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[48].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[47].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[46].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[45].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[44].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[43].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[42].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[41].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[40].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[39].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[38].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[37].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[36].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[35].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[34].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[33].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[32].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[31].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[30].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[29].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[28].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[27].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[26].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[25].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[24].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[23].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[22].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[21].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[20].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[19].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[18].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[17].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[16].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[15].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[14].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[13].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[12].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[11].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[10].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[9].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[8].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[7].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[6].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[5].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[4].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[3].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[2].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[1].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[0].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<3>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<2>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<1>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<0>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_12__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_renamed_17 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_12 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_10 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_renamed_18 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_12 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_10 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_12__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_renamed_19 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_renamed_20 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[0].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[1].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[2].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[3].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[4].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[5].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[6].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[7].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[8].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[9].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[10].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[11].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[12].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[13].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[14].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[15].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[16].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[17].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[18].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[19].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[20].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[21].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[22].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[23].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[24].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[25].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[26].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[27].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[28].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[29].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[30].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[31].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[32].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[33].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[34].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[35].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[36].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[37].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[38].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[39].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[40].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[41].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[42].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[43].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[44].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[45].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[46].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[47].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[48].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[49].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[50].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[51].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[52].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[53].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[54].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[55].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[56].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[57].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[58].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[59].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[60].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[61].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[62].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[63].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[64].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_renamed_21 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_2 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_3 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_4 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_5 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_6 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_7 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_8 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_9 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_10 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_11 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_12 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_13 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_14 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_15 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_16 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_16")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_17 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_17")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_18 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_18")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_19 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_19")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_20 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_20")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_21 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_21")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_22 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_22")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_23 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_23")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_24 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_24")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_25 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_25")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_26 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_26")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_27 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_27")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_28 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_28")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_29 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_29")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_30 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_30")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_31 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_31")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_i_tready_renamed_22 "slave_fifo32/fifo64_to_gpmc32_tx/i_tready")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<0>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<1>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<2>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<3>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<4>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<5>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<6>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<7>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<8>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<9>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<10>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<11>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<12>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<0>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<1>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<2>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<3>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<4>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<5>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<6>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<7>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<8>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<9>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<10>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<11>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<12>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<0>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<1>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<2>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<3>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_renamed_23 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_renamed_24 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_15__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_14__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_14__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_13__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_13__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[0].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[1].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[2].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[3].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[4].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[5].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[6].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[7].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[8].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[9].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[10].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[11].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[12].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[13].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[14].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[15].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[16].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[17].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[18].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[19].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[20].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[21].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[22].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[23].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[24].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[25].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[26].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[27].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[28].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[29].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[30].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[31].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[32].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[33].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[34].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[35].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[36].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[37].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[38].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[39].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[40].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[41].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[42].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[43].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[44].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[45].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[46].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[47].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[48].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[49].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[50].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[51].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[52].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[53].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[54].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[55].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[56].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[57].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[58].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[59].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[60].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[61].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[62].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[63].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[64].srlc32e")
+              (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx"))
+              (property INIT (string "00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_renamed_25 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_10 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_12 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_13 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_14 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_15 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_16 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_16")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_17 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_17")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_18 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_18")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_19 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_19")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_20 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_20")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_21")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_22 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_22")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_23 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_23")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_24 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_24")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_25")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_26")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_27")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_28")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_29")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_30")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_31")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_i_tready_renamed_26 "slave_fifo32/fifo64_to_gpmc32_ctrl/i_tready")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<0>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AC") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<1>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AC") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<2>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<3>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<4>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<5>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<6>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<7>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<8>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<9>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<0>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<1>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<2>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<3>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<4>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<5>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<6>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<7>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<8>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<9>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_renamed_27 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_renamed_28 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_becoming_full_cy_4__ "f1/Mcompar_becoming_full_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_becoming_full_lut_4__ "f1/Mcompar_becoming_full_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_becoming_full_cy_3__ "f1/Mcompar_becoming_full_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_becoming_full_lut_3__ "f1/Mcompar_becoming_full_lut<3>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_becoming_full_cy_2__ "f1/Mcompar_becoming_full_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_becoming_full_lut_2__ "f1/Mcompar_becoming_full_lut<2>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_becoming_full_cy_1__ "f1/Mcompar_becoming_full_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_becoming_full_lut_1__ "f1/Mcompar_becoming_full_lut<1>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_becoming_full_cy_0__ "f1/Mcompar_becoming_full_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_becoming_full_lut_0__ "f1/Mcompar_becoming_full_lut<0>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_xor_12__ "f1/Mcount_rd_addr_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_xor_11__ "f1/Mcount_rd_addr_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_11__ "f1/Mcount_rd_addr_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_xor_10__ "f1/Mcount_rd_addr_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_10__ "f1/Mcount_rd_addr_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_xor_9__ "f1/Mcount_rd_addr_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_9__ "f1/Mcount_rd_addr_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_xor_8__ "f1/Mcount_rd_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_8__ "f1/Mcount_rd_addr_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_xor_7__ "f1/Mcount_rd_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_7__ "f1/Mcount_rd_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_xor_6__ "f1/Mcount_rd_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_6__ "f1/Mcount_rd_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_xor_5__ "f1/Mcount_rd_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_5__ "f1/Mcount_rd_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_xor_4__ "f1/Mcount_rd_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_4__ "f1/Mcount_rd_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_xor_3__ "f1/Mcount_rd_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_3__ "f1/Mcount_rd_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_xor_2__ "f1/Mcount_rd_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_2__ "f1/Mcount_rd_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_xor_1__ "f1/Mcount_rd_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_1__ "f1/Mcount_rd_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_xor_0__ "f1/Mcount_rd_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_0__ "f1/Mcount_rd_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_xor_12__ "f1/Mcount_wr_addr_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_xor_11__ "f1/Mcount_wr_addr_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_11__ "f1/Mcount_wr_addr_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_xor_10__ "f1/Mcount_wr_addr_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_10__ "f1/Mcount_wr_addr_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_xor_9__ "f1/Mcount_wr_addr_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_9__ "f1/Mcount_wr_addr_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_xor_8__ "f1/Mcount_wr_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_8__ "f1/Mcount_wr_addr_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_xor_7__ "f1/Mcount_wr_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_7__ "f1/Mcount_wr_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_xor_6__ "f1/Mcount_wr_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_6__ "f1/Mcount_wr_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_xor_5__ "f1/Mcount_wr_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_5__ "f1/Mcount_wr_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_xor_4__ "f1/Mcount_wr_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_4__ "f1/Mcount_wr_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_xor_3__ "f1/Mcount_wr_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_3__ "f1/Mcount_wr_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_xor_2__ "f1/Mcount_wr_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_2__ "f1/Mcount_wr_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_xor_1__ "f1/Mcount_wr_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_1__ "f1/Mcount_wr_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_xor_0__ "f1/Mcount_wr_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_0__ "f1/Mcount_wr_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_xor_12__ "f1/Msub_dont_write_past_me_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_xor_11__ "f1/Msub_dont_write_past_me_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_cy_11__ "f1/Msub_dont_write_past_me_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_xor_10__ "f1/Msub_dont_write_past_me_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_cy_10__ "f1/Msub_dont_write_past_me_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_xor_9__ "f1/Msub_dont_write_past_me_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_cy_9__ "f1/Msub_dont_write_past_me_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_xor_8__ "f1/Msub_dont_write_past_me_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_cy_8__ "f1/Msub_dont_write_past_me_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_xor_7__ "f1/Msub_dont_write_past_me_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_cy_7__ "f1/Msub_dont_write_past_me_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_xor_6__ "f1/Msub_dont_write_past_me_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_cy_6__ "f1/Msub_dont_write_past_me_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_xor_5__ "f1/Msub_dont_write_past_me_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_cy_5__ "f1/Msub_dont_write_past_me_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_xor_4__ "f1/Msub_dont_write_past_me_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_cy_4__ "f1/Msub_dont_write_past_me_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_xor_3__ "f1/Msub_dont_write_past_me_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_cy_3__ "f1/Msub_dont_write_past_me_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_xor_2__ "f1/Msub_dont_write_past_me_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_cy_2__ "f1/Msub_dont_write_past_me_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_xor_1__ "f1/Msub_dont_write_past_me_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_cy_1__ "f1/Msub_dont_write_past_me_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_xor_0__ "f1/Msub_dont_write_past_me_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_cy_0__ "f1/Msub_dont_write_past_me_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_wr_addr_0 "f1/wr_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_rd_addr_0 "f1/rd_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_read_state_FSM_FFd1_renamed_29 "f1/read_state_FSM_FFd1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_read_state_FSM_FFd2_renamed_30 "f1/read_state_FSM_FFd2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_wr_addr_12 "f1/wr_addr_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_wr_addr_11 "f1/wr_addr_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_wr_addr_10 "f1/wr_addr_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_wr_addr_9 "f1/wr_addr_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_wr_addr_8 "f1/wr_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_wr_addr_7 "f1/wr_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_wr_addr_6 "f1/wr_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_wr_addr_5 "f1/wr_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_wr_addr_4 "f1/wr_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_wr_addr_3 "f1/wr_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_wr_addr_2 "f1/wr_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_wr_addr_1 "f1/wr_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_rd_addr_12 "f1/rd_addr_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_rd_addr_11 "f1/rd_addr_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_rd_addr_10 "f1/rd_addr_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_rd_addr_9 "f1/rd_addr_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_rd_addr_8 "f1/rd_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_rd_addr_7 "f1/rd_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_rd_addr_6 "f1/rd_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_rd_addr_5 "f1/rd_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_rd_addr_4 "f1/rd_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_rd_addr_3 "f1/rd_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_rd_addr_2 "f1/rd_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_rd_addr_1 "f1/rd_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_becoming_full_cy_4__ "f0/Mcompar_becoming_full_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_becoming_full_lut_4__ "f0/Mcompar_becoming_full_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_becoming_full_cy_3__ "f0/Mcompar_becoming_full_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_becoming_full_lut_3__ "f0/Mcompar_becoming_full_lut<3>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_becoming_full_cy_2__ "f0/Mcompar_becoming_full_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_becoming_full_lut_2__ "f0/Mcompar_becoming_full_lut<2>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_becoming_full_cy_1__ "f0/Mcompar_becoming_full_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_becoming_full_lut_1__ "f0/Mcompar_becoming_full_lut<1>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_becoming_full_cy_0__ "f0/Mcompar_becoming_full_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_becoming_full_lut_0__ "f0/Mcompar_becoming_full_lut<0>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_xor_12__ "f0/Mcount_rd_addr_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_xor_11__ "f0/Mcount_rd_addr_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_11__ "f0/Mcount_rd_addr_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_xor_10__ "f0/Mcount_rd_addr_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_10__ "f0/Mcount_rd_addr_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_xor_9__ "f0/Mcount_rd_addr_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_9__ "f0/Mcount_rd_addr_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_xor_8__ "f0/Mcount_rd_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_8__ "f0/Mcount_rd_addr_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_xor_7__ "f0/Mcount_rd_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_7__ "f0/Mcount_rd_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_xor_6__ "f0/Mcount_rd_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_6__ "f0/Mcount_rd_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_xor_5__ "f0/Mcount_rd_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_5__ "f0/Mcount_rd_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_xor_4__ "f0/Mcount_rd_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_4__ "f0/Mcount_rd_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_xor_3__ "f0/Mcount_rd_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_3__ "f0/Mcount_rd_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_xor_2__ "f0/Mcount_rd_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_2__ "f0/Mcount_rd_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_xor_1__ "f0/Mcount_rd_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_1__ "f0/Mcount_rd_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_xor_0__ "f0/Mcount_rd_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_0__ "f0/Mcount_rd_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_xor_12__ "f0/Mcount_wr_addr_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_xor_11__ "f0/Mcount_wr_addr_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_11__ "f0/Mcount_wr_addr_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_xor_10__ "f0/Mcount_wr_addr_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_10__ "f0/Mcount_wr_addr_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_xor_9__ "f0/Mcount_wr_addr_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_9__ "f0/Mcount_wr_addr_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_xor_8__ "f0/Mcount_wr_addr_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_8__ "f0/Mcount_wr_addr_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_xor_7__ "f0/Mcount_wr_addr_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_7__ "f0/Mcount_wr_addr_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_xor_6__ "f0/Mcount_wr_addr_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_6__ "f0/Mcount_wr_addr_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_xor_5__ "f0/Mcount_wr_addr_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_5__ "f0/Mcount_wr_addr_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_xor_4__ "f0/Mcount_wr_addr_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_4__ "f0/Mcount_wr_addr_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_xor_3__ "f0/Mcount_wr_addr_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_3__ "f0/Mcount_wr_addr_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_xor_2__ "f0/Mcount_wr_addr_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_2__ "f0/Mcount_wr_addr_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_xor_1__ "f0/Mcount_wr_addr_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_1__ "f0/Mcount_wr_addr_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_xor_0__ "f0/Mcount_wr_addr_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_0__ "f0/Mcount_wr_addr_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_xor_12__ "f0/Msub_dont_write_past_me_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_xor_11__ "f0/Msub_dont_write_past_me_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_cy_11__ "f0/Msub_dont_write_past_me_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_xor_10__ "f0/Msub_dont_write_past_me_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_cy_10__ "f0/Msub_dont_write_past_me_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_xor_9__ "f0/Msub_dont_write_past_me_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_cy_9__ "f0/Msub_dont_write_past_me_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_xor_8__ "f0/Msub_dont_write_past_me_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_cy_8__ "f0/Msub_dont_write_past_me_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_xor_7__ "f0/Msub_dont_write_past_me_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_cy_7__ "f0/Msub_dont_write_past_me_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_xor_6__ "f0/Msub_dont_write_past_me_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_cy_6__ "f0/Msub_dont_write_past_me_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_xor_5__ "f0/Msub_dont_write_past_me_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_cy_5__ "f0/Msub_dont_write_past_me_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_xor_4__ "f0/Msub_dont_write_past_me_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_cy_4__ "f0/Msub_dont_write_past_me_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_xor_3__ "f0/Msub_dont_write_past_me_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_cy_3__ "f0/Msub_dont_write_past_me_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_xor_2__ "f0/Msub_dont_write_past_me_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_cy_2__ "f0/Msub_dont_write_past_me_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_xor_1__ "f0/Msub_dont_write_past_me_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_cy_1__ "f0/Msub_dont_write_past_me_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_xor_0__ "f0/Msub_dont_write_past_me_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_cy_0__ "f0/Msub_dont_write_past_me_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_wr_addr_0 "f0/wr_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_rd_addr_0 "f0/rd_addr_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_read_state_FSM_FFd1_renamed_31 "f0/read_state_FSM_FFd1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_read_state_FSM_FFd2_renamed_32 "f0/read_state_FSM_FFd2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_wr_addr_12 "f0/wr_addr_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_wr_addr_11 "f0/wr_addr_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_wr_addr_10 "f0/wr_addr_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_wr_addr_9 "f0/wr_addr_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_wr_addr_8 "f0/wr_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_wr_addr_7 "f0/wr_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_wr_addr_6 "f0/wr_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_wr_addr_5 "f0/wr_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_wr_addr_4 "f0/wr_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_wr_addr_3 "f0/wr_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_wr_addr_2 "f0/wr_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_wr_addr_1 "f0/wr_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_rd_addr_12 "f0/rd_addr_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_rd_addr_11 "f0/rd_addr_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_rd_addr_10 "f0/rd_addr_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_rd_addr_9 "f0/rd_addr_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_rd_addr_8 "f0/rd_addr_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_rd_addr_7 "f0/rd_addr_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_rd_addr_6 "f0/rd_addr_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_rd_addr_5 "f0/rd_addr_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_rd_addr_4 "f0/rd_addr_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_rd_addr_3 "f0/rd_addr_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_rd_addr_2 "f0/rd_addr_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_rd_addr_1 "f0/rd_addr_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance fx3_miso1
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___180___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1") (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance cat_mosi1
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___178___cat_mosi1") (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance cat_sclk1
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___178___cat_mosi1") (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance reset_global_locked_OR_1_o1
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___179___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1") (owner "Xilinx"))
+              (property INIT (string "D") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata110")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___151___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata110") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata210 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata210")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___151___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata110") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata33 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata33")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___150___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata33") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata41 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata41")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___150___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata33") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata51 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata51")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___149___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata51") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata61 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata61")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___149___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata51") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata71 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata71")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___148___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata71") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata81 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata81")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___148___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata71") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata91 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata91")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___147___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata91") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata101 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata101")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___146___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata101") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata111 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata111")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___146___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata101") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata121 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata121")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___145___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata121") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata131 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata131")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___145___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata121") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata141 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata141")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___144___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata141") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata151 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata151")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___144___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata141") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata161 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata161")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___143___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata161") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata171 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata171")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___143___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata161") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata181 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata181")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___142___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata181") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata191 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata191")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___142___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata181") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata201 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata201")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___141___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata201") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata211 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata211")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___141___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata201") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata221 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata221")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___140___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata221") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata231 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata231")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___140___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata221") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata241 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata241")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___139___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata241") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata251 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata251")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___139___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata241") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata261 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata261")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___138___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata261") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata271 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata271")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___138___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata261") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata281 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata281")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___137___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata281") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata291 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata291")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
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+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata301 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata301")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___147___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata91") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata311 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata311")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
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+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata321 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata321")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
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+              (property PK_HLUTNM (string "___XLNM___136___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata311") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata110")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___167___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata110") (owner "Xilinx"))
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+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_i_tready1 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/i_tready1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___172___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/o_tlast1") (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mcount_idle_cycles_xor_0_11 "slave_fifo32/Mcount_idle_cycles_xor<0>11")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___177___slave_fifo32/Mcount_idle_cycles_xor<0>11") (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32__n0230_inv1 "slave_fifo32/_n0230_inv1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___48___slave_fifo32/_n0230_inv1") (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mcount_idle_cycles_xor_2_11 "slave_fifo32/Mcount_idle_cycles_xor<2>11")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___23___slave_fifo32/Mcount_idle_cycles_xor<2>11") (owner "Xilinx"))
+              (property INIT (string "1444") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32__n0223_inv1 "slave_fifo32/_n0223_inv1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___21___slave_fifo32/_n0223_inv1") (owner "Xilinx"))
+              (property INIT (string "82") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1 "slave_fifo32/ctrl_tx_tready_data_tx_tready_OR_55_o1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5410") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mcount_idle_cycles_xor_1_11 "slave_fifo32/Mcount_idle_cycles_xor<1>11")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___23___slave_fifo32/Mcount_idle_cycles_xor<2>11") (owner "Xilinx"))
+              (property INIT (string "14") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT110")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT101")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT111")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT121")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT131")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT141")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT151")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT161")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT171 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT171")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT181 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT181")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT191")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT210")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT201")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT211 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT211")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT221")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT231")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT241")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT251")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT261")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT271")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT281")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT291")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT33")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT301")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT311")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT321")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT41 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT41")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT51 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT51")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT61 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT61")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT71 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT71")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT81 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT81")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT91 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT91")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___42___slave_fifo32/Mcount_fifoadr_xor<1>11") (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32__n0237_inv1 "slave_fifo32/_n0237_inv1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000100000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32__n0290_inv1 "slave_fifo32/_n0290_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___21___slave_fifo32/_n0223_inv1") (owner "Xilinx"))
+              (property INIT (string "20002222") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_ctrl_tx_tvalid1 "slave_fifo32/ctrl_tx_tvalid1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "01000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_data_tx_tvalid1 "slave_fifo32/data_tx_tvalid1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00010000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___20___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11") (owner "Xilinx"))
+              (property INIT (string "6AA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<1>11")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "69") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<3>11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___20___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11") (owner "Xilinx"))
+              (property INIT (string "6AAAAAA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<4>11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6AAAAAAAAAAAAAA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___18___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11") (owner "Xilinx"))
+              (property INIT (string "6AA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<1>11")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "69") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<3>11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___18___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11") (owner "Xilinx"))
+              (property INIT (string "6AAAAAA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<4>11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6AAAAAAAAAAAAAA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___22___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (owner "Xilinx"))
+              (property INIT (string "BF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT61")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "99AA99A6AAAAAAA6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___36___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (owner "Xilinx"))
+              (property INIT (string "7") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___45___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1") (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___25___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (owner "Xilinx"))
+              (property INIT (string "BF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT61")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "99AA99A6AAAAAAA6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___34___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (owner "Xilinx"))
+              (property INIT (string "7") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/write1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1021 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___168___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021") (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1011 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___49___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011") (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o81")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o61")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o71")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o41")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<4>11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6AAAAAAAAAAAAAA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___11___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11") (owner "Xilinx"))
+              (property INIT (string "6AAAAAA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___117___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11") (owner "Xilinx"))
+              (property INIT (string "69") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<2>11")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___11___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11") (owner "Xilinx"))
+              (property INIT (string "6AA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o41")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0121111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___174___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___19___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421") (owner "Xilinx"))
+              (property INIT (string "0111") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full411")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___19___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421") (owner "Xilinx"))
+              (property INIT (string "FEEE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o71")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full921 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___116___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921") (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o61")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___174___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111") (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tvalid11")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___127___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tvalid11") (owner "Xilinx"))
+              (property INIT (string "E0") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT17")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT21")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT31")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT41")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT51")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT61")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___135___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT91")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___135___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___134___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT111")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___134___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___133___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT131")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___133___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
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+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___41___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") (owner "Xilinx"))
+              (property INIT (string "FFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___40___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write1") (owner "Xilinx"))
+              (property INIT (string "EFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___46___slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1") (owner "Xilinx"))
+              (property INIT (string "0455") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<4>11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6AAAAAAAAAAAAAA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___9___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11") (owner "Xilinx"))
+              (property INIT (string "6AAAAAA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___115___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11") (owner "Xilinx"))
+              (property INIT (string "69") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<2>11")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___9___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11") (owner "Xilinx"))
+              (property INIT (string "6AA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o41")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___173___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___17___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421") (owner "Xilinx"))
+              (property INIT (string "0111") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full411")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___17___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421") (owner "Xilinx"))
+              (property INIT (string "FEEE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o71")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full921 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___114___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921") (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o61")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___173___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111") (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___125___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11") (owner "Xilinx"))
+              (property INIT (string "E0") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT17")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___175___slave_fifo32/fifo64_to_gpmc32_resp/fifo_rst_gpif_rst_OR_155_o1") (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT21")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT31")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT41")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT51")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT61")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___131___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT91")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___131___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___130___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT111")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___130___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___129___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT131")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___129___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___128___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT151")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___128___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT161")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata110")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___81___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata110") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata210 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata210")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___78___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata210") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata310 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata310")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___50___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata310") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata410 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata410")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___77___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata410") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata510 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata510")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___76___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata510") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata65 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata65")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___75___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata65") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata71 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata71")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___74___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata71") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata81 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata81")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___73___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata81") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
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+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata461 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata461")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___70___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata101") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata471 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata471")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___69___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata111") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata481 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata481")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___68___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata131") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata491 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata491")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___67___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata141") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata501 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata501")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___66___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata151") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata511 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata511")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___65___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata161") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata521 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata521")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___64___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata171") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata531 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata531")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___63___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata181") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata541 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata541")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___62___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata191") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata551 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata551")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___61___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata201") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata561 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata561")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___60___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata311") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata571 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata571")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___59___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata211") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata581 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata581")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___58___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata221") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata591 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata591")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___57___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata241") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata601 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata601")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___56___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata251") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata611 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata611")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___55___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata321") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata621 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata621")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___54___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata331") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata631 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata631")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___53___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata351") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata641 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata641")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___52___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata361") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/i_tvalid_o_tready_AND_73_o1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___125___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11") (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1 "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/read1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___47___slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/read1") (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0154_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0154_inv1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___37___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0154_inv1") (owner "Xilinx"))
+              (property INIT (string "DC") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o71")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o61")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o81")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full1021 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___43___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021") (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/write1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___37___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0154_inv1") (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___38___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1") (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<3>1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___39___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11") (owner "Xilinx"))
+              (property INIT (string "FFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_6_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<6>1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid31")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___4___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1") (owner "Xilinx"))
+              (property INIT (string "0455") (owner "Xilinx"))
+            )
+            (instance (rename f1_write11 "f1/write11")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___123___f1/write11") (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename f0_write11 "f0/write11")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___122___f0/write11") (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/read_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "80000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_renamed_33 "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/read")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0111111111111111") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/read_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "80000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read_renamed_34 "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/read")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0111111111111111") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32__n0258_inv_SW0 "slave_fifo32/_n0258_inv_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___121___slave_fifo32/_n0258_inv_SW0") (owner "Xilinx"))
+              (property INIT (string "BF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0 "slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___24___slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0") (owner "Xilinx"))
+              (property INIT (string "D0") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1 "slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "777FF7FFFFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0 "slave_fifo32/Mmux_state[1]_wr_fifo_eof_Mux_22_o1_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___24___slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0") (owner "Xilinx"))
+              (property INIT (string "80008080") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1 "slave_fifo32/Mmux_state[1]_wr_fifo_eof_Mux_22_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2A7F7F7FFFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32__n0279_inv_SW0 "slave_fifo32/_n0279_inv_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___121___slave_fifo32/_n0258_inv_SW0") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32__n0279_inv_renamed_35 "slave_fifo32/_n0279_inv")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0020202008282828") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_state_FSM_FFd1_In4 "slave_fifo32/state_FSM_FFd1-In4")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___176___slave_fifo32/state_FSM_FFd1-In4") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_state_FSM_FFd1_In2_renamed_36 "slave_fifo32/state_FSM_FFd1-In2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2700050022000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_state_FSM_FFd2_In1_renamed_37 "slave_fifo32/state_FSM_FFd2-In1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___177___slave_fifo32/Mcount_idle_cycles_xor<0>11") (owner "Xilinx"))
+              (property INIT (string "8000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_state_FSM_FFd2_In2_renamed_38 "slave_fifo32/state_FSM_FFd2-In2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1054101010101010") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_state_FSM_FFd2_In3 "slave_fifo32/state_FSM_FFd2-In3")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___176___slave_fifo32/state_FSM_FFd1-In4") (owner "Xilinx"))
+              (property INIT (string "FFF4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___7___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx"))
+              (property INIT (string "FFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___5___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx"))
+              (property INIT (string "FFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9CCC9CC6CCCCCCC6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tready_int1_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2F") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tready_int1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00000C0000000800") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_i_tvalid_int1_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_i_tvalid_int1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1555555555555555") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9CCC9CC6CCCCCCC6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tready_int1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "C000000080000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_i_tvalid_int1_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_i_tvalid_int1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1555555555555555") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8000000000000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0102_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___117___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11") (owner "Xilinx"))
+              (property INIT (string "FF57") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___27___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx"))
+              (property INIT (string "FFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_renamed_39 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "04040000FF04FF00") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212_renamed_40 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01212")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0010001000000010") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01214_renamed_41 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01214")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "99900000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01216_renamed_42 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01216")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01219 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01219")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FAF8AA0000000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113_renamed_43 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012113")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114_renamed_44 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012114")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB33A820A820A820") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8A8A8A8A8A8B9A8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tready1_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "80000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tready1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0111111111111111") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___126___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0") (owner "Xilinx"))
+              (property INIT (string "D") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_renamed_45 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___41___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_renamed_46 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00000001FFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCCCCC0F5AF05A") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCCCCCF05A0F5A") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_47 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int11")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int12")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000010005") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14_renamed_48 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int14")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "010F") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int15")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "7FFFFFFFFFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4_renamed_49 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv4")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___33___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11") (owner "Xilinx"))
+              (property INIT (string "A8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31_renamed_50 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In31")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32_renamed_51 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In32")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In33")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FDFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In34")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFB") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFF9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12_renamed_52 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In12")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFAAB9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0102_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___115___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11") (owner "Xilinx"))
+              (property INIT (string "FF57") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___26___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx"))
+              (property INIT (string "FFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_renamed_53 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "04040000FF04FF00") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0010001000000010") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214_renamed_55 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01214")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "99900000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216_renamed_56 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01216")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01219")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FAF8AA0000000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113_renamed_57 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012113")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012114")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB33A820A820A820") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8A8A8A8A8A8B9A8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219_renamed_59 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01219")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AA08880800008008") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___44___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0") (owner "Xilinx"))
+              (property INIT (string "BF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tready1_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "80000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tready1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0111111111111111") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "D") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_renamed_60 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___39___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_renamed_61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00000001FFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCCCCCF0550FAA") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_62 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int11")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0307") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int12")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "7FFFFFFFFFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int13")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F700") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5_renamed_64 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv5")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FB") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In31")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In32")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In33")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FDFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In34")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFB") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11_renamed_67 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___4___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1") (owner "Xilinx"))
+              (property INIT (string "DFDDFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12_renamed_68 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In12")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFBEEEA55514440") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In14")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAAAAAA2A080808") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___118___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11") (owner "Xilinx"))
+              (property INIT (string "FFF9") (owner "Xilinx"))
+            )
+            (instance (rename cat_miso_IBUF_renamed_69 "cat_miso_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename fx3_ce_IBUF_renamed_70 "fx3_ce_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename fx3_mosi_IBUF_renamed_71 "fx3_mosi_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename fx3_sclk_IBUF_renamed_72 "fx3_sclk_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename GPIF_CTL4_IBUF_renamed_73 "GPIF_CTL4_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename GPIF_CTL5_IBUF_renamed_74 "GPIF_CTL5_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename GPIF_CTL9_IBUF_renamed_75 "GPIF_CTL9_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance codec_ctrl_in_3_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance codec_ctrl_in_2_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance codec_ctrl_in_1_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance codec_ctrl_in_0_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename tx_codec_d_11_OBUF_renamed_76 "tx_codec_d_11_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename tx_codec_d_10_OBUF_renamed_77 "tx_codec_d_10_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename tx_codec_d_9_OBUF_renamed_78 "tx_codec_d_9_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename tx_codec_d_8_OBUF_renamed_79 "tx_codec_d_8_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename tx_codec_d_7_OBUF_renamed_80 "tx_codec_d_7_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename tx_codec_d_6_OBUF_renamed_81 "tx_codec_d_6_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename tx_codec_d_5_OBUF_renamed_82 "tx_codec_d_5_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename tx_codec_d_4_OBUF_renamed_83 "tx_codec_d_4_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename tx_codec_d_3_OBUF_renamed_84 "tx_codec_d_3_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename tx_codec_d_2_OBUF_renamed_85 "tx_codec_d_2_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename tx_codec_d_1_OBUF_renamed_86 "tx_codec_d_1_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename tx_codec_d_0_OBUF_renamed_87 "tx_codec_d_0_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_31_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_30_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_29_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_28_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_27_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_26_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_25_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_24_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_23_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_22_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_21_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_20_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_19_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_18_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_17_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_16_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_15_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_14_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_13_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_12_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_11_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_10_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_9_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_8_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_7_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_6_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_5_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_4_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_3_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_2_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_1_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_0_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename debug_clk_1_OBUF_renamed_88 "debug_clk_1_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance debug_clk_0_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance cat_ce_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename cat_mosi_OBUF_renamed_89 "cat_mosi_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename cat_sclk_OBUF_renamed_90 "cat_sclk_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename fx3_miso_OBUF_renamed_91 "fx3_miso_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance pll_ce_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance pll_mosi_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance pll_sclk_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance codec_enable_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance codec_en_agc_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance codec_reset_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance codec_sync_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance codec_txrx_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename codec_fb_clk_p_OBUF_renamed_92 "codec_fb_clk_p_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename tx_frame_p_OBUF_renamed_93 "tx_frame_p_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename IFCLK_OBUF_renamed_94 "IFCLK_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance FX3_EXTINT_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance GPIF_CTL0_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance GPIF_CTL1_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance GPIF_CTL2_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance GPIF_CTL3_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance GPIF_CTL7_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance GPIF_CTL11_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance GPIF_CTL12_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance gps_out_enable_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance gps_ref_enable_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance LED_RX1_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance LED_RX2_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance LED_TXRX1_RX_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance LED_TXRX1_TX_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance LED_TXRX2_RX_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance LED_TXRX2_TX_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance ext_ref_enable_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance pps_fpga_out_enable_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SFDX1_RX_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SFDX1_TX_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SFDX2_RX_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SFDX2_TX_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRX1_RX_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRX1_TX_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRX2_RX_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRX2_TX_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance tx_bandsel_a_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance tx_bandsel_b_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance tx_enable1_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance tx_enable2_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance rx_bandsel_a_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance rx_bandsel_b_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename rx_bandsel_c_OBUF_renamed_95 "rx_bandsel_c_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_renamed_96 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_renamed_97 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_renamed_98 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_renamed_99 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_renamed_100 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_renamed_101 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_renamed_102 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_renamed_103 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/full_reg")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_renamed_104 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_renamed_105 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_renamed_106 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/state")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_renamed_107 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_renamed_108 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_renamed_109 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_renamed_110 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_renamed_111 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_renamed_112 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_renamed_113 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_renamed_114 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/full_reg")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_renamed_115 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_full_reg_renamed_116 "f1/full_reg")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_full_reg_renamed_117 "f0/full_reg")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__rt_renamed_118 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0__rt_renamed_119 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<0>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__rt_renamed_120 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<11>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10__rt_renamed_121 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<10>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9__rt_renamed_122 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<9>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt_renamed_123 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt_renamed_124 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt_renamed_125 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt_renamed_126 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt_renamed_127 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt_renamed_128 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt_renamed_129 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt_renamed_130 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt_renamed_131 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11__rt_renamed_132 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<11>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__rt_renamed_133 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<10>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__rt_renamed_134 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<9>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt_renamed_135 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt_renamed_136 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt_renamed_137 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt_renamed_138 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt_renamed_139 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt_renamed_140 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt_renamed_141 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt_renamed_142 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt_renamed_143 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt_renamed_144 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt_renamed_145 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt_renamed_146 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt_renamed_147 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt_renamed_148 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt_renamed_149 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt_renamed_150 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt_renamed_151 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt_renamed_152 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt_renamed_153 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt_renamed_154 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt_renamed_155 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt_renamed_156 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt_renamed_157 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt_renamed_158 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt_renamed_159 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt_renamed_160 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt_renamed_161 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7__rt_renamed_162 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6__rt_renamed_163 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5__rt_renamed_164 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__rt_renamed_165 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__rt_renamed_166 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2__rt_renamed_167 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__rt_renamed_168 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__rt_renamed_169 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<0>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7__rt_renamed_170 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__rt_renamed_171 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5__rt_renamed_172 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4__rt_renamed_173 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__rt_renamed_174 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__rt_renamed_175 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1__rt_renamed_176 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__rt_renamed_177 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<0>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt_renamed_178 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<0>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__rt_renamed_179 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__rt_renamed_180 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt_renamed_181 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__rt_renamed_182 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt_renamed_183 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt_renamed_184 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt_renamed_185 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt_renamed_186 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt_renamed_187 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt_renamed_188 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__rt_renamed_189 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt_renamed_190 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt_renamed_191 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt_renamed_192 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__rt_renamed_193 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt_renamed_194 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt_renamed_195 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_11__rt_renamed_196 "f1/Mcount_rd_addr_cy<11>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_10__rt_renamed_197 "f1/Mcount_rd_addr_cy<10>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_9__rt_renamed_198 "f1/Mcount_rd_addr_cy<9>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_8__rt_renamed_199 "f1/Mcount_rd_addr_cy<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_7__rt_renamed_200 "f1/Mcount_rd_addr_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_6__rt_renamed_201 "f1/Mcount_rd_addr_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_5__rt_renamed_202 "f1/Mcount_rd_addr_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_4__rt_renamed_203 "f1/Mcount_rd_addr_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_3__rt_renamed_204 "f1/Mcount_rd_addr_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_2__rt_renamed_205 "f1/Mcount_rd_addr_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_cy_1__rt_renamed_206 "f1/Mcount_rd_addr_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_11__rt_renamed_207 "f1/Mcount_wr_addr_cy<11>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_10__rt_renamed_208 "f1/Mcount_wr_addr_cy<10>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_9__rt_renamed_209 "f1/Mcount_wr_addr_cy<9>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_8__rt_renamed_210 "f1/Mcount_wr_addr_cy<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_7__rt_renamed_211 "f1/Mcount_wr_addr_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_6__rt_renamed_212 "f1/Mcount_wr_addr_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_5__rt_renamed_213 "f1/Mcount_wr_addr_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_4__rt_renamed_214 "f1/Mcount_wr_addr_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_3__rt_renamed_215 "f1/Mcount_wr_addr_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_2__rt_renamed_216 "f1/Mcount_wr_addr_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_cy_1__rt_renamed_217 "f1/Mcount_wr_addr_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_cy_1__rt_renamed_218 "f1/Msub_dont_write_past_me_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_cy_0__rt_renamed_219 "f1/Msub_dont_write_past_me_cy<0>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_11__rt_renamed_220 "f0/Mcount_rd_addr_cy<11>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_10__rt_renamed_221 "f0/Mcount_rd_addr_cy<10>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_9__rt_renamed_222 "f0/Mcount_rd_addr_cy<9>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_8__rt_renamed_223 "f0/Mcount_rd_addr_cy<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_7__rt_renamed_224 "f0/Mcount_rd_addr_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_6__rt_renamed_225 "f0/Mcount_rd_addr_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_5__rt_renamed_226 "f0/Mcount_rd_addr_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_4__rt_renamed_227 "f0/Mcount_rd_addr_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_3__rt_renamed_228 "f0/Mcount_rd_addr_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_2__rt_renamed_229 "f0/Mcount_rd_addr_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_cy_1__rt_renamed_230 "f0/Mcount_rd_addr_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_11__rt_renamed_231 "f0/Mcount_wr_addr_cy<11>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_10__rt_renamed_232 "f0/Mcount_wr_addr_cy<10>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_9__rt_renamed_233 "f0/Mcount_wr_addr_cy<9>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_8__rt_renamed_234 "f0/Mcount_wr_addr_cy<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_7__rt_renamed_235 "f0/Mcount_wr_addr_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_6__rt_renamed_236 "f0/Mcount_wr_addr_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_5__rt_renamed_237 "f0/Mcount_wr_addr_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_4__rt_renamed_238 "f0/Mcount_wr_addr_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_3__rt_renamed_239 "f0/Mcount_wr_addr_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_2__rt_renamed_240 "f0/Mcount_wr_addr_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_cy_1__rt_renamed_241 "f0/Mcount_wr_addr_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_cy_1__rt_renamed_242 "f0/Msub_dont_write_past_me_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_cy_0__rt_renamed_243 "f0/Msub_dont_write_past_me_cy<0>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12__rt_renamed_244 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<12>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_12__rt_renamed_245 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<12>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9__rt_renamed_246 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__rt_renamed_247 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__rt_renamed_248 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8__rt_renamed_249 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt_renamed_250 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__rt_renamed_251 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_xor_12__rt_renamed_252 "f1/Mcount_rd_addr_xor<12>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_xor_12__rt_renamed_253 "f1/Mcount_wr_addr_xor<12>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_xor_12__rt_renamed_254 "f0/Mcount_rd_addr_xor<12>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_xor_12__rt_renamed_255 "f0/Mcount_wr_addr_xor<12>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_wr_one_renamed_256 "slave_fifo32/wr_one")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_slrd_renamed_257 "slave_fifo32/slrd")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_rd_one_rstpot "slave_fifo32/rd_one_rstpot")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_renamed_258 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_1_renamed_259 "slave_fifo32/sloe_1")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB_renamed_260 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB_renamed_261 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr2_FRB_renamed_262 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr3_FRB_renamed_263 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr3_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB_renamed_264 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB_renamed_265 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB_renamed_266 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB_renamed_267 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr7_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB_renamed_268 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr8_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB_renamed_269 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr9_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr10_FRB_renamed_270 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr10_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr11_FRB_renamed_271 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr11_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr12_FRB_renamed_272 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr12_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB_renamed_273 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_1__FRB_renamed_274 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<1>_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_2__FRB_renamed_275 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<2>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_3__FRB_renamed_276 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<3>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_4__FRB_renamed_277 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<4>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_5__FRB_renamed_278 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<5>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_6__FRB_renamed_279 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<6>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_7__FRB_renamed_280 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<7>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_8__FRB_renamed_281 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<8>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_9__FRB_renamed_282 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<9>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_10__FRB_renamed_283 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<10>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_11__FRB_renamed_284 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<11>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_12__FRB_renamed_285 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<12>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_0__FRB_renamed_286 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<0>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB_renamed_287 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB_renamed_288 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB_renamed_289 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr3_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr4_FRB_renamed_290 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr4_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB_renamed_291 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr5_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB_renamed_292 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr6_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB_renamed_293 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr7_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB_renamed_294 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr8_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB_renamed_295 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr9_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr10_FRB_renamed_296 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr10_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr11_FRB_renamed_297 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr11_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr12_FRB_renamed_298 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr12_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB_renamed_299 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB_renamed_300 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr2_FRB_renamed_301 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr3_FRB_renamed_302 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr3_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB_renamed_303 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB_renamed_304 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB_renamed_305 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB_renamed_306 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr7_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB_renamed_307 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr8_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB_renamed_308 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr9_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB_renamed_309 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB_renamed_310 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB_renamed_311 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB_renamed_312 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr3_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr4_FRB_renamed_313 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr4_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB_renamed_314 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr5_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB_renamed_315 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr6_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB_renamed_316 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr7_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB_renamed_317 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr8_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB_renamed_318 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr9_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_FRB_renamed_319 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr1_FRB_renamed_320 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr2_FRB_renamed_321 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr3_FRB_renamed_322 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr3_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr4_FRB_renamed_323 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr4_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr5_FRB_renamed_324 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr5_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr6_FRB_renamed_325 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr6_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr7_FRB_renamed_326 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr7_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr8_FRB_renamed_327 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr8_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB_renamed_328 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB_renamed_329 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr2_FRB_renamed_330 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB_renamed_331 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr3_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr4_FRB_renamed_332 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr4_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr5_FRB_renamed_333 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr5_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB_renamed_334 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr6_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr7_FRB_renamed_335 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr7_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB_renamed_336 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr8_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_0_2_FRB_renamed_337 "f1/Result<0>2_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_1_2_FRB_renamed_338 "f1/Result<1>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_2_2_FRB_renamed_339 "f1/Result<2>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_3_2_FRB_renamed_340 "f1/Result<3>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_4_2_FRB_renamed_341 "f1/Result<4>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_5_2_FRB_renamed_342 "f1/Result<5>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_6_2_FRB_renamed_343 "f1/Result<6>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_7_2_FRB_renamed_344 "f1/Result<7>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_8_2_FRB_renamed_345 "f1/Result<8>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_9_2_FRB_renamed_346 "f1/Result<9>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_10_2_FRB_renamed_347 "f1/Result<10>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_11_2_FRB_renamed_348 "f1/Result<11>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_12_2_FRB_renamed_349 "f1/Result<12>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_0_1_FRB_renamed_350 "f1/Result<0>1_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_1_1_FRB_renamed_351 "f1/Result<1>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_2_1_FRB_renamed_352 "f1/Result<2>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_3_1_FRB_renamed_353 "f1/Result<3>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_4_1_FRB_renamed_354 "f1/Result<4>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_5_1_FRB_renamed_355 "f1/Result<5>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_6_1_FRB_renamed_356 "f1/Result<6>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_7_1_FRB_renamed_357 "f1/Result<7>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_8_1_FRB_renamed_358 "f1/Result<8>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_9_1_FRB_renamed_359 "f1/Result<9>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_10_1_FRB_renamed_360 "f1/Result<10>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_11_1_FRB_renamed_361 "f1/Result<11>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Result_12_1_FRB_renamed_362 "f1/Result<12>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_dont_write_past_me_0__FRB_renamed_363 "f1/dont_write_past_me<0>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_dont_write_past_me_1__FRB_renamed_364 "f1/dont_write_past_me<1>_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_dont_write_past_me_2__FRB_renamed_365 "f1/dont_write_past_me<2>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_dont_write_past_me_3__FRB_renamed_366 "f1/dont_write_past_me<3>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_dont_write_past_me_4__FRB_renamed_367 "f1/dont_write_past_me<4>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_dont_write_past_me_5__FRB_renamed_368 "f1/dont_write_past_me<5>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_dont_write_past_me_6__FRB_renamed_369 "f1/dont_write_past_me<6>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_dont_write_past_me_7__FRB_renamed_370 "f1/dont_write_past_me<7>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_dont_write_past_me_8__FRB_renamed_371 "f1/dont_write_past_me<8>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_dont_write_past_me_9__FRB_renamed_372 "f1/dont_write_past_me<9>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_dont_write_past_me_10__FRB_renamed_373 "f1/dont_write_past_me<10>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_dont_write_past_me_11__FRB_renamed_374 "f1/dont_write_past_me<11>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_dont_write_past_me_12__FRB_renamed_375 "f1/dont_write_past_me<12>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_0_2_FRB_renamed_376 "f0/Result<0>2_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_1_2_FRB_renamed_377 "f0/Result<1>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_2_2_FRB_renamed_378 "f0/Result<2>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_3_2_FRB_renamed_379 "f0/Result<3>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_4_2_FRB_renamed_380 "f0/Result<4>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_5_2_FRB_renamed_381 "f0/Result<5>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_6_2_FRB_renamed_382 "f0/Result<6>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_7_2_FRB_renamed_383 "f0/Result<7>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_8_2_FRB_renamed_384 "f0/Result<8>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_9_2_FRB_renamed_385 "f0/Result<9>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_10_2_FRB_renamed_386 "f0/Result<10>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_11_2_FRB_renamed_387 "f0/Result<11>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_12_2_FRB_renamed_388 "f0/Result<12>2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_0_1_FRB_renamed_389 "f0/Result<0>1_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_1_1_FRB_renamed_390 "f0/Result<1>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_2_1_FRB_renamed_391 "f0/Result<2>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_3_1_FRB_renamed_392 "f0/Result<3>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_4_1_FRB_renamed_393 "f0/Result<4>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_5_1_FRB_renamed_394 "f0/Result<5>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_6_1_FRB_renamed_395 "f0/Result<6>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_7_1_FRB_renamed_396 "f0/Result<7>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_8_1_FRB_renamed_397 "f0/Result<8>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_9_1_FRB_renamed_398 "f0/Result<9>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_10_1_FRB_renamed_399 "f0/Result<10>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_11_1_FRB_renamed_400 "f0/Result<11>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Result_12_1_FRB_renamed_401 "f0/Result<12>1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_dont_write_past_me_0__FRB_renamed_402 "f0/dont_write_past_me<0>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_dont_write_past_me_1__FRB_renamed_403 "f0/dont_write_past_me<1>_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_dont_write_past_me_2__FRB_renamed_404 "f0/dont_write_past_me<2>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_dont_write_past_me_3__FRB_renamed_405 "f0/dont_write_past_me<3>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_dont_write_past_me_4__FRB_renamed_406 "f0/dont_write_past_me<4>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_dont_write_past_me_5__FRB_renamed_407 "f0/dont_write_past_me<5>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_dont_write_past_me_6__FRB_renamed_408 "f0/dont_write_past_me<6>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_dont_write_past_me_7__FRB_renamed_409 "f0/dont_write_past_me<7>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_dont_write_past_me_8__FRB_renamed_410 "f0/dont_write_past_me<8>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_dont_write_past_me_9__FRB_renamed_411 "f0/dont_write_past_me<9>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_dont_write_past_me_10__FRB_renamed_412 "f0/dont_write_past_me<10>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_dont_write_past_me_11__FRB_renamed_413 "f0/dont_write_past_me<11>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_dont_write_past_me_12__FRB_renamed_414 "f0/dont_write_past_me<12>_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "55555504FFFFFF5D") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___32___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___32___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0") (owner "Xilinx"))
+              (property INIT (string "F110") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0303CFCF0203DFCF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A9AAA9A9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<3>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A9AAA9A9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "56555656") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___124___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0") (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCCCCCF50A05FA") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFEFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_space_xor<3>111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EFEFEFEEEEEEEEEE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EFEFEFEEEEEEEEEE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "54A855AA55AA55AA") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tvalid11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000FFFF0000FEFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_o_tvalid11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5555555555545555") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid61")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF0001FFFE0000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int16")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0E4D8CC00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___38___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1") (owner "Xilinx"))
+              (property INIT (string "A8EA") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv1_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2_renamed_415 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000023003300") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<9>11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAAAAB9AAAAAAA8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<4>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A9AAA9A9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full621")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFEFEFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full611 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full611")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000100010001") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full621")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFEFEFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full621")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFEFEFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full611")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000100010001") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0EE00FF00FF00FF0") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0021FFFF00FFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int16")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00F7000000F7F7F7") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FB") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000FFFB0004FFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<5>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A9AAA9A9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0121211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0121211")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8282414141418228") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212211")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01212211")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8020401008020401") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0121211")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8282414141418228") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01211_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF05FF04FF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0001FFFF00007FFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int14_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF55FF01FF55FF55") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int14_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF55FF00FF55FF54") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_renamed_417 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FBFBFBFFFB00FB00") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_renamed_418 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FBFBFBFFFB00FB00") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AABAAAAA") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4000FBFF4400FFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___1___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0") (owner "Xilinx"))
+              (property INIT (string "FFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___1___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0") (owner "Xilinx"))
+              (property INIT (string "8000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFB0400FFFA0500") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00FFE8FF17FFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5599665556955695") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF0000FFFF1000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0102_SW1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___27___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx"))
+              (property INIT (string "80") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set_renamed_419 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full_glue_set")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8A8FDA8A8A8A8A8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0102_SW1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___26___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx"))
+              (property INIT (string "80") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set_renamed_420 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full_glue_set")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8A8FDA8A8A8A8A8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_space_xor<3>111_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1111000111111111") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>111_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1111000111111111") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11_SW1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_o_tready_int11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "3333333333323333") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000100000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tlast1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0C0C0C0C0C0D0C0C") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0001") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0404040404040504") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21_SW1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "01") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_tlast1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0C0C0C0C0C0C0D0C") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01217_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01217_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A521") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n012110_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00008400") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set_renamed_421 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/full_reg_glue_set")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF008C008C008C") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E1E1E1E10FF0F00F") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT52")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A9A9A9A9AA5555AA") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set_renamed_422 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump_glue_set")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00400000AAEAAAAA") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int16_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EEEEFEEE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFBF8FFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_cy")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_cy1")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0F0F08877EE11") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFDBFDDBFDFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___43___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021") (owner "Xilinx"))
+              (property INIT (string "EFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FCBFFBEFFC7FF7DF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_renamed_423 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "350035F0") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In12_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In12_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___46___slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1") (owner "Xilinx"))
+              (property INIT (string "D") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In13")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AA3B8819AA2A8808") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In12_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In12_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___47___slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/read1") (owner "Xilinx"))
+              (property INIT (string "D") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In13")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AA3B8819AA2A8808") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<9>11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAAAAB9AAAAAAA8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8000000000000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___29___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111") (owner "Xilinx"))
+              (property INIT (string "FFAEFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___28___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111") (owner "Xilinx"))
+              (property INIT (string "FFAEFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01212111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full621")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFEFEFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111_renamed_424 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2002000000002002") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111_renamed_425 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2002000000002002") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___35___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAAAAAAA9AAAAAA") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "01FE00FF00FF807F") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAA8AAAAAAABAAA") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<5>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "999A999999959999") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5140514055555140") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5140514055555140") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set_renamed_426 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/full_reg_glue_set")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4C4CFF4C4C4C4C4C") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___171___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11") (owner "Xilinx"))
+              (property INIT (string "C8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___169___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11") (owner "Xilinx"))
+              (property INIT (string "C8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217_renamed_427 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01217")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0080000000000080") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217_renamed_428 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01217")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0080000000000080") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv31 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___14___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31") (owner "Xilinx"))
+              (property INIT (string "4500") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___12___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31") (owner "Xilinx"))
+              (property INIT (string "4500") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213_renamed_429 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01213")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9090900000900000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213_renamed_430 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01213")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9090900000900000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_rstpot")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFF0FFFFFF80FF80") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9996") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "7") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_renamed_431 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4141414141411441") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set_renamed_432 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump_glue_set")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00400000AAEAAAAA") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1_SW1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___118___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11") (owner "Xilinx"))
+              (property INIT (string "04") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_0")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int16_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF0D2F087F") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW2")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot_renamed_433 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_0_rstpot")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6AAA595566AA5555") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set_renamed_434 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___120___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set") (owner "Xilinx"))
+              (property INIT (string "FFA2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set_renamed_435 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___119___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set") (owner "Xilinx"))
+              (property INIT (string "FFA2") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0_cy")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11_SW1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "01") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut_renamed_436 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0_lut")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1111111011111111") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_FRB_renamed_437 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB_renamed_438 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr2_FRB_renamed_439 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr3_FRB_renamed_440 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr3_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr4_FRB_renamed_441 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr4_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB_renamed_442 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr5_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB_renamed_443 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr6_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr7_FRB_renamed_444 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr7_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr8_FRB_renamed_445 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr8_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB_renamed_446 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB_renamed_447 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr1_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB_renamed_448 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr2_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB_renamed_449 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr3_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB_renamed_450 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr4_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB_renamed_451 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr5_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr6_FRB_renamed_452 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr6_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB_renamed_453 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr7_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB_renamed_454 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr8_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421_FRB_renamed_455 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411_FRB_renamed_456 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full411_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB_renamed_457 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB_renamed_458 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full411_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB_renamed_459 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB_renamed_460 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB_renamed_461 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full621_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB_renamed_462 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full621_FRB")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB_renamed_463 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218_SW0_FRB")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0_renamed_464 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1_renamed_465 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1_renamed_466 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_13_BRB1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_14_BRB1_renamed_467 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_14_BRB1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15_BRB1_renamed_468 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_15_BRB1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0_renamed_469 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1_renamed_470 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1_renamed_471 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_13_BRB1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1_renamed_472 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_14_BRB1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1_renamed_473 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_15_BRB1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB0_renamed_474 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd2_BRB0")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB1_renamed_475 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd2_BRB1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0_renamed_476 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB0")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1_renamed_477 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_478 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1_renamed_479 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2_renamed_480 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_481 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4_renamed_482 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5_renamed_483 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_484 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1_renamed_485 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2_renamed_486 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_487 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4_renamed_488 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5_renamed_489 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_BRB1_renamed_490 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_11_BRB1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1_renamed_491 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_11_BRB1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1_renamed_492 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_10_BRB1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1_renamed_493 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_10_BRB1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1_renamed_494 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_9_BRB1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1_renamed_495 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_9_BRB1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_17_BRB0_renamed_496 "slave_fifo32/debug1_17_BRB0")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_debug1_16_BRB0_renamed_497 "slave_fifo32/debug1_16_BRB0")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_rd_one_BRB0_renamed_498 "slave_fifo32/rd_one_BRB0")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_rd_one_BRB1_renamed_499 "slave_fifo32/rd_one_BRB1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112_renamed_500 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012112")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8822228C80202084") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112_renamed_501 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012112")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8822228C80202084") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1_renamed_502 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3_renamed_503 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB3")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4_renamed_504 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB4")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv6_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___124___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0") (owner "Xilinx"))
+              (property INIT (string "EEEF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF0C080C0C0C0C") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___16___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1") (owner "Xilinx"))
+              (property INIT (string "5400") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___15___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1") (owner "Xilinx"))
+              (property INIT (string "5400") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1_renamed_505 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF1110FFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/GND_56_o_read_OR_123_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "11101110FFFF1110") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/clear_inv1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut_renamed_506 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000FAFB00000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___13___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1") (owner "Xilinx"))
+              (property INIT (string "2E22") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___10___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1") (owner "Xilinx"))
+              (property INIT (string "2E22") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0146_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFB8FF88") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt__n0074_inv1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/_n0074_inv1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "C60ACC000A0A0000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/_n0074_inv1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "C60ACC000A0A0000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/GND_56_o_read_OR_123_o1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___171___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/GND_66_o_read_OR_144_o1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___169___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename f1__n0161_inv1_lut_renamed_507 "f1/_n0161_inv1_lut")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename f1__n0161_inv1_cy "f1/_n0161_inv1_cy")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1__n0161_inv1_lut1_renamed_508 "f1/_n0161_inv1_lut1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "D") (owner "Xilinx"))
+            )
+            (instance (rename f1__n0161_inv1_cy1 "f1/_n0161_inv1_cy1")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0__n0161_inv1_lut_renamed_509 "f0/_n0161_inv1_lut")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename f0__n0161_inv1_cy "f0/_n0161_inv1_cy")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0__n0161_inv1_lut1_renamed_510 "f0/_n0161_inv1_lut1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "D") (owner "Xilinx"))
+            )
+            (instance (rename f0__n0161_inv1_cy1 "f0/_n0161_inv1_cy1")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFD") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2_G")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFEFFFFFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EEFFFEFFFFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EEFFEFFFFFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFEFFFFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFAAAAFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1_G")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FB") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot_renamed_511 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___0___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot") (owner "Xilinx"))
+              (property INIT (string "FFFF7222") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_wr_one_rstpot_renamed_512 "slave_fifo32/wr_one_rstpot")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___48___slave_fifo32/_n0230_inv1") (owner "Xilinx"))
+              (property INIT (string "EEAAA2AA") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_glue_set_renamed_513 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/state_glue_set")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___16___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1") (owner "Xilinx"))
+              (property INIT (string "A2A6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set_renamed_514 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state_glue_set")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___15___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1") (owner "Xilinx"))
+              (property INIT (string "A2A6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty_glue_rst_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_slrd_rstpot_SW0 "slave_fifo32/slrd_rstpot_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_slrd_rstpot_renamed_515 "slave_fifo32/slrd_rstpot")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AA2AAAFAAA2AFAFA") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_renamed_516 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00000000DD09C000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E178E1E1E1E1E1E1") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E178E1E1E1E1E1E1") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215_renamed_517 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01215")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0220000000000220") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215_renamed_518 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01215")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0220000000000220") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_GND_50_o_read_OR_57_o1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/GND_50_o_read_OR_57_o1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2272") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/GND_50_o_read_OR_57_o1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2272") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF7FFFFFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___22___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (owner "Xilinx"))
+              (property INIT (string "BF4040BF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF7FFFFFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___25___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (owner "Xilinx"))
+              (property INIT (string "BF4040BF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218_renamed_519 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01218")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___116___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921") (owner "Xilinx"))
+              (property INIT (string "0440") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218_renamed_520 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01218")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___114___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921") (owner "Xilinx"))
+              (property INIT (string "0440") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAAAAAAAAAAAAA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAAAAAAAAAAAAA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/clear_inv1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/write1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___120___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set") (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/write1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___119___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set") (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_inv1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0155115501111111") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<0>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<0>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<1>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<1>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<2>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<2>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___3___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (owner "Xilinx"))
+              (property INIT (string "FFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___2___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (owner "Xilinx"))
+              (property INIT (string "FFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAAAAAAAAAAAAA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___126___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0") (owner "Xilinx"))
+              (property INIT (string "CCC9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAAAAAAAAAAAAA9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___35___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") (owner "Xilinx"))
+              (property INIT (string "CCC9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<3>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<3>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<4>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<4>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<5>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<5>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<6>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<6>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<7>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<7>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<8>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<8>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<9>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<9>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<10>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<10>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<11>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<11>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<12>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<12>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<13>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<13>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<14>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<14>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_write1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/write1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000100000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/write1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0001000000000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<15>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<15>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename f1_GND_14_o_read_OR_37_o1 "f1/GND_14_o_read_OR_37_o1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___31___f1/GND_14_o_read_OR_37_o1") (owner "Xilinx"))
+              (property INIT (string "72") (owner "Xilinx"))
+            )
+            (instance (rename f0_GND_14_o_read_OR_37_o1 "f0/GND_14_o_read_OR_37_o1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___30___f0/GND_14_o_read_OR_37_o1") (owner "Xilinx"))
+              (property INIT (string "72") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___180___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1") (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___179___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1") (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51_renamed_521 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAA9AAAA6A696A6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1-In111")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___13___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1") (owner "Xilinx"))
+              (property INIT (string "7F2A") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51_renamed_522 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAA9AAAA6A696A6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1-In111")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___10___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1") (owner "Xilinx"))
+              (property INIT (string "7F2A") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set_renamed_523 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg_glue_set")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___45___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1") (owner "Xilinx"))
+              (property INIT (string "5540FFC0") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1 "slave_fifo32/ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8A8A88820202000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF0040BFBF4000FF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF0040BFBF4000FF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01216_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFF6FFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217_renamed_524 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01217")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "999F999699999990") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A6AAA6A6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A6AAA6A6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<2>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<2>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<6>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<6>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename f1_read_state_FSM_FFd1_In111 "f1/read_state_FSM_FFd1-In111")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___31___f1/GND_14_o_read_OR_37_o1") (owner "Xilinx"))
+              (property INIT (string "FDA8") (owner "Xilinx"))
+            )
+            (instance (rename f0_read_state_FSM_FFd1_In111 "f0/read_state_FSM_FFd1-In111")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___30___f0/GND_14_o_read_OR_37_o1") (owner "Xilinx"))
+              (property INIT (string "FDA8") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0146_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___0___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot") (owner "Xilinx"))
+              (property INIT (string "FFFF8D88") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "59555959") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/GND_66_o_read_OR_144_o1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___44___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___8___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In11") (owner "Xilinx"))
+              (property INIT (string "8A8ADF8A") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___6___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11") (owner "Xilinx"))
+              (property INIT (string "8A8ADF8A") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_renamed_525 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0004FFFF00040004") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_renamed_526 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0004FFFF00040004") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___49___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011") (owner "Xilinx"))
+              (property INIT (string "9F") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_renamed_527 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0020000002200200") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8421000000000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8421000000000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000000000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set_renamed_528 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state_glue_set")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___28___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111") (owner "Xilinx"))
+              (property INIT (string "A9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set_renamed_529 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state_glue_set")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___29___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111") (owner "Xilinx"))
+              (property INIT (string "A9") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0144_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0144_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___8___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In11") (owner "Xilinx"))
+              (property INIT (string "00440F44") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0144_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___6___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11") (owner "Xilinx"))
+              (property INIT (string "00440F44") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF5455FFFF5657") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212_SW1_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___168___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021") (owner "Xilinx"))
+              (property INIT (string "EA") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF66FF69FFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_SW1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set_SW1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___7___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx"))
+              (property INIT (string "FFFF7FFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_renamed_530 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AA8AAA8AFFCFAA8A") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_SW1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full_glue_set_SW1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___5___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx"))
+              (property INIT (string "FFFF7FFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_renamed_531 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full_glue_set")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AA8AAA8AFFCFAA8A") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o1_SW1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1 "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF55555554") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/GND_63_o_space[15]_LessThan_2_o1_SW1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/GND_63_o_space[15]_LessThan_2_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF55555554") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___3___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (owner "Xilinx"))
+              (property INIT (string "8000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___2___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (owner "Xilinx"))
+              (property INIT (string "8000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_write_AND_42_o_inv2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_write_AND_42_o_inv2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFCF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_write_AND_42_o_inv2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFCF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41_renamed_532 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___36___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (owner "Xilinx"))
+              (property INIT (string "9AAAAAA6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41_renamed_533 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___34___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (owner "Xilinx"))
+              (property INIT (string "9AAAAAA6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_1_rstpot_renamed_534 "slave_fifo32/sloe_1_rstpot")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAA2AAAAAAAFFAA") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_renamed_535 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FC55FC54FF55FF55") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_renamed_536 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty_glue_rst")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FC55FC54FF55FF55") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2-In1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "7FFF7F7F2AFF2A2A") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2-In1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "7FFF7F7F2AFF2A2A") (owner "Xilinx"))
+            )
+            (instance (rename f1_read_state_FSM_FFd2_In1 "f1/read_state_FSM_FFd2-In1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FDFDFDFFA8A8A8FF") (owner "Xilinx"))
+            )
+            (instance (rename f0_read_state_FSM_FFd2_In1 "f0/read_state_FSM_FFd2-In1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FDFDFDFFA8A8A8FF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00FBFB0005FBFB05") (owner "Xilinx"))
+            )
+            (instance (rename f1_full_reg_glue_set_renamed_537 "f1/full_reg_glue_set")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___123___f1/write11") (owner "Xilinx"))
+              (property INIT (string "F0FF4044") (owner "Xilinx"))
+            )
+            (instance (rename f0_full_reg_glue_set_renamed_538 "f0/full_reg_glue_set")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___122___f0/write11") (owner "Xilinx"))
+              (property INIT (string "F0FF4044") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___14___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31") (owner "Xilinx"))
+              (property INIT (string "FFFF4B44") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___12___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31") (owner "Xilinx"))
+              (property INIT (string "FFFF4B44") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<15>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<15>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<9>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<9>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<10>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<10>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<11>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<11>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<12>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<12>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<13>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<13>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1_renamed_539 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2_1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_renamed_540 "slave_fifo32/sloe")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_rstpot_renamed_541 "slave_fifo32/sloe_rstpot")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_31_rstpot_renamed_542 "slave_fifo32/gpif_data_out_31_rstpot")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<12>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<11>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<10>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<9>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<8>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<7>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<6>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<5>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<4>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<3>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<2>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<2>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<3>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<4>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<5>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<6>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<7>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<8>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<9>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<10>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<11>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<12>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_rd_addr_lut_0__INV_0 "f1/Mcount_rd_addr_lut<0>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Mcount_wr_addr_lut_0__INV_0 "f1/Mcount_wr_addr_lut<0>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_lut_12__INV_0 "f1/Msub_dont_write_past_me_lut<12>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_lut_11__INV_0 "f1/Msub_dont_write_past_me_lut<11>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_lut_10__INV_0 "f1/Msub_dont_write_past_me_lut<10>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_lut_9__INV_0 "f1/Msub_dont_write_past_me_lut<9>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_lut_8__INV_0 "f1/Msub_dont_write_past_me_lut<8>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_lut_7__INV_0 "f1/Msub_dont_write_past_me_lut<7>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_lut_6__INV_0 "f1/Msub_dont_write_past_me_lut<6>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_lut_5__INV_0 "f1/Msub_dont_write_past_me_lut<5>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_lut_4__INV_0 "f1/Msub_dont_write_past_me_lut<4>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_lut_3__INV_0 "f1/Msub_dont_write_past_me_lut<3>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f1_Msub_dont_write_past_me_lut_2__INV_0 "f1/Msub_dont_write_past_me_lut<2>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_rd_addr_lut_0__INV_0 "f0/Mcount_rd_addr_lut<0>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Mcount_wr_addr_lut_0__INV_0 "f0/Mcount_wr_addr_lut<0>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_lut_12__INV_0 "f0/Msub_dont_write_past_me_lut<12>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_lut_11__INV_0 "f0/Msub_dont_write_past_me_lut<11>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_lut_10__INV_0 "f0/Msub_dont_write_past_me_lut<10>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_lut_9__INV_0 "f0/Msub_dont_write_past_me_lut<9>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_lut_8__INV_0 "f0/Msub_dont_write_past_me_lut<8>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_lut_7__INV_0 "f0/Msub_dont_write_past_me_lut<7>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_lut_6__INV_0 "f0/Msub_dont_write_past_me_lut<6>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_lut_5__INV_0 "f0/Msub_dont_write_past_me_lut<5>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_lut_4__INV_0 "f0/Msub_dont_write_past_me_lut<4>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_lut_3__INV_0 "f0/Msub_dont_write_past_me_lut<3>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_Msub_dont_write_past_me_lut_2__INV_0 "f0/Msub_dont_write_past_me_lut<2>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance gpif_clk_INV_4_o1_INV_0
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_Mcount_fifoadr_xor_0_11_INV_0 "slave_fifo32/Mcount_fifoadr_xor<0>11_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename catcap_data_clk_INV_6_o1_INV_0 "catcap/data_clk_INV_6_o1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<0>11_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<0>11_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<0>11_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv1_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state<0>_inv1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_o_tvalid1_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/o_tvalid1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<0>11_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_0__inv1_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state<0>_inv1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename f0_i_tready1_INV_0 "f0/i_tready1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>_inv_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_state_FSM_FFd1_In3_renamed_543 "slave_fifo32/state_FSM_FFd1-In3")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_state_FSM_FFd1_In3_F "slave_fifo32/state_FSM_FFd1-In3_F")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "80808000") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_state_FSM_FFd1_In3_G "slave_fifo32/state_FSM_FFd1-In3_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "04155555FFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAA2A22FFAA7F22") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A2AAA6A6F7FFA6A6") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFF5554") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1_G")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EFEEEFEEEFEEFFFF") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "54555454FCFFFCFC") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_slrd2_1_renamed_544 "slave_fifo32/slrd2_1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_EP_WMARK1_1_renamed_545 "slave_fifo32/EP_WMARK1_1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_EP_READY1_1_renamed_546 "slave_fifo32/EP_READY1_1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_31_1_renamed_547 "slave_fifo32/gpif_data_out_31_1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_slwr_1_renamed_548 "slave_fifo32/slwr_1")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_34_renamed_549 "slave_fifo32/sloe_34")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_slrd_1_renamed_550 "slave_fifo32/slrd_1")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_pktend_1_renamed_551 "slave_fifo32/pktend_1")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifoadr_1_1_renamed_552 "slave_fifo32/fifoadr_1_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifoadr_0_1_renamed_553 "slave_fifo32/fifoadr_0_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance GPIF_D_31_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_33_renamed_554 "slave_fifo32/sloe_33")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_31 "slave_fifo32/gpif_data_out_31")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_30_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_32_renamed_555 "slave_fifo32/sloe_32")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_30 "slave_fifo32/gpif_data_out_30")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_29_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_31_renamed_556 "slave_fifo32/sloe_31")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_29 "slave_fifo32/gpif_data_out_29")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_28_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_30_renamed_557 "slave_fifo32/sloe_30")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_28 "slave_fifo32/gpif_data_out_28")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_27_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_29_renamed_558 "slave_fifo32/sloe_29")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_27 "slave_fifo32/gpif_data_out_27")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_26_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_28_renamed_559 "slave_fifo32/sloe_28")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_26 "slave_fifo32/gpif_data_out_26")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_25_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_27_renamed_560 "slave_fifo32/sloe_27")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_25 "slave_fifo32/gpif_data_out_25")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_24_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_26_renamed_561 "slave_fifo32/sloe_26")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_24 "slave_fifo32/gpif_data_out_24")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_23_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_25_renamed_562 "slave_fifo32/sloe_25")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_23 "slave_fifo32/gpif_data_out_23")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_22_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_24_renamed_563 "slave_fifo32/sloe_24")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_22 "slave_fifo32/gpif_data_out_22")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_21_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_23_renamed_564 "slave_fifo32/sloe_23")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_21 "slave_fifo32/gpif_data_out_21")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_20_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_22_renamed_565 "slave_fifo32/sloe_22")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_20 "slave_fifo32/gpif_data_out_20")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_19_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_21_renamed_566 "slave_fifo32/sloe_21")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_19 "slave_fifo32/gpif_data_out_19")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_18_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_20_renamed_567 "slave_fifo32/sloe_20")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_18 "slave_fifo32/gpif_data_out_18")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_17_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_19_renamed_568 "slave_fifo32/sloe_19")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_17 "slave_fifo32/gpif_data_out_17")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_16_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_18_renamed_569 "slave_fifo32/sloe_18")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_16 "slave_fifo32/gpif_data_out_16")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_15_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_17_renamed_570 "slave_fifo32/sloe_17")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_15 "slave_fifo32/gpif_data_out_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_14_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_16_renamed_571 "slave_fifo32/sloe_16")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_14 "slave_fifo32/gpif_data_out_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_13_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_15_renamed_572 "slave_fifo32/sloe_15")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_13 "slave_fifo32/gpif_data_out_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_12_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_14_renamed_573 "slave_fifo32/sloe_14")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_12 "slave_fifo32/gpif_data_out_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_11_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_13_renamed_574 "slave_fifo32/sloe_13")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_11 "slave_fifo32/gpif_data_out_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_10_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_12_renamed_575 "slave_fifo32/sloe_12")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_10 "slave_fifo32/gpif_data_out_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_9_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_11_renamed_576 "slave_fifo32/sloe_11")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_9 "slave_fifo32/gpif_data_out_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_8_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_10_renamed_577 "slave_fifo32/sloe_10")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_8 "slave_fifo32/gpif_data_out_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_7_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_9_renamed_578 "slave_fifo32/sloe_9")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_7 "slave_fifo32/gpif_data_out_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_6_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_8_renamed_579 "slave_fifo32/sloe_8")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_6 "slave_fifo32/gpif_data_out_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_5_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_7_renamed_580 "slave_fifo32/sloe_7")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_5 "slave_fifo32/gpif_data_out_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_4_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_6_renamed_581 "slave_fifo32/sloe_6")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_4 "slave_fifo32/gpif_data_out_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_3_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_5_renamed_582 "slave_fifo32/sloe_5")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_3 "slave_fifo32/gpif_data_out_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_2_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_4_renamed_583 "slave_fifo32/sloe_4")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_2 "slave_fifo32/gpif_data_out_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_1_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_3_renamed_584 "slave_fifo32/sloe_3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_1 "slave_fifo32/gpif_data_out_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance GPIF_D_0_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_sloe_2_renamed_585 "slave_fifo32/sloe_2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_gpif_data_out_0 "slave_fifo32/gpif_data_out_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property IOB (string "true") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram17")
+              (viewRef view_1 (cellRef RAMB8BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "13:INPUT:ADDRAWRADDR<12:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "13:INPUT:ADDRBRDADDR<12:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "2:OUTPUT:DOPADOP<1:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "2:OUTPUT:DOPBDOP<1:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "2:INPUT:DIPBDIP<1:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "2:INPUT:DIPADIP<1:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "2:INPUT:WEAWEL<1:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "2:INPUT:WEBWEU<1:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "16:OUTPUT:DOADO<15:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "16:INPUT:DIBDI<15:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "16:INPUT:DIADI<15:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "16:OUTPUT:DOBDO<15:0>") (owner "Xilinx"))
+              (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_10 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_11 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_12 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_13 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_14 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_15 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_16 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_17 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_18 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_19 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property WRITE_MODE_A (string "READ_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
+              (property DATA_WIDTH_A (integer 1) (owner "Xilinx"))
+              (property DATA_WIDTH_B (integer 1) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx"))
+              (property EN_RSTRAM_B (string "TRUE") (owner "Xilinx"))
+              (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_A (string "00000") (owner "Xilinx"))
+              (property INIT_B (string "00000") (owner "Xilinx"))
+              (property RAM_MODE (string "TDP") (owner "Xilinx"))
+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
+              (property RSTTYPE (string "SYNC") (owner "Xilinx"))
+              (property SRVAL_A (string "00000") (owner "Xilinx"))
+              (property SRVAL_B (string "00000") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram16")
+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIA<31:0>") (owner "Xilinx"))
+              (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
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+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
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+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
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+              (property INIT_3F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property WRITE_MODE_A (string "READ_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
+              (property DATA_WIDTH_A (integer 2) (owner "Xilinx"))
+              (property DATA_WIDTH_B (integer 2) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx"))
+              (property EN_RSTRAM_B (string "TRUE") (owner "Xilinx"))
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+              (property INIT_A (string "000000000") (owner "Xilinx"))
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+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
+              (property RSTTYPE (string "SYNC") (owner "Xilinx"))
+              (property SRVAL_A (string "000000000") (owner "Xilinx"))
+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
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+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIA<31:0>") (owner "Xilinx"))
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+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
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+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
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+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
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+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
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+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
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+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
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+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
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+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
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+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
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+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
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+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
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+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
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+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
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+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
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+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
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+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
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+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
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+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
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+              (property WRITE_MODE_A (string "READ_FIRST") (owner "Xilinx"))
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+              (property DATA_WIDTH_B (integer 2) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx"))
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+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
+              (property RSTTYPE (string "SYNC") (owner "Xilinx"))
+              (property SRVAL_A (string "000000000") (owner "Xilinx"))
+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram7")
+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIA<31:0>") (owner "Xilinx"))
+              (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_10 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_12 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_13 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_14 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_15 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_16 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_17 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_18 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_19 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_20 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_21 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_22 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_23 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_24 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_25 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_28 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_29 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_30 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_31 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_39 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property WRITE_MODE_A (string "READ_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
+              (property DATA_WIDTH_A (integer 2) (owner "Xilinx"))
+              (property DATA_WIDTH_B (integer 2) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx"))
+              (property EN_RSTRAM_B (string "TRUE") (owner "Xilinx"))
+              (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_05 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_A (string "000000000") (owner "Xilinx"))
+              (property INIT_B (string "000000000") (owner "Xilinx"))
+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
+              (property RSTTYPE (string "SYNC") (owner "Xilinx"))
+              (property SRVAL_A (string "000000000") (owner "Xilinx"))
+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram8")
+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIA<31:0>") (owner "Xilinx"))
+              (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_10 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_11 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_12 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_13 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_14 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_15 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_16 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_17 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_18 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_19 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_20 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_21 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_22 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_24 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_25 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_29 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_30 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_31 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_3A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property WRITE_MODE_A (string "READ_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
+              (property DATA_WIDTH_A (integer 2) (owner "Xilinx"))
+              (property DATA_WIDTH_B (integer 2) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx"))
+              (property EN_RSTRAM_B (string "TRUE") (owner "Xilinx"))
+              (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_05 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_A (string "000000000") (owner "Xilinx"))
+              (property INIT_B (string "000000000") (owner "Xilinx"))
+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
+              (property RSTTYPE (string "SYNC") (owner "Xilinx"))
+              (property SRVAL_A (string "000000000") (owner "Xilinx"))
+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram9")
+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIA<31:0>") (owner "Xilinx"))
+              (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_12 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_13 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_15 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_16 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_17 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_18 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_19 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_20 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_21 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_22 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_23 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_24 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_25 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_26 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_27 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_28 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_29 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_30 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_31 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_36 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_37 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_38 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_39 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property WRITE_MODE_A (string "READ_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
+              (property DATA_WIDTH_A (integer 2) (owner "Xilinx"))
+              (property DATA_WIDTH_B (integer 2) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx"))
+              (property EN_RSTRAM_B (string "TRUE") (owner "Xilinx"))
+              (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_05 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_A (string "000000000") (owner "Xilinx"))
+              (property INIT_B (string "000000000") (owner "Xilinx"))
+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
+              (property RSTTYPE (string "SYNC") (owner "Xilinx"))
+              (property SRVAL_A (string "000000000") (owner "Xilinx"))
+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram12")
+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
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+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
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+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
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+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIA<31:0>") (owner "Xilinx"))
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+              (property WRITE_MODE_A (string "READ_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
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+              (property DATA_WIDTH_B (integer 2) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx"))
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+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
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+              (property SRVAL_A (string "000000000") (owner "Xilinx"))
+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
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+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIA<31:0>") (owner "Xilinx"))
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+              (property INIT_3E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property WRITE_MODE_A (string "READ_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
+              (property DATA_WIDTH_A (integer 2) (owner "Xilinx"))
+              (property DATA_WIDTH_B (integer 2) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx"))
+              (property EN_RSTRAM_B (string "TRUE") (owner "Xilinx"))
+              (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INITP_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_A (string "000000000") (owner "Xilinx"))
+              (property INIT_B (string "000000000") (owner "Xilinx"))
+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
+              (property RSTTYPE (string "SYNC") (owner "Xilinx"))
+              (property SRVAL_A (string "000000000") (owner "Xilinx"))
+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram13")
+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
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+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
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+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
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+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIA<31:0>") (owner "Xilinx"))
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+              (property WRITE_MODE_A (string "READ_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
+              (property DATA_WIDTH_A (integer 2) (owner "Xilinx"))
+              (property DATA_WIDTH_B (integer 2) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx"))
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+              (property INIT_B (string "000000000") (owner "Xilinx"))
+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
+              (property RSTTYPE (string "SYNC") (owner "Xilinx"))
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+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
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+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIA<31:0>") (owner "Xilinx"))
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+              (property INIT_3C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_3E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property WRITE_MODE_A (string "READ_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
+              (property DATA_WIDTH_A (integer 2) (owner "Xilinx"))
+              (property DATA_WIDTH_B (integer 2) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx"))
+              (property EN_RSTRAM_B (string "TRUE") (owner "Xilinx"))
+              (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_A (string "000000000") (owner "Xilinx"))
+              (property INIT_B (string "000000000") (owner "Xilinx"))
+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
+              (property RSTTYPE (string "SYNC") (owner "Xilinx"))
+              (property SRVAL_A (string "000000000") (owner "Xilinx"))
+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram16")
+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIA<31:0>") (owner "Xilinx"))
+              (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property DOB_REG (integer 0) (owner "Xilinx"))
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+              (property RAM_MODE (string "TDP") (owner "Xilinx"))
+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
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+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
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+            (instance (rename f0_ram_Mram_ram31 "f0/ram/Mram_ram31")
+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIA<31:0>") (owner "Xilinx"))
+              (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_10 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_11 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_12 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_13 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_14 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_15 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_16 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_17 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_18 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_19 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_20 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_21 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_22 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_23 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_24 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_25 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_26 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_27 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_28 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_29 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_30 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_31 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_32 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_33 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_34 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_35 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_36 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_37 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_38 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_39 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property WRITE_MODE_A (string "READ_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
+              (property DATA_WIDTH_A (integer 2) (owner "Xilinx"))
+              (property DATA_WIDTH_B (integer 2) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx"))
+              (property EN_RSTRAM_B (string "TRUE") (owner "Xilinx"))
+              (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_05 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_A (string "000000000") (owner "Xilinx"))
+              (property INIT_B (string "000000000") (owner "Xilinx"))
+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
+              (property RSTTYPE (string "SYNC") (owner "Xilinx"))
+              (property SRVAL_A (string "000000000") (owner "Xilinx"))
+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
+            )
+            (instance (rename f0_ram_Mram_ram30 "f0/ram/Mram_ram30")
+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIA<31:0>") (owner "Xilinx"))
+              (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_10 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_11 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_12 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_13 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_14 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_15 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_16 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_17 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_18 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_19 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_20 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_21 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_22 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_23 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_24 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_25 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_26 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_27 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_28 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_29 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_30 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_31 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_32 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_33 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_35 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_37 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_38 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_39 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property WRITE_MODE_A (string "READ_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
+              (property DATA_WIDTH_A (integer 2) (owner "Xilinx"))
+              (property DATA_WIDTH_B (integer 2) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx"))
+              (property EN_RSTRAM_B (string "TRUE") (owner "Xilinx"))
+              (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_05 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_A (string "000000000") (owner "Xilinx"))
+              (property INIT_B (string "000000000") (owner "Xilinx"))
+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
+              (property RSTTYPE (string "SYNC") (owner "Xilinx"))
+              (property SRVAL_A (string "000000000") (owner "Xilinx"))
+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
+            )
+            (instance (rename f0_ram_Mram_ram32 "f0/ram/Mram_ram32")
+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIA<31:0>") (owner "Xilinx"))
+              (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_10 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_11 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_12 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_13 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_14 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_15 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_16 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_17 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_18 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_19 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_1F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_20 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_21 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_22 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_23 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_24 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_25 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_26 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_27 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_28 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_29 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_2F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_30 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_31 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_33 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
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+              (property INIT_35 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_36 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_37 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_38 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_39 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property WRITE_MODE_A (string "READ_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
+              (property DATA_WIDTH_A (integer 2) (owner "Xilinx"))
+              (property DATA_WIDTH_B (integer 2) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx"))
+              (property EN_RSTRAM_B (string "TRUE") (owner "Xilinx"))
+              (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_05 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_A (string "000000000") (owner "Xilinx"))
+              (property INIT_B (string "000000000") (owner "Xilinx"))
+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
+              (property RSTTYPE (string "SYNC") (owner "Xilinx"))
+              (property SRVAL_A (string "000000000") (owner "Xilinx"))
+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
+            )
+            (instance (rename f0_ram_Mram_ram28 "f0/ram/Mram_ram28")
+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
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+              (property INIT_2F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_30 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_31 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_32 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_33 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_34 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_35 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_36 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_37 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_38 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_39 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3A (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3B (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3C (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3D (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3E (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_3F (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property WRITE_MODE_A (string "READ_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
+              (property DATA_WIDTH_A (integer 2) (owner "Xilinx"))
+              (property DATA_WIDTH_B (integer 2) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx"))
+              (property EN_RSTRAM_B (string "TRUE") (owner "Xilinx"))
+              (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_05 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_A (string "000000000") (owner "Xilinx"))
+              (property INIT_B (string "000000000") (owner "Xilinx"))
+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
+              (property RSTTYPE (string "SYNC") (owner "Xilinx"))
+              (property SRVAL_A (string "000000000") (owner "Xilinx"))
+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/fifo_4k_2clk")
+              (viewRef view_1 (cellRef fifo_4k_2clk (libraryRef b200_lib)))
+              (property BUS_INFO (string "72:INPUT:din<71:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "72:OUTPUT:dout<71:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "10:OUTPUT:rd_data_count<9:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/fifo_4k_2clk")
+              (viewRef view_1 (cellRef fifo_4k_2clk (libraryRef b200_lib)))
+              (property BUS_INFO (string "72:INPUT:din<71:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "72:OUTPUT:dout<71:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "10:OUTPUT:rd_data_count<9:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/fifo_4k_2clk")
+              (viewRef view_1 (cellRef fifo_4k_2clk (libraryRef b200_lib)))
+              (property BUS_INFO (string "72:INPUT:din<71:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "72:OUTPUT:dout<71:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "10:OUTPUT:rd_data_count<9:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>") (owner "Xilinx"))
+            )
+            (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/fifo_4k_2clk")
+              (viewRef view_1 (cellRef fifo_4k_2clk (libraryRef b200_lib)))
+              (property BUS_INFO (string "72:INPUT:din<71:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "72:OUTPUT:dout<71:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "10:OUTPUT:rd_data_count<9:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>") (owner "Xilinx"))
+            )
+            (net cat_miso_IBUF
+              (joined
+                (portRef I1 (instanceRef fx3_miso1))
+                (portRef O (instanceRef cat_miso_IBUF_renamed_69))
+              )
+            )
+            (net fx3_ce_IBUF
+              (joined
+                (portRef I0 (instanceRef fx3_miso1))
+                (portRef I0 (instanceRef cat_mosi1))
+                (portRef I0 (instanceRef cat_sclk1))
+                (portRef O (instanceRef fx3_ce_IBUF_renamed_70))
+              )
+            )
+            (net fx3_mosi_IBUF
+              (joined
+                (portRef I1 (instanceRef cat_mosi1))
+                (portRef O (instanceRef fx3_mosi_IBUF_renamed_71))
+              )
+            )
+            (net fx3_sclk_IBUF
+              (joined
+                (portRef I1 (instanceRef cat_sclk1))
+                (portRef O (instanceRef fx3_sclk_IBUF_renamed_72))
+              )
+            )
+            (net codec_data_clk_p
+              (joined
+                (portRef codec_data_clk_p)
+                (portRef I (instanceRef codec_data_clk_bufg))
+              )
+            )
+            (net codec_main_clk_p
+              (joined
+                (portRef codec_main_clk_p)
+                (portRef I (instanceRef gen_clks_clkin1_buf))
+              )
+            )
+            (net codec_main_clk_n
+              (joined
+                (portRef codec_main_clk_n)
+                (portRef IB (instanceRef gen_clks_clkin1_buf))
+              )
+            )
+            (net GPIF_CTL4_IBUF
+              (joined
+                (portRef D (instanceRef slave_fifo32_EP_READY_renamed_13))
+                (portRef O (instanceRef GPIF_CTL4_IBUF_renamed_73))
+              )
+            )
+            (net GPIF_CTL5_IBUF
+              (joined
+                (portRef D (instanceRef slave_fifo32_EP_WMARK_renamed_16))
+                (portRef O (instanceRef GPIF_CTL5_IBUF_renamed_74))
+              )
+            )
+            (net GPIF_CTL9_IBUF
+              (joined
+                (portRef RST (instanceRef gen_clks_dcm_sp_inst))
+                (portRef I1 (instanceRef reset_global_locked_OR_1_o1))
+                (portRef O (instanceRef GPIF_CTL9_IBUF_renamed_75))
+              )
+            )
+            (net fx3_miso_OBUF
+              (joined
+                (portRef O (instanceRef fx3_miso1))
+                (portRef I (instanceRef fx3_miso_OBUF_renamed_91))
+              )
+            )
+            (net cat_mosi_OBUF
+              (joined
+                (portRef O (instanceRef cat_mosi1))
+                (portRef I (instanceRef cat_mosi_OBUF_renamed_89))
+              )
+            )
+            (net cat_sclk_OBUF
+              (joined
+                (portRef O (instanceRef cat_sclk1))
+                (portRef I (instanceRef cat_sclk_OBUF_renamed_90))
+              )
+            )
+            (net codec_data_clk
+              (joined
+                (portRef O (instanceRef codec_data_clk_bufg))
+                (portRef C0 (instanceRef catgen_gen_pins_0__oddr2))
+                (portRef C0 (instanceRef catgen_gen_pins_1__oddr2))
+                (portRef C0 (instanceRef catgen_gen_pins_2__oddr2))
+                (portRef C0 (instanceRef catgen_gen_pins_3__oddr2))
+                (portRef C0 (instanceRef catgen_gen_pins_4__oddr2))
+                (portRef C0 (instanceRef catgen_gen_pins_5__oddr2))
+                (portRef C0 (instanceRef catgen_gen_pins_6__oddr2))
+                (portRef C0 (instanceRef catgen_gen_pins_7__oddr2))
+                (portRef C0 (instanceRef catgen_gen_pins_8__oddr2))
+                (portRef C0 (instanceRef catgen_gen_pins_9__oddr2))
+                (portRef C0 (instanceRef catgen_gen_pins_10__oddr2))
+                (portRef C0 (instanceRef catgen_gen_pins_11__oddr2))
+                (portRef C0 (instanceRef catgen_oddr2_frame))
+                (portRef C0 (instanceRef catgen_oddr2_clk))
+                (portRef I (instanceRef debug_clk_0_OBUF))
+                (portRef I (instanceRef catcap_data_clk_INV_6_o1_INV_0))
+              )
+            )
+            (net gpif_clk
+              (joined
+                (portRef C (instanceRef gpif_sync_reset_int_renamed_3))
+                (portRef C (instanceRef gpif_sync_reset_out_renamed_2))
+                (portRef C0 (instanceRef ODDR2_ifclk))
+                (portRef C0 (instanceRef ODDR2_ifclk_dbg))
+                (portRef O (instanceRef gen_clks_clkout2_buf))
+                (portRef C (instanceRef slave_fifo32_EP_WMARK_renamed_16))
+                (portRef C (instanceRef slave_fifo32_read_ready_go_renamed_15))
+                (portRef C (instanceRef slave_fifo32_write_ready_go_renamed_14))
+                (portRef C (instanceRef slave_fifo32_EP_READY_renamed_13))
+                (portRef C (instanceRef slave_fifo32_EP_READY1_renamed_12))
+                (portRef C (instanceRef slave_fifo32_EP_WMARK1_renamed_11))
+                (portRef C (instanceRef slave_fifo32_slrd1_renamed_10))
+                (portRef C (instanceRef slave_fifo32_slrd2_renamed_9))
+                (portRef C (instanceRef slave_fifo32_slrd3_renamed_8))
+                (portRef C (instanceRef slave_fifo32_slwr_renamed_7))
+                (portRef C (instanceRef slave_fifo32_pktend_renamed_6))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_0))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_1))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_2))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_3))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_4))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_5))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_6))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_7))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_8))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_9))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_10))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_11))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_12))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_13))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_14))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_15))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_16))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_17))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_18))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_19))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_20))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_21))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_22))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_23))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_24))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_25))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_26))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_27))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_28))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_29))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_30))
+                (portRef C (instanceRef slave_fifo32_gpif_data_in_31))
+                (portRef C (instanceRef slave_fifo32_debug1_0))
+                (portRef C (instanceRef slave_fifo32_debug1_1))
+                (portRef C (instanceRef slave_fifo32_debug1_2))
+                (portRef C (instanceRef slave_fifo32_debug1_3))
+                (portRef C (instanceRef slave_fifo32_debug1_4))
+                (portRef C (instanceRef slave_fifo32_debug1_5))
+                (portRef C (instanceRef slave_fifo32_debug1_6))
+                (portRef C (instanceRef slave_fifo32_debug1_7))
+                (portRef C (instanceRef slave_fifo32_debug1_8))
+                (portRef C (instanceRef slave_fifo32_debug1_9))
+                (portRef C (instanceRef slave_fifo32_debug1_10))
+                (portRef C (instanceRef slave_fifo32_debug1_11))
+                (portRef C (instanceRef slave_fifo32_debug1_12))
+                (portRef C (instanceRef slave_fifo32_debug1_13))
+                (portRef C (instanceRef slave_fifo32_debug1_14))
+                (portRef C (instanceRef slave_fifo32_debug1_15))
+                (portRef C (instanceRef slave_fifo32_debug1_18))
+                (portRef C (instanceRef slave_fifo32_debug1_19))
+                (portRef C (instanceRef slave_fifo32_debug1_21))
+                (portRef C (instanceRef slave_fifo32_debug1_22))
+                (portRef C (instanceRef slave_fifo32_debug1_23))
+                (portRef C (instanceRef slave_fifo32_debug1_26))
+                (portRef C (instanceRef slave_fifo32_debug1_27))
+                (portRef C (instanceRef slave_fifo32_debug1_28))
+                (portRef C (instanceRef slave_fifo32_debug1_29))
+                (portRef C (instanceRef slave_fifo32_debug1_31))
+                (portRef C (instanceRef slave_fifo32_debug2_0))
+                (portRef C (instanceRef slave_fifo32_debug2_1))
+                (portRef C (instanceRef slave_fifo32_debug2_2))
+                (portRef C (instanceRef slave_fifo32_debug2_3))
+                (portRef C (instanceRef slave_fifo32_debug2_4))
+                (portRef C (instanceRef slave_fifo32_debug2_5))
+                (portRef C (instanceRef slave_fifo32_debug2_6))
+                (portRef C (instanceRef slave_fifo32_debug2_7))
+                (portRef C (instanceRef slave_fifo32_debug2_8))
+                (portRef C (instanceRef slave_fifo32_debug2_9))
+                (portRef C (instanceRef slave_fifo32_debug2_10))
+                (portRef C (instanceRef slave_fifo32_debug2_11))
+                (portRef C (instanceRef slave_fifo32_debug2_12))
+                (portRef C (instanceRef slave_fifo32_debug2_13))
+                (portRef C (instanceRef slave_fifo32_debug2_14))
+                (portRef C (instanceRef slave_fifo32_debug2_15))
+                (portRef C (instanceRef slave_fifo32_debug2_16))
+                (portRef C (instanceRef slave_fifo32_debug2_17))
+                (portRef C (instanceRef slave_fifo32_debug2_18))
+                (portRef C (instanceRef slave_fifo32_debug2_19))
+                (portRef C (instanceRef slave_fifo32_debug2_21))
+                (portRef C (instanceRef slave_fifo32_debug2_22))
+                (portRef C (instanceRef slave_fifo32_debug2_23))
+                (portRef C (instanceRef slave_fifo32_debug2_26))
+                (portRef C (instanceRef slave_fifo32_debug2_27))
+                (portRef C (instanceRef slave_fifo32_debug2_28))
+                (portRef C (instanceRef slave_fifo32_debug2_29))
+                (portRef C (instanceRef slave_fifo32_debug2_31))
+                (portRef C (instanceRef slave_fifo32_state_FSM_FFd2_renamed_5))
+                (portRef C (instanceRef slave_fifo32_state_FSM_FFd1_renamed_4))
+                (portRef C (instanceRef slave_fifo32_fifoadr_0))
+                (portRef C (instanceRef slave_fifo32_fifoadr_1))
+                (portRef C (instanceRef slave_fifo32_idle_cycles_0))
+                (portRef C (instanceRef slave_fifo32_idle_cycles_1))
+                (portRef C (instanceRef slave_fifo32_idle_cycles_2))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_0))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_1))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_2))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_3))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_4))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_5))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_6))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_0))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_2))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_3))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_4))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_5))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_6))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_7))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_8))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_9))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_10))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_11))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_12))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_renamed_18))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_0))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_1))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_2))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_3))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_4))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_5))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_6))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_7))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_8))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_9))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_10))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_11))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_12))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_renamed_17))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7))
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+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB_renamed_334))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr7_FRB_renamed_335))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB_renamed_336))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_FRB_renamed_437))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB_renamed_438))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr2_FRB_renamed_439))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr3_FRB_renamed_440))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr4_FRB_renamed_441))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB_renamed_442))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB_renamed_443))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr7_FRB_renamed_444))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr8_FRB_renamed_445))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB_renamed_446))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB_renamed_447))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB_renamed_448))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB_renamed_449))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB_renamed_450))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB_renamed_451))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr6_FRB_renamed_452))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB_renamed_453))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB_renamed_454))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421_FRB_renamed_455))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411_FRB_renamed_456))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB_renamed_457))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB_renamed_458))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB_renamed_459))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB_renamed_460))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB_renamed_461))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB_renamed_462))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0_renamed_464))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1_renamed_465))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1_renamed_466))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_14_BRB1_renamed_467))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15_BRB1_renamed_468))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0_renamed_469))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1_renamed_470))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1_renamed_471))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1_renamed_472))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1_renamed_473))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB0_renamed_474))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB1_renamed_475))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0_renamed_476))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1_renamed_477))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_BRB1_renamed_490))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1_renamed_491))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1_renamed_492))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1_renamed_493))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1_renamed_494))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1_renamed_495))
+                (portRef C (instanceRef slave_fifo32_debug1_17_BRB0_renamed_496))
+                (portRef C (instanceRef slave_fifo32_debug1_16_BRB0_renamed_497))
+                (portRef C (instanceRef slave_fifo32_rd_one_BRB0_renamed_498))
+                (portRef C (instanceRef slave_fifo32_rd_one_BRB1_renamed_499))
+                (portRef C (instanceRef slave_fifo32_sloe_renamed_540))
+                (portRef I (instanceRef gpif_clk_INV_4_o1_INV_0))
+                (portRef C (instanceRef slave_fifo32_slrd2_1_renamed_544))
+                (portRef C (instanceRef slave_fifo32_EP_WMARK1_1_renamed_545))
+                (portRef C (instanceRef slave_fifo32_EP_READY1_1_renamed_546))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_31_1_renamed_547))
+                (portRef C (instanceRef slave_fifo32_slwr_1_renamed_548))
+                (portRef C (instanceRef slave_fifo32_sloe_34_renamed_549))
+                (portRef C (instanceRef slave_fifo32_slrd_1_renamed_550))
+                (portRef C (instanceRef slave_fifo32_pktend_1_renamed_551))
+                (portRef C (instanceRef slave_fifo32_fifoadr_1_1_renamed_552))
+                (portRef C (instanceRef slave_fifo32_fifoadr_0_1_renamed_553))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_31))
+                (portRef C (instanceRef slave_fifo32_sloe_33_renamed_554))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_30))
+                (portRef C (instanceRef slave_fifo32_sloe_32_renamed_555))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_29))
+                (portRef C (instanceRef slave_fifo32_sloe_31_renamed_556))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_28))
+                (portRef C (instanceRef slave_fifo32_sloe_30_renamed_557))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_27))
+                (portRef C (instanceRef slave_fifo32_sloe_29_renamed_558))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_26))
+                (portRef C (instanceRef slave_fifo32_sloe_28_renamed_559))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_25))
+                (portRef C (instanceRef slave_fifo32_sloe_27_renamed_560))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_24))
+                (portRef C (instanceRef slave_fifo32_sloe_26_renamed_561))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_23))
+                (portRef C (instanceRef slave_fifo32_sloe_25_renamed_562))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_22))
+                (portRef C (instanceRef slave_fifo32_sloe_24_renamed_563))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_21))
+                (portRef C (instanceRef slave_fifo32_sloe_23_renamed_564))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_20))
+                (portRef C (instanceRef slave_fifo32_sloe_22_renamed_565))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_19))
+                (portRef C (instanceRef slave_fifo32_sloe_21_renamed_566))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_18))
+                (portRef C (instanceRef slave_fifo32_sloe_20_renamed_567))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_17))
+                (portRef C (instanceRef slave_fifo32_sloe_19_renamed_568))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_16))
+                (portRef C (instanceRef slave_fifo32_sloe_18_renamed_569))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_15))
+                (portRef C (instanceRef slave_fifo32_sloe_17_renamed_570))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_14))
+                (portRef C (instanceRef slave_fifo32_sloe_16_renamed_571))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_13))
+                (portRef C (instanceRef slave_fifo32_sloe_15_renamed_572))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_12))
+                (portRef C (instanceRef slave_fifo32_sloe_14_renamed_573))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_11))
+                (portRef C (instanceRef slave_fifo32_sloe_13_renamed_574))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_10))
+                (portRef C (instanceRef slave_fifo32_sloe_12_renamed_575))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_9))
+                (portRef C (instanceRef slave_fifo32_sloe_11_renamed_576))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_8))
+                (portRef C (instanceRef slave_fifo32_sloe_10_renamed_577))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_7))
+                (portRef C (instanceRef slave_fifo32_sloe_9_renamed_578))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_6))
+                (portRef C (instanceRef slave_fifo32_sloe_8_renamed_579))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_5))
+                (portRef C (instanceRef slave_fifo32_sloe_7_renamed_580))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_4))
+                (portRef C (instanceRef slave_fifo32_sloe_6_renamed_581))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_3))
+                (portRef C (instanceRef slave_fifo32_sloe_5_renamed_582))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_2))
+                (portRef C (instanceRef slave_fifo32_sloe_4_renamed_583))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_1))
+                (portRef C (instanceRef slave_fifo32_sloe_3_renamed_584))
+                (portRef C (instanceRef slave_fifo32_gpif_data_out_0))
+                (portRef C (instanceRef slave_fifo32_sloe_2_renamed_585))
+                (portRef CLKAWRCLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+                (portRef CLKBRDCLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef wr_clk (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef wr_clk (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef rd_clk (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef rd_clk (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net bus_clk
+              (joined
+                (portRef C (instanceRef bus_sync_reset_int_renamed_1))
+                (portRef C (instanceRef bus_sync_reset_out_renamed_0))
+                (portRef O (instanceRef gen_clks_clkout3_buf))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_9__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_11__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e))
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+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef CLK (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_renamed_28))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_renamed_27))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9))
+                (portRef C (instanceRef f1_rd_addr_1))
+                (portRef C (instanceRef f1_rd_addr_2))
+                (portRef C (instanceRef f1_rd_addr_3))
+                (portRef C (instanceRef f1_rd_addr_4))
+                (portRef C (instanceRef f1_rd_addr_5))
+                (portRef C (instanceRef f1_rd_addr_6))
+                (portRef C (instanceRef f1_rd_addr_7))
+                (portRef C (instanceRef f1_rd_addr_8))
+                (portRef C (instanceRef f1_rd_addr_9))
+                (portRef C (instanceRef f1_rd_addr_10))
+                (portRef C (instanceRef f1_rd_addr_11))
+                (portRef C (instanceRef f1_rd_addr_12))
+                (portRef C (instanceRef f1_wr_addr_1))
+                (portRef C (instanceRef f1_wr_addr_2))
+                (portRef C (instanceRef f1_wr_addr_3))
+                (portRef C (instanceRef f1_wr_addr_4))
+                (portRef C (instanceRef f1_wr_addr_5))
+                (portRef C (instanceRef f1_wr_addr_6))
+                (portRef C (instanceRef f1_wr_addr_7))
+                (portRef C (instanceRef f1_wr_addr_8))
+                (portRef C (instanceRef f1_wr_addr_9))
+                (portRef C (instanceRef f1_wr_addr_10))
+                (portRef C (instanceRef f1_wr_addr_11))
+                (portRef C (instanceRef f1_wr_addr_12))
+                (portRef C (instanceRef f1_read_state_FSM_FFd2_renamed_30))
+                (portRef C (instanceRef f1_read_state_FSM_FFd1_renamed_29))
+                (portRef C (instanceRef f1_rd_addr_0))
+                (portRef C (instanceRef f1_wr_addr_0))
+                (portRef C (instanceRef f0_rd_addr_1))
+                (portRef C (instanceRef f0_rd_addr_2))
+                (portRef C (instanceRef f0_rd_addr_3))
+                (portRef C (instanceRef f0_rd_addr_4))
+                (portRef C (instanceRef f0_rd_addr_5))
+                (portRef C (instanceRef f0_rd_addr_6))
+                (portRef C (instanceRef f0_rd_addr_7))
+                (portRef C (instanceRef f0_rd_addr_8))
+                (portRef C (instanceRef f0_rd_addr_9))
+                (portRef C (instanceRef f0_rd_addr_10))
+                (portRef C (instanceRef f0_rd_addr_11))
+                (portRef C (instanceRef f0_rd_addr_12))
+                (portRef C (instanceRef f0_wr_addr_1))
+                (portRef C (instanceRef f0_wr_addr_2))
+                (portRef C (instanceRef f0_wr_addr_3))
+                (portRef C (instanceRef f0_wr_addr_4))
+                (portRef C (instanceRef f0_wr_addr_5))
+                (portRef C (instanceRef f0_wr_addr_6))
+                (portRef C (instanceRef f0_wr_addr_7))
+                (portRef C (instanceRef f0_wr_addr_8))
+                (portRef C (instanceRef f0_wr_addr_9))
+                (portRef C (instanceRef f0_wr_addr_10))
+                (portRef C (instanceRef f0_wr_addr_11))
+                (portRef C (instanceRef f0_wr_addr_12))
+                (portRef C (instanceRef f0_read_state_FSM_FFd2_renamed_32))
+                (portRef C (instanceRef f0_read_state_FSM_FFd1_renamed_31))
+                (portRef C (instanceRef f0_rd_addr_0))
+                (portRef C (instanceRef f0_wr_addr_0))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_renamed_96))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_renamed_97))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_renamed_98))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_renamed_99))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_renamed_100))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_renamed_101))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_renamed_104))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_renamed_105))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_renamed_106))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_renamed_108))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_renamed_109))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_renamed_110))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_renamed_111))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_renamed_112))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_renamed_114))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_renamed_115))
+                (portRef C (instanceRef f1_full_reg_renamed_116))
+                (portRef C (instanceRef f0_full_reg_renamed_117))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_renamed_258))
+                (portRef C (instanceRef f1_Result_0_2_FRB_renamed_337))
+                (portRef C (instanceRef f1_Result_1_2_FRB_renamed_338))
+                (portRef C (instanceRef f1_Result_2_2_FRB_renamed_339))
+                (portRef C (instanceRef f1_Result_3_2_FRB_renamed_340))
+                (portRef C (instanceRef f1_Result_4_2_FRB_renamed_341))
+                (portRef C (instanceRef f1_Result_5_2_FRB_renamed_342))
+                (portRef C (instanceRef f1_Result_6_2_FRB_renamed_343))
+                (portRef C (instanceRef f1_Result_7_2_FRB_renamed_344))
+                (portRef C (instanceRef f1_Result_8_2_FRB_renamed_345))
+                (portRef C (instanceRef f1_Result_9_2_FRB_renamed_346))
+                (portRef C (instanceRef f1_Result_10_2_FRB_renamed_347))
+                (portRef C (instanceRef f1_Result_11_2_FRB_renamed_348))
+                (portRef C (instanceRef f1_Result_12_2_FRB_renamed_349))
+                (portRef C (instanceRef f1_Result_0_1_FRB_renamed_350))
+                (portRef C (instanceRef f1_Result_1_1_FRB_renamed_351))
+                (portRef C (instanceRef f1_Result_2_1_FRB_renamed_352))
+                (portRef C (instanceRef f1_Result_3_1_FRB_renamed_353))
+                (portRef C (instanceRef f1_Result_4_1_FRB_renamed_354))
+                (portRef C (instanceRef f1_Result_5_1_FRB_renamed_355))
+                (portRef C (instanceRef f1_Result_6_1_FRB_renamed_356))
+                (portRef C (instanceRef f1_Result_7_1_FRB_renamed_357))
+                (portRef C (instanceRef f1_Result_8_1_FRB_renamed_358))
+                (portRef C (instanceRef f1_Result_9_1_FRB_renamed_359))
+                (portRef C (instanceRef f1_Result_10_1_FRB_renamed_360))
+                (portRef C (instanceRef f1_Result_11_1_FRB_renamed_361))
+                (portRef C (instanceRef f1_Result_12_1_FRB_renamed_362))
+                (portRef C (instanceRef f1_dont_write_past_me_0__FRB_renamed_363))
+                (portRef C (instanceRef f1_dont_write_past_me_1__FRB_renamed_364))
+                (portRef C (instanceRef f1_dont_write_past_me_2__FRB_renamed_365))
+                (portRef C (instanceRef f1_dont_write_past_me_3__FRB_renamed_366))
+                (portRef C (instanceRef f1_dont_write_past_me_4__FRB_renamed_367))
+                (portRef C (instanceRef f1_dont_write_past_me_5__FRB_renamed_368))
+                (portRef C (instanceRef f1_dont_write_past_me_6__FRB_renamed_369))
+                (portRef C (instanceRef f1_dont_write_past_me_7__FRB_renamed_370))
+                (portRef C (instanceRef f1_dont_write_past_me_8__FRB_renamed_371))
+                (portRef C (instanceRef f1_dont_write_past_me_9__FRB_renamed_372))
+                (portRef C (instanceRef f1_dont_write_past_me_10__FRB_renamed_373))
+                (portRef C (instanceRef f1_dont_write_past_me_11__FRB_renamed_374))
+                (portRef C (instanceRef f1_dont_write_past_me_12__FRB_renamed_375))
+                (portRef C (instanceRef f0_Result_0_2_FRB_renamed_376))
+                (portRef C (instanceRef f0_Result_1_2_FRB_renamed_377))
+                (portRef C (instanceRef f0_Result_2_2_FRB_renamed_378))
+                (portRef C (instanceRef f0_Result_3_2_FRB_renamed_379))
+                (portRef C (instanceRef f0_Result_4_2_FRB_renamed_380))
+                (portRef C (instanceRef f0_Result_5_2_FRB_renamed_381))
+                (portRef C (instanceRef f0_Result_6_2_FRB_renamed_382))
+                (portRef C (instanceRef f0_Result_7_2_FRB_renamed_383))
+                (portRef C (instanceRef f0_Result_8_2_FRB_renamed_384))
+                (portRef C (instanceRef f0_Result_9_2_FRB_renamed_385))
+                (portRef C (instanceRef f0_Result_10_2_FRB_renamed_386))
+                (portRef C (instanceRef f0_Result_11_2_FRB_renamed_387))
+                (portRef C (instanceRef f0_Result_12_2_FRB_renamed_388))
+                (portRef C (instanceRef f0_Result_0_1_FRB_renamed_389))
+                (portRef C (instanceRef f0_Result_1_1_FRB_renamed_390))
+                (portRef C (instanceRef f0_Result_2_1_FRB_renamed_391))
+                (portRef C (instanceRef f0_Result_3_1_FRB_renamed_392))
+                (portRef C (instanceRef f0_Result_4_1_FRB_renamed_393))
+                (portRef C (instanceRef f0_Result_5_1_FRB_renamed_394))
+                (portRef C (instanceRef f0_Result_6_1_FRB_renamed_395))
+                (portRef C (instanceRef f0_Result_7_1_FRB_renamed_396))
+                (portRef C (instanceRef f0_Result_8_1_FRB_renamed_397))
+                (portRef C (instanceRef f0_Result_9_1_FRB_renamed_398))
+                (portRef C (instanceRef f0_Result_10_1_FRB_renamed_399))
+                (portRef C (instanceRef f0_Result_11_1_FRB_renamed_400))
+                (portRef C (instanceRef f0_Result_12_1_FRB_renamed_401))
+                (portRef C (instanceRef f0_dont_write_past_me_0__FRB_renamed_402))
+                (portRef C (instanceRef f0_dont_write_past_me_1__FRB_renamed_403))
+                (portRef C (instanceRef f0_dont_write_past_me_2__FRB_renamed_404))
+                (portRef C (instanceRef f0_dont_write_past_me_3__FRB_renamed_405))
+                (portRef C (instanceRef f0_dont_write_past_me_4__FRB_renamed_406))
+                (portRef C (instanceRef f0_dont_write_past_me_5__FRB_renamed_407))
+                (portRef C (instanceRef f0_dont_write_past_me_6__FRB_renamed_408))
+                (portRef C (instanceRef f0_dont_write_past_me_7__FRB_renamed_409))
+                (portRef C (instanceRef f0_dont_write_past_me_8__FRB_renamed_410))
+                (portRef C (instanceRef f0_dont_write_past_me_9__FRB_renamed_411))
+                (portRef C (instanceRef f0_dont_write_past_me_10__FRB_renamed_412))
+                (portRef C (instanceRef f0_dont_write_past_me_11__FRB_renamed_413))
+                (portRef C (instanceRef f0_dont_write_past_me_12__FRB_renamed_414))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB_renamed_463))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_478))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1_renamed_479))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2_renamed_480))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_481))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4_renamed_482))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5_renamed_483))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_484))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1_renamed_485))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2_renamed_486))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_487))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4_renamed_488))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5_renamed_489))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1_renamed_502))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3_renamed_503))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4_renamed_504))
+                (portRef C (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1_renamed_539))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef CLKAWRCLK (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+                (portRef CLKBRDCLK (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef CLKA (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef CLKB (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef CLKAWRCLK (instanceRef f1_ram_Mram_ram33))
+                (portRef CLKBRDCLK (instanceRef f1_ram_Mram_ram33))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram31))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram31))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram30))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram30))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram32))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram32))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram28))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram28))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram27))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram27))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram29))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram29))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram25))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram25))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram24))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram24))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram26))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram26))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram22))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram22))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram21))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram21))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram23))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram23))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram19))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram19))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram18))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram18))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram20))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram20))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram16))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram16))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram15))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram15))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram17))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram17))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram14))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram14))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram13))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram13))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram12))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram12))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram11))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram11))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram9))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram9))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram8))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram8))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram10))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram10))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram6))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram6))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram5))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram5))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram7))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram7))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram3))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram3))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram2))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram2))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram4))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram4))
+                (portRef CLKA (instanceRef f1_ram_Mram_ram1))
+                (portRef CLKB (instanceRef f1_ram_Mram_ram1))
+                (portRef CLKAWRCLK (instanceRef f0_ram_Mram_ram33))
+                (portRef CLKBRDCLK (instanceRef f0_ram_Mram_ram33))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram31))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram31))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram30))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram30))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram32))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram32))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram28))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram28))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram27))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram27))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram29))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram29))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram25))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram25))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram24))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram24))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram26))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram26))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram22))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram22))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram21))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram21))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram23))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram23))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram19))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram19))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram18))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram18))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram20))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram20))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram16))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram16))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram15))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram15))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram17))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram17))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram14))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram14))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram13))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram13))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram12))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram12))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram11))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram11))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram9))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram9))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram8))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram8))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram10))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram10))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram6))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram6))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram5))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram5))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram7))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram7))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram3))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram3))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram2))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram2))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram4))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram4))
+                (portRef CLKA (instanceRef f0_ram_Mram_ram1))
+                (portRef CLKB (instanceRef f0_ram_Mram_ram1))
+                (portRef rd_clk (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef rd_clk (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef wr_clk (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef wr_clk (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net locked
+              (joined
+                (portRef LOCKED (instanceRef gen_clks_dcm_sp_inst))
+                (portRef D (instanceRef slave_fifo32_debug1_21))
+                (portRef I0 (instanceRef reset_global_locked_OR_1_o1))
+                (portRef I1 (instanceRef slave_fifo32__n0230_inv1))
+                (portRef I0 (instanceRef slave_fifo32__n0223_inv1))
+                (portRef I5 (instanceRef slave_fifo32__n0237_inv1))
+                (portRef I0 (instanceRef slave_fifo32__n0290_inv1))
+                (portRef I0 (instanceRef slave_fifo32__n0279_inv_renamed_35))
+                (portRef I1 (instanceRef slave_fifo32_state_FSM_FFd2_In1_renamed_37))
+                (portRef I1 (instanceRef slave_fifo32_wr_one_rstpot_renamed_512))
+                (portRef I2 (instanceRef slave_fifo32_slrd_rstpot_renamed_515))
+                (portRef I3 (instanceRef slave_fifo32_sloe_1_rstpot_renamed_534))
+                (portRef I1 (instanceRef slave_fifo32_state_FSM_FFd1_In3_F))
+                (portRef I5 (instanceRef slave_fifo32_state_FSM_FFd1_In3_G))
+                (portRef I0 (instanceRef slave_fifo32_state_FSM_FFd2_In3))
+              )
+            )
+            (net reset_global_locked_OR_1_o
+              (joined
+                (portRef PRE (instanceRef bus_sync_reset_int_renamed_1))
+                (portRef PRE (instanceRef bus_sync_reset_out_renamed_0))
+                (portRef PRE (instanceRef gpif_sync_reset_int_renamed_3))
+                (portRef PRE (instanceRef gpif_sync_reset_out_renamed_2))
+                (portRef O (instanceRef reset_global_locked_OR_1_o1))
+              )
+            )
+            (net tx_codec_d_11_OBUF
+              (joined
+                (portRef Q (instanceRef catgen_gen_pins_11__oddr2))
+                (portRef I (instanceRef tx_codec_d_11_OBUF_renamed_76))
+              )
+            )
+            (net tx_codec_d_10_OBUF
+              (joined
+                (portRef Q (instanceRef catgen_gen_pins_10__oddr2))
+                (portRef I (instanceRef tx_codec_d_10_OBUF_renamed_77))
+              )
+            )
+            (net tx_codec_d_9_OBUF
+              (joined
+                (portRef Q (instanceRef catgen_gen_pins_9__oddr2))
+                (portRef I (instanceRef tx_codec_d_9_OBUF_renamed_78))
+              )
+            )
+            (net tx_codec_d_8_OBUF
+              (joined
+                (portRef Q (instanceRef catgen_gen_pins_8__oddr2))
+                (portRef I (instanceRef tx_codec_d_8_OBUF_renamed_79))
+              )
+            )
+            (net tx_codec_d_7_OBUF
+              (joined
+                (portRef Q (instanceRef catgen_gen_pins_7__oddr2))
+                (portRef I (instanceRef tx_codec_d_7_OBUF_renamed_80))
+              )
+            )
+            (net tx_codec_d_6_OBUF
+              (joined
+                (portRef Q (instanceRef catgen_gen_pins_6__oddr2))
+                (portRef I (instanceRef tx_codec_d_6_OBUF_renamed_81))
+              )
+            )
+            (net tx_codec_d_5_OBUF
+              (joined
+                (portRef Q (instanceRef catgen_gen_pins_5__oddr2))
+                (portRef I (instanceRef tx_codec_d_5_OBUF_renamed_82))
+              )
+            )
+            (net tx_codec_d_4_OBUF
+              (joined
+                (portRef Q (instanceRef catgen_gen_pins_4__oddr2))
+                (portRef I (instanceRef tx_codec_d_4_OBUF_renamed_83))
+              )
+            )
+            (net tx_codec_d_3_OBUF
+              (joined
+                (portRef Q (instanceRef catgen_gen_pins_3__oddr2))
+                (portRef I (instanceRef tx_codec_d_3_OBUF_renamed_84))
+              )
+            )
+            (net tx_codec_d_2_OBUF
+              (joined
+                (portRef Q (instanceRef catgen_gen_pins_2__oddr2))
+                (portRef I (instanceRef tx_codec_d_2_OBUF_renamed_85))
+              )
+            )
+            (net tx_codec_d_1_OBUF
+              (joined
+                (portRef Q (instanceRef catgen_gen_pins_1__oddr2))
+                (portRef I (instanceRef tx_codec_d_1_OBUF_renamed_86))
+              )
+            )
+            (net tx_codec_d_0_OBUF
+              (joined
+                (portRef Q (instanceRef catgen_gen_pins_0__oddr2))
+                (portRef I (instanceRef tx_codec_d_0_OBUF_renamed_87))
+              )
+            )
+            (net codec_fb_clk_p_OBUF
+              (joined
+                (portRef Q (instanceRef catgen_oddr2_clk))
+                (portRef I (instanceRef codec_fb_clk_p_OBUF_renamed_92))
+              )
+            )
+            (net tx_frame_p_OBUF
+              (joined
+                (portRef Q (instanceRef catgen_oddr2_frame))
+                (portRef I (instanceRef tx_frame_p_OBUF_renamed_93))
+              )
+            )
+            (net (rename gpif_sync_reset_out "gpif_sync/reset_out")
+              (joined
+                (portRef Q (instanceRef gpif_sync_reset_out_renamed_2))
+                (portRef S (instanceRef slave_fifo32_slwr_renamed_7))
+                (portRef S (instanceRef slave_fifo32_pktend_renamed_6))
+                (portRef R (instanceRef slave_fifo32_state_FSM_FFd2_renamed_5))
+                (portRef R (instanceRef slave_fifo32_state_FSM_FFd1_renamed_4))
+                (portRef R (instanceRef slave_fifo32_fifoadr_0))
+                (portRef R (instanceRef slave_fifo32_fifoadr_1))
+                (portRef R (instanceRef slave_fifo32_idle_cycles_0))
+                (portRef R (instanceRef slave_fifo32_idle_cycles_1))
+                (portRef R (instanceRef slave_fifo32_idle_cycles_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_8))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_9))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_10))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_11))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_12))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_8))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_9))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_10))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_11))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_12))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_renamed_17))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_8))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_8))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_9))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_renamed_19))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_8))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_renamed_21))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_renamed_25))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_renamed_18))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_renamed_20))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo_rst_gpif_rst_OR_155_o1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_renamed_102))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_renamed_103))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_renamed_107))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_renamed_113))
+                (portRef R (instanceRef slave_fifo32_wr_one_renamed_256))
+                (portRef S (instanceRef slave_fifo32_slrd_renamed_257))
+                (portRef S (instanceRef slave_fifo32_sloe_1_renamed_259))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB_renamed_260))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB_renamed_261))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr2_FRB_renamed_262))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr3_FRB_renamed_263))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB_renamed_264))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB_renamed_265))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB_renamed_266))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB_renamed_267))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB_renamed_268))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB_renamed_269))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr10_FRB_renamed_270))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr11_FRB_renamed_271))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr12_FRB_renamed_272))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB_renamed_273))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_1__FRB_renamed_274))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_2__FRB_renamed_275))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_3__FRB_renamed_276))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_4__FRB_renamed_277))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_5__FRB_renamed_278))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_6__FRB_renamed_279))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_7__FRB_renamed_280))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_8__FRB_renamed_281))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_9__FRB_renamed_282))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_10__FRB_renamed_283))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_11__FRB_renamed_284))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_12__FRB_renamed_285))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_0__FRB_renamed_286))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB_renamed_287))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB_renamed_288))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB_renamed_289))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr4_FRB_renamed_290))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB_renamed_291))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB_renamed_292))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB_renamed_293))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB_renamed_294))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB_renamed_295))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr10_FRB_renamed_296))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr11_FRB_renamed_297))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr12_FRB_renamed_298))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB_renamed_299))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB_renamed_300))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr2_FRB_renamed_301))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr3_FRB_renamed_302))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB_renamed_303))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB_renamed_304))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB_renamed_305))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB_renamed_306))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB_renamed_307))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB_renamed_308))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB_renamed_309))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB_renamed_310))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB_renamed_311))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB_renamed_312))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr4_FRB_renamed_313))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB_renamed_314))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB_renamed_315))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB_renamed_316))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB_renamed_317))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB_renamed_318))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_FRB_renamed_319))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr1_FRB_renamed_320))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr2_FRB_renamed_321))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr3_FRB_renamed_322))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr4_FRB_renamed_323))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr5_FRB_renamed_324))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr6_FRB_renamed_325))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr7_FRB_renamed_326))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr8_FRB_renamed_327))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB_renamed_328))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB_renamed_329))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr2_FRB_renamed_330))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB_renamed_331))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr4_FRB_renamed_332))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr5_FRB_renamed_333))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB_renamed_334))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr7_FRB_renamed_335))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB_renamed_336))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_FRB_renamed_437))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB_renamed_438))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr2_FRB_renamed_439))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr3_FRB_renamed_440))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr4_FRB_renamed_441))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB_renamed_442))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB_renamed_443))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr7_FRB_renamed_444))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr8_FRB_renamed_445))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB_renamed_446))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB_renamed_447))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB_renamed_448))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB_renamed_449))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB_renamed_450))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB_renamed_451))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr6_FRB_renamed_452))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB_renamed_453))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB_renamed_454))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421_FRB_renamed_455))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411_FRB_renamed_456))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB_renamed_457))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB_renamed_458))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB_renamed_459))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB_renamed_460))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB_renamed_461))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB_renamed_462))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0_renamed_464))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0_renamed_469))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB0_renamed_474))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0_renamed_476))
+                (portRef R (instanceRef slave_fifo32_rd_one_BRB0_renamed_498))
+                (portRef R (instanceRef slave_fifo32_rd_one_BRB1_renamed_499))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1))
+                (portRef R (instanceRef slave_fifo32_sloe_renamed_540))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_31_1_renamed_547))
+                (portRef S (instanceRef slave_fifo32_slwr_1_renamed_548))
+                (portRef S (instanceRef slave_fifo32_sloe_34_renamed_549))
+                (portRef S (instanceRef slave_fifo32_slrd_1_renamed_550))
+                (portRef S (instanceRef slave_fifo32_pktend_1_renamed_551))
+                (portRef R (instanceRef slave_fifo32_fifoadr_1_1_renamed_552))
+                (portRef R (instanceRef slave_fifo32_fifoadr_0_1_renamed_553))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_31))
+                (portRef R (instanceRef slave_fifo32_sloe_33_renamed_554))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_30))
+                (portRef R (instanceRef slave_fifo32_sloe_32_renamed_555))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_29))
+                (portRef R (instanceRef slave_fifo32_sloe_31_renamed_556))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_28))
+                (portRef R (instanceRef slave_fifo32_sloe_30_renamed_557))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_27))
+                (portRef R (instanceRef slave_fifo32_sloe_29_renamed_558))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_26))
+                (portRef R (instanceRef slave_fifo32_sloe_28_renamed_559))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_25))
+                (portRef R (instanceRef slave_fifo32_sloe_27_renamed_560))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_24))
+                (portRef R (instanceRef slave_fifo32_sloe_26_renamed_561))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_23))
+                (portRef R (instanceRef slave_fifo32_sloe_25_renamed_562))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_22))
+                (portRef R (instanceRef slave_fifo32_sloe_24_renamed_563))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_21))
+                (portRef R (instanceRef slave_fifo32_sloe_23_renamed_564))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_20))
+                (portRef R (instanceRef slave_fifo32_sloe_22_renamed_565))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_19))
+                (portRef R (instanceRef slave_fifo32_sloe_21_renamed_566))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_18))
+                (portRef R (instanceRef slave_fifo32_sloe_20_renamed_567))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_17))
+                (portRef R (instanceRef slave_fifo32_sloe_19_renamed_568))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_16))
+                (portRef R (instanceRef slave_fifo32_sloe_18_renamed_569))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_15))
+                (portRef R (instanceRef slave_fifo32_sloe_17_renamed_570))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_14))
+                (portRef R (instanceRef slave_fifo32_sloe_16_renamed_571))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_13))
+                (portRef R (instanceRef slave_fifo32_sloe_15_renamed_572))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_12))
+                (portRef R (instanceRef slave_fifo32_sloe_14_renamed_573))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_11))
+                (portRef R (instanceRef slave_fifo32_sloe_13_renamed_574))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_10))
+                (portRef R (instanceRef slave_fifo32_sloe_12_renamed_575))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_9))
+                (portRef R (instanceRef slave_fifo32_sloe_11_renamed_576))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_8))
+                (portRef R (instanceRef slave_fifo32_sloe_10_renamed_577))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_7))
+                (portRef R (instanceRef slave_fifo32_sloe_9_renamed_578))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_6))
+                (portRef R (instanceRef slave_fifo32_sloe_8_renamed_579))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_5))
+                (portRef R (instanceRef slave_fifo32_sloe_7_renamed_580))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_4))
+                (portRef R (instanceRef slave_fifo32_sloe_6_renamed_581))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_3))
+                (portRef R (instanceRef slave_fifo32_sloe_5_renamed_582))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_2))
+                (portRef R (instanceRef slave_fifo32_sloe_4_renamed_583))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_1))
+                (portRef R (instanceRef slave_fifo32_sloe_3_renamed_584))
+                (portRef R (instanceRef slave_fifo32_gpif_data_out_0))
+                (portRef R (instanceRef slave_fifo32_sloe_2_renamed_585))
+              )
+            )
+            (net IFCLK_OBUF
+              (joined
+                (portRef Q (instanceRef ODDR2_ifclk))
+                (portRef I (instanceRef IFCLK_OBUF_renamed_94))
+              )
+            )
+            (net gpif_clk_INV_4_o
+              (joined
+                (portRef C1 (instanceRef ODDR2_ifclk))
+                (portRef C1 (instanceRef ODDR2_ifclk_dbg))
+                (portRef O (instanceRef gpif_clk_INV_4_o1_INV_0))
+              )
+            )
+            (net debug_clk_1_OBUF
+              (joined
+                (portRef Q (instanceRef ODDR2_ifclk_dbg))
+                (portRef I (instanceRef debug_clk_1_OBUF_renamed_88))
+              )
+            )
+            (net rx_bandsel_c_OBUF
+              (joined
+                (portRef G (instanceRef XST_GND))
+                (portRef D (instanceRef bus_sync_reset_int_renamed_1))
+                (portRef D (instanceRef gpif_sync_reset_int_renamed_3))
+                (portRef D1 (instanceRef ODDR2_ifclk))
+                (portRef R (instanceRef ODDR2_ifclk))
+                (portRef S (instanceRef ODDR2_ifclk))
+                (portRef D1 (instanceRef ODDR2_ifclk_dbg))
+                (portRef R (instanceRef ODDR2_ifclk_dbg))
+                (portRef S (instanceRef ODDR2_ifclk_dbg))
+                (portRef DSSEN (instanceRef gen_clks_dcm_sp_inst))
+                (portRef PSCLK (instanceRef gen_clks_dcm_sp_inst))
+                (portRef PSEN (instanceRef gen_clks_dcm_sp_inst))
+                (portRef PSINCDEC (instanceRef gen_clks_dcm_sp_inst))
+                (portRef D0 (instanceRef catgen_gen_pins_0__oddr2))
+                (portRef D1 (instanceRef catgen_gen_pins_0__oddr2))
+                (portRef R (instanceRef catgen_gen_pins_0__oddr2))
+                (portRef S (instanceRef catgen_gen_pins_0__oddr2))
+                (portRef D0 (instanceRef catgen_gen_pins_1__oddr2))
+                (portRef D1 (instanceRef catgen_gen_pins_1__oddr2))
+                (portRef R (instanceRef catgen_gen_pins_1__oddr2))
+                (portRef S (instanceRef catgen_gen_pins_1__oddr2))
+                (portRef D0 (instanceRef catgen_gen_pins_2__oddr2))
+                (portRef D1 (instanceRef catgen_gen_pins_2__oddr2))
+                (portRef R (instanceRef catgen_gen_pins_2__oddr2))
+                (portRef S (instanceRef catgen_gen_pins_2__oddr2))
+                (portRef D0 (instanceRef catgen_gen_pins_3__oddr2))
+                (portRef D1 (instanceRef catgen_gen_pins_3__oddr2))
+                (portRef R (instanceRef catgen_gen_pins_3__oddr2))
+                (portRef S (instanceRef catgen_gen_pins_3__oddr2))
+                (portRef D0 (instanceRef catgen_gen_pins_4__oddr2))
+                (portRef D1 (instanceRef catgen_gen_pins_4__oddr2))
+                (portRef R (instanceRef catgen_gen_pins_4__oddr2))
+                (portRef S (instanceRef catgen_gen_pins_4__oddr2))
+                (portRef D0 (instanceRef catgen_gen_pins_5__oddr2))
+                (portRef D1 (instanceRef catgen_gen_pins_5__oddr2))
+                (portRef R (instanceRef catgen_gen_pins_5__oddr2))
+                (portRef S (instanceRef catgen_gen_pins_5__oddr2))
+                (portRef D0 (instanceRef catgen_gen_pins_6__oddr2))
+                (portRef D1 (instanceRef catgen_gen_pins_6__oddr2))
+                (portRef R (instanceRef catgen_gen_pins_6__oddr2))
+                (portRef S (instanceRef catgen_gen_pins_6__oddr2))
+                (portRef D0 (instanceRef catgen_gen_pins_7__oddr2))
+                (portRef D1 (instanceRef catgen_gen_pins_7__oddr2))
+                (portRef R (instanceRef catgen_gen_pins_7__oddr2))
+                (portRef S (instanceRef catgen_gen_pins_7__oddr2))
+                (portRef D0 (instanceRef catgen_gen_pins_8__oddr2))
+                (portRef D1 (instanceRef catgen_gen_pins_8__oddr2))
+                (portRef R (instanceRef catgen_gen_pins_8__oddr2))
+                (portRef S (instanceRef catgen_gen_pins_8__oddr2))
+                (portRef D0 (instanceRef catgen_gen_pins_9__oddr2))
+                (portRef D1 (instanceRef catgen_gen_pins_9__oddr2))
+                (portRef R (instanceRef catgen_gen_pins_9__oddr2))
+                (portRef S (instanceRef catgen_gen_pins_9__oddr2))
+                (portRef D0 (instanceRef catgen_gen_pins_10__oddr2))
+                (portRef D1 (instanceRef catgen_gen_pins_10__oddr2))
+                (portRef R (instanceRef catgen_gen_pins_10__oddr2))
+                (portRef S (instanceRef catgen_gen_pins_10__oddr2))
+                (portRef D0 (instanceRef catgen_gen_pins_11__oddr2))
+                (portRef D1 (instanceRef catgen_gen_pins_11__oddr2))
+                (portRef R (instanceRef catgen_gen_pins_11__oddr2))
+                (portRef S (instanceRef catgen_gen_pins_11__oddr2))
+                (portRef D0 (instanceRef catgen_oddr2_frame))
+                (portRef D1 (instanceRef catgen_oddr2_frame))
+                (portRef R (instanceRef catgen_oddr2_frame))
+                (portRef S (instanceRef catgen_oddr2_frame))
+                (portRef D1 (instanceRef catgen_oddr2_clk))
+                (portRef R (instanceRef catgen_oddr2_clk))
+                (portRef S (instanceRef catgen_oddr2_clk))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__))
+                (portRef DI
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__))
+                (portRef DI
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__))
+                (portRef DI
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__))
+                (portRef DI
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__))
+                (portRef DI
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_10__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_10__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_11__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_11__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_12__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_10__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_10__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_11__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_11__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_12__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_4__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8__))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9__))
+                (portRef DI (instanceRef f1_Msub_dont_write_past_me_cy_0__))
+                (portRef DI (instanceRef f1_Msub_dont_write_past_me_cy_1__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_cy_0__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_xor_0__))
+                (portRef DI (instanceRef f1_Mcount_wr_addr_cy_1__))
+                (portRef DI (instanceRef f1_Mcount_wr_addr_cy_2__))
+                (portRef DI (instanceRef f1_Mcount_wr_addr_cy_3__))
+                (portRef DI (instanceRef f1_Mcount_wr_addr_cy_4__))
+                (portRef DI (instanceRef f1_Mcount_wr_addr_cy_5__))
+                (portRef DI (instanceRef f1_Mcount_wr_addr_cy_6__))
+                (portRef DI (instanceRef f1_Mcount_wr_addr_cy_7__))
+                (portRef DI (instanceRef f1_Mcount_wr_addr_cy_8__))
+                (portRef DI (instanceRef f1_Mcount_wr_addr_cy_9__))
+                (portRef DI (instanceRef f1_Mcount_wr_addr_cy_10__))
+                (portRef DI (instanceRef f1_Mcount_wr_addr_cy_11__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_cy_0__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_xor_0__))
+                (portRef DI (instanceRef f1_Mcount_rd_addr_cy_1__))
+                (portRef DI (instanceRef f1_Mcount_rd_addr_cy_2__))
+                (portRef DI (instanceRef f1_Mcount_rd_addr_cy_3__))
+                (portRef DI (instanceRef f1_Mcount_rd_addr_cy_4__))
+                (portRef DI (instanceRef f1_Mcount_rd_addr_cy_5__))
+                (portRef DI (instanceRef f1_Mcount_rd_addr_cy_6__))
+                (portRef DI (instanceRef f1_Mcount_rd_addr_cy_7__))
+                (portRef DI (instanceRef f1_Mcount_rd_addr_cy_8__))
+                (portRef DI (instanceRef f1_Mcount_rd_addr_cy_9__))
+                (portRef DI (instanceRef f1_Mcount_rd_addr_cy_10__))
+                (portRef DI (instanceRef f1_Mcount_rd_addr_cy_11__))
+                (portRef DI (instanceRef f1_Mcompar_becoming_full_cy_0__))
+                (portRef DI (instanceRef f1_Mcompar_becoming_full_cy_1__))
+                (portRef DI (instanceRef f1_Mcompar_becoming_full_cy_2__))
+                (portRef DI (instanceRef f1_Mcompar_becoming_full_cy_3__))
+                (portRef DI (instanceRef f1_Mcompar_becoming_full_cy_4__))
+                (portRef DI (instanceRef f0_Msub_dont_write_past_me_cy_0__))
+                (portRef DI (instanceRef f0_Msub_dont_write_past_me_cy_1__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_cy_0__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_xor_0__))
+                (portRef DI (instanceRef f0_Mcount_wr_addr_cy_1__))
+                (portRef DI (instanceRef f0_Mcount_wr_addr_cy_2__))
+                (portRef DI (instanceRef f0_Mcount_wr_addr_cy_3__))
+                (portRef DI (instanceRef f0_Mcount_wr_addr_cy_4__))
+                (portRef DI (instanceRef f0_Mcount_wr_addr_cy_5__))
+                (portRef DI (instanceRef f0_Mcount_wr_addr_cy_6__))
+                (portRef DI (instanceRef f0_Mcount_wr_addr_cy_7__))
+                (portRef DI (instanceRef f0_Mcount_wr_addr_cy_8__))
+                (portRef DI (instanceRef f0_Mcount_wr_addr_cy_9__))
+                (portRef DI (instanceRef f0_Mcount_wr_addr_cy_10__))
+                (portRef DI (instanceRef f0_Mcount_wr_addr_cy_11__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_cy_0__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_xor_0__))
+                (portRef DI (instanceRef f0_Mcount_rd_addr_cy_1__))
+                (portRef DI (instanceRef f0_Mcount_rd_addr_cy_2__))
+                (portRef DI (instanceRef f0_Mcount_rd_addr_cy_3__))
+                (portRef DI (instanceRef f0_Mcount_rd_addr_cy_4__))
+                (portRef DI (instanceRef f0_Mcount_rd_addr_cy_5__))
+                (portRef DI (instanceRef f0_Mcount_rd_addr_cy_6__))
+                (portRef DI (instanceRef f0_Mcount_rd_addr_cy_7__))
+                (portRef DI (instanceRef f0_Mcount_rd_addr_cy_8__))
+                (portRef DI (instanceRef f0_Mcount_rd_addr_cy_9__))
+                (portRef DI (instanceRef f0_Mcount_rd_addr_cy_10__))
+                (portRef DI (instanceRef f0_Mcount_rd_addr_cy_11__))
+                (portRef DI (instanceRef f0_Mcompar_becoming_full_cy_0__))
+                (portRef DI (instanceRef f0_Mcompar_becoming_full_cy_1__))
+                (portRef DI (instanceRef f0_Mcompar_becoming_full_cy_2__))
+                (portRef DI (instanceRef f0_Mcompar_becoming_full_cy_3__))
+                (portRef DI (instanceRef f0_Mcompar_becoming_full_cy_4__))
+                (portRef I (instanceRef codec_ctrl_in_3_OBUF))
+                (portRef I (instanceRef codec_ctrl_in_2_OBUF))
+                (portRef I (instanceRef codec_ctrl_in_1_OBUF))
+                (portRef I (instanceRef codec_ctrl_in_0_OBUF))
+                (portRef I (instanceRef debug_20_OBUF))
+                (portRef I (instanceRef cat_ce_OBUF))
+                (portRef I (instanceRef pll_ce_OBUF))
+                (portRef I (instanceRef pll_mosi_OBUF))
+                (portRef I (instanceRef pll_sclk_OBUF))
+                (portRef I (instanceRef codec_en_agc_OBUF))
+                (portRef I (instanceRef codec_sync_OBUF))
+                (portRef I (instanceRef codec_txrx_OBUF))
+                (portRef I (instanceRef GPIF_CTL0_OBUF))
+                (portRef I (instanceRef gps_out_enable_OBUF))
+                (portRef I (instanceRef gps_ref_enable_OBUF))
+                (portRef I (instanceRef ext_ref_enable_OBUF))
+                (portRef I (instanceRef pps_fpga_out_enable_OBUF))
+                (portRef I (instanceRef tx_bandsel_a_OBUF))
+                (portRef I (instanceRef tx_bandsel_b_OBUF))
+                (portRef I (instanceRef rx_bandsel_a_OBUF))
+                (portRef I (instanceRef rx_bandsel_b_OBUF))
+                (portRef I (instanceRef rx_bandsel_c_OBUF_renamed_95))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy))
+                (portRef CI
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__))
+                (portRef CI (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__))
+                (portRef DI (instanceRef f1__n0161_inv1_cy))
+                (portRef CI (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__))
+                (portRef DI (instanceRef f0__n0161_inv1_cy))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+                (portRef REGCEBREGCE (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+                (portRef RSTBRST (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+                (portRef (member WEBWEU 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+                (portRef (member WEBWEU 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIA 16) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member DIB 16) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member DIPA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member DIPA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member DIPB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member DIPB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIPA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIPA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIPA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIPB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIPB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIPB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+                (portRef REGCEBREGCE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+                (portRef RSTBRST (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+                (portRef (member WEBWEU 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+                (portRef (member WEBWEU 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+                (portRef (member DIPA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIPA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIPA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIPB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIPB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIPB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIA 16) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member DIB 16) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member DIPA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member DIPA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member DIPB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member DIPB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef REGCEA (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef REGCEB (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef RSTA (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef RSTB (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram33))
+                (portRef REGCEBREGCE (instanceRef f1_ram_Mram_ram33))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram33))
+                (portRef RSTBRST (instanceRef f1_ram_Mram_ram33))
+                (portRef (member WEBWEU 1) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member WEBWEU 0) (instanceRef f1_ram_Mram_ram33))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram31))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram31))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram31))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram31))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram31))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram30))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram30))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram30))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram30))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram30))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram32))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram32))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram32))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram32))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram32))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram28))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram28))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram28))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram28))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram28))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram27))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram27))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram27))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram27))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram27))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram29))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram29))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram29))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram29))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram29))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram25))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram25))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram25))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram25))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram25))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram24))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram24))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram24))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram24))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram24))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram26))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram26))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram26))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram26))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram26))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram22))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram22))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram22))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram22))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram22))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram21))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram21))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram21))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram21))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram21))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram23))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram23))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram23))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram23))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram23))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram19))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram19))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram19))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram19))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram19))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram18))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram18))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram18))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram18))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram18))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram20))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram20))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram20))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram20))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram20))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram16))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram16))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram16))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram16))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram16))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram15))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram15))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram15))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram15))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram15))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram17))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram17))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram17))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram17))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram17))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram14))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram14))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram14))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram14))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram14))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram13))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram13))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram13))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram13))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram13))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram12))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram12))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram12))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram12))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram12))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram11))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram11))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram11))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram11))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram11))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram9))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram9))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram9))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram9))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram9))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram8))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram8))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram8))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram8))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram8))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram10))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram10))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram10))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram10))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram10))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram6))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram6))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram6))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram6))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram6))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram5))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram5))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram5))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram5))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram5))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram7))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram7))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram7))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram7))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram7))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram3))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram3))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram3))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram3))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram3))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram2))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram2))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram2))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram2))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram2))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram4))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram4))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram4))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram4))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram4))
+                (portRef REGCEA (instanceRef f1_ram_Mram_ram1))
+                (portRef REGCEB (instanceRef f1_ram_Mram_ram1))
+                (portRef RSTA (instanceRef f1_ram_Mram_ram1))
+                (portRef RSTB (instanceRef f1_ram_Mram_ram1))
+                (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram1))
+                (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram1))
+                (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram1))
+                (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram1))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram33))
+                (portRef REGCEBREGCE (instanceRef f0_ram_Mram_ram33))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram33))
+                (portRef RSTBRST (instanceRef f0_ram_Mram_ram33))
+                (portRef (member WEBWEU 1) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member WEBWEU 0) (instanceRef f0_ram_Mram_ram33))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram31))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram31))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram31))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram31))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram31))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram30))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram30))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram30))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram30))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram30))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram32))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram32))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram32))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram32))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram32))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram28))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram28))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram28))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram28))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram28))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram27))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram27))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram27))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram27))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram27))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram29))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram29))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram29))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram29))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram29))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram25))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram25))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram25))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram25))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram25))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram24))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram24))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram24))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram24))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram24))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram26))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram26))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram26))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram26))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram26))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram22))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram22))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram22))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram22))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram22))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram21))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram21))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram21))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram21))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram21))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram23))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram23))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram23))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram23))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram23))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram19))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram19))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram19))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram19))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram19))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram18))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram18))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram18))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram18))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram18))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram20))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram20))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram20))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram20))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram20))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram16))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram16))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram16))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram16))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram16))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram15))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram15))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram15))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram15))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram15))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram17))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram17))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram17))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram17))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram17))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram14))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram14))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram14))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram14))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram14))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram13))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram13))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram13))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram13))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram13))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram12))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram12))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram12))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram12))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram12))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram11))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram11))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram11))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram11))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram11))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram9))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram9))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram9))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram9))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram9))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram8))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram8))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram8))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram8))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram8))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram10))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram10))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram10))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram10))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram10))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram6))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram6))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram6))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram6))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram6))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram5))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram5))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram5))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram5))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram5))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram7))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram7))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram7))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram7))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram7))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram3))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram3))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram3))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram3))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram3))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram2))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram2))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram2))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram2))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram2))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram4))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram4))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram4))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram4))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram4))
+                (portRef REGCEA (instanceRef f0_ram_Mram_ram1))
+                (portRef REGCEB (instanceRef f0_ram_Mram_ram1))
+                (portRef RSTA (instanceRef f0_ram_Mram_ram1))
+                (portRef RSTB (instanceRef f0_ram_Mram_ram1))
+                (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram1))
+                (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram1))
+                (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram1))
+                (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1__))
+                (portRef (member din 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 13) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 14) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 15) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 16) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 17) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 18) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 19) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 20) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 21) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 22) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 23) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 24) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 25) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 26) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 27) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 28) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 29) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 32) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 33) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 34) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 35) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 36) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 37) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 38) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 13) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 14) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 15) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 16) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 17) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 18) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 19) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 20) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 21) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
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+                (portRef (member din 36) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
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+                (portRef (member din 38) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
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+                (portRef (member din 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 13) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 14) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 15) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 16) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 17) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 18) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 19) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 20) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 21) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 22) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 23) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 24) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 25) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 26) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 27) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
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+                (portRef (member din 29) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
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+                (portRef (member din 32) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
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+                (portRef (member din 37) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 38) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 13) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 14) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 15) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 16) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 17) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 18) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 19) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 20) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 21) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 22) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 23) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 24) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 25) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 26) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 27) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 28) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 29) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 32) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 33) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 34) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 35) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 36) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 37) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+                (portRef (member din 38) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename GPIF_D_31_ "GPIF_D<31>")
+              (joined
+                (portRef (member GPIF_D 0))
+                (portRef IO (instanceRef GPIF_D_31_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_30_ "GPIF_D<30>")
+              (joined
+                (portRef (member GPIF_D 1))
+                (portRef IO (instanceRef GPIF_D_30_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_29_ "GPIF_D<29>")
+              (joined
+                (portRef (member GPIF_D 2))
+                (portRef IO (instanceRef GPIF_D_29_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_28_ "GPIF_D<28>")
+              (joined
+                (portRef (member GPIF_D 3))
+                (portRef IO (instanceRef GPIF_D_28_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_27_ "GPIF_D<27>")
+              (joined
+                (portRef (member GPIF_D 4))
+                (portRef IO (instanceRef GPIF_D_27_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_26_ "GPIF_D<26>")
+              (joined
+                (portRef (member GPIF_D 5))
+                (portRef IO (instanceRef GPIF_D_26_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_25_ "GPIF_D<25>")
+              (joined
+                (portRef (member GPIF_D 6))
+                (portRef IO (instanceRef GPIF_D_25_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_24_ "GPIF_D<24>")
+              (joined
+                (portRef (member GPIF_D 7))
+                (portRef IO (instanceRef GPIF_D_24_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_23_ "GPIF_D<23>")
+              (joined
+                (portRef (member GPIF_D 8))
+                (portRef IO (instanceRef GPIF_D_23_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_22_ "GPIF_D<22>")
+              (joined
+                (portRef (member GPIF_D 9))
+                (portRef IO (instanceRef GPIF_D_22_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_21_ "GPIF_D<21>")
+              (joined
+                (portRef (member GPIF_D 10))
+                (portRef IO (instanceRef GPIF_D_21_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_20_ "GPIF_D<20>")
+              (joined
+                (portRef (member GPIF_D 11))
+                (portRef IO (instanceRef GPIF_D_20_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_19_ "GPIF_D<19>")
+              (joined
+                (portRef (member GPIF_D 12))
+                (portRef IO (instanceRef GPIF_D_19_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_18_ "GPIF_D<18>")
+              (joined
+                (portRef (member GPIF_D 13))
+                (portRef IO (instanceRef GPIF_D_18_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_17_ "GPIF_D<17>")
+              (joined
+                (portRef (member GPIF_D 14))
+                (portRef IO (instanceRef GPIF_D_17_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_16_ "GPIF_D<16>")
+              (joined
+                (portRef (member GPIF_D 15))
+                (portRef IO (instanceRef GPIF_D_16_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_15_ "GPIF_D<15>")
+              (joined
+                (portRef (member GPIF_D 16))
+                (portRef IO (instanceRef GPIF_D_15_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_14_ "GPIF_D<14>")
+              (joined
+                (portRef (member GPIF_D 17))
+                (portRef IO (instanceRef GPIF_D_14_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_13_ "GPIF_D<13>")
+              (joined
+                (portRef (member GPIF_D 18))
+                (portRef IO (instanceRef GPIF_D_13_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_12_ "GPIF_D<12>")
+              (joined
+                (portRef (member GPIF_D 19))
+                (portRef IO (instanceRef GPIF_D_12_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_11_ "GPIF_D<11>")
+              (joined
+                (portRef (member GPIF_D 20))
+                (portRef IO (instanceRef GPIF_D_11_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_10_ "GPIF_D<10>")
+              (joined
+                (portRef (member GPIF_D 21))
+                (portRef IO (instanceRef GPIF_D_10_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_9_ "GPIF_D<9>")
+              (joined
+                (portRef (member GPIF_D 22))
+                (portRef IO (instanceRef GPIF_D_9_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_8_ "GPIF_D<8>")
+              (joined
+                (portRef (member GPIF_D 23))
+                (portRef IO (instanceRef GPIF_D_8_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_7_ "GPIF_D<7>")
+              (joined
+                (portRef (member GPIF_D 24))
+                (portRef IO (instanceRef GPIF_D_7_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_6_ "GPIF_D<6>")
+              (joined
+                (portRef (member GPIF_D 25))
+                (portRef IO (instanceRef GPIF_D_6_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_5_ "GPIF_D<5>")
+              (joined
+                (portRef (member GPIF_D 26))
+                (portRef IO (instanceRef GPIF_D_5_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_4_ "GPIF_D<4>")
+              (joined
+                (portRef (member GPIF_D 27))
+                (portRef IO (instanceRef GPIF_D_4_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_3_ "GPIF_D<3>")
+              (joined
+                (portRef (member GPIF_D 28))
+                (portRef IO (instanceRef GPIF_D_3_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_2_ "GPIF_D<2>")
+              (joined
+                (portRef (member GPIF_D 29))
+                (portRef IO (instanceRef GPIF_D_2_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_1_ "GPIF_D<1>")
+              (joined
+                (portRef (member GPIF_D 30))
+                (portRef IO (instanceRef GPIF_D_1_IOBUF))
+              )
+            )
+            (net (rename GPIF_D_0_ "GPIF_D<0>")
+              (joined
+                (portRef (member GPIF_D 31))
+                (portRef IO (instanceRef GPIF_D_0_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_fifoadr_1_ "slave_fifo32/fifoadr<1>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifoadr_1))
+                (portRef I (instanceRef GPIF_CTL11_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_fifoadr_0_ "slave_fifo32/fifoadr<0>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifoadr_0))
+                (portRef I (instanceRef GPIF_CTL12_OBUF))
+              )
+            )
+            (net (rename tx_tdata_63_ "tx_tdata<63>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram32))
+              )
+            )
+            (net (rename tx_tdata_62_ "tx_tdata<62>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram32))
+              )
+            )
+            (net (rename tx_tdata_61_ "tx_tdata<61>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram31))
+              )
+            )
+            (net (rename tx_tdata_60_ "tx_tdata<60>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram31))
+              )
+            )
+            (net (rename tx_tdata_59_ "tx_tdata<59>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_59__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram30))
+              )
+            )
+            (net (rename tx_tdata_58_ "tx_tdata<58>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram30))
+              )
+            )
+            (net (rename tx_tdata_57_ "tx_tdata<57>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram29))
+              )
+            )
+            (net (rename tx_tdata_56_ "tx_tdata<56>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram29))
+              )
+            )
+            (net (rename tx_tdata_55_ "tx_tdata<55>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram28))
+              )
+            )
+            (net (rename tx_tdata_54_ "tx_tdata<54>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram28))
+              )
+            )
+            (net (rename tx_tdata_53_ "tx_tdata<53>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_53__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram27))
+              )
+            )
+            (net (rename tx_tdata_52_ "tx_tdata<52>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_52__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram27))
+              )
+            )
+            (net (rename tx_tdata_51_ "tx_tdata<51>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_51__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram26))
+              )
+            )
+            (net (rename tx_tdata_50_ "tx_tdata<50>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram26))
+              )
+            )
+            (net (rename tx_tdata_49_ "tx_tdata<49>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram25))
+              )
+            )
+            (net (rename tx_tdata_48_ "tx_tdata<48>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_48__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram25))
+              )
+            )
+            (net (rename tx_tdata_47_ "tx_tdata<47>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_47__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram24))
+              )
+            )
+            (net (rename tx_tdata_46_ "tx_tdata<46>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_46__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram24))
+              )
+            )
+            (net (rename tx_tdata_45_ "tx_tdata<45>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram23))
+              )
+            )
+            (net (rename tx_tdata_44_ "tx_tdata<44>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_44__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram23))
+              )
+            )
+            (net (rename tx_tdata_43_ "tx_tdata<43>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_43__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram22))
+              )
+            )
+            (net (rename tx_tdata_42_ "tx_tdata<42>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_42__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram22))
+              )
+            )
+            (net (rename tx_tdata_41_ "tx_tdata<41>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_41__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram21))
+              )
+            )
+            (net (rename tx_tdata_40_ "tx_tdata<40>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_40__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram21))
+              )
+            )
+            (net (rename tx_tdata_39_ "tx_tdata<39>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_39__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram20))
+              )
+            )
+            (net (rename tx_tdata_38_ "tx_tdata<38>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_38__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram20))
+              )
+            )
+            (net (rename tx_tdata_37_ "tx_tdata<37>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram19))
+              )
+            )
+            (net (rename tx_tdata_36_ "tx_tdata<36>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram19))
+              )
+            )
+            (net (rename tx_tdata_35_ "tx_tdata<35>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram18))
+              )
+            )
+            (net (rename tx_tdata_34_ "tx_tdata<34>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram18))
+              )
+            )
+            (net (rename tx_tdata_33_ "tx_tdata<33>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_33__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram17))
+              )
+            )
+            (net (rename tx_tdata_32_ "tx_tdata<32>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_32__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram17))
+              )
+            )
+            (net (rename tx_tdata_31_ "tx_tdata<31>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_31__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram16))
+              )
+            )
+            (net (rename tx_tdata_30_ "tx_tdata<30>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_30__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram16))
+              )
+            )
+            (net (rename tx_tdata_29_ "tx_tdata<29>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_29__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram15))
+              )
+            )
+            (net (rename tx_tdata_28_ "tx_tdata<28>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_28__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram15))
+              )
+            )
+            (net (rename tx_tdata_27_ "tx_tdata<27>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram14))
+              )
+            )
+            (net (rename tx_tdata_26_ "tx_tdata<26>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram14))
+              )
+            )
+            (net (rename tx_tdata_25_ "tx_tdata<25>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram13))
+              )
+            )
+            (net (rename tx_tdata_24_ "tx_tdata<24>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_24__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram13))
+              )
+            )
+            (net (rename tx_tdata_23_ "tx_tdata<23>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_23__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram12))
+              )
+            )
+            (net (rename tx_tdata_22_ "tx_tdata<22>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_22__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram12))
+              )
+            )
+            (net (rename tx_tdata_21_ "tx_tdata<21>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_21__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram11))
+              )
+            )
+            (net (rename tx_tdata_20_ "tx_tdata<20>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_20__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram11))
+              )
+            )
+            (net (rename tx_tdata_19_ "tx_tdata<19>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram10))
+              )
+            )
+            (net (rename tx_tdata_18_ "tx_tdata<18>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram10))
+              )
+            )
+            (net (rename tx_tdata_17_ "tx_tdata<17>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram9))
+              )
+            )
+            (net (rename tx_tdata_16_ "tx_tdata<16>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram9))
+              )
+            )
+            (net (rename tx_tdata_15_ "tx_tdata<15>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_15__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram8))
+              )
+            )
+            (net (rename tx_tdata_14_ "tx_tdata<14>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_14__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram8))
+              )
+            )
+            (net (rename tx_tdata_13_ "tx_tdata<13>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_13__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram7))
+              )
+            )
+            (net (rename tx_tdata_12_ "tx_tdata<12>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_12__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram7))
+              )
+            )
+            (net (rename tx_tdata_11_ "tx_tdata<11>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_11__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram6))
+              )
+            )
+            (net (rename tx_tdata_10_ "tx_tdata<10>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram6))
+              )
+            )
+            (net (rename tx_tdata_9_ "tx_tdata<9>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram5))
+              )
+            )
+            (net (rename tx_tdata_8_ "tx_tdata<8>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_8__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram5))
+              )
+            )
+            (net (rename tx_tdata_7_ "tx_tdata<7>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_7__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram4))
+              )
+            )
+            (net (rename tx_tdata_6_ "tx_tdata<6>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_6__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram4))
+              )
+            )
+            (net (rename tx_tdata_5_ "tx_tdata<5>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_5__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram3))
+              )
+            )
+            (net (rename tx_tdata_4_ "tx_tdata<4>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_4__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram3))
+              )
+            )
+            (net (rename tx_tdata_3_ "tx_tdata<3>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_3__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram2))
+              )
+            )
+            (net (rename tx_tdata_2_ "tx_tdata<2>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_2__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram2))
+              )
+            )
+            (net (rename tx_tdata_1_ "tx_tdata<1>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_1__srlc32e))
+                (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename tx_tdata_0_ "tx_tdata<0>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e))
+                (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename ctrl_tdata_63_ "ctrl_tdata<63>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram32))
+              )
+            )
+            (net (rename ctrl_tdata_62_ "ctrl_tdata<62>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram32))
+              )
+            )
+            (net (rename ctrl_tdata_61_ "ctrl_tdata<61>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram31))
+              )
+            )
+            (net (rename ctrl_tdata_60_ "ctrl_tdata<60>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram31))
+              )
+            )
+            (net (rename ctrl_tdata_59_ "ctrl_tdata<59>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram30))
+              )
+            )
+            (net (rename ctrl_tdata_58_ "ctrl_tdata<58>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram30))
+              )
+            )
+            (net (rename ctrl_tdata_57_ "ctrl_tdata<57>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram29))
+              )
+            )
+            (net (rename ctrl_tdata_56_ "ctrl_tdata<56>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram29))
+              )
+            )
+            (net (rename ctrl_tdata_55_ "ctrl_tdata<55>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram28))
+              )
+            )
+            (net (rename ctrl_tdata_54_ "ctrl_tdata<54>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram28))
+              )
+            )
+            (net (rename ctrl_tdata_53_ "ctrl_tdata<53>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram27))
+              )
+            )
+            (net (rename ctrl_tdata_52_ "ctrl_tdata<52>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram27))
+              )
+            )
+            (net (rename ctrl_tdata_51_ "ctrl_tdata<51>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram26))
+              )
+            )
+            (net (rename ctrl_tdata_50_ "ctrl_tdata<50>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram26))
+              )
+            )
+            (net (rename ctrl_tdata_49_ "ctrl_tdata<49>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram25))
+              )
+            )
+            (net (rename ctrl_tdata_48_ "ctrl_tdata<48>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram25))
+              )
+            )
+            (net (rename ctrl_tdata_47_ "ctrl_tdata<47>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram24))
+              )
+            )
+            (net (rename ctrl_tdata_46_ "ctrl_tdata<46>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram24))
+              )
+            )
+            (net (rename ctrl_tdata_45_ "ctrl_tdata<45>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram23))
+              )
+            )
+            (net (rename ctrl_tdata_44_ "ctrl_tdata<44>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram23))
+              )
+            )
+            (net (rename ctrl_tdata_43_ "ctrl_tdata<43>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram22))
+              )
+            )
+            (net (rename ctrl_tdata_42_ "ctrl_tdata<42>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram22))
+              )
+            )
+            (net (rename ctrl_tdata_41_ "ctrl_tdata<41>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram21))
+              )
+            )
+            (net (rename ctrl_tdata_40_ "ctrl_tdata<40>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram21))
+              )
+            )
+            (net (rename ctrl_tdata_39_ "ctrl_tdata<39>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram20))
+              )
+            )
+            (net (rename ctrl_tdata_38_ "ctrl_tdata<38>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram20))
+              )
+            )
+            (net (rename ctrl_tdata_37_ "ctrl_tdata<37>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram19))
+              )
+            )
+            (net (rename ctrl_tdata_36_ "ctrl_tdata<36>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram19))
+              )
+            )
+            (net (rename ctrl_tdata_35_ "ctrl_tdata<35>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram18))
+              )
+            )
+            (net (rename ctrl_tdata_34_ "ctrl_tdata<34>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram18))
+              )
+            )
+            (net (rename ctrl_tdata_33_ "ctrl_tdata<33>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram17))
+              )
+            )
+            (net (rename ctrl_tdata_32_ "ctrl_tdata<32>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram17))
+              )
+            )
+            (net (rename ctrl_tdata_31_ "ctrl_tdata<31>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram16))
+              )
+            )
+            (net (rename ctrl_tdata_30_ "ctrl_tdata<30>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram16))
+              )
+            )
+            (net (rename ctrl_tdata_29_ "ctrl_tdata<29>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram15))
+              )
+            )
+            (net (rename ctrl_tdata_28_ "ctrl_tdata<28>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram15))
+              )
+            )
+            (net (rename ctrl_tdata_27_ "ctrl_tdata<27>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram14))
+              )
+            )
+            (net (rename ctrl_tdata_26_ "ctrl_tdata<26>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram14))
+              )
+            )
+            (net (rename ctrl_tdata_25_ "ctrl_tdata<25>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram13))
+              )
+            )
+            (net (rename ctrl_tdata_24_ "ctrl_tdata<24>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram13))
+              )
+            )
+            (net (rename ctrl_tdata_23_ "ctrl_tdata<23>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram12))
+              )
+            )
+            (net (rename ctrl_tdata_22_ "ctrl_tdata<22>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram12))
+              )
+            )
+            (net (rename ctrl_tdata_21_ "ctrl_tdata<21>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram11))
+              )
+            )
+            (net (rename ctrl_tdata_20_ "ctrl_tdata<20>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram11))
+              )
+            )
+            (net (rename ctrl_tdata_19_ "ctrl_tdata<19>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram10))
+              )
+            )
+            (net (rename ctrl_tdata_18_ "ctrl_tdata<18>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram10))
+              )
+            )
+            (net (rename ctrl_tdata_17_ "ctrl_tdata<17>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram9))
+              )
+            )
+            (net (rename ctrl_tdata_16_ "ctrl_tdata<16>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram9))
+              )
+            )
+            (net (rename ctrl_tdata_15_ "ctrl_tdata<15>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram8))
+              )
+            )
+            (net (rename ctrl_tdata_14_ "ctrl_tdata<14>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram8))
+              )
+            )
+            (net (rename ctrl_tdata_13_ "ctrl_tdata<13>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram7))
+              )
+            )
+            (net (rename ctrl_tdata_12_ "ctrl_tdata<12>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram7))
+              )
+            )
+            (net (rename ctrl_tdata_11_ "ctrl_tdata<11>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram6))
+              )
+            )
+            (net (rename ctrl_tdata_10_ "ctrl_tdata<10>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram6))
+              )
+            )
+            (net (rename ctrl_tdata_9_ "ctrl_tdata<9>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram5))
+              )
+            )
+            (net (rename ctrl_tdata_8_ "ctrl_tdata<8>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram5))
+              )
+            )
+            (net (rename ctrl_tdata_7_ "ctrl_tdata<7>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram4))
+              )
+            )
+            (net (rename ctrl_tdata_6_ "ctrl_tdata<6>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram4))
+              )
+            )
+            (net (rename ctrl_tdata_5_ "ctrl_tdata<5>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram3))
+              )
+            )
+            (net (rename ctrl_tdata_4_ "ctrl_tdata<4>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram3))
+              )
+            )
+            (net (rename ctrl_tdata_3_ "ctrl_tdata<3>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram2))
+              )
+            )
+            (net (rename ctrl_tdata_2_ "ctrl_tdata<2>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram2))
+              )
+            )
+            (net (rename ctrl_tdata_1_ "ctrl_tdata<1>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e))
+                (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename ctrl_tdata_0_ "ctrl_tdata<0>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
+                (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_debug2_31__ "slave_fifo32/debug2<31>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_31))
+                (portRef I (instanceRef debug_31_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_slrd2 "slave_fifo32/slrd2")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_slrd2_renamed_9))
+                (portRef I (instanceRef debug_30_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_29__ "slave_fifo32/debug2<29>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_29))
+                (portRef I (instanceRef debug_29_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_28__ "slave_fifo32/debug2<28>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_28))
+                (portRef I (instanceRef debug_28_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_27__ "slave_fifo32/debug2<27>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_27))
+                (portRef I (instanceRef debug_27_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_26__ "slave_fifo32/debug2<26>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_26))
+                (portRef I (instanceRef debug_26_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_EP_WMARK1 "slave_fifo32/EP_WMARK1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_EP_WMARK1_renamed_11))
+                (portRef I (instanceRef debug_25_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_EP_READY1 "slave_fifo32/EP_READY1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_EP_READY1_renamed_12))
+                (portRef I (instanceRef debug_24_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_23__ "slave_fifo32/debug2<23>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_23))
+                (portRef I (instanceRef debug_23_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_22__ "slave_fifo32/debug2<22>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_22))
+                (portRef I (instanceRef debug_22_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_21__ "slave_fifo32/debug2<21>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_21))
+                (portRef I (instanceRef debug_21_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_19__ "slave_fifo32/debug2<19>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_19))
+                (portRef I (instanceRef debug_19_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_18__ "slave_fifo32/debug2<18>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_18))
+                (portRef I (instanceRef debug_18_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_17__ "slave_fifo32/debug2<17>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_17))
+                (portRef I (instanceRef debug_17_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_16__ "slave_fifo32/debug2<16>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_16))
+                (portRef I (instanceRef debug_16_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_15__ "slave_fifo32/debug2<15>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_15))
+                (portRef I (instanceRef debug_15_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_14__ "slave_fifo32/debug2<14>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_14))
+                (portRef I (instanceRef debug_14_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_13__ "slave_fifo32/debug2<13>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_13))
+                (portRef I (instanceRef debug_13_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_12__ "slave_fifo32/debug2<12>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_12))
+                (portRef I (instanceRef debug_12_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_11__ "slave_fifo32/debug2<11>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_11))
+                (portRef I (instanceRef debug_11_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_10__ "slave_fifo32/debug2<10>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_10))
+                (portRef I (instanceRef debug_10_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_9__ "slave_fifo32/debug2<9>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_9))
+                (portRef I (instanceRef debug_9_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_8__ "slave_fifo32/debug2<8>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_8))
+                (portRef I (instanceRef debug_8_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_7__ "slave_fifo32/debug2<7>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_7))
+                (portRef I (instanceRef debug_7_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_6__ "slave_fifo32/debug2<6>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_6))
+                (portRef I (instanceRef debug_6_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_5__ "slave_fifo32/debug2<5>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_5))
+                (portRef I (instanceRef debug_5_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_4__ "slave_fifo32/debug2<4>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_4))
+                (portRef I (instanceRef debug_4_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_3__ "slave_fifo32/debug2<3>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_3))
+                (portRef I (instanceRef debug_3_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_2__ "slave_fifo32/debug2<2>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_2))
+                (portRef I (instanceRef debug_2_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_1__ "slave_fifo32/debug2<1>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_1))
+                (portRef I (instanceRef debug_1_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_debug2_0__ "slave_fifo32/debug2<0>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug2_0))
+                (portRef I (instanceRef debug_0_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe "slave_fifo32/sloe")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_sloe_rstpot_renamed_541))
+                (portRef Q (instanceRef slave_fifo32_sloe_renamed_540))
+              )
+            )
+            (net (rename slave_fifo32_slrd "slave_fifo32/slrd")
+              (joined
+                (portRef I (instanceRef GPIF_CTL3_OBUF))
+                (portRef Q (instanceRef slave_fifo32_slrd_renamed_257))
+              )
+            )
+            (net (rename slave_fifo32_slwr "slave_fifo32/slwr")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_slwr_renamed_7))
+                (portRef I (instanceRef GPIF_CTL1_OBUF))
+              )
+            )
+            (net (rename slave_fifo32_pktend "slave_fifo32/pktend")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_pktend_renamed_6))
+                (portRef I (instanceRef GPIF_CTL7_OBUF))
+              )
+            )
+            (net tx_tlast
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef (member DIADI 15) (instanceRef f1_ram_Mram_ram33))
+              )
+            )
+            (net ctrl_tlast
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef (member DIADI 15) (instanceRef f0_ram_Mram_ram33))
+              )
+            )
+            (net (rename bus_sync_reset_out "bus_sync/reset_out")
+              (joined
+                (portRef Q (instanceRef bus_sync_reset_out_renamed_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_8))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_9))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_renamed_24))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_renamed_23))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_11))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_renamed_28))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_renamed_27))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9))
+                (portRef R (instanceRef f1_read_state_FSM_FFd2_renamed_30))
+                (portRef R (instanceRef f0_read_state_FSM_FFd2_renamed_32))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7))
+                (portRef R (instanceRef f1_wr_addr_9))
+                (portRef R (instanceRef f1_wr_addr_8))
+                (portRef R (instanceRef f1_wr_addr_7))
+                (portRef R (instanceRef f1_wr_addr_6))
+                (portRef R (instanceRef f1_wr_addr_5))
+                (portRef R (instanceRef f1_wr_addr_4))
+                (portRef R (instanceRef f1_wr_addr_3))
+                (portRef R (instanceRef f1_wr_addr_2))
+                (portRef R (instanceRef f1_wr_addr_12))
+                (portRef R (instanceRef f1_wr_addr_11))
+                (portRef R (instanceRef f1_wr_addr_10))
+                (portRef R (instanceRef f1_wr_addr_1))
+                (portRef R (instanceRef f1_wr_addr_0))
+                (portRef R (instanceRef f1_rd_addr_9))
+                (portRef R (instanceRef f1_rd_addr_8))
+                (portRef R (instanceRef f1_rd_addr_7))
+                (portRef R (instanceRef f1_rd_addr_6))
+                (portRef R (instanceRef f1_rd_addr_5))
+                (portRef R (instanceRef f1_rd_addr_4))
+                (portRef R (instanceRef f1_rd_addr_3))
+                (portRef R (instanceRef f1_rd_addr_2))
+                (portRef R (instanceRef f1_rd_addr_12))
+                (portRef R (instanceRef f1_rd_addr_11))
+                (portRef R (instanceRef f1_rd_addr_10))
+                (portRef R (instanceRef f1_rd_addr_1))
+                (portRef R (instanceRef f1_rd_addr_0))
+                (portRef R (instanceRef f1_read_state_FSM_FFd1_renamed_29))
+                (portRef R (instanceRef f0_wr_addr_9))
+                (portRef R (instanceRef f0_wr_addr_8))
+                (portRef R (instanceRef f0_wr_addr_7))
+                (portRef R (instanceRef f0_wr_addr_6))
+                (portRef R (instanceRef f0_wr_addr_5))
+                (portRef R (instanceRef f0_wr_addr_4))
+                (portRef R (instanceRef f0_wr_addr_3))
+                (portRef R (instanceRef f0_wr_addr_2))
+                (portRef R (instanceRef f0_wr_addr_12))
+                (portRef R (instanceRef f0_wr_addr_11))
+                (portRef R (instanceRef f0_wr_addr_10))
+                (portRef R (instanceRef f0_wr_addr_1))
+                (portRef R (instanceRef f0_wr_addr_0))
+                (portRef R (instanceRef f0_rd_addr_9))
+                (portRef R (instanceRef f0_rd_addr_8))
+                (portRef R (instanceRef f0_rd_addr_7))
+                (portRef R (instanceRef f0_rd_addr_6))
+                (portRef R (instanceRef f0_rd_addr_5))
+                (portRef R (instanceRef f0_rd_addr_4))
+                (portRef R (instanceRef f0_rd_addr_3))
+                (portRef R (instanceRef f0_rd_addr_2))
+                (portRef R (instanceRef f0_rd_addr_12))
+                (portRef R (instanceRef f0_rd_addr_11))
+                (portRef R (instanceRef f0_rd_addr_10))
+                (portRef R (instanceRef f0_rd_addr_1))
+                (portRef R (instanceRef f0_rd_addr_0))
+                (portRef R (instanceRef f0_read_state_FSM_FFd1_renamed_31))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo_rst_gpif_rst_OR_155_o1))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_renamed_96))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_renamed_97))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_renamed_98))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_renamed_99))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_renamed_100))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_renamed_101))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_renamed_104))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_renamed_105))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_renamed_106))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_renamed_108))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_renamed_109))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_renamed_110))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_renamed_111))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_renamed_112))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_renamed_114))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_renamed_115))
+                (portRef R (instanceRef f1_full_reg_renamed_116))
+                (portRef R (instanceRef f0_full_reg_renamed_117))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_renamed_258))
+                (portRef S (instanceRef f1_Result_0_2_FRB_renamed_337))
+                (portRef R (instanceRef f1_Result_1_2_FRB_renamed_338))
+                (portRef R (instanceRef f1_Result_2_2_FRB_renamed_339))
+                (portRef R (instanceRef f1_Result_3_2_FRB_renamed_340))
+                (portRef R (instanceRef f1_Result_4_2_FRB_renamed_341))
+                (portRef R (instanceRef f1_Result_5_2_FRB_renamed_342))
+                (portRef R (instanceRef f1_Result_6_2_FRB_renamed_343))
+                (portRef R (instanceRef f1_Result_7_2_FRB_renamed_344))
+                (portRef R (instanceRef f1_Result_8_2_FRB_renamed_345))
+                (portRef R (instanceRef f1_Result_9_2_FRB_renamed_346))
+                (portRef R (instanceRef f1_Result_10_2_FRB_renamed_347))
+                (portRef R (instanceRef f1_Result_11_2_FRB_renamed_348))
+                (portRef R (instanceRef f1_Result_12_2_FRB_renamed_349))
+                (portRef S (instanceRef f1_Result_0_1_FRB_renamed_350))
+                (portRef R (instanceRef f1_Result_1_1_FRB_renamed_351))
+                (portRef R (instanceRef f1_Result_2_1_FRB_renamed_352))
+                (portRef R (instanceRef f1_Result_3_1_FRB_renamed_353))
+                (portRef R (instanceRef f1_Result_4_1_FRB_renamed_354))
+                (portRef R (instanceRef f1_Result_5_1_FRB_renamed_355))
+                (portRef R (instanceRef f1_Result_6_1_FRB_renamed_356))
+                (portRef R (instanceRef f1_Result_7_1_FRB_renamed_357))
+                (portRef R (instanceRef f1_Result_8_1_FRB_renamed_358))
+                (portRef R (instanceRef f1_Result_9_1_FRB_renamed_359))
+                (portRef R (instanceRef f1_Result_10_1_FRB_renamed_360))
+                (portRef R (instanceRef f1_Result_11_1_FRB_renamed_361))
+                (portRef R (instanceRef f1_Result_12_1_FRB_renamed_362))
+                (portRef S (instanceRef f1_dont_write_past_me_0__FRB_renamed_363))
+                (portRef R (instanceRef f1_dont_write_past_me_1__FRB_renamed_364))
+                (portRef S (instanceRef f1_dont_write_past_me_2__FRB_renamed_365))
+                (portRef S (instanceRef f1_dont_write_past_me_3__FRB_renamed_366))
+                (portRef S (instanceRef f1_dont_write_past_me_4__FRB_renamed_367))
+                (portRef S (instanceRef f1_dont_write_past_me_5__FRB_renamed_368))
+                (portRef S (instanceRef f1_dont_write_past_me_6__FRB_renamed_369))
+                (portRef S (instanceRef f1_dont_write_past_me_7__FRB_renamed_370))
+                (portRef S (instanceRef f1_dont_write_past_me_8__FRB_renamed_371))
+                (portRef S (instanceRef f1_dont_write_past_me_9__FRB_renamed_372))
+                (portRef S (instanceRef f1_dont_write_past_me_10__FRB_renamed_373))
+                (portRef S (instanceRef f1_dont_write_past_me_11__FRB_renamed_374))
+                (portRef S (instanceRef f1_dont_write_past_me_12__FRB_renamed_375))
+                (portRef S (instanceRef f0_Result_0_2_FRB_renamed_376))
+                (portRef R (instanceRef f0_Result_1_2_FRB_renamed_377))
+                (portRef R (instanceRef f0_Result_2_2_FRB_renamed_378))
+                (portRef R (instanceRef f0_Result_3_2_FRB_renamed_379))
+                (portRef R (instanceRef f0_Result_4_2_FRB_renamed_380))
+                (portRef R (instanceRef f0_Result_5_2_FRB_renamed_381))
+                (portRef R (instanceRef f0_Result_6_2_FRB_renamed_382))
+                (portRef R (instanceRef f0_Result_7_2_FRB_renamed_383))
+                (portRef R (instanceRef f0_Result_8_2_FRB_renamed_384))
+                (portRef R (instanceRef f0_Result_9_2_FRB_renamed_385))
+                (portRef R (instanceRef f0_Result_10_2_FRB_renamed_386))
+                (portRef R (instanceRef f0_Result_11_2_FRB_renamed_387))
+                (portRef R (instanceRef f0_Result_12_2_FRB_renamed_388))
+                (portRef S (instanceRef f0_Result_0_1_FRB_renamed_389))
+                (portRef R (instanceRef f0_Result_1_1_FRB_renamed_390))
+                (portRef R (instanceRef f0_Result_2_1_FRB_renamed_391))
+                (portRef R (instanceRef f0_Result_3_1_FRB_renamed_392))
+                (portRef R (instanceRef f0_Result_4_1_FRB_renamed_393))
+                (portRef R (instanceRef f0_Result_5_1_FRB_renamed_394))
+                (portRef R (instanceRef f0_Result_6_1_FRB_renamed_395))
+                (portRef R (instanceRef f0_Result_7_1_FRB_renamed_396))
+                (portRef R (instanceRef f0_Result_8_1_FRB_renamed_397))
+                (portRef R (instanceRef f0_Result_9_1_FRB_renamed_398))
+                (portRef R (instanceRef f0_Result_10_1_FRB_renamed_399))
+                (portRef R (instanceRef f0_Result_11_1_FRB_renamed_400))
+                (portRef R (instanceRef f0_Result_12_1_FRB_renamed_401))
+                (portRef S (instanceRef f0_dont_write_past_me_0__FRB_renamed_402))
+                (portRef R (instanceRef f0_dont_write_past_me_1__FRB_renamed_403))
+                (portRef S (instanceRef f0_dont_write_past_me_2__FRB_renamed_404))
+                (portRef S (instanceRef f0_dont_write_past_me_3__FRB_renamed_405))
+                (portRef S (instanceRef f0_dont_write_past_me_4__FRB_renamed_406))
+                (portRef S (instanceRef f0_dont_write_past_me_5__FRB_renamed_407))
+                (portRef S (instanceRef f0_dont_write_past_me_6__FRB_renamed_408))
+                (portRef S (instanceRef f0_dont_write_past_me_7__FRB_renamed_409))
+                (portRef S (instanceRef f0_dont_write_past_me_8__FRB_renamed_410))
+                (portRef S (instanceRef f0_dont_write_past_me_9__FRB_renamed_411))
+                (portRef S (instanceRef f0_dont_write_past_me_10__FRB_renamed_412))
+                (portRef S (instanceRef f0_dont_write_past_me_11__FRB_renamed_413))
+                (portRef S (instanceRef f0_dont_write_past_me_12__FRB_renamed_414))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_renamed_417))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_renamed_418))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB_renamed_463))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_478))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_484))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_renamed_535))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_renamed_536))
+                (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1_renamed_539))
+              )
+            )
+            (net (rename n0035_63_ "n0035<63>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram32))
+              )
+            )
+            (net (rename n0035_62_ "n0035<62>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram32))
+              )
+            )
+            (net (rename n0035_61_ "n0035<61>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram31))
+              )
+            )
+            (net (rename n0035_60_ "n0035<60>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram31))
+              )
+            )
+            (net (rename n0035_59_ "n0035<59>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram30))
+              )
+            )
+            (net (rename n0035_58_ "n0035<58>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_58__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram30))
+              )
+            )
+            (net (rename n0035_57_ "n0035<57>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_57__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram29))
+              )
+            )
+            (net (rename n0035_56_ "n0035<56>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_56__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram29))
+              )
+            )
+            (net (rename n0035_55_ "n0035<55>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_55__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram28))
+              )
+            )
+            (net (rename n0035_54_ "n0035<54>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram28))
+              )
+            )
+            (net (rename n0035_53_ "n0035<53>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_53__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram27))
+              )
+            )
+            (net (rename n0035_52_ "n0035<52>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_52__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram27))
+              )
+            )
+            (net (rename n0035_51_ "n0035<51>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_51__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram26))
+              )
+            )
+            (net (rename n0035_50_ "n0035<50>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_50__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram26))
+              )
+            )
+            (net (rename n0035_49_ "n0035<49>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_49__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram25))
+              )
+            )
+            (net (rename n0035_48_ "n0035<48>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_48__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram25))
+              )
+            )
+            (net (rename n0035_47_ "n0035<47>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_47__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram24))
+              )
+            )
+            (net (rename n0035_46_ "n0035<46>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_46__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram24))
+              )
+            )
+            (net (rename n0035_45_ "n0035<45>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_45__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram23))
+              )
+            )
+            (net (rename n0035_44_ "n0035<44>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_44__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram23))
+              )
+            )
+            (net (rename n0035_43_ "n0035<43>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_43__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram22))
+              )
+            )
+            (net (rename n0035_42_ "n0035<42>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_42__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram22))
+              )
+            )
+            (net (rename n0035_41_ "n0035<41>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_41__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram21))
+              )
+            )
+            (net (rename n0035_40_ "n0035<40>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_40__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram21))
+              )
+            )
+            (net (rename n0035_39_ "n0035<39>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_39__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram20))
+              )
+            )
+            (net (rename n0035_38_ "n0035<38>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_38__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram20))
+              )
+            )
+            (net (rename n0035_37_ "n0035<37>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_37__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram19))
+              )
+            )
+            (net (rename n0035_36_ "n0035<36>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_36__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram19))
+              )
+            )
+            (net (rename n0035_35_ "n0035<35>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_35__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram18))
+              )
+            )
+            (net (rename n0035_34_ "n0035<34>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_34__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram18))
+              )
+            )
+            (net (rename n0035_33_ "n0035<33>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_33__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram17))
+              )
+            )
+            (net (rename n0035_32_ "n0035<32>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_32__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram17))
+              )
+            )
+            (net (rename n0035_31_ "n0035<31>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_31__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram16))
+              )
+            )
+            (net (rename n0035_30_ "n0035<30>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_30__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram16))
+              )
+            )
+            (net (rename n0035_29_ "n0035<29>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_29__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram15))
+              )
+            )
+            (net (rename n0035_28_ "n0035<28>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_28__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram15))
+              )
+            )
+            (net (rename n0035_27_ "n0035<27>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_27__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram14))
+              )
+            )
+            (net (rename n0035_26_ "n0035<26>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_26__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram14))
+              )
+            )
+            (net (rename n0035_25_ "n0035<25>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_25__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram13))
+              )
+            )
+            (net (rename n0035_24_ "n0035<24>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_24__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram13))
+              )
+            )
+            (net (rename n0035_23_ "n0035<23>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_23__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram12))
+              )
+            )
+            (net (rename n0035_22_ "n0035<22>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_22__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram12))
+              )
+            )
+            (net (rename n0035_21_ "n0035<21>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_21__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram11))
+              )
+            )
+            (net (rename n0035_20_ "n0035<20>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_20__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram11))
+              )
+            )
+            (net (rename n0035_19_ "n0035<19>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_19__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram10))
+              )
+            )
+            (net (rename n0035_18_ "n0035<18>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_18__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram10))
+              )
+            )
+            (net (rename n0035_17_ "n0035<17>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_17__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram9))
+              )
+            )
+            (net (rename n0035_16_ "n0035<16>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_16__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram9))
+              )
+            )
+            (net (rename n0035_15_ "n0035<15>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_15__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram8))
+              )
+            )
+            (net (rename n0035_14_ "n0035<14>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_14__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram8))
+              )
+            )
+            (net (rename n0035_13_ "n0035<13>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_13__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram7))
+              )
+            )
+            (net (rename n0035_12_ "n0035<12>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_12__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram7))
+              )
+            )
+            (net (rename n0035_11_ "n0035<11>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_11__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram6))
+              )
+            )
+            (net (rename n0035_10_ "n0035<10>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram6))
+              )
+            )
+            (net (rename n0035_9_ "n0035<9>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_9__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram5))
+              )
+            )
+            (net (rename n0035_8_ "n0035<8>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_8__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram5))
+              )
+            )
+            (net (rename n0035_7_ "n0035<7>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_7__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram4))
+              )
+            )
+            (net (rename n0035_6_ "n0035<6>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_6__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram4))
+              )
+            )
+            (net (rename n0035_5_ "n0035<5>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_5__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram3))
+              )
+            )
+            (net (rename n0035_4_ "n0035<4>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram3))
+              )
+            )
+            (net (rename n0035_3_ "n0035<3>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram2))
+              )
+            )
+            (net (rename n0035_2_ "n0035<2>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram2))
+              )
+            )
+            (net (rename n0035_1_ "n0035<1>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e))
+                (portRef (member DOB 30) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename n0035_0_ "n0035<0>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e))
+                (portRef (member DOB 31) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename n0035_64_ "n0035<64>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef (member DOBDO 15) (instanceRef f0_ram_Mram_ram33))
+              )
+            )
+            (net (rename n0036_63_ "n0036<63>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram32))
+              )
+            )
+            (net (rename n0036_62_ "n0036<62>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram32))
+              )
+            )
+            (net (rename n0036_61_ "n0036<61>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram31))
+              )
+            )
+            (net (rename n0036_60_ "n0036<60>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram31))
+              )
+            )
+            (net (rename n0036_59_ "n0036<59>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_59__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram30))
+              )
+            )
+            (net (rename n0036_58_ "n0036<58>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_58__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram30))
+              )
+            )
+            (net (rename n0036_57_ "n0036<57>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_57__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram29))
+              )
+            )
+            (net (rename n0036_56_ "n0036<56>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_56__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram29))
+              )
+            )
+            (net (rename n0036_55_ "n0036<55>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_55__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram28))
+              )
+            )
+            (net (rename n0036_54_ "n0036<54>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_54__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram28))
+              )
+            )
+            (net (rename n0036_53_ "n0036<53>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_53__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram27))
+              )
+            )
+            (net (rename n0036_52_ "n0036<52>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_52__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram27))
+              )
+            )
+            (net (rename n0036_51_ "n0036<51>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram26))
+              )
+            )
+            (net (rename n0036_50_ "n0036<50>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram26))
+              )
+            )
+            (net (rename n0036_49_ "n0036<49>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_49__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram25))
+              )
+            )
+            (net (rename n0036_48_ "n0036<48>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_48__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram25))
+              )
+            )
+            (net (rename n0036_47_ "n0036<47>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram24))
+              )
+            )
+            (net (rename n0036_46_ "n0036<46>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram24))
+              )
+            )
+            (net (rename n0036_45_ "n0036<45>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram23))
+              )
+            )
+            (net (rename n0036_44_ "n0036<44>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram23))
+              )
+            )
+            (net (rename n0036_43_ "n0036<43>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram22))
+              )
+            )
+            (net (rename n0036_42_ "n0036<42>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_42__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram22))
+              )
+            )
+            (net (rename n0036_41_ "n0036<41>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_41__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram21))
+              )
+            )
+            (net (rename n0036_40_ "n0036<40>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram21))
+              )
+            )
+            (net (rename n0036_39_ "n0036<39>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_39__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram20))
+              )
+            )
+            (net (rename n0036_38_ "n0036<38>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram20))
+              )
+            )
+            (net (rename n0036_37_ "n0036<37>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram19))
+              )
+            )
+            (net (rename n0036_36_ "n0036<36>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_36__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram19))
+              )
+            )
+            (net (rename n0036_35_ "n0036<35>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_35__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram18))
+              )
+            )
+            (net (rename n0036_34_ "n0036<34>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_34__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram18))
+              )
+            )
+            (net (rename n0036_33_ "n0036<33>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_33__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram17))
+              )
+            )
+            (net (rename n0036_32_ "n0036<32>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_32__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram17))
+              )
+            )
+            (net (rename n0036_31_ "n0036<31>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_31__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram16))
+              )
+            )
+            (net (rename n0036_30_ "n0036<30>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_30__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram16))
+              )
+            )
+            (net (rename n0036_29_ "n0036<29>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_29__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram15))
+              )
+            )
+            (net (rename n0036_28_ "n0036<28>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_28__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram15))
+              )
+            )
+            (net (rename n0036_27_ "n0036<27>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_27__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram14))
+              )
+            )
+            (net (rename n0036_26_ "n0036<26>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_26__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram14))
+              )
+            )
+            (net (rename n0036_25_ "n0036<25>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_25__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram13))
+              )
+            )
+            (net (rename n0036_24_ "n0036<24>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_24__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram13))
+              )
+            )
+            (net (rename n0036_23_ "n0036<23>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_23__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram12))
+              )
+            )
+            (net (rename n0036_22_ "n0036<22>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_22__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram12))
+              )
+            )
+            (net (rename n0036_21_ "n0036<21>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_21__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram11))
+              )
+            )
+            (net (rename n0036_20_ "n0036<20>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_20__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram11))
+              )
+            )
+            (net (rename n0036_19_ "n0036<19>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_19__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram10))
+              )
+            )
+            (net (rename n0036_18_ "n0036<18>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_18__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram10))
+              )
+            )
+            (net (rename n0036_17_ "n0036<17>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_17__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram9))
+              )
+            )
+            (net (rename n0036_16_ "n0036<16>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_16__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram9))
+              )
+            )
+            (net (rename n0036_15_ "n0036<15>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_15__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram8))
+              )
+            )
+            (net (rename n0036_14_ "n0036<14>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_14__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram8))
+              )
+            )
+            (net (rename n0036_13_ "n0036<13>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram7))
+              )
+            )
+            (net (rename n0036_12_ "n0036<12>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram7))
+              )
+            )
+            (net (rename n0036_11_ "n0036<11>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_11__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram6))
+              )
+            )
+            (net (rename n0036_10_ "n0036<10>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram6))
+              )
+            )
+            (net (rename n0036_9_ "n0036<9>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_9__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram5))
+              )
+            )
+            (net (rename n0036_8_ "n0036<8>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram5))
+              )
+            )
+            (net (rename n0036_7_ "n0036<7>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram4))
+              )
+            )
+            (net (rename n0036_6_ "n0036<6>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram4))
+              )
+            )
+            (net (rename n0036_5_ "n0036<5>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram3))
+              )
+            )
+            (net (rename n0036_4_ "n0036<4>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram3))
+              )
+            )
+            (net (rename n0036_3_ "n0036<3>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram2))
+              )
+            )
+            (net (rename n0036_2_ "n0036<2>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram2))
+              )
+            )
+            (net (rename n0036_1_ "n0036<1>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e))
+                (portRef (member DOB 30) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename n0036_0_ "n0036<0>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e))
+                (portRef (member DOB 31) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename n0036_64_ "n0036<64>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef (member DOBDO 15) (instanceRef f1_ram_Mram_ram33))
+              )
+            )
+            (net (rename gen_clks_CLK_OUT1_40_int "gen_clks/CLK_OUT1_40_int")
+              (joined
+                (portRef O (instanceRef gen_clks_clkout1_buf))
+                (portRef CLKFB (instanceRef gen_clks_dcm_sp_inst))
+              )
+            )
+            (net (rename gen_clks_clkfx "gen_clks/clkfx")
+              (joined
+                (portRef I (instanceRef gen_clks_clkout3_buf))
+                (portRef I (instanceRef gen_clks_clkout2_buf))
+                (portRef CLKFX (instanceRef gen_clks_dcm_sp_inst))
+              )
+            )
+            (net (rename gen_clks_clk0 "gen_clks/clk0")
+              (joined
+                (portRef I (instanceRef gen_clks_clkout1_buf))
+                (portRef CLK0 (instanceRef gen_clks_dcm_sp_inst))
+              )
+            )
+            (net (rename gen_clks_clkin1 "gen_clks/clkin1")
+              (joined
+                (portRef CLKIN (instanceRef gen_clks_dcm_sp_inst))
+                (portRef O (instanceRef gen_clks_clkin1_buf))
+              )
+            )
+            (net (rename bus_sync_reset_int "bus_sync/reset_int")
+              (joined
+                (portRef Q (instanceRef bus_sync_reset_int_renamed_1))
+                (portRef D (instanceRef bus_sync_reset_out_renamed_0))
+              )
+            )
+            (net (rename gpif_sync_reset_int "gpif_sync/reset_int")
+              (joined
+                (portRef Q (instanceRef gpif_sync_reset_int_renamed_3))
+                (portRef D (instanceRef gpif_sync_reset_out_renamed_2))
+              )
+            )
+            (net (rename slave_fifo32_Mcount_idle_cycles2 "slave_fifo32/Mcount_idle_cycles2")
+              (joined
+                (portRef D (instanceRef slave_fifo32_idle_cycles_2))
+                (portRef O (instanceRef slave_fifo32_Mcount_idle_cycles_xor_2_11))
+              )
+            )
+            (net (rename slave_fifo32_Mcount_idle_cycles1 "slave_fifo32/Mcount_idle_cycles1")
+              (joined
+                (portRef D (instanceRef slave_fifo32_idle_cycles_1))
+                (portRef O (instanceRef slave_fifo32_Mcount_idle_cycles_xor_1_11))
+              )
+            )
+            (net (rename slave_fifo32_Mcount_idle_cycles "slave_fifo32/Mcount_idle_cycles")
+              (joined
+                (portRef D (instanceRef slave_fifo32_idle_cycles_0))
+                (portRef O (instanceRef slave_fifo32_Mcount_idle_cycles_xor_0_11))
+              )
+            )
+            (net (rename slave_fifo32__n0230_inv "slave_fifo32/_n0230_inv")
+              (joined
+                (portRef CE (instanceRef slave_fifo32_idle_cycles_0))
+                (portRef CE (instanceRef slave_fifo32_idle_cycles_1))
+                (portRef CE (instanceRef slave_fifo32_idle_cycles_2))
+                (portRef O (instanceRef slave_fifo32__n0230_inv1))
+              )
+            )
+            (net (rename slave_fifo32_Result_1_ "slave_fifo32/Result<1>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifoadr_1))
+                (portRef O (instanceRef slave_fifo32_Mcount_fifoadr_xor_1_11))
+                (portRef D (instanceRef slave_fifo32_fifoadr_1_1_renamed_552))
+              )
+            )
+            (net (rename slave_fifo32_Result_0_ "slave_fifo32/Result<0>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifoadr_0))
+                (portRef O (instanceRef slave_fifo32_Mcount_fifoadr_xor_0_11_INV_0))
+                (portRef D (instanceRef slave_fifo32_fifoadr_0_1_renamed_553))
+              )
+            )
+            (net (rename slave_fifo32__n0237_inv "slave_fifo32/_n0237_inv")
+              (joined
+                (portRef CE (instanceRef slave_fifo32_fifoadr_0))
+                (portRef CE (instanceRef slave_fifo32_fifoadr_1))
+                (portRef O (instanceRef slave_fifo32__n0237_inv1))
+                (portRef CE (instanceRef slave_fifo32_fifoadr_1_1_renamed_552))
+                (portRef CE (instanceRef slave_fifo32_fifoadr_0_1_renamed_553))
+              )
+            )
+            (net (rename slave_fifo32_state_FSM_FFd1_In "slave_fifo32/state_FSM_FFd1-In")
+              (joined
+                (portRef D (instanceRef slave_fifo32_state_FSM_FFd1_renamed_4))
+                (portRef O (instanceRef slave_fifo32_state_FSM_FFd1_In4))
+              )
+            )
+            (net (rename slave_fifo32_state_FSM_FFd2_In "slave_fifo32/state_FSM_FFd2-In")
+              (joined
+                (portRef D (instanceRef slave_fifo32_state_FSM_FFd2_renamed_5))
+                (portRef O (instanceRef slave_fifo32_state_FSM_FFd2_In3))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_63_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<63>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata251))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_62_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<62>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata241))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_61_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<61>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata221))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_60_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<60>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata211))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_59_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<59>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata201))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_58_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<58>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_58__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata191))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_57_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<57>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_57__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata181))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_56_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<56>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_56__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata171))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_55_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<55>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_55__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata161))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_54_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<54>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata151))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_53_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<53>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_53__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata141))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_52_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<52>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_52__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata131))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_51_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<51>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_51__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata111))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_50_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<50>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_50__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata101))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_49_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<49>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_49__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata91))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_48_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<48>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_48__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata81))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_47_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<47>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_47__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata71))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_46_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<46>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_46__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata61))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_45_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<45>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_45__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata51))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_44_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003<44>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_44__srlc32e))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata41))
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+                (portRef (member dout 63) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_7_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005<7>")
+              (joined
+                (portRef (member DIA 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+                (portRef (member dout 64) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_6_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005<6>")
+              (joined
+                (portRef (member DIA 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+                (portRef (member dout 65) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_5_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005<5>")
+              (joined
+                (portRef (member DIA 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+                (portRef (member dout 66) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_4_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005<4>")
+              (joined
+                (portRef (member DIA 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+                (portRef (member dout 67) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_3_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005<3>")
+              (joined
+                (portRef (member DIA 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 68) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_2_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005<2>")
+              (joined
+                (portRef (member DIA 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 69) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_1_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005<1>")
+              (joined
+                (portRef (member DIA 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef (member dout 70) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_0_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005<0>")
+              (joined
+                (portRef (member DIA 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef (member dout 71) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_32_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005<32>")
+              (joined
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+                (portRef (member DIADI 15) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt__n0074_inv1))
+                (portRef (member dout 39) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32__n0223_inv "slave_fifo32/_n0223_inv")
+              (joined
+                (portRef CE (instanceRef slave_fifo32_pktend_renamed_6))
+                (portRef CE (instanceRef slave_fifo32_slwr_renamed_7))
+                (portRef O (instanceRef slave_fifo32__n0223_inv1))
+                (portRef I0 (instanceRef slave_fifo32_gpif_data_out_31_rstpot_renamed_542))
+                (portRef CE (instanceRef slave_fifo32_slwr_1_renamed_548))
+                (portRef CE (instanceRef slave_fifo32_pktend_1_renamed_551))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_30))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_29))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_28))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_27))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_26))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_25))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_24))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_23))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_22))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_21))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_20))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_19))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_18))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_17))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_16))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_15))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_14))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_13))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_12))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_11))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_10))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_9))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_8))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_7))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_6))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_5))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_4))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_3))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_2))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_1))
+                (portRef CE (instanceRef slave_fifo32_gpif_data_out_0))
+              )
+            )
+            (net (rename slave_fifo32__n0290_inv "slave_fifo32/_n0290_inv")
+              (joined
+                (portRef O (instanceRef slave_fifo32__n0290_inv1))
+                (portRef I0 (instanceRef slave_fifo32_sloe_rstpot_renamed_541))
+              )
+            )
+            (net (rename slave_fifo32__n0279_inv "slave_fifo32/_n0279_inv")
+              (joined
+                (portRef O (instanceRef slave_fifo32__n0279_inv_renamed_35))
+                (portRef D (instanceRef slave_fifo32_rd_one_BRB0_renamed_498))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o "slave_fifo32/ctrl_tx_tready_data_tx_tready_OR_55_o")
+              (joined
+                (portRef D (instanceRef slave_fifo32_read_ready_go_renamed_15))
+                (portRef O (instanceRef slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o "slave_fifo32/ctrl_rx_tvalid_data_rx_tvalid_OR_56_o")
+              (joined
+                (portRef D (instanceRef slave_fifo32_write_ready_go_renamed_14))
+                (portRef O (instanceRef slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_tx_tvalid "slave_fifo32/ctrl_tx_tvalid")
+              (joined
+                (portRef D (instanceRef slave_fifo32_debug1_19))
+                (portRef O (instanceRef slave_fifo32_ctrl_tx_tvalid1))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0_renamed_476))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2))
+              )
+            )
+            (net (rename slave_fifo32_data_tx_tvalid "slave_fifo32/data_tx_tvalid")
+              (joined
+                (portRef O (instanceRef slave_fifo32_data_tx_tvalid1))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB0_renamed_474))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv31))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_write_AND_42_o_inv2))
+              )
+            )
+            (net (rename slave_fifo32_state_1__wr_fifo_eof_Mux_22_o "slave_fifo32/state[1]_wr_fifo_eof_Mux_22_o")
+              (joined
+                (portRef D (instanceRef slave_fifo32_pktend_renamed_6))
+                (portRef O (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1))
+                (portRef D (instanceRef slave_fifo32_pktend_1_renamed_551))
+              )
+            )
+            (net (rename slave_fifo32_state_1__wr_fifo_xfer_Mux_21_o "slave_fifo32/state[1]_wr_fifo_xfer_Mux_21_o")
+              (joined
+                (portRef D (instanceRef slave_fifo32_slwr_renamed_7))
+                (portRef O (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1))
+                (portRef D (instanceRef slave_fifo32_slwr_1_renamed_548))
+              )
+            )
+            (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_0_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT<0>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110))
+                (portRef D (instanceRef slave_fifo32_gpif_data_out_0))
+              )
+            )
+            (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_1_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT<1>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121))
+                (portRef D (instanceRef slave_fifo32_gpif_data_out_1))
+              )
+            )
+            (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_2_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT<2>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231))
+                (portRef D (instanceRef slave_fifo32_gpif_data_out_2))
+              )
+            )
+            (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_3_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT<3>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261))
+                (portRef D (instanceRef slave_fifo32_gpif_data_out_3))
+              )
+            )
+            (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_4_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT<4>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271))
+                (portRef D (instanceRef slave_fifo32_gpif_data_out_4))
+              )
+            )
+            (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_5_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT<5>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281))
+                (portRef D (instanceRef slave_fifo32_gpif_data_out_5))
+              )
+            )
+            (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_6_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT<6>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291))
+                (portRef D (instanceRef slave_fifo32_gpif_data_out_6))
+              )
+            )
+            (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_7_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT<7>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301))
+                (portRef D (instanceRef slave_fifo32_gpif_data_out_7))
+              )
+            )
+            (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_8_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT<8>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311))
+                (portRef D (instanceRef slave_fifo32_gpif_data_out_8))
+              )
+            )
+            (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_9_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT<9>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321))
+                (portRef D (instanceRef slave_fifo32_gpif_data_out_9))
+              )
+            )
+            (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_10_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT<10>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210))
+                (portRef D (instanceRef slave_fifo32_gpif_data_out_10))
+              )
+            )
+            (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_11_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT<11>")
+              (joined
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+              )
+            )
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+            (net (rename slave_fifo32_wr_one "slave_fifo32/wr_one")
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+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0))
+                (portRef Q (instanceRef slave_fifo32_wr_one_renamed_256))
+                (portRef I0 (instanceRef slave_fifo32_wr_one_rstpot_renamed_512))
+                (portRef I0 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0))
+              )
+            )
+            (net (rename slave_fifo32_idle_cycles_0_ "slave_fifo32/idle_cycles<0>")
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+                (portRef I1 (instanceRef slave_fifo32_Mcount_idle_cycles_xor_0_11))
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+                (portRef I1 (instanceRef slave_fifo32_Mcount_idle_cycles_xor_1_11))
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+                (portRef I2 (instanceRef slave_fifo32_state_FSM_FFd2_In1_renamed_37))
+              )
+            )
+            (net (rename slave_fifo32_idle_cycles_1_ "slave_fifo32/idle_cycles<1>")
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+                (portRef I3 (instanceRef slave_fifo32_state_FSM_FFd2_In1_renamed_37))
+              )
+            )
+            (net (rename slave_fifo32_idle_cycles_2_ "slave_fifo32/idle_cycles<2>")
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+              )
+            )
+            (net (rename slave_fifo32_state_FSM_FFd2 "slave_fifo32/state_FSM_FFd2")
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+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_write1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1))
+                (portRef I5 (instanceRef slave_fifo32_sloe_1_rstpot_renamed_534))
+                (portRef I2 (instanceRef slave_fifo32_sloe_rstpot_renamed_541))
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+                (portRef I0 (instanceRef slave_fifo32_state_FSM_FFd1_In3_G))
+                (portRef I1 (instanceRef slave_fifo32_ctrl_tx_tvalid1))
+                (portRef I1 (instanceRef slave_fifo32_data_tx_tvalid1))
+                (portRef I1 (instanceRef slave_fifo32_state_FSM_FFd2_In3))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1))
+              )
+            )
+            (net (rename slave_fifo32_state_FSM_FFd1 "slave_fifo32/state_FSM_FFd1")
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+                (portRef I0 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1))
+                (portRef I0 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0))
+                (portRef I1 (instanceRef slave_fifo32__n0279_inv_renamed_35))
+                (portRef I0 (instanceRef slave_fifo32_state_FSM_FFd2_In2_renamed_38))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1))
+                (portRef I4 (instanceRef slave_fifo32_wr_one_rstpot_renamed_512))
+                (portRef I3 (instanceRef slave_fifo32_slrd_rstpot_renamed_515))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_write1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1))
+                (portRef I4 (instanceRef slave_fifo32_sloe_1_rstpot_renamed_534))
+                (portRef S (instanceRef slave_fifo32_state_FSM_FFd1_In3_renamed_543))
+                (portRef I4 (instanceRef slave_fifo32_ctrl_tx_tvalid1))
+                (portRef I4 (instanceRef slave_fifo32_data_tx_tvalid1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1))
+              )
+            )
+            (net (rename slave_fifo32_EP_READY "slave_fifo32/EP_READY")
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+                (portRef D (instanceRef slave_fifo32_EP_READY1_renamed_12))
+                (portRef D (instanceRef slave_fifo32_EP_READY1_1_renamed_546))
+              )
+            )
+            (net (rename slave_fifo32_debug1_0__ "slave_fifo32/debug1<0>")
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+              )
+            )
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+              )
+            )
+            (net (rename slave_fifo32_debug1_2__ "slave_fifo32/debug1<2>")
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+              )
+            )
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+              )
+            )
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+              )
+            )
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+                (portRef D (instanceRef slave_fifo32_debug2_5))
+              )
+            )
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+              )
+            )
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+              )
+            )
+            (net (rename slave_fifo32_debug1_9__ "slave_fifo32/debug1<9>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_9))
+                (portRef D (instanceRef slave_fifo32_debug2_9))
+              )
+            )
+            (net (rename slave_fifo32_debug1_10__ "slave_fifo32/debug1<10>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_10))
+                (portRef D (instanceRef slave_fifo32_debug2_10))
+              )
+            )
+            (net (rename slave_fifo32_debug1_11__ "slave_fifo32/debug1<11>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_11))
+                (portRef D (instanceRef slave_fifo32_debug2_11))
+              )
+            )
+            (net (rename slave_fifo32_debug1_12__ "slave_fifo32/debug1<12>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_12))
+                (portRef D (instanceRef slave_fifo32_debug2_12))
+              )
+            )
+            (net (rename slave_fifo32_debug1_13__ "slave_fifo32/debug1<13>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_13))
+                (portRef D (instanceRef slave_fifo32_debug2_13))
+              )
+            )
+            (net (rename slave_fifo32_debug1_14__ "slave_fifo32/debug1<14>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_14))
+                (portRef D (instanceRef slave_fifo32_debug2_14))
+              )
+            )
+            (net (rename slave_fifo32_debug1_15__ "slave_fifo32/debug1<15>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_15))
+                (portRef D (instanceRef slave_fifo32_debug2_15))
+              )
+            )
+            (net (rename slave_fifo32_debug1_16__ "slave_fifo32/debug1<16>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_debug2_16))
+                (portRef O (instanceRef f0_i_tready1_INV_0))
+              )
+            )
+            (net (rename slave_fifo32_debug1_17__ "slave_fifo32/debug1<17>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_debug2_17))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_o_tvalid1_INV_0))
+              )
+            )
+            (net (rename slave_fifo32_debug1_18__ "slave_fifo32/debug1<18>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_18))
+                (portRef D (instanceRef slave_fifo32_debug2_18))
+              )
+            )
+            (net (rename slave_fifo32_debug1_19__ "slave_fifo32/debug1<19>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_19))
+                (portRef D (instanceRef slave_fifo32_debug2_19))
+              )
+            )
+            (net (rename slave_fifo32_debug1_21__ "slave_fifo32/debug1<21>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_21))
+                (portRef D (instanceRef slave_fifo32_debug2_21))
+              )
+            )
+            (net (rename slave_fifo32_debug1_22__ "slave_fifo32/debug1<22>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_22))
+                (portRef D (instanceRef slave_fifo32_debug2_22))
+              )
+            )
+            (net (rename slave_fifo32_debug1_23__ "slave_fifo32/debug1<23>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_23))
+                (portRef D (instanceRef slave_fifo32_debug2_23))
+                (portRef I2 (instanceRef slave_fifo32_rd_one_rstpot))
+                (portRef I2 (instanceRef slave_fifo32_state_FSM_FFd1_In3_G))
+              )
+            )
+            (net (rename slave_fifo32_debug1_26__ "slave_fifo32/debug1<26>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_26))
+                (portRef D (instanceRef slave_fifo32_debug2_26))
+              )
+            )
+            (net (rename slave_fifo32_debug1_27__ "slave_fifo32/debug1<27>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_27))
+                (portRef D (instanceRef slave_fifo32_debug2_27))
+              )
+            )
+            (net (rename slave_fifo32_debug1_28__ "slave_fifo32/debug1<28>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_28))
+                (portRef D (instanceRef slave_fifo32_debug2_28))
+              )
+            )
+            (net (rename slave_fifo32_debug1_29__ "slave_fifo32/debug1<29>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_29))
+                (portRef D (instanceRef slave_fifo32_debug2_29))
+              )
+            )
+            (net (rename slave_fifo32_slrd1 "slave_fifo32/slrd1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_slrd1_renamed_10))
+                (portRef D (instanceRef slave_fifo32_slrd2_renamed_9))
+                (portRef D (instanceRef slave_fifo32_slrd2_1_renamed_544))
+              )
+            )
+            (net (rename slave_fifo32_debug1_31__ "slave_fifo32/debug1<31>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_31))
+                (portRef D (instanceRef slave_fifo32_debug2_31))
+              )
+            )
+            (net (rename slave_fifo32_write_ready_go "slave_fifo32/write_ready_go")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_write_ready_go_renamed_14))
+                (portRef I1 (instanceRef slave_fifo32__n0258_inv_SW0))
+                (portRef I0 (instanceRef slave_fifo32__n0279_inv_SW0))
+                (portRef I5 (instanceRef slave_fifo32_state_FSM_FFd2_In2_renamed_38))
+                (portRef I4 (instanceRef slave_fifo32_state_FSM_FFd1_In3_F))
+              )
+            )
+            (net (rename slave_fifo32_read_ready_go "slave_fifo32/read_ready_go")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_read_ready_go_renamed_15))
+                (portRef I2 (instanceRef slave_fifo32__n0290_inv1))
+                (portRef I0 (instanceRef slave_fifo32__n0258_inv_SW0))
+                (portRef I1 (instanceRef slave_fifo32__n0279_inv_SW0))
+                (portRef I3 (instanceRef slave_fifo32_state_FSM_FFd2_In2_renamed_38))
+                (portRef I1 (instanceRef slave_fifo32_slrd_rstpot_SW0))
+                (portRef I2 (instanceRef slave_fifo32_sloe_1_rstpot_renamed_534))
+                (portRef I3 (instanceRef slave_fifo32_state_FSM_FFd1_In3_F))
+              )
+            )
+            (net (rename slave_fifo32_slrd3 "slave_fifo32/slrd3")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_slrd3_renamed_8))
+                (portRef I5 (instanceRef slave_fifo32__n0279_inv_renamed_35))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_write1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1))
+                (portRef I4 (instanceRef slave_fifo32_state_FSM_FFd1_In3_G))
+                (portRef I0 (instanceRef slave_fifo32_ctrl_tx_tvalid1))
+                (portRef I0 (instanceRef slave_fifo32_data_tx_tvalid1))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_0_ "slave_fifo32/gpif_data_in<0>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_0))
+                (portRef D (instanceRef slave_fifo32_debug1_0))
+                (portRef (member DIA 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_1_ "slave_fifo32/gpif_data_in<1>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_1))
+                (portRef D (instanceRef slave_fifo32_debug1_1))
+                (portRef (member DIA 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_2_ "slave_fifo32/gpif_data_in<2>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_2))
+                (portRef D (instanceRef slave_fifo32_debug1_2))
+                (portRef (member DIA 29) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 29) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_3_ "slave_fifo32/gpif_data_in<3>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_3))
+                (portRef D (instanceRef slave_fifo32_debug1_3))
+                (portRef (member DIA 28) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 28) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_4_ "slave_fifo32/gpif_data_in<4>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_4))
+                (portRef D (instanceRef slave_fifo32_debug1_4))
+                (portRef (member DIA 27) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 27) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_5_ "slave_fifo32/gpif_data_in<5>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_5))
+                (portRef D (instanceRef slave_fifo32_debug1_5))
+                (portRef (member DIA 26) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 26) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_6_ "slave_fifo32/gpif_data_in<6>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_6))
+                (portRef D (instanceRef slave_fifo32_debug1_6))
+                (portRef (member DIA 25) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 25) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_7_ "slave_fifo32/gpif_data_in<7>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_7))
+                (portRef D (instanceRef slave_fifo32_debug1_7))
+                (portRef (member DIA 24) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 24) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_8_ "slave_fifo32/gpif_data_in<8>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_8))
+                (portRef D (instanceRef slave_fifo32_debug1_8))
+                (portRef (member DIA 23) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 23) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_9_ "slave_fifo32/gpif_data_in<9>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_9))
+                (portRef D (instanceRef slave_fifo32_debug1_9))
+                (portRef (member DIA 22) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 22) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_10_ "slave_fifo32/gpif_data_in<10>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_10))
+                (portRef D (instanceRef slave_fifo32_debug1_10))
+                (portRef (member DIA 21) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 21) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_11_ "slave_fifo32/gpif_data_in<11>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_11))
+                (portRef D (instanceRef slave_fifo32_debug1_11))
+                (portRef (member DIA 20) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 20) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_12_ "slave_fifo32/gpif_data_in<12>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_12))
+                (portRef D (instanceRef slave_fifo32_debug1_12))
+                (portRef (member DIA 19) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 19) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_13_ "slave_fifo32/gpif_data_in<13>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_13))
+                (portRef D (instanceRef slave_fifo32_debug1_13))
+                (portRef (member DIA 18) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 18) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_14_ "slave_fifo32/gpif_data_in<14>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_14))
+                (portRef D (instanceRef slave_fifo32_debug1_14))
+                (portRef (member DIA 17) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 17) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_15_ "slave_fifo32/gpif_data_in<15>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_15))
+                (portRef D (instanceRef slave_fifo32_debug1_15))
+                (portRef (member DIA 16) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 16) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_16_ "slave_fifo32/gpif_data_in<16>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_16))
+                (portRef (member DIA 15) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 15) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_17_ "slave_fifo32/gpif_data_in<17>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_17))
+                (portRef (member DIA 14) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 14) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_18_ "slave_fifo32/gpif_data_in<18>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_18))
+                (portRef (member DIA 13) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 13) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_19_ "slave_fifo32/gpif_data_in<19>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_19))
+                (portRef (member DIA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_20_ "slave_fifo32/gpif_data_in<20>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_20))
+                (portRef (member DIA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_21_ "slave_fifo32/gpif_data_in<21>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_21))
+                (portRef (member DIA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_22_ "slave_fifo32/gpif_data_in<22>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_22))
+                (portRef (member DIA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_23_ "slave_fifo32/gpif_data_in<23>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_23))
+                (portRef (member DIA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_24_ "slave_fifo32/gpif_data_in<24>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_24))
+                (portRef (member DIA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_25_ "slave_fifo32/gpif_data_in<25>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_25))
+                (portRef (member DIA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_26_ "slave_fifo32/gpif_data_in<26>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_26))
+                (portRef (member DIA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_27_ "slave_fifo32/gpif_data_in<27>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_27))
+                (portRef (member DIA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_28_ "slave_fifo32/gpif_data_in<28>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_28))
+                (portRef (member DIA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_29_ "slave_fifo32/gpif_data_in<29>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_29))
+                (portRef (member DIA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_30_ "slave_fifo32/gpif_data_in<30>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_30))
+                (portRef (member DIA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_in_31_ "slave_fifo32/gpif_data_in<31>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_in_31))
+                (portRef (member DIA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_EP_WMARK "slave_fifo32/EP_WMARK")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_EP_WMARK_renamed_16))
+                (portRef D (instanceRef slave_fifo32_EP_WMARK1_renamed_11))
+                (portRef D (instanceRef slave_fifo32_EP_WMARK1_1_renamed_545))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_i_tready "slave_fifo32/fifo64_to_gpmc32_ctrl/i_tready")
+              (joined
+                (portRef D (instanceRef slave_fifo32_debug1_18))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_i_tready_renamed_26))
+                (portRef I3 (instanceRef slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_i_tready "slave_fifo32/fifo64_to_gpmc32_tx/i_tready")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_i_tready_renamed_22))
+                (portRef I2 (instanceRef slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tvalid "slave_fifo32/ctrl_rx_tvalid")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11))
+                (portRef I5 (instanceRef slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1))
+                (portRef I4 (instanceRef slave_fifo32_state_FSM_FFd1_In2_renamed_36))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tlast "slave_fifo32/ctrl_rx_tlast")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1))
+                (portRef (member DOB 17) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef I1 (instanceRef slave_fifo32_state_FSM_FFd1_In2_renamed_36))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_0_ "slave_fifo32/ctrl_rx_tdata<0>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110))
+                (portRef (member DOB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_1_ "slave_fifo32/ctrl_rx_tdata<1>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121))
+                (portRef (member DOB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_2_ "slave_fifo32/ctrl_rx_tdata<2>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231))
+                (portRef (member DOB 29) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_3_ "slave_fifo32/ctrl_rx_tdata<3>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261))
+                (portRef (member DOB 28) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_4_ "slave_fifo32/ctrl_rx_tdata<4>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271))
+                (portRef (member DOB 27) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_5_ "slave_fifo32/ctrl_rx_tdata<5>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281))
+                (portRef (member DOB 26) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_6_ "slave_fifo32/ctrl_rx_tdata<6>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291))
+                (portRef (member DOB 25) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_7_ "slave_fifo32/ctrl_rx_tdata<7>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301))
+                (portRef (member DOB 24) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_8_ "slave_fifo32/ctrl_rx_tdata<8>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311))
+                (portRef (member DOB 23) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_9_ "slave_fifo32/ctrl_rx_tdata<9>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321))
+                (portRef (member DOB 22) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_10_ "slave_fifo32/ctrl_rx_tdata<10>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210))
+                (portRef (member DOB 21) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_11_ "slave_fifo32/ctrl_rx_tdata<11>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33))
+                (portRef (member DOB 20) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_12_ "slave_fifo32/ctrl_rx_tdata<12>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT41))
+                (portRef (member DOB 19) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_13_ "slave_fifo32/ctrl_rx_tdata<13>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT51))
+                (portRef (member DOB 18) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_14_ "slave_fifo32/ctrl_rx_tdata<14>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT61))
+                (portRef (member DOB 17) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_15_ "slave_fifo32/ctrl_rx_tdata<15>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT71))
+                (portRef (member DOB 16) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_16_ "slave_fifo32/ctrl_rx_tdata<16>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT81))
+                (portRef (member DOPB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_17_ "slave_fifo32/ctrl_rx_tdata<17>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT91))
+                (portRef (member DOPB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_18_ "slave_fifo32/ctrl_rx_tdata<18>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101))
+                (portRef (member DOB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_19_ "slave_fifo32/ctrl_rx_tdata<19>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111))
+                (portRef (member DOB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_20_ "slave_fifo32/ctrl_rx_tdata<20>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131))
+                (portRef (member DOB 29) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_21_ "slave_fifo32/ctrl_rx_tdata<21>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141))
+                (portRef (member DOB 28) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_22_ "slave_fifo32/ctrl_rx_tdata<22>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151))
+                (portRef (member DOB 27) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_23_ "slave_fifo32/ctrl_rx_tdata<23>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161))
+                (portRef (member DOB 26) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_24_ "slave_fifo32/ctrl_rx_tdata<24>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT171))
+                (portRef (member DOB 25) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_25_ "slave_fifo32/ctrl_rx_tdata<25>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT181))
+                (portRef (member DOB 24) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_26_ "slave_fifo32/ctrl_rx_tdata<26>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191))
+                (portRef (member DOB 23) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_27_ "slave_fifo32/ctrl_rx_tdata<27>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201))
+                (portRef (member DOB 22) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_28_ "slave_fifo32/ctrl_rx_tdata<28>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT211))
+                (portRef (member DOB 21) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_29_ "slave_fifo32/ctrl_rx_tdata<29>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221))
+                (portRef (member DOB 20) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_30_ "slave_fifo32/ctrl_rx_tdata<30>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241))
+                (portRef (member DOB 19) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_ctrl_rx_tdata_31_ "slave_fifo32/ctrl_rx_tdata<31>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251))
+                (portRef (member DOB 18) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_data_rx_tvalid "slave_fifo32/data_rx_tvalid")
+              (joined
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1))
+                (portRef I4 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tvalid11))
+                (portRef I5 (instanceRef slave_fifo32_state_FSM_FFd1_In2_renamed_36))
+              )
+            )
+            (net (rename slave_fifo32_data_rx_tlast "slave_fifo32/data_rx_tlast")
+              (joined
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1))
+                (portRef (member DOBDO 15) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+                (portRef I2 (instanceRef slave_fifo32_state_FSM_FFd1_In2_renamed_36))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt__n0074_inv1))
+              )
+            )
+            (net (rename slave_fifo32_data_rx_tdata_0_ "slave_fifo32/data_rx_tdata<0>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110))
+                (portRef (member DOB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_data_rx_tdata_1_ "slave_fifo32/data_rx_tdata<1>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121))
+                (portRef (member DOB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_data_rx_tdata_2_ "slave_fifo32/data_rx_tdata<2>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231))
+                (portRef (member DOB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_data_rx_tdata_3_ "slave_fifo32/data_rx_tdata<3>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261))
+                (portRef (member DOB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_data_rx_tdata_4_ "slave_fifo32/data_rx_tdata<4>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271))
+                (portRef (member DOB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+              )
+            )
+            (net (rename slave_fifo32_data_rx_tdata_5_ "slave_fifo32/data_rx_tdata<5>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281))
+                (portRef (member DOB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+              )
+            )
+            (net (rename slave_fifo32_data_rx_tdata_6_ "slave_fifo32/data_rx_tdata<6>")
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+            (net (rename slave_fifo32_data_rx_tdata_21_ "slave_fifo32/data_rx_tdata<21>")
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+            (net (rename slave_fifo32_data_rx_tdata_23_ "slave_fifo32/data_rx_tdata<23>")
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+            (net (rename slave_fifo32_data_rx_tdata_24_ "slave_fifo32/data_rx_tdata<24>")
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+            (net (rename slave_fifo32_data_rx_tdata_25_ "slave_fifo32/data_rx_tdata<25>")
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+            (net (rename slave_fifo32_data_rx_tdata_26_ "slave_fifo32/data_rx_tdata<26>")
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+            (net (rename slave_fifo32_data_rx_tdata_27_ "slave_fifo32/data_rx_tdata<27>")
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+            (net (rename slave_fifo32_data_rx_tdata_28_ "slave_fifo32/data_rx_tdata<28>")
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+            (net (rename slave_fifo32_data_rx_tdata_29_ "slave_fifo32/data_rx_tdata<29>")
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+            (net (rename slave_fifo32_data_rx_tdata_30_ "slave_fifo32/data_rx_tdata<30>")
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+            (net (rename slave_fifo32_data_rx_tdata_31_ "slave_fifo32/data_rx_tdata<31>")
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+            (net (rename slave_fifo32_state_FSM_FFd1_In2 "slave_fifo32/state_FSM_FFd1-In2")
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+                (portRef I3 (instanceRef slave_fifo32_state_FSM_FFd2_In3))
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+            )
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+                (portRef C1 (instanceRef catgen_oddr2_frame))
+                (portRef C1 (instanceRef catgen_oddr2_clk))
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv")
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1))
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty")
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_write1))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_renamed_99))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_renamed_525))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set_renamed_529))
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+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_renamed_535))
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0_ "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a<0>")
+              (joined
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+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_0_11_INV_0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1_ "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a<1>")
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+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e))
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+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e))
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+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_48__srlc32e))
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+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_56__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_57__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_58__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_59__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_1_11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_3_11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2_ "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a<2>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e))
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+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e))
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+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_16__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_17__srlc32e))
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+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_20__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_21__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_22__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_23__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_24__srlc32e))
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+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_33__srlc32e))
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+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_54__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_55__srlc32e))
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+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_62__srlc32e))
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+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_3_11))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3_ "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a<3>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e))
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+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_SW0))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_SW1))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_0_11_INV_0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1_ "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a<1>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_5__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_6__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_7__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_8__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_9__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_11__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_12__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_13__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_14__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_15__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_16__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_17__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_18__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_19__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_20__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_21__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_22__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_23__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_24__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_25__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_26__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_27__srlc32e))
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+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_30__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_31__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_32__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_33__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_34__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_35__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_36__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_37__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_38__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_39__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_40__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_41__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_42__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_43__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_44__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_45__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_46__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_47__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_48__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_49__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_50__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_51__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_52__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_53__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_55__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_56__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_57__srlc32e))
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+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_2_11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_1_11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_3_11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_4_11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2_ "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a<2>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e))
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+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_2_11))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_3_11))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_4_11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_SW1))
+              )
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+                (portRef I (instanceRef LED_TXRX2_TX_OBUF))
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+                (portRef DI
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+                (portRef DI
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+                (portRef DI
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+                (portRef DI
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+                (portRef (member DIPB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member DIBDI 15) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+                (portRef ENAWREN (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 29) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 28) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 27) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 26) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 25) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 24) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 23) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 22) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 21) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 20) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 19) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 18) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 17) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 16) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 15) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 14) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 13) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
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+                (portRef ENA (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member DIB 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 29) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 28) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 27) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 26) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 25) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 24) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 23) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 22) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 21) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 20) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 19) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 18) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member DIB 17) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
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+                (portRef (member DIB 30) (instanceRef f1_ram_Mram_ram13))
+                (portRef ENA (instanceRef f1_ram_Mram_ram13))
+                (portRef (member DIB 31) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member DIB 30) (instanceRef f1_ram_Mram_ram12))
+                (portRef ENA (instanceRef f1_ram_Mram_ram12))
+                (portRef (member DIB 31) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member DIB 30) (instanceRef f1_ram_Mram_ram11))
+                (portRef ENA (instanceRef f1_ram_Mram_ram11))
+                (portRef (member DIB 31) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member DIB 30) (instanceRef f1_ram_Mram_ram9))
+                (portRef ENA (instanceRef f1_ram_Mram_ram9))
+                (portRef (member DIB 31) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member DIB 30) (instanceRef f1_ram_Mram_ram8))
+                (portRef ENA (instanceRef f1_ram_Mram_ram8))
+                (portRef (member DIB 31) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member DIB 30) (instanceRef f1_ram_Mram_ram10))
+                (portRef ENA (instanceRef f1_ram_Mram_ram10))
+                (portRef (member DIB 31) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member DIB 30) (instanceRef f1_ram_Mram_ram6))
+                (portRef ENA (instanceRef f1_ram_Mram_ram6))
+                (portRef (member DIB 31) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member DIB 30) (instanceRef f1_ram_Mram_ram5))
+                (portRef ENA (instanceRef f1_ram_Mram_ram5))
+                (portRef (member DIB 31) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member DIB 30) (instanceRef f1_ram_Mram_ram7))
+                (portRef ENA (instanceRef f1_ram_Mram_ram7))
+                (portRef (member DIB 31) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member DIB 30) (instanceRef f1_ram_Mram_ram3))
+                (portRef ENA (instanceRef f1_ram_Mram_ram3))
+                (portRef (member DIB 31) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member DIB 30) (instanceRef f1_ram_Mram_ram2))
+                (portRef ENA (instanceRef f1_ram_Mram_ram2))
+                (portRef (member DIB 31) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member DIB 30) (instanceRef f1_ram_Mram_ram4))
+                (portRef ENA (instanceRef f1_ram_Mram_ram4))
+                (portRef (member DIB 31) (instanceRef f1_ram_Mram_ram1))
+                (portRef (member DIB 30) (instanceRef f1_ram_Mram_ram1))
+                (portRef ENA (instanceRef f1_ram_Mram_ram1))
+                (portRef (member DIBDI 15) (instanceRef f0_ram_Mram_ram33))
+                (portRef ENAWREN (instanceRef f0_ram_Mram_ram33))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram31))
+                (portRef ENA (instanceRef f0_ram_Mram_ram31))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram30))
+                (portRef ENA (instanceRef f0_ram_Mram_ram30))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram32))
+                (portRef ENA (instanceRef f0_ram_Mram_ram32))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram28))
+                (portRef ENA (instanceRef f0_ram_Mram_ram28))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram27))
+                (portRef ENA (instanceRef f0_ram_Mram_ram27))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram29))
+                (portRef ENA (instanceRef f0_ram_Mram_ram29))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram25))
+                (portRef ENA (instanceRef f0_ram_Mram_ram25))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram24))
+                (portRef ENA (instanceRef f0_ram_Mram_ram24))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram26))
+                (portRef ENA (instanceRef f0_ram_Mram_ram26))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram22))
+                (portRef ENA (instanceRef f0_ram_Mram_ram22))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram21))
+                (portRef ENA (instanceRef f0_ram_Mram_ram21))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram23))
+                (portRef ENA (instanceRef f0_ram_Mram_ram23))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram19))
+                (portRef ENA (instanceRef f0_ram_Mram_ram19))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram18))
+                (portRef ENA (instanceRef f0_ram_Mram_ram18))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram20))
+                (portRef ENA (instanceRef f0_ram_Mram_ram20))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram16))
+                (portRef ENA (instanceRef f0_ram_Mram_ram16))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram15))
+                (portRef ENA (instanceRef f0_ram_Mram_ram15))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram17))
+                (portRef ENA (instanceRef f0_ram_Mram_ram17))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram14))
+                (portRef ENA (instanceRef f0_ram_Mram_ram14))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram13))
+                (portRef ENA (instanceRef f0_ram_Mram_ram13))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram12))
+                (portRef ENA (instanceRef f0_ram_Mram_ram12))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram11))
+                (portRef ENA (instanceRef f0_ram_Mram_ram11))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram9))
+                (portRef ENA (instanceRef f0_ram_Mram_ram9))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram8))
+                (portRef ENA (instanceRef f0_ram_Mram_ram8))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram10))
+                (portRef ENA (instanceRef f0_ram_Mram_ram10))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram6))
+                (portRef ENA (instanceRef f0_ram_Mram_ram6))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram5))
+                (portRef ENA (instanceRef f0_ram_Mram_ram5))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram7))
+                (portRef ENA (instanceRef f0_ram_Mram_ram7))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram3))
+                (portRef ENA (instanceRef f0_ram_Mram_ram3))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram2))
+                (portRef ENA (instanceRef f0_ram_Mram_ram2))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram4))
+                (portRef ENA (instanceRef f0_ram_Mram_ram4))
+                (portRef (member DIB 31) (instanceRef f0_ram_Mram_ram1))
+                (portRef (member DIB 30) (instanceRef f0_ram_Mram_ram1))
+                (portRef ENA (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv")
+              (joined
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_0))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_1))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_2))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_3))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_4))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_5))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_6))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_7))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_8))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB_renamed_309))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB_renamed_310))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB_renamed_311))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB_renamed_312))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr4_FRB_renamed_313))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB_renamed_314))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB_renamed_315))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB_renamed_316))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB_renamed_317))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB_renamed_318))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/GND_66_o_read_OR_144_o")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_write "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/write")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_write1))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_2))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_3))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_4))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_5))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_6))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_7))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_8))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_9))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB_renamed_299))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB_renamed_300))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr2_FRB_renamed_301))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr3_FRB_renamed_302))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB_renamed_303))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB_renamed_304))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB_renamed_305))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB_renamed_306))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB_renamed_307))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB_renamed_308))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/full_reg")
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_write1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_renamed_33))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_renamed_103))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set_renamed_426))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_renamed_20))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set_renamed_426))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full")
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_renamed_105))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_renamed_417))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set_renamed_419))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut_renamed_436))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1_renamed_505))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_glue_set_renamed_513))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_renamed_39))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_write1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut_renamed_506))
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+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_4_ "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a<4>")
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+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_4_11))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_3_11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_2_ "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a<2>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_2))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_1__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_2__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_3__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_4__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_5__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_6__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_7__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_8__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_11__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_12__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_13__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_14__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_15__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_20__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_21__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_22__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_23__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_24__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e))
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+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_32__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_33__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e))
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+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_39__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_40__srlc32e))
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+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_43__srlc32e))
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+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_46__srlc32e))
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+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_48__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_51__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_52__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_53__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e))
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+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_4_11))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_3_11))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_2_11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_1_ "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a<1>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_1))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e))
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+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_4_11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_3_11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_1_11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_2_11))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0_ "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a<0>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_1__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_2__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_3__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_4__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_5__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_6__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_7__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_8__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_11__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_12__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_13__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_14__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_15__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_20__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_21__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_22__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_23__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_24__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_28__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_29__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_30__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_31__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_32__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_33__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_38__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_39__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_40__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_41__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_42__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_43__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_44__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_46__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_47__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_48__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_51__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_52__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_53__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e))
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+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_59__srlc32e))
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+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_4_11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_3_11))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_1_11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_2_11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_0_11_INV_0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty")
+              (joined
+                (portRef I0 (instanceRef f1_write11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_renamed_104))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_renamed_417))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set_renamed_419))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0))
+                (portRef I3 (instanceRef f1_read_state_FSM_FFd2_In1))
+                (portRef I0 (instanceRef f1_full_reg_glue_set_renamed_537))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_renamed_39))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_write "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write")
+              (joined
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e))
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+              )
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+              )
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+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<10>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<9>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<9>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<8>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<6>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<4>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<2>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<0>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_write_AND_42_o_inv "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_write_AND_42_o_inv")
+              (joined
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_write_AND_42_o_inv2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_renamed_21))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In11))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr<8>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr8_FRB")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr8_FRB_renamed_327))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__rt_renamed_248))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr<7>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_7))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111_renamed_424))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr7_FRB")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_7))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr7_FRB_renamed_326))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7__rt_renamed_162))
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+              )
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+              )
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+              )
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+              )
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+              )
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+              )
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+              )
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+              )
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+              )
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+              )
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+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1_renamed_492))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1_renamed_494))
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+              )
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+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_write1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv31))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0144_inv1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_write_AND_42_o_inv2))
+                (portRef full (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_empty "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/empty")
+              (joined
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+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_47))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31_renamed_50))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In12_SW0))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14_renamed_48))
+                (portRef empty (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_write "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/write")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_write1))
+                (portRef wr_en (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_i_tready_renamed_22))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tvalid "slave_fifo32/fifo64_to_gpmc32_tx/o64_tvalid")
+              (joined
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+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_renamed_417))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set_renamed_419))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_renamed_39))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_0_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata<0>")
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata110))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_1_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata<1>")
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata121))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_2_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata<2>")
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata231))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_3_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata<3>")
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata341))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_4_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata<4>")
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata451))
+              )
+            )
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+                (portRef (member DIA 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21))
+                (portRef (member dout 65) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
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+                (portRef (member DIA 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21))
+                (portRef (member dout 64) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
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+                (portRef (member DIA 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member dout 63) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
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+              )
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+                (portRef (member dout 61) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+              )
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+                (portRef (member dout 60) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+              )
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+                (portRef (member DIA 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member dout 59) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+              )
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+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_12__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12))
+                (portRef I0
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRBRDADDR 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr<11>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_11__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11))
+                (portRef I4
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRBRDADDR 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr<10>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_10__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10))
+                (portRef I2
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRBRDADDR 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr<9>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9))
+                (portRef I0
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRBRDADDR 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr<8>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8))
+                (portRef I4
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRBRDADDR 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr<7>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7))
+                (portRef I2
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRBRDADDR 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr<6>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6))
+                (portRef I0
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRBRDADDR 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr<5>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5))
+                (portRef I4
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRBRDADDR 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr<4>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4))
+                (portRef I2
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRBRDADDR 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr<3>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3))
+                (portRef I0
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRBRDADDR 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr<2>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2))
+                (portRef I4
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRBRDADDR 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr<1>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1))
+                (portRef I2
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__rt_renamed_179))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRBRDADDR 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr<0>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0))
+                (portRef I0
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt_renamed_178))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRB 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRBRDADDR 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr<12>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_12__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12))
+                (portRef I1
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_4__))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRAWRADDR 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr<11>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_11__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_11))
+                (portRef I5
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3__))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRAWRADDR 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr<10>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_10__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10))
+                (portRef I3
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3__))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRAWRADDR 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr<9>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9))
+                (portRef I1
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3__))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRAWRADDR 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr<8>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8))
+                (portRef I5
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2__))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRAWRADDR 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr<7>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7))
+                (portRef I3
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2__))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRAWRADDR 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr<6>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6))
+                (portRef I1
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2__))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRAWRADDR 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr<5>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5))
+                (portRef I5
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1__))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRAWRADDR 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr<4>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4))
+                (portRef I3
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1__))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRAWRADDR 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr<3>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3))
+                (portRef I1
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1__))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRAWRADDR 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr<2>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2))
+                (portRef I5
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0__))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRA 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRAWRADDR 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr<1>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1))
+                (portRef I3
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0__))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRA 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRAWRADDR 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr<0>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0))
+                (portRef I1
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0__))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member ADDRA 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member ADDRAWRADDR 12) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg")
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut_renamed_436))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1_renamed_479))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1_renamed_505))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut_renamed_506))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg")
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_renamed_108))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set_renamed_432))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5_renamed_483))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1_renamed_505))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write1))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef (member WEAWEL 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+                (portRef (member WEAWEL 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/GND_56_o_read_OR_123_o")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+                (portRef ENBRDEN (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me<12>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_12__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me<11>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_11__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me<10>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_10__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me<9>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me<8>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me<7>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me<6>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me<5>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me<4>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me<3>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_3__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me<2>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_2__))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me<1>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_1__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me<0>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_0__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12__wr_addr_12__equal_11_o "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[12]_wr_addr[12]_equal_11_o")
+              (joined
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy))
+                (portRef I
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv_INV_0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_becoming_full "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/becoming_full")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_4__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0146_inv")
+              (joined
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/clear_inv")
+              (joined
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<0>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0__))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<0>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr1")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<1>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1__))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<1>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr2")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<2>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2__))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<2>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr3")
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+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_10__))
+              )
+            )
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+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr11")
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+              )
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+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_11__))
+              )
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+              )
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr12")
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+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12))
+              )
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+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_12__))
+              )
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2")
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1))
+              )
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+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_1__))
+              )
+            )
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+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_2__))
+              )
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+              )
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+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_3__))
+              )
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+              )
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+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4__))
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+              )
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+              )
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+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5__))
+              )
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+              )
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+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6__))
+              )
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+              )
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+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7__))
+              )
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+              )
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+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8__))
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+              )
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+              )
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+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9__))
+              )
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+              )
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+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10__))
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+              )
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+              )
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+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_11__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<11>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_11__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<11>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_12__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<12>")
+              (joined
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_12__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>")
+              (joined
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef S
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>")
+              (joined
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__))
+                (portRef CI
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>")
+              (joined
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef S
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>")
+              (joined
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__))
+                (portRef CI
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>")
+              (joined
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef S
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>")
+              (joined
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__))
+                (portRef CI
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>")
+              (joined
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef S
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>")
+              (joined
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__))
+                (portRef CI
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>")
+              (joined
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__))
+                (portRef S
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<0>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0__))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<0>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<1>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1__))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<1>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<2>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2__))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<2>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<3>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3__))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<3>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<4>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_4__))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets<7>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_renamed_46))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1_renamed_505))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_renamed_45))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4_renamed_49))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut_renamed_506))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets<6>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_renamed_46))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut_renamed_436))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_renamed_45))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets<5>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_renamed_46))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut_renamed_436))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_renamed_45))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets<4>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_renamed_45))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets<3>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets<2>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets<1>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_renamed_46))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4_renamed_49))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_renamed_109))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set_renamed_432))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14_renamed_48))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o")
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_10__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_11__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_12__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_10__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_11__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_12__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_renamed_45))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_478))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1_renamed_505))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut_renamed_506))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_i_tvalid_int "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/i_tvalid_int")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write1))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set_renamed_432))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4_renamed_482))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut_renamed_506))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_o_tready_int "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/o_tready_int")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4_renamed_504))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot_renamed_433))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<7>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<6>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<5>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<4>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<3>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<2>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<1>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_renamed_46))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set_renamed_432))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv")
+              (joined
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets<0>")
+              (joined
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot_renamed_433))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<3>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT41 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41")
+              (joined
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_renamed_46))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut_renamed_436))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_renamed_45))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT53 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT53")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<4>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<5>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1_renamed_505))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut_renamed_506))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4_renamed_49))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT51 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror_bdd0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror_bdd0")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror_bdd6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror_bdd6")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12_renamed_52))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In_bdd1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In_bdd1")
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<2>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_2__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines322 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines322")
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+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<1>")
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+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<1>")
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines321 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines321")
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_1__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1))
+              )
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<0>")
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+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<0>")
+              (joined
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+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_0__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32")
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_0__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0))
+              )
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv")
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+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_8))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_9))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/state<0>_inv")
+              (joined
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_0__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv1_INV_0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In")
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In")
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+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror")
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+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set_renamed_432))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_tlast")
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+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set_renamed_432))
+                (portRef (member DIADI 15) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<0>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<1>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<2>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31_renamed_50))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<3>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_3))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<4>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_4))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32_renamed_51))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<5>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_5))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32_renamed_51))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_5__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<6>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_6))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32_renamed_51))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_6__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<7>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_7))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32_renamed_51))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_7__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<8>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_8))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_8__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<9>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_9))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_9__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<10>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31_renamed_50))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<11>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31_renamed_50))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<12>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31_renamed_50))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<13>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<14>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32_renamed_51))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32<15>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32_renamed_51))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_renamed_24))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_0__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_1__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_2__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_3__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_4__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_5__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_6__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_7__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_8__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_9__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15__))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv1_INV_0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_renamed_23))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_47))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14_renamed_48))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full")
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_renamed_111))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_renamed_418))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set_renamed_420))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set_renamed_514))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_renamed_53))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a<4>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef (member A 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a<3>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef (member A 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a<2>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef (member A 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a<1>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef (member A 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a<0>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef (member A 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_0_11_INV_0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty")
+              (joined
+                (portRef I0 (instanceRef f0_write11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_renamed_110))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_renamed_418))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set_renamed_420))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0))
+                (portRef D (instanceRef slave_fifo32_debug1_17_BRB0_renamed_496))
+                (portRef I3 (instanceRef f0_read_state_FSM_FFd2_In1))
+                (portRef I0 (instanceRef f0_full_reg_glue_set_renamed_538))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_renamed_53))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write")
+              (joined
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e))
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+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e))
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+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e))
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+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e))
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+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
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+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
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+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e))
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+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv")
+              (joined
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_renamed_53))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a1")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_0_11_INV_0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a2 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a2")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a3 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a3")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a4 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a4")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a5 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a5")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>11")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_renamed_53))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o5")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213_renamed_430))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o")
+              (joined
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full92 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full92")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full921))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o7")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121211 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121211")
+              (joined
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217_renamed_428))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv3")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214_renamed_55))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01211 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01211")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219))
+              )
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012111")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217_renamed_428))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421_FRB")
+              (joined
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213_renamed_430))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB_renamed_457))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full411_FRB")
+              (joined
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213_renamed_430))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB_renamed_458))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full621_FRB")
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213_renamed_430))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB_renamed_462))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112_renamed_501))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_dont_write_past_me_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/dont_write_past_me<8>")
+              (joined
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+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214_renamed_55))
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o8")
+              (joined
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<15>")
+              (joined
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<14>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<13>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<13>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<12>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<12>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<11>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<11>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<10>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<10>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<9>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<9>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<8>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<6>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<4>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<2>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<0>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_write_AND_42_o_inv")
+              (joined
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_renamed_25))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr<8>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr8_FRB")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB_renamed_336))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt_renamed_250))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr<7>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111_renamed_425))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr7_FRB")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr7_FRB_renamed_335))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__rt_renamed_180))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr<6>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213_renamed_430))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112_renamed_501))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr6_FRB")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB_renamed_334))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt_renamed_181))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_6__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr<5>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111_renamed_425))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112_renamed_501))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr5_FRB")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr5_FRB_renamed_333))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__rt_renamed_182))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_5__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr<4>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112_renamed_501))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr4_FRB")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr4_FRB_renamed_332))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt_renamed_183))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr<3>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113_renamed_57))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111_renamed_425))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr3_FRB")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB_renamed_331))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt_renamed_184))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr<2>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217_renamed_428))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215_renamed_518))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218_renamed_520))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr2_FRB")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr2_FRB_renamed_330))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt_renamed_185))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr<1>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full921))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217_renamed_428))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215_renamed_518))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218_renamed_520))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr1_FRB")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB_renamed_329))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt_renamed_186))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr<0>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216_renamed_56))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215_renamed_518))
+                (portRef (member ADDRB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_FRB")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB_renamed_328))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt_renamed_187))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0144_inv")
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+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0))
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+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6))
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+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB_renamed_328))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB_renamed_329))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr2_FRB_renamed_330))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB_renamed_331))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr4_FRB_renamed_332))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr5_FRB_renamed_333))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB_renamed_334))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr7_FRB_renamed_335))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB_renamed_336))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB_renamed_457))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB_renamed_458))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB_renamed_460))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB_renamed_462))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr<8>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214_renamed_55))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr8_FRB")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB_renamed_454))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__rt_renamed_251))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr<7>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111_renamed_425))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr7_FRB")
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+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB_renamed_453))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt_renamed_188))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<6>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr<6>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_6))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213_renamed_430))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr6_FRB")
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+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_6))
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+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__rt_renamed_189))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_6__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr<5>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111))
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+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
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+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5))
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+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt_renamed_190))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr<4>")
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+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr4_FRB")
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+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt_renamed_191))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__))
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+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr<3>")
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+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113_renamed_57))
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+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
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+              )
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+              )
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+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_8))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT<7>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_7))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT<6>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT<5>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT<4>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT<3>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT<2>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT<1>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT<0>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/GND_50_o_read_OR_57_o")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<15>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1_renamed_473))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<14>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1_renamed_472))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<13>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1_renamed_471))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<12>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1_renamed_470))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<11>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1_renamed_491))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<10>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1_renamed_493))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<9>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1_renamed_495))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<8>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<7>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<6>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<5>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<4>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<3>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<2>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<1>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<0>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set_renamed_435))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv")
+              (joined
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_7))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_8))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0_renamed_469))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1_renamed_470))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1_renamed_471))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1_renamed_472))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1_renamed_473))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1_renamed_491))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1_renamed_493))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1_renamed_495))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_full "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/full")
+              (joined
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set_renamed_435))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13__))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2))
+                (portRef full (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_empty "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/empty")
+              (joined
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+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1__))
+                (portRef (member DIA 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1))
+                (portRef (member dout 70) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<2>")
+              (joined
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2__))
+                (portRef (member DIA 29) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member dout 69) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<3>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3__))
+                (portRef (member DIA 28) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member dout 68) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<4>")
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4__))
+                (portRef (member DIA 27) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member dout 67) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<5>")
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5__))
+                (portRef (member DIA 26) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F))
+                (portRef (member dout 66) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<6>")
+              (joined
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6__))
+                (portRef (member DIA 25) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F))
+                (portRef (member dout 65) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<7>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7__))
+                (portRef (member DIA 24) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F))
+                (portRef (member dout 64) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<8>")
+              (joined
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8__))
+                (portRef (member DIA 23) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61))
+                (portRef (member dout 63) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<9>")
+              (joined
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9__))
+                (portRef (member DIA 22) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1))
+                (portRef (member dout 62) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<10>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12_renamed_68))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10__))
+                (portRef (member DIA 21) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16))
+                (portRef (member dout 61) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<11>")
+              (joined
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11__))
+                (portRef (member DIA 20) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F))
+                (portRef (member dout 60) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<12>")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12__))
+                (portRef (member DIA 19) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F))
+                (portRef (member dout 59) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<13>")
+              (joined
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13__))
+                (portRef (member DIA 18) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31))
+                (portRef (member dout 58) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<14>")
+              (joined
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14__))
+                (portRef (member DIA 17) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F))
+                (portRef (member dout 57) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<15>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15__))
+                (portRef (member DIA 16) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F))
+                (portRef (member dout 56) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_16_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<16>")
+              (joined
+                (portRef (member DIPA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member dout 55) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_17_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<17>")
+              (joined
+                (portRef (member DIPA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member dout 54) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_18_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<18>")
+              (joined
+                (portRef (member DIA 31) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 53) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_19_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<19>")
+              (joined
+                (portRef (member DIA 30) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 52) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_20_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<20>")
+              (joined
+                (portRef (member DIA 29) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 51) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_21_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<21>")
+              (joined
+                (portRef (member DIA 28) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 50) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_22_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<22>")
+              (joined
+                (portRef (member DIA 27) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 49) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_23_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<23>")
+              (joined
+                (portRef (member DIA 26) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 48) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_24_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<24>")
+              (joined
+                (portRef (member DIA 25) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 47) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_25_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<25>")
+              (joined
+                (portRef (member DIA 24) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 46) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_26_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<26>")
+              (joined
+                (portRef (member DIA 23) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 45) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_27_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<27>")
+              (joined
+                (portRef (member DIA 22) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 44) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_28_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<28>")
+              (joined
+                (portRef (member DIA 21) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 43) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<29>")
+              (joined
+                (portRef (member DIA 20) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 42) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_30_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<30>")
+              (joined
+                (portRef (member DIA 19) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 41) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_31_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008<31>")
+              (joined
+                (portRef (member DIA 18) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member dout 40) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space<0>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space<1>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space<2>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space<3>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space<4>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space<5>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space<6>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space<7>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_7))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space<8>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_8))
+                (portRef DI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__))
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+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space<9>")
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space<10>")
+              (joined
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space<11>")
+              (joined
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space<12>")
+              (joined
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space<13>")
+              (joined
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space<14>")
+              (joined
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<0>")
+              (joined
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+                (portRef (member din 71) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<1>")
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+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<2>")
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+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<3>")
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+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<4>")
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+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<5>")
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+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<6>")
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+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<7>")
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+                (portRef (member din 64) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<8>")
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+                (portRef (member din 63) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<9>")
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+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<10>")
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+                (portRef (member din 61) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<11>")
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+                (portRef (member din 60) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<12>")
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+                (portRef (member din 59) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<13>")
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+              )
+            )
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+              )
+            )
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+              )
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+              )
+            )
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+              )
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+              )
+            )
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+                (portRef (member din 52) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
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+              (joined
+                (portRef (member DOB 11) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member din 51) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___21_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<21>")
+              (joined
+                (portRef (member DOB 10) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member din 50) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___22_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<22>")
+              (joined
+                (portRef (member DOB 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member din 49) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___23_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<23>")
+              (joined
+                (portRef (member DOB 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member din 48) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___24_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<24>")
+              (joined
+                (portRef (member DOB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member din 47) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___25_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<25>")
+              (joined
+                (portRef (member DOB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member din 46) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___26_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<26>")
+              (joined
+                (portRef (member DOB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member din 45) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___27_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<27>")
+              (joined
+                (portRef (member DOB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member din 44) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___28_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<28>")
+              (joined
+                (portRef (member DOB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member din 43) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<29>")
+              (joined
+                (portRef (member DOB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member din 42) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___30_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<30>")
+              (joined
+                (portRef (member DOB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member din 41) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___31_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<31>")
+              (joined
+                (portRef (member DOB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member din 40) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0___32_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0]<32>")
+              (joined
+                (portRef (member DOPB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+                (portRef (member din 39) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr<9>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr<8>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217_renamed_524))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr<7>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217_renamed_524))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr<6>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219_renamed_59))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217_renamed_524))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr<5>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr<4>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_renamed_431))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr<3>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_renamed_431))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr<2>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_renamed_431))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRB 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr<9>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr<8>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217_renamed_524))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr<7>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr<6>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr<5>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 4) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr<4>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_renamed_431))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 5) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr<3>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 6) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr<2>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 7) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr<1>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full1021))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 8) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr<0>")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0__))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member ADDRA 9) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg")
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_renamed_258))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1_renamed_485))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot_renamed_511))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2_renamed_415))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set_renamed_421))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/full_reg")
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5_renamed_64))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_renamed_114))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv1_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set_renamed_421))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set_renamed_422))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_renamed_431))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5_renamed_489))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0154_inv1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/write")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write1))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef (member WEA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEA 2) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEA 1) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef (member WEA 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/GND_66_o_read_OR_144_o")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+                (portRef ENB (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0146_inv")
+              (joined
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB_renamed_463))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/clear_inv")
+              (joined
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<0>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0__))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<0>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr1")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0))
+              )
+            )
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<8>")
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+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1__))
+              )
+            )
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+              )
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr2")
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+              )
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<2>")
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+              )
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr3")
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+              )
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<3>")
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+              )
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<4>")
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr5")
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<5>")
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<6>")
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<7>")
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<7>")
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr8")
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<8>")
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<8>")
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr9")
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<9>")
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+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_dont_write_past_me_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/dont_write_past_me<9>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full61")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219_renamed_59))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217_renamed_524))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full62 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full62")
+              (joined
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219_renamed_59))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217_renamed_524))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012121 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n012121")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_renamed_423))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121221 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0121221")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_renamed_423))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o9")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o8")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219_renamed_59))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o7")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219_renamed_59))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full102 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full102")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full1021))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o")
+              (joined
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot_renamed_511))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets<7>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_renamed_61))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_renamed_60))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets<6>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6))
+                (portRef I0
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_6_1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_renamed_61))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_renamed_60))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets<5>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_renamed_60))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_renamed_61))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11))
+                (portRef I0
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63))
+                (portRef I3
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets<4>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_renamed_60))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11))
+                (portRef I1
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets<3>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3))
+                (portRef I0
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+                (portRef I2
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets<2>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2))
+                (portRef I0
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63))
+                (portRef I0
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets<1>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump")
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_renamed_61))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_renamed_115))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv1_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set_renamed_422))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_62))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o")
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_renamed_60))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_484))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot_renamed_511))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0__))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1__))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0154_inv1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set_renamed_421))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_i_tvalid_int "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/i_tvalid_int")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write1))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set_renamed_422))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4_renamed_488))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0154_inv1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set_renamed_421))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_o_tready_int "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/o_tready_int")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set_renamed_421))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot_renamed_511))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2_renamed_415))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<7>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<6>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<5>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<4>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<3>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<2>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<1>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<0>")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_renamed_61))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set_renamed_422))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv")
+              (joined
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6))
+                (portRef CE (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets<0>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311")
+              (joined
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+                (portRef I5
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>")
+              (joined
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<3>")
+              (joined
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT41 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_renamed_61))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_renamed_60))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT53 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT53")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<5>")
+              (joined
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<6>")
+              (joined
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_6_1))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT51 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror_bdd6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror_bdd6")
+              (joined
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12_renamed_68))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid_bdd2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid_bdd2")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12_renamed_68))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid_bdd8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid_bdd8")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12_renamed_68))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In_bdd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In_bdd1")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<15>")
+              (joined
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3215 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3215")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<14>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_14__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<14>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_14__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_14__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3214 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3214")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_14__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<13>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_14__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_14__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<13>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3213 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3213")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<12>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<12>")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12__))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3212 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3212")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12__))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<11>")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_11__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<11>")
+              (joined
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3211")
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<8>")
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_renamed_27))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_renamed_28))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror")
+              (joined
+                (portRef I1
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1))
+                (portRef I1
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1))
+                (portRef I1
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_6_1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5_renamed_64))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set_renamed_422))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2_renamed_415))
+                (portRef I4
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tlast")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5_renamed_64))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set_renamed_422))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+                (portRef (member DIA 17) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2_renamed_415))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<0>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<1>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<2>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<3>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<4>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<5>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<6>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<7>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<8>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<9>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<10>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<11>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<12>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<13>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<14>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<15>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_renamed_28))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11_renamed_67))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15__))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_0__inv1_INV_0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_62))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_renamed_27))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_62))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11_renamed_67))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F))
+              )
+            )
+            (net (rename f1_Mcompar_becoming_full_lut_4_ "f1/Mcompar_becoming_full_lut<4>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_becoming_full_lut_4__))
+                (portRef S (instanceRef f1_Mcompar_becoming_full_cy_4__))
+              )
+            )
+            (net (rename f1_Mcompar_becoming_full_cy_3_ "f1/Mcompar_becoming_full_cy<3>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_becoming_full_cy_3__))
+                (portRef CI (instanceRef f1_Mcompar_becoming_full_cy_4__))
+              )
+            )
+            (net (rename f1_Mcompar_becoming_full_lut_3_ "f1/Mcompar_becoming_full_lut<3>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_becoming_full_lut_3__))
+                (portRef S (instanceRef f1_Mcompar_becoming_full_cy_3__))
+              )
+            )
+            (net (rename f1_Mcompar_becoming_full_cy_2_ "f1/Mcompar_becoming_full_cy<2>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_becoming_full_cy_2__))
+                (portRef CI (instanceRef f1_Mcompar_becoming_full_cy_3__))
+              )
+            )
+            (net (rename f1_Mcompar_becoming_full_lut_2_ "f1/Mcompar_becoming_full_lut<2>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_becoming_full_lut_2__))
+                (portRef S (instanceRef f1_Mcompar_becoming_full_cy_2__))
+              )
+            )
+            (net (rename f1_Mcompar_becoming_full_cy_1_ "f1/Mcompar_becoming_full_cy<1>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_becoming_full_cy_1__))
+                (portRef CI (instanceRef f1_Mcompar_becoming_full_cy_2__))
+              )
+            )
+            (net (rename f1_Mcompar_becoming_full_lut_1_ "f1/Mcompar_becoming_full_lut<1>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_becoming_full_lut_1__))
+                (portRef S (instanceRef f1_Mcompar_becoming_full_cy_1__))
+              )
+            )
+            (net (rename f1_Mcompar_becoming_full_cy_0_ "f1/Mcompar_becoming_full_cy<0>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_becoming_full_cy_0__))
+                (portRef CI (instanceRef f1_Mcompar_becoming_full_cy_1__))
+              )
+            )
+            (net (rename f1_Mcompar_becoming_full_lut_0_ "f1/Mcompar_becoming_full_lut<0>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_becoming_full_lut_0__))
+                (portRef S (instanceRef f1_Mcompar_becoming_full_cy_0__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_cy_10_ "f1/Mcount_rd_addr_cy<10>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_10__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_cy_11__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_xor_11__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_cy_9_ "f1/Mcount_rd_addr_cy<9>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_9__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_cy_10__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_xor_10__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_cy_8_ "f1/Mcount_rd_addr_cy<8>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_8__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_cy_9__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_xor_9__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_cy_7_ "f1/Mcount_rd_addr_cy<7>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_7__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_cy_8__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_xor_8__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_cy_6_ "f1/Mcount_rd_addr_cy<6>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_6__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_cy_7__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_xor_7__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_cy_5_ "f1/Mcount_rd_addr_cy<5>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_5__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_cy_6__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_xor_6__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_cy_4_ "f1/Mcount_rd_addr_cy<4>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_4__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_cy_5__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_xor_5__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_cy_3_ "f1/Mcount_rd_addr_cy<3>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_3__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_cy_4__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_xor_4__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_cy_2_ "f1/Mcount_rd_addr_cy<2>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_2__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_cy_3__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_xor_3__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_cy_1_ "f1/Mcount_rd_addr_cy<1>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_1__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_cy_2__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_xor_2__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_cy_0_ "f1/Mcount_rd_addr_cy<0>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_0__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_cy_1__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_xor_1__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_lut_0_ "f1/Mcount_rd_addr_lut<0>")
+              (joined
+                (portRef S (instanceRef f1_Mcount_rd_addr_cy_0__))
+                (portRef LI (instanceRef f1_Mcount_rd_addr_xor_0__))
+                (portRef O (instanceRef f1_Mcount_rd_addr_lut_0__INV_0))
+              )
+            )
+            (net (rename f1_Mcount_wr_addr_cy_10_ "f1/Mcount_wr_addr_cy<10>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_wr_addr_cy_10__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_cy_11__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_xor_11__))
+              )
+            )
+            (net (rename f1_Mcount_wr_addr_cy_9_ "f1/Mcount_wr_addr_cy<9>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_wr_addr_cy_9__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_cy_10__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_xor_10__))
+              )
+            )
+            (net (rename f1_Mcount_wr_addr_cy_8_ "f1/Mcount_wr_addr_cy<8>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_wr_addr_cy_8__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_cy_9__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_xor_9__))
+              )
+            )
+            (net (rename f1_Mcount_wr_addr_cy_7_ "f1/Mcount_wr_addr_cy<7>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_wr_addr_cy_7__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_cy_8__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_xor_8__))
+              )
+            )
+            (net (rename f1_Mcount_wr_addr_cy_6_ "f1/Mcount_wr_addr_cy<6>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_wr_addr_cy_6__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_cy_7__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_xor_7__))
+              )
+            )
+            (net (rename f1_Mcount_wr_addr_cy_5_ "f1/Mcount_wr_addr_cy<5>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_wr_addr_cy_5__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_cy_6__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_xor_6__))
+              )
+            )
+            (net (rename f1_Mcount_wr_addr_cy_4_ "f1/Mcount_wr_addr_cy<4>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_wr_addr_cy_4__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_cy_5__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_xor_5__))
+              )
+            )
+            (net (rename f1_Mcount_wr_addr_cy_3_ "f1/Mcount_wr_addr_cy<3>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_wr_addr_cy_3__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_cy_4__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_xor_4__))
+              )
+            )
+            (net (rename f1_Mcount_wr_addr_cy_2_ "f1/Mcount_wr_addr_cy<2>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_wr_addr_cy_2__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_cy_3__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_xor_3__))
+              )
+            )
+            (net (rename f1_Mcount_wr_addr_cy_1_ "f1/Mcount_wr_addr_cy<1>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_wr_addr_cy_1__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_cy_2__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_xor_2__))
+              )
+            )
+            (net (rename f1_Mcount_wr_addr_cy_0_ "f1/Mcount_wr_addr_cy<0>")
+              (joined
+                (portRef O (instanceRef f1_Mcount_wr_addr_cy_0__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_cy_1__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_xor_1__))
+              )
+            )
+            (net (rename f1_Mcount_wr_addr_lut_0_ "f1/Mcount_wr_addr_lut<0>")
+              (joined
+                (portRef S (instanceRef f1_Mcount_wr_addr_cy_0__))
+                (portRef LI (instanceRef f1_Mcount_wr_addr_xor_0__))
+                (portRef O (instanceRef f1_Mcount_wr_addr_lut_0__INV_0))
+              )
+            )
+            (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__))
+                (portRef S (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__))
+              )
+            )
+            (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__))
+                (portRef CI (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__))
+              )
+            )
+            (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef S (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__))
+              )
+            )
+            (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__))
+                (portRef CI (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__))
+              )
+            )
+            (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef S (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__))
+              )
+            )
+            (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__))
+                (portRef CI (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__))
+              )
+            )
+            (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef S (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__))
+              )
+            )
+            (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__))
+                (portRef CI (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__))
+              )
+            )
+            (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef S (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_lut_12_ "f1/Msub_dont_write_past_me_lut<12>")
+              (joined
+                (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_12__))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_12__INV_0))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_lut_11_ "f1/Msub_dont_write_past_me_lut<11>")
+              (joined
+                (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_11__))
+                (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_11__))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_11__INV_0))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_cy_10_ "f1/Msub_dont_write_past_me_cy<10>")
+              (joined
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_10__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_11__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_11__))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_lut_10_ "f1/Msub_dont_write_past_me_lut<10>")
+              (joined
+                (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_10__))
+                (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_10__))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_10__INV_0))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_cy_9_ "f1/Msub_dont_write_past_me_cy<9>")
+              (joined
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_9__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_10__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_10__))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_lut_9_ "f1/Msub_dont_write_past_me_lut<9>")
+              (joined
+                (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_9__))
+                (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_9__))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_9__INV_0))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_cy_8_ "f1/Msub_dont_write_past_me_cy<8>")
+              (joined
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_8__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_9__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_9__))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_lut_8_ "f1/Msub_dont_write_past_me_lut<8>")
+              (joined
+                (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_8__))
+                (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_8__))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_8__INV_0))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_cy_7_ "f1/Msub_dont_write_past_me_cy<7>")
+              (joined
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_7__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_8__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_8__))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_lut_7_ "f1/Msub_dont_write_past_me_lut<7>")
+              (joined
+                (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_7__))
+                (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_7__))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_7__INV_0))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_cy_6_ "f1/Msub_dont_write_past_me_cy<6>")
+              (joined
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_6__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_7__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_7__))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_lut_6_ "f1/Msub_dont_write_past_me_lut<6>")
+              (joined
+                (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_6__))
+                (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_6__))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_6__INV_0))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_cy_5_ "f1/Msub_dont_write_past_me_cy<5>")
+              (joined
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_5__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_6__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_6__))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_lut_5_ "f1/Msub_dont_write_past_me_lut<5>")
+              (joined
+                (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_5__))
+                (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_5__))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_5__INV_0))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_cy_4_ "f1/Msub_dont_write_past_me_cy<4>")
+              (joined
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_4__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_5__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_5__))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_lut_4_ "f1/Msub_dont_write_past_me_lut<4>")
+              (joined
+                (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_4__))
+                (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_4__))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_4__INV_0))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_cy_3_ "f1/Msub_dont_write_past_me_cy<3>")
+              (joined
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_3__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_4__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_4__))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_lut_3_ "f1/Msub_dont_write_past_me_lut<3>")
+              (joined
+                (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_3__))
+                (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_3__))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_3__INV_0))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_cy_2_ "f1/Msub_dont_write_past_me_cy<2>")
+              (joined
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_2__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_3__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_3__))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_lut_2_ "f1/Msub_dont_write_past_me_lut<2>")
+              (joined
+                (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_2__))
+                (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_2__))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_2__INV_0))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_cy_1_ "f1/Msub_dont_write_past_me_cy<1>")
+              (joined
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_1__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_2__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_2__))
+              )
+            )
+            (net (rename f1_Msub_dont_write_past_me_cy_0_ "f1/Msub_dont_write_past_me_cy<0>")
+              (joined
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_0__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_1__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_1__))
+              )
+            )
+            (net (rename f1_read_state_FSM_FFd2 "f1/read_state_FSM_FFd2")
+              (joined
+                (portRef Q (instanceRef f1_read_state_FSM_FFd2_renamed_30))
+                (portRef I0 (instanceRef f1__n0161_inv1_lut1_renamed_508))
+                (portRef I2 (instanceRef f1_GND_14_o_read_OR_37_o1))
+                (portRef I3 (instanceRef f1_read_state_FSM_FFd1_In111))
+                (portRef I5 (instanceRef f1_read_state_FSM_FFd2_In1))
+              )
+            )
+            (net (rename f1_read_state_FSM_FFd2_In "f1/read_state_FSM_FFd2-In")
+              (joined
+                (portRef D (instanceRef f1_read_state_FSM_FFd2_renamed_30))
+                (portRef O (instanceRef f1_read_state_FSM_FFd2_In1))
+              )
+            )
+            (net (rename f1_read_state_FSM_FFd1_In1 "f1/read_state_FSM_FFd1-In1")
+              (joined
+                (portRef D (instanceRef f1_read_state_FSM_FFd1_renamed_29))
+                (portRef O (instanceRef f1_read_state_FSM_FFd1_In111))
+              )
+            )
+            (net (rename f1_Result_12_2_FRB "f1/Result<12>2_FRB")
+              (joined
+                (portRef D (instanceRef f1_wr_addr_12))
+                (portRef Q (instanceRef f1_Result_12_2_FRB_renamed_349))
+                (portRef I0 (instanceRef f1_Mcount_wr_addr_xor_12__rt_renamed_253))
+              )
+            )
+            (net (rename f1_Result_11_2_FRB "f1/Result<11>2_FRB")
+              (joined
+                (portRef D (instanceRef f1_wr_addr_11))
+                (portRef Q (instanceRef f1_Result_11_2_FRB_renamed_348))
+                (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_11__rt_renamed_207))
+              )
+            )
+            (net (rename f1_Result_10_2_FRB "f1/Result<10>2_FRB")
+              (joined
+                (portRef D (instanceRef f1_wr_addr_10))
+                (portRef Q (instanceRef f1_Result_10_2_FRB_renamed_347))
+                (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_10__rt_renamed_208))
+              )
+            )
+            (net (rename f1_Result_9_2_FRB "f1/Result<9>2_FRB")
+              (joined
+                (portRef D (instanceRef f1_wr_addr_9))
+                (portRef Q (instanceRef f1_Result_9_2_FRB_renamed_346))
+                (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_9__rt_renamed_209))
+              )
+            )
+            (net (rename f1_Result_8_2_FRB "f1/Result<8>2_FRB")
+              (joined
+                (portRef D (instanceRef f1_wr_addr_8))
+                (portRef Q (instanceRef f1_Result_8_2_FRB_renamed_345))
+                (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_8__rt_renamed_210))
+              )
+            )
+            (net (rename f1_Result_7_2_FRB "f1/Result<7>2_FRB")
+              (joined
+                (portRef D (instanceRef f1_wr_addr_7))
+                (portRef Q (instanceRef f1_Result_7_2_FRB_renamed_344))
+                (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_7__rt_renamed_211))
+              )
+            )
+            (net (rename f1_Result_6_2_FRB "f1/Result<6>2_FRB")
+              (joined
+                (portRef D (instanceRef f1_wr_addr_6))
+                (portRef Q (instanceRef f1_Result_6_2_FRB_renamed_343))
+                (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_6__rt_renamed_212))
+              )
+            )
+            (net (rename f1_Result_5_2_FRB "f1/Result<5>2_FRB")
+              (joined
+                (portRef D (instanceRef f1_wr_addr_5))
+                (portRef Q (instanceRef f1_Result_5_2_FRB_renamed_342))
+                (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_5__rt_renamed_213))
+              )
+            )
+            (net (rename f1_Result_4_2_FRB "f1/Result<4>2_FRB")
+              (joined
+                (portRef D (instanceRef f1_wr_addr_4))
+                (portRef Q (instanceRef f1_Result_4_2_FRB_renamed_341))
+                (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_4__rt_renamed_214))
+              )
+            )
+            (net (rename f1_Result_3_2_FRB "f1/Result<3>2_FRB")
+              (joined
+                (portRef D (instanceRef f1_wr_addr_3))
+                (portRef Q (instanceRef f1_Result_3_2_FRB_renamed_340))
+                (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_3__rt_renamed_215))
+              )
+            )
+            (net (rename f1_Result_2_2_FRB "f1/Result<2>2_FRB")
+              (joined
+                (portRef D (instanceRef f1_wr_addr_2))
+                (portRef Q (instanceRef f1_Result_2_2_FRB_renamed_339))
+                (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_2__rt_renamed_216))
+              )
+            )
+            (net (rename f1_Result_1_2_FRB "f1/Result<1>2_FRB")
+              (joined
+                (portRef D (instanceRef f1_wr_addr_1))
+                (portRef Q (instanceRef f1_Result_1_2_FRB_renamed_338))
+                (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_1__rt_renamed_217))
+              )
+            )
+            (net (rename f1_Result_0_2_FRB "f1/Result<0>2_FRB")
+              (joined
+                (portRef D (instanceRef f1_wr_addr_0))
+                (portRef Q (instanceRef f1_Result_0_2_FRB_renamed_337))
+                (portRef I (instanceRef f1_Mcount_wr_addr_lut_0__INV_0))
+              )
+            )
+            (net (rename f1_Result_12_1_FRB "f1/Result<12>1_FRB")
+              (joined
+                (portRef D (instanceRef f1_rd_addr_12))
+                (portRef Q (instanceRef f1_Result_12_1_FRB_renamed_362))
+                (portRef I0 (instanceRef f1_Mcount_rd_addr_xor_12__rt_renamed_252))
+                (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_12__INV_0))
+              )
+            )
+            (net (rename f1_Result_11_1_FRB "f1/Result<11>1_FRB")
+              (joined
+                (portRef D (instanceRef f1_rd_addr_11))
+                (portRef Q (instanceRef f1_Result_11_1_FRB_renamed_361))
+                (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_11__rt_renamed_196))
+                (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_11__INV_0))
+              )
+            )
+            (net (rename f1_Result_10_1_FRB "f1/Result<10>1_FRB")
+              (joined
+                (portRef D (instanceRef f1_rd_addr_10))
+                (portRef Q (instanceRef f1_Result_10_1_FRB_renamed_360))
+                (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_10__rt_renamed_197))
+                (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_10__INV_0))
+              )
+            )
+            (net (rename f1_Result_9_1_FRB "f1/Result<9>1_FRB")
+              (joined
+                (portRef D (instanceRef f1_rd_addr_9))
+                (portRef Q (instanceRef f1_Result_9_1_FRB_renamed_359))
+                (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_9__rt_renamed_198))
+                (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_9__INV_0))
+              )
+            )
+            (net (rename f1_Result_8_1_FRB "f1/Result<8>1_FRB")
+              (joined
+                (portRef D (instanceRef f1_rd_addr_8))
+                (portRef Q (instanceRef f1_Result_8_1_FRB_renamed_358))
+                (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_8__rt_renamed_199))
+                (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_8__INV_0))
+              )
+            )
+            (net (rename f1_Result_7_1_FRB "f1/Result<7>1_FRB")
+              (joined
+                (portRef D (instanceRef f1_rd_addr_7))
+                (portRef Q (instanceRef f1_Result_7_1_FRB_renamed_357))
+                (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_7__rt_renamed_200))
+                (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_7__INV_0))
+              )
+            )
+            (net (rename f1_Result_6_1_FRB "f1/Result<6>1_FRB")
+              (joined
+                (portRef D (instanceRef f1_rd_addr_6))
+                (portRef Q (instanceRef f1_Result_6_1_FRB_renamed_356))
+                (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_6__rt_renamed_201))
+                (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_6__INV_0))
+              )
+            )
+            (net (rename f1_Result_5_1_FRB "f1/Result<5>1_FRB")
+              (joined
+                (portRef D (instanceRef f1_rd_addr_5))
+                (portRef Q (instanceRef f1_Result_5_1_FRB_renamed_355))
+                (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_5__rt_renamed_202))
+                (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_5__INV_0))
+              )
+            )
+            (net (rename f1_Result_4_1_FRB "f1/Result<4>1_FRB")
+              (joined
+                (portRef D (instanceRef f1_rd_addr_4))
+                (portRef Q (instanceRef f1_Result_4_1_FRB_renamed_354))
+                (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_4__rt_renamed_203))
+                (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_4__INV_0))
+              )
+            )
+            (net (rename f1_Result_3_1_FRB "f1/Result<3>1_FRB")
+              (joined
+                (portRef D (instanceRef f1_rd_addr_3))
+                (portRef Q (instanceRef f1_Result_3_1_FRB_renamed_353))
+                (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_3__rt_renamed_204))
+                (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_3__INV_0))
+              )
+            )
+            (net (rename f1_Result_2_1_FRB "f1/Result<2>1_FRB")
+              (joined
+                (portRef D (instanceRef f1_rd_addr_2))
+                (portRef Q (instanceRef f1_Result_2_1_FRB_renamed_352))
+                (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_2__rt_renamed_205))
+                (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_2__INV_0))
+              )
+            )
+            (net (rename f1_Result_1_1_FRB "f1/Result<1>1_FRB")
+              (joined
+                (portRef D (instanceRef f1_rd_addr_1))
+                (portRef Q (instanceRef f1_Result_1_1_FRB_renamed_351))
+                (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_1__rt_renamed_206))
+                (portRef I0 (instanceRef f1_Msub_dont_write_past_me_cy_1__rt_renamed_218))
+              )
+            )
+            (net (rename f1_Result_0_1_FRB "f1/Result<0>1_FRB")
+              (joined
+                (portRef D (instanceRef f1_rd_addr_0))
+                (portRef Q (instanceRef f1_Result_0_1_FRB_renamed_350))
+                (portRef I0 (instanceRef f1_Msub_dont_write_past_me_cy_0__rt_renamed_219))
+                (portRef I (instanceRef f1_Mcount_rd_addr_lut_0__INV_0))
+              )
+            )
+            (net (rename f1__n0161_inv "f1/_n0161_inv")
+              (joined
+                (portRef CE (instanceRef f1_rd_addr_1))
+                (portRef CE (instanceRef f1_rd_addr_2))
+                (portRef CE (instanceRef f1_rd_addr_3))
+                (portRef CE (instanceRef f1_rd_addr_4))
+                (portRef CE (instanceRef f1_rd_addr_5))
+                (portRef CE (instanceRef f1_rd_addr_6))
+                (portRef CE (instanceRef f1_rd_addr_7))
+                (portRef CE (instanceRef f1_rd_addr_8))
+                (portRef CE (instanceRef f1_rd_addr_9))
+                (portRef CE (instanceRef f1_rd_addr_10))
+                (portRef CE (instanceRef f1_rd_addr_11))
+                (portRef CE (instanceRef f1_rd_addr_12))
+                (portRef CE (instanceRef f1_rd_addr_0))
+                (portRef CE (instanceRef f1_Result_0_1_FRB_renamed_350))
+                (portRef CE (instanceRef f1_Result_1_1_FRB_renamed_351))
+                (portRef CE (instanceRef f1_Result_2_1_FRB_renamed_352))
+                (portRef CE (instanceRef f1_Result_3_1_FRB_renamed_353))
+                (portRef CE (instanceRef f1_Result_4_1_FRB_renamed_354))
+                (portRef CE (instanceRef f1_Result_5_1_FRB_renamed_355))
+                (portRef CE (instanceRef f1_Result_6_1_FRB_renamed_356))
+                (portRef CE (instanceRef f1_Result_7_1_FRB_renamed_357))
+                (portRef CE (instanceRef f1_Result_8_1_FRB_renamed_358))
+                (portRef CE (instanceRef f1_Result_9_1_FRB_renamed_359))
+                (portRef CE (instanceRef f1_Result_10_1_FRB_renamed_360))
+                (portRef CE (instanceRef f1_Result_11_1_FRB_renamed_361))
+                (portRef CE (instanceRef f1_Result_12_1_FRB_renamed_362))
+                (portRef CE (instanceRef f1_dont_write_past_me_0__FRB_renamed_363))
+                (portRef CE (instanceRef f1_dont_write_past_me_1__FRB_renamed_364))
+                (portRef CE (instanceRef f1_dont_write_past_me_2__FRB_renamed_365))
+                (portRef CE (instanceRef f1_dont_write_past_me_3__FRB_renamed_366))
+                (portRef CE (instanceRef f1_dont_write_past_me_4__FRB_renamed_367))
+                (portRef CE (instanceRef f1_dont_write_past_me_5__FRB_renamed_368))
+                (portRef CE (instanceRef f1_dont_write_past_me_6__FRB_renamed_369))
+                (portRef CE (instanceRef f1_dont_write_past_me_7__FRB_renamed_370))
+                (portRef CE (instanceRef f1_dont_write_past_me_8__FRB_renamed_371))
+                (portRef CE (instanceRef f1_dont_write_past_me_9__FRB_renamed_372))
+                (portRef CE (instanceRef f1_dont_write_past_me_10__FRB_renamed_373))
+                (portRef CE (instanceRef f1_dont_write_past_me_11__FRB_renamed_374))
+                (portRef CE (instanceRef f1_dont_write_past_me_12__FRB_renamed_375))
+                (portRef O (instanceRef f1__n0161_inv1_cy1))
+              )
+            )
+            (net (rename f1_becoming_full "f1/becoming_full")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_becoming_full_cy_4__))
+                (portRef I1 (instanceRef f1_full_reg_glue_set_renamed_537))
+              )
+            )
+            (net (rename f1_rd_addr_12__wr_addr_12__equal_11_o "f1/rd_addr[12]_wr_addr[12]_equal_11_o")
+              (joined
+                (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__))
+                (portRef CI (instanceRef f1__n0161_inv1_cy))
+                (portRef I2 (instanceRef f1_read_state_FSM_FFd1_In111))
+                (portRef I1 (instanceRef f1_read_state_FSM_FFd2_In1))
+              )
+            )
+            (net (rename f1_dont_write_past_me_0__FRB "f1/dont_write_past_me<0>_FRB")
+              (joined
+                (portRef I1 (instanceRef f1_Mcompar_becoming_full_lut_0__))
+                (portRef Q (instanceRef f1_dont_write_past_me_0__FRB_renamed_363))
+              )
+            )
+            (net (rename f1_dont_write_past_me_1__FRB "f1/dont_write_past_me<1>_FRB")
+              (joined
+                (portRef I3 (instanceRef f1_Mcompar_becoming_full_lut_0__))
+                (portRef Q (instanceRef f1_dont_write_past_me_1__FRB_renamed_364))
+              )
+            )
+            (net (rename f1_dont_write_past_me_2__FRB "f1/dont_write_past_me<2>_FRB")
+              (joined
+                (portRef I5 (instanceRef f1_Mcompar_becoming_full_lut_0__))
+                (portRef Q (instanceRef f1_dont_write_past_me_2__FRB_renamed_365))
+              )
+            )
+            (net (rename f1_dont_write_past_me_3__FRB "f1/dont_write_past_me<3>_FRB")
+              (joined
+                (portRef I1 (instanceRef f1_Mcompar_becoming_full_lut_1__))
+                (portRef Q (instanceRef f1_dont_write_past_me_3__FRB_renamed_366))
+              )
+            )
+            (net (rename f1_dont_write_past_me_4__FRB "f1/dont_write_past_me<4>_FRB")
+              (joined
+                (portRef I3 (instanceRef f1_Mcompar_becoming_full_lut_1__))
+                (portRef Q (instanceRef f1_dont_write_past_me_4__FRB_renamed_367))
+              )
+            )
+            (net (rename f1_dont_write_past_me_5__FRB "f1/dont_write_past_me<5>_FRB")
+              (joined
+                (portRef I5 (instanceRef f1_Mcompar_becoming_full_lut_1__))
+                (portRef Q (instanceRef f1_dont_write_past_me_5__FRB_renamed_368))
+              )
+            )
+            (net (rename f1_dont_write_past_me_6__FRB "f1/dont_write_past_me<6>_FRB")
+              (joined
+                (portRef I1 (instanceRef f1_Mcompar_becoming_full_lut_2__))
+                (portRef Q (instanceRef f1_dont_write_past_me_6__FRB_renamed_369))
+              )
+            )
+            (net (rename f1_dont_write_past_me_7__FRB "f1/dont_write_past_me<7>_FRB")
+              (joined
+                (portRef I3 (instanceRef f1_Mcompar_becoming_full_lut_2__))
+                (portRef Q (instanceRef f1_dont_write_past_me_7__FRB_renamed_370))
+              )
+            )
+            (net (rename f1_dont_write_past_me_8__FRB "f1/dont_write_past_me<8>_FRB")
+              (joined
+                (portRef I5 (instanceRef f1_Mcompar_becoming_full_lut_2__))
+                (portRef Q (instanceRef f1_dont_write_past_me_8__FRB_renamed_371))
+              )
+            )
+            (net (rename f1_dont_write_past_me_9__FRB "f1/dont_write_past_me<9>_FRB")
+              (joined
+                (portRef I1 (instanceRef f1_Mcompar_becoming_full_lut_3__))
+                (portRef Q (instanceRef f1_dont_write_past_me_9__FRB_renamed_372))
+              )
+            )
+            (net (rename f1_dont_write_past_me_10__FRB "f1/dont_write_past_me<10>_FRB")
+              (joined
+                (portRef I3 (instanceRef f1_Mcompar_becoming_full_lut_3__))
+                (portRef Q (instanceRef f1_dont_write_past_me_10__FRB_renamed_373))
+              )
+            )
+            (net (rename f1_dont_write_past_me_11__FRB "f1/dont_write_past_me<11>_FRB")
+              (joined
+                (portRef I5 (instanceRef f1_Mcompar_becoming_full_lut_3__))
+                (portRef Q (instanceRef f1_dont_write_past_me_11__FRB_renamed_374))
+              )
+            )
+            (net (rename f1_dont_write_past_me_12__FRB "f1/dont_write_past_me<12>_FRB")
+              (joined
+                (portRef I1 (instanceRef f1_Mcompar_becoming_full_lut_4__))
+                (portRef Q (instanceRef f1_dont_write_past_me_12__FRB_renamed_375))
+              )
+            )
+            (net (rename f1_GND_14_o_read_OR_37_o "f1/GND_14_o_read_OR_37_o")
+              (joined
+                (portRef O (instanceRef f1_GND_14_o_read_OR_37_o1))
+                (portRef ENBRDEN (instanceRef f1_ram_Mram_ram33))
+                (portRef ENB (instanceRef f1_ram_Mram_ram31))
+                (portRef ENB (instanceRef f1_ram_Mram_ram30))
+                (portRef ENB (instanceRef f1_ram_Mram_ram32))
+                (portRef ENB (instanceRef f1_ram_Mram_ram28))
+                (portRef ENB (instanceRef f1_ram_Mram_ram27))
+                (portRef ENB (instanceRef f1_ram_Mram_ram29))
+                (portRef ENB (instanceRef f1_ram_Mram_ram25))
+                (portRef ENB (instanceRef f1_ram_Mram_ram24))
+                (portRef ENB (instanceRef f1_ram_Mram_ram26))
+                (portRef ENB (instanceRef f1_ram_Mram_ram22))
+                (portRef ENB (instanceRef f1_ram_Mram_ram21))
+                (portRef ENB (instanceRef f1_ram_Mram_ram23))
+                (portRef ENB (instanceRef f1_ram_Mram_ram19))
+                (portRef ENB (instanceRef f1_ram_Mram_ram18))
+                (portRef ENB (instanceRef f1_ram_Mram_ram20))
+                (portRef ENB (instanceRef f1_ram_Mram_ram16))
+                (portRef ENB (instanceRef f1_ram_Mram_ram15))
+                (portRef ENB (instanceRef f1_ram_Mram_ram17))
+                (portRef ENB (instanceRef f1_ram_Mram_ram14))
+                (portRef ENB (instanceRef f1_ram_Mram_ram13))
+                (portRef ENB (instanceRef f1_ram_Mram_ram12))
+                (portRef ENB (instanceRef f1_ram_Mram_ram11))
+                (portRef ENB (instanceRef f1_ram_Mram_ram9))
+                (portRef ENB (instanceRef f1_ram_Mram_ram8))
+                (portRef ENB (instanceRef f1_ram_Mram_ram10))
+                (portRef ENB (instanceRef f1_ram_Mram_ram6))
+                (portRef ENB (instanceRef f1_ram_Mram_ram5))
+                (portRef ENB (instanceRef f1_ram_Mram_ram7))
+                (portRef ENB (instanceRef f1_ram_Mram_ram3))
+                (portRef ENB (instanceRef f1_ram_Mram_ram2))
+                (portRef ENB (instanceRef f1_ram_Mram_ram4))
+                (portRef ENB (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_write "f1/write")
+              (joined
+                (portRef CE (instanceRef f1_wr_addr_1))
+                (portRef CE (instanceRef f1_wr_addr_2))
+                (portRef CE (instanceRef f1_wr_addr_3))
+                (portRef CE (instanceRef f1_wr_addr_4))
+                (portRef CE (instanceRef f1_wr_addr_5))
+                (portRef CE (instanceRef f1_wr_addr_6))
+                (portRef CE (instanceRef f1_wr_addr_7))
+                (portRef CE (instanceRef f1_wr_addr_8))
+                (portRef CE (instanceRef f1_wr_addr_9))
+                (portRef CE (instanceRef f1_wr_addr_10))
+                (portRef CE (instanceRef f1_wr_addr_11))
+                (portRef CE (instanceRef f1_wr_addr_12))
+                (portRef CE (instanceRef f1_wr_addr_0))
+                (portRef O (instanceRef f1_write11))
+                (portRef CE (instanceRef f1_Result_0_2_FRB_renamed_337))
+                (portRef CE (instanceRef f1_Result_1_2_FRB_renamed_338))
+                (portRef CE (instanceRef f1_Result_2_2_FRB_renamed_339))
+                (portRef CE (instanceRef f1_Result_3_2_FRB_renamed_340))
+                (portRef CE (instanceRef f1_Result_4_2_FRB_renamed_341))
+                (portRef CE (instanceRef f1_Result_5_2_FRB_renamed_342))
+                (portRef CE (instanceRef f1_Result_6_2_FRB_renamed_343))
+                (portRef CE (instanceRef f1_Result_7_2_FRB_renamed_344))
+                (portRef CE (instanceRef f1_Result_8_2_FRB_renamed_345))
+                (portRef CE (instanceRef f1_Result_9_2_FRB_renamed_346))
+                (portRef CE (instanceRef f1_Result_10_2_FRB_renamed_347))
+                (portRef CE (instanceRef f1_Result_11_2_FRB_renamed_348))
+                (portRef CE (instanceRef f1_Result_12_2_FRB_renamed_349))
+                (portRef (member WEAWEL 1) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member WEAWEL 0) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram1))
+                (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram1))
+                (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram1))
+                (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_wr_addr_0_ "f1/wr_addr<0>")
+              (joined
+                (portRef Q (instanceRef f1_wr_addr_0))
+                (portRef I1 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef I0 (instanceRef f1_Mcompar_becoming_full_lut_0__))
+                (portRef (member ADDRAWRADDR 12) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_wr_addr_1_ "f1/wr_addr<1>")
+              (joined
+                (portRef Q (instanceRef f1_wr_addr_1))
+                (portRef I3 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef I2 (instanceRef f1_Mcompar_becoming_full_lut_0__))
+                (portRef (member ADDRAWRADDR 11) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_wr_addr_2_ "f1/wr_addr<2>")
+              (joined
+                (portRef Q (instanceRef f1_wr_addr_2))
+                (portRef I5 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef I4 (instanceRef f1_Mcompar_becoming_full_lut_0__))
+                (portRef (member ADDRAWRADDR 10) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRA 10) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_wr_addr_3_ "f1/wr_addr<3>")
+              (joined
+                (portRef Q (instanceRef f1_wr_addr_3))
+                (portRef I1 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef I0 (instanceRef f1_Mcompar_becoming_full_lut_1__))
+                (portRef (member ADDRAWRADDR 9) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_wr_addr_4_ "f1/wr_addr<4>")
+              (joined
+                (portRef Q (instanceRef f1_wr_addr_4))
+                (portRef I3 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef I2 (instanceRef f1_Mcompar_becoming_full_lut_1__))
+                (portRef (member ADDRAWRADDR 8) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_wr_addr_5_ "f1/wr_addr<5>")
+              (joined
+                (portRef Q (instanceRef f1_wr_addr_5))
+                (portRef I5 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef I4 (instanceRef f1_Mcompar_becoming_full_lut_1__))
+                (portRef (member ADDRAWRADDR 7) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_wr_addr_6_ "f1/wr_addr<6>")
+              (joined
+                (portRef Q (instanceRef f1_wr_addr_6))
+                (portRef I1 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef I0 (instanceRef f1_Mcompar_becoming_full_lut_2__))
+                (portRef (member ADDRAWRADDR 6) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_wr_addr_7_ "f1/wr_addr<7>")
+              (joined
+                (portRef Q (instanceRef f1_wr_addr_7))
+                (portRef I3 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef I2 (instanceRef f1_Mcompar_becoming_full_lut_2__))
+                (portRef (member ADDRAWRADDR 5) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_wr_addr_8_ "f1/wr_addr<8>")
+              (joined
+                (portRef Q (instanceRef f1_wr_addr_8))
+                (portRef I5 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef I4 (instanceRef f1_Mcompar_becoming_full_lut_2__))
+                (portRef (member ADDRAWRADDR 4) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_wr_addr_9_ "f1/wr_addr<9>")
+              (joined
+                (portRef Q (instanceRef f1_wr_addr_9))
+                (portRef I1 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef I0 (instanceRef f1_Mcompar_becoming_full_lut_3__))
+                (portRef (member ADDRAWRADDR 3) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_wr_addr_10_ "f1/wr_addr<10>")
+              (joined
+                (portRef Q (instanceRef f1_wr_addr_10))
+                (portRef I3 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef I2 (instanceRef f1_Mcompar_becoming_full_lut_3__))
+                (portRef (member ADDRAWRADDR 2) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_wr_addr_11_ "f1/wr_addr<11>")
+              (joined
+                (portRef Q (instanceRef f1_wr_addr_11))
+                (portRef I5 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef I4 (instanceRef f1_Mcompar_becoming_full_lut_3__))
+                (portRef (member ADDRAWRADDR 1) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_wr_addr_12_ "f1/wr_addr<12>")
+              (joined
+                (portRef Q (instanceRef f1_wr_addr_12))
+                (portRef I1 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__))
+                (portRef I0 (instanceRef f1_Mcompar_becoming_full_lut_4__))
+                (portRef (member ADDRAWRADDR 0) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_rd_addr_0_ "f1/rd_addr<0>")
+              (joined
+                (portRef Q (instanceRef f1_rd_addr_0))
+                (portRef I0 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef (member ADDRBRDADDR 12) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_rd_addr_1_ "f1/rd_addr<1>")
+              (joined
+                (portRef Q (instanceRef f1_rd_addr_1))
+                (portRef I2 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef (member ADDRBRDADDR 11) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_rd_addr_2_ "f1/rd_addr<2>")
+              (joined
+                (portRef Q (instanceRef f1_rd_addr_2))
+                (portRef I4 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef (member ADDRBRDADDR 10) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_rd_addr_3_ "f1/rd_addr<3>")
+              (joined
+                (portRef Q (instanceRef f1_rd_addr_3))
+                (portRef I0 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef (member ADDRBRDADDR 9) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_rd_addr_4_ "f1/rd_addr<4>")
+              (joined
+                (portRef Q (instanceRef f1_rd_addr_4))
+                (portRef I2 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef (member ADDRBRDADDR 8) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_rd_addr_5_ "f1/rd_addr<5>")
+              (joined
+                (portRef Q (instanceRef f1_rd_addr_5))
+                (portRef I4 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef (member ADDRBRDADDR 7) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_rd_addr_6_ "f1/rd_addr<6>")
+              (joined
+                (portRef Q (instanceRef f1_rd_addr_6))
+                (portRef I0 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef (member ADDRBRDADDR 6) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_rd_addr_7_ "f1/rd_addr<7>")
+              (joined
+                (portRef Q (instanceRef f1_rd_addr_7))
+                (portRef I2 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef (member ADDRBRDADDR 5) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_rd_addr_8_ "f1/rd_addr<8>")
+              (joined
+                (portRef Q (instanceRef f1_rd_addr_8))
+                (portRef I4 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef (member ADDRBRDADDR 4) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_rd_addr_9_ "f1/rd_addr<9>")
+              (joined
+                (portRef Q (instanceRef f1_rd_addr_9))
+                (portRef I0 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef (member ADDRBRDADDR 3) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_rd_addr_10_ "f1/rd_addr<10>")
+              (joined
+                (portRef Q (instanceRef f1_rd_addr_10))
+                (portRef I2 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef (member ADDRBRDADDR 2) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_rd_addr_11_ "f1/rd_addr<11>")
+              (joined
+                (portRef Q (instanceRef f1_rd_addr_11))
+                (portRef I4 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef (member ADDRBRDADDR 1) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_rd_addr_12_ "f1/rd_addr<12>")
+              (joined
+                (portRef Q (instanceRef f1_rd_addr_12))
+                (portRef I0 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__))
+                (portRef (member ADDRBRDADDR 0) (instanceRef f1_ram_Mram_ram33))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram31))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram30))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram32))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram28))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram27))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram29))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram25))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram24))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram26))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram22))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram21))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram23))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram19))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram18))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram20))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram16))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram15))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram17))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram14))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram13))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram12))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram11))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram9))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram8))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram10))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram6))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram5))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram7))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram3))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram2))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram4))
+                (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram1))
+              )
+            )
+            (net (rename f1_full_reg "f1/full_reg")
+              (joined
+                (portRef I1 (instanceRef f1_write11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0))
+                (portRef Q (instanceRef f1_full_reg_renamed_116))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_renamed_417))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set_renamed_419))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+                (portRef I4 (instanceRef f1_read_state_FSM_FFd2_In1))
+                (portRef I4 (instanceRef f1_full_reg_glue_set_renamed_537))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_renamed_39))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111))
+              )
+            )
+            (net (rename f1_read_state_FSM_FFd1 "f1/read_state_FSM_FFd1")
+              (joined
+                (portRef Q (instanceRef f1_read_state_FSM_FFd1_renamed_29))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111))
+                (portRef I1 (instanceRef f1__n0161_inv1_lut_renamed_507))
+                (portRef I1 (instanceRef f1__n0161_inv1_lut1_renamed_508))
+                (portRef I0 (instanceRef f1_GND_14_o_read_OR_37_o1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1))
+                (portRef I0 (instanceRef f1_read_state_FSM_FFd1_In111))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_renamed_525))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_renamed_530))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_renamed_535))
+                (portRef I0 (instanceRef f1_read_state_FSM_FFd2_In1))
+                (portRef I3 (instanceRef f1_full_reg_glue_set_renamed_537))
+              )
+            )
+            (net (rename f0_Mcompar_becoming_full_lut_4_ "f0/Mcompar_becoming_full_lut<4>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_becoming_full_lut_4__))
+                (portRef S (instanceRef f0_Mcompar_becoming_full_cy_4__))
+              )
+            )
+            (net (rename f0_Mcompar_becoming_full_cy_3_ "f0/Mcompar_becoming_full_cy<3>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_becoming_full_cy_3__))
+                (portRef CI (instanceRef f0_Mcompar_becoming_full_cy_4__))
+              )
+            )
+            (net (rename f0_Mcompar_becoming_full_lut_3_ "f0/Mcompar_becoming_full_lut<3>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_becoming_full_lut_3__))
+                (portRef S (instanceRef f0_Mcompar_becoming_full_cy_3__))
+              )
+            )
+            (net (rename f0_Mcompar_becoming_full_cy_2_ "f0/Mcompar_becoming_full_cy<2>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_becoming_full_cy_2__))
+                (portRef CI (instanceRef f0_Mcompar_becoming_full_cy_3__))
+              )
+            )
+            (net (rename f0_Mcompar_becoming_full_lut_2_ "f0/Mcompar_becoming_full_lut<2>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_becoming_full_lut_2__))
+                (portRef S (instanceRef f0_Mcompar_becoming_full_cy_2__))
+              )
+            )
+            (net (rename f0_Mcompar_becoming_full_cy_1_ "f0/Mcompar_becoming_full_cy<1>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_becoming_full_cy_1__))
+                (portRef CI (instanceRef f0_Mcompar_becoming_full_cy_2__))
+              )
+            )
+            (net (rename f0_Mcompar_becoming_full_lut_1_ "f0/Mcompar_becoming_full_lut<1>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_becoming_full_lut_1__))
+                (portRef S (instanceRef f0_Mcompar_becoming_full_cy_1__))
+              )
+            )
+            (net (rename f0_Mcompar_becoming_full_cy_0_ "f0/Mcompar_becoming_full_cy<0>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_becoming_full_cy_0__))
+                (portRef CI (instanceRef f0_Mcompar_becoming_full_cy_1__))
+              )
+            )
+            (net (rename f0_Mcompar_becoming_full_lut_0_ "f0/Mcompar_becoming_full_lut<0>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_becoming_full_lut_0__))
+                (portRef S (instanceRef f0_Mcompar_becoming_full_cy_0__))
+              )
+            )
+            (net (rename f0_Mcount_rd_addr_cy_10_ "f0/Mcount_rd_addr_cy<10>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_rd_addr_cy_10__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_cy_11__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_xor_11__))
+              )
+            )
+            (net (rename f0_Mcount_rd_addr_cy_9_ "f0/Mcount_rd_addr_cy<9>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_rd_addr_cy_9__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_cy_10__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_xor_10__))
+              )
+            )
+            (net (rename f0_Mcount_rd_addr_cy_8_ "f0/Mcount_rd_addr_cy<8>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_rd_addr_cy_8__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_cy_9__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_xor_9__))
+              )
+            )
+            (net (rename f0_Mcount_rd_addr_cy_7_ "f0/Mcount_rd_addr_cy<7>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_rd_addr_cy_7__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_cy_8__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_xor_8__))
+              )
+            )
+            (net (rename f0_Mcount_rd_addr_cy_6_ "f0/Mcount_rd_addr_cy<6>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_rd_addr_cy_6__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_cy_7__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_xor_7__))
+              )
+            )
+            (net (rename f0_Mcount_rd_addr_cy_5_ "f0/Mcount_rd_addr_cy<5>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_rd_addr_cy_5__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_cy_6__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_xor_6__))
+              )
+            )
+            (net (rename f0_Mcount_rd_addr_cy_4_ "f0/Mcount_rd_addr_cy<4>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_rd_addr_cy_4__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_cy_5__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_xor_5__))
+              )
+            )
+            (net (rename f0_Mcount_rd_addr_cy_3_ "f0/Mcount_rd_addr_cy<3>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_rd_addr_cy_3__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_cy_4__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_xor_4__))
+              )
+            )
+            (net (rename f0_Mcount_rd_addr_cy_2_ "f0/Mcount_rd_addr_cy<2>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_rd_addr_cy_2__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_cy_3__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_xor_3__))
+              )
+            )
+            (net (rename f0_Mcount_rd_addr_cy_1_ "f0/Mcount_rd_addr_cy<1>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_rd_addr_cy_1__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_cy_2__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_xor_2__))
+              )
+            )
+            (net (rename f0_Mcount_rd_addr_cy_0_ "f0/Mcount_rd_addr_cy<0>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_rd_addr_cy_0__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_cy_1__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_xor_1__))
+              )
+            )
+            (net (rename f0_Mcount_rd_addr_lut_0_ "f0/Mcount_rd_addr_lut<0>")
+              (joined
+                (portRef S (instanceRef f0_Mcount_rd_addr_cy_0__))
+                (portRef LI (instanceRef f0_Mcount_rd_addr_xor_0__))
+                (portRef O (instanceRef f0_Mcount_rd_addr_lut_0__INV_0))
+              )
+            )
+            (net (rename f0_Mcount_wr_addr_cy_10_ "f0/Mcount_wr_addr_cy<10>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_wr_addr_cy_10__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_cy_11__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_xor_11__))
+              )
+            )
+            (net (rename f0_Mcount_wr_addr_cy_9_ "f0/Mcount_wr_addr_cy<9>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_wr_addr_cy_9__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_cy_10__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_xor_10__))
+              )
+            )
+            (net (rename f0_Mcount_wr_addr_cy_8_ "f0/Mcount_wr_addr_cy<8>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_wr_addr_cy_8__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_cy_9__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_xor_9__))
+              )
+            )
+            (net (rename f0_Mcount_wr_addr_cy_7_ "f0/Mcount_wr_addr_cy<7>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_wr_addr_cy_7__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_cy_8__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_xor_8__))
+              )
+            )
+            (net (rename f0_Mcount_wr_addr_cy_6_ "f0/Mcount_wr_addr_cy<6>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_wr_addr_cy_6__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_cy_7__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_xor_7__))
+              )
+            )
+            (net (rename f0_Mcount_wr_addr_cy_5_ "f0/Mcount_wr_addr_cy<5>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_wr_addr_cy_5__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_cy_6__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_xor_6__))
+              )
+            )
+            (net (rename f0_Mcount_wr_addr_cy_4_ "f0/Mcount_wr_addr_cy<4>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_wr_addr_cy_4__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_cy_5__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_xor_5__))
+              )
+            )
+            (net (rename f0_Mcount_wr_addr_cy_3_ "f0/Mcount_wr_addr_cy<3>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_wr_addr_cy_3__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_cy_4__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_xor_4__))
+              )
+            )
+            (net (rename f0_Mcount_wr_addr_cy_2_ "f0/Mcount_wr_addr_cy<2>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_wr_addr_cy_2__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_cy_3__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_xor_3__))
+              )
+            )
+            (net (rename f0_Mcount_wr_addr_cy_1_ "f0/Mcount_wr_addr_cy<1>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_wr_addr_cy_1__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_cy_2__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_xor_2__))
+              )
+            )
+            (net (rename f0_Mcount_wr_addr_cy_0_ "f0/Mcount_wr_addr_cy<0>")
+              (joined
+                (portRef O (instanceRef f0_Mcount_wr_addr_cy_0__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_cy_1__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_xor_1__))
+              )
+            )
+            (net (rename f0_Mcount_wr_addr_lut_0_ "f0/Mcount_wr_addr_lut<0>")
+              (joined
+                (portRef S (instanceRef f0_Mcount_wr_addr_cy_0__))
+                (portRef LI (instanceRef f0_Mcount_wr_addr_xor_0__))
+                (portRef O (instanceRef f0_Mcount_wr_addr_lut_0__INV_0))
+              )
+            )
+            (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__))
+                (portRef S (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__))
+              )
+            )
+            (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__))
+                (portRef CI (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__))
+              )
+            )
+            (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef S (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__))
+              )
+            )
+            (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__))
+                (portRef CI (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__))
+              )
+            )
+            (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef S (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__))
+              )
+            )
+            (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__))
+                (portRef CI (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__))
+              )
+            )
+            (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef S (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__))
+              )
+            )
+            (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__))
+                (portRef CI (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__))
+              )
+            )
+            (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef S (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_lut_12_ "f0/Msub_dont_write_past_me_lut<12>")
+              (joined
+                (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_12__))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_12__INV_0))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_lut_11_ "f0/Msub_dont_write_past_me_lut<11>")
+              (joined
+                (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_11__))
+                (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_11__))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_11__INV_0))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_cy_10_ "f0/Msub_dont_write_past_me_cy<10>")
+              (joined
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_10__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_11__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_11__))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_lut_10_ "f0/Msub_dont_write_past_me_lut<10>")
+              (joined
+                (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_10__))
+                (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_10__))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_10__INV_0))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_cy_9_ "f0/Msub_dont_write_past_me_cy<9>")
+              (joined
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_9__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_10__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_10__))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_lut_9_ "f0/Msub_dont_write_past_me_lut<9>")
+              (joined
+                (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_9__))
+                (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_9__))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_9__INV_0))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_cy_8_ "f0/Msub_dont_write_past_me_cy<8>")
+              (joined
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_8__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_9__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_9__))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_lut_8_ "f0/Msub_dont_write_past_me_lut<8>")
+              (joined
+                (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_8__))
+                (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_8__))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_8__INV_0))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_cy_7_ "f0/Msub_dont_write_past_me_cy<7>")
+              (joined
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_7__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_8__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_8__))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_lut_7_ "f0/Msub_dont_write_past_me_lut<7>")
+              (joined
+                (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_7__))
+                (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_7__))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_7__INV_0))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_cy_6_ "f0/Msub_dont_write_past_me_cy<6>")
+              (joined
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_6__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_7__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_7__))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_lut_6_ "f0/Msub_dont_write_past_me_lut<6>")
+              (joined
+                (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_6__))
+                (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_6__))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_6__INV_0))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_cy_5_ "f0/Msub_dont_write_past_me_cy<5>")
+              (joined
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_5__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_6__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_6__))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_lut_5_ "f0/Msub_dont_write_past_me_lut<5>")
+              (joined
+                (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_5__))
+                (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_5__))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_5__INV_0))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_cy_4_ "f0/Msub_dont_write_past_me_cy<4>")
+              (joined
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_4__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_5__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_5__))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_lut_4_ "f0/Msub_dont_write_past_me_lut<4>")
+              (joined
+                (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_4__))
+                (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_4__))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_4__INV_0))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_cy_3_ "f0/Msub_dont_write_past_me_cy<3>")
+              (joined
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_3__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_4__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_4__))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_lut_3_ "f0/Msub_dont_write_past_me_lut<3>")
+              (joined
+                (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_3__))
+                (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_3__))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_3__INV_0))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_cy_2_ "f0/Msub_dont_write_past_me_cy<2>")
+              (joined
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_2__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_3__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_3__))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_lut_2_ "f0/Msub_dont_write_past_me_lut<2>")
+              (joined
+                (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_2__))
+                (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_2__))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_2__INV_0))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_cy_1_ "f0/Msub_dont_write_past_me_cy<1>")
+              (joined
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_1__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_2__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_2__))
+              )
+            )
+            (net (rename f0_Msub_dont_write_past_me_cy_0_ "f0/Msub_dont_write_past_me_cy<0>")
+              (joined
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_0__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_1__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_1__))
+              )
+            )
+            (net (rename f0_read_state_FSM_FFd2 "f0/read_state_FSM_FFd2")
+              (joined
+                (portRef Q (instanceRef f0_read_state_FSM_FFd2_renamed_32))
+                (portRef I0 (instanceRef f0__n0161_inv1_lut1_renamed_510))
+                (portRef I2 (instanceRef f0_GND_14_o_read_OR_37_o1))
+                (portRef I3 (instanceRef f0_read_state_FSM_FFd1_In111))
+                (portRef I5 (instanceRef f0_read_state_FSM_FFd2_In1))
+              )
+            )
+            (net (rename f0_read_state_FSM_FFd2_In "f0/read_state_FSM_FFd2-In")
+              (joined
+                (portRef D (instanceRef f0_read_state_FSM_FFd2_renamed_32))
+                (portRef O (instanceRef f0_read_state_FSM_FFd2_In1))
+              )
+            )
+            (net (rename f0_read_state_FSM_FFd1_In1 "f0/read_state_FSM_FFd1-In1")
+              (joined
+                (portRef D (instanceRef f0_read_state_FSM_FFd1_renamed_31))
+                (portRef O (instanceRef f0_read_state_FSM_FFd1_In111))
+              )
+            )
+            (net (rename f0_Result_12_2_FRB "f0/Result<12>2_FRB")
+              (joined
+                (portRef D (instanceRef f0_wr_addr_12))
+                (portRef Q (instanceRef f0_Result_12_2_FRB_renamed_388))
+                (portRef I0 (instanceRef f0_Mcount_wr_addr_xor_12__rt_renamed_255))
+              )
+            )
+            (net (rename f0_Result_11_2_FRB "f0/Result<11>2_FRB")
+              (joined
+                (portRef D (instanceRef f0_wr_addr_11))
+                (portRef Q (instanceRef f0_Result_11_2_FRB_renamed_387))
+                (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_11__rt_renamed_231))
+              )
+            )
+            (net (rename f0_Result_10_2_FRB "f0/Result<10>2_FRB")
+              (joined
+                (portRef D (instanceRef f0_wr_addr_10))
+                (portRef Q (instanceRef f0_Result_10_2_FRB_renamed_386))
+                (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_10__rt_renamed_232))
+              )
+            )
+            (net (rename f0_Result_9_2_FRB "f0/Result<9>2_FRB")
+              (joined
+                (portRef D (instanceRef f0_wr_addr_9))
+                (portRef Q (instanceRef f0_Result_9_2_FRB_renamed_385))
+                (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_9__rt_renamed_233))
+              )
+            )
+            (net (rename f0_Result_8_2_FRB "f0/Result<8>2_FRB")
+              (joined
+                (portRef D (instanceRef f0_wr_addr_8))
+                (portRef Q (instanceRef f0_Result_8_2_FRB_renamed_384))
+                (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_8__rt_renamed_234))
+              )
+            )
+            (net (rename f0_Result_7_2_FRB "f0/Result<7>2_FRB")
+              (joined
+                (portRef D (instanceRef f0_wr_addr_7))
+                (portRef Q (instanceRef f0_Result_7_2_FRB_renamed_383))
+                (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_7__rt_renamed_235))
+              )
+            )
+            (net (rename f0_Result_6_2_FRB "f0/Result<6>2_FRB")
+              (joined
+                (portRef D (instanceRef f0_wr_addr_6))
+                (portRef Q (instanceRef f0_Result_6_2_FRB_renamed_382))
+                (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_6__rt_renamed_236))
+              )
+            )
+            (net (rename f0_Result_5_2_FRB "f0/Result<5>2_FRB")
+              (joined
+                (portRef D (instanceRef f0_wr_addr_5))
+                (portRef Q (instanceRef f0_Result_5_2_FRB_renamed_381))
+                (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_5__rt_renamed_237))
+              )
+            )
+            (net (rename f0_Result_4_2_FRB "f0/Result<4>2_FRB")
+              (joined
+                (portRef D (instanceRef f0_wr_addr_4))
+                (portRef Q (instanceRef f0_Result_4_2_FRB_renamed_380))
+                (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_4__rt_renamed_238))
+              )
+            )
+            (net (rename f0_Result_3_2_FRB "f0/Result<3>2_FRB")
+              (joined
+                (portRef D (instanceRef f0_wr_addr_3))
+                (portRef Q (instanceRef f0_Result_3_2_FRB_renamed_379))
+                (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_3__rt_renamed_239))
+              )
+            )
+            (net (rename f0_Result_2_2_FRB "f0/Result<2>2_FRB")
+              (joined
+                (portRef D (instanceRef f0_wr_addr_2))
+                (portRef Q (instanceRef f0_Result_2_2_FRB_renamed_378))
+                (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_2__rt_renamed_240))
+              )
+            )
+            (net (rename f0_Result_1_2_FRB "f0/Result<1>2_FRB")
+              (joined
+                (portRef D (instanceRef f0_wr_addr_1))
+                (portRef Q (instanceRef f0_Result_1_2_FRB_renamed_377))
+                (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_1__rt_renamed_241))
+              )
+            )
+            (net (rename f0_Result_0_2_FRB "f0/Result<0>2_FRB")
+              (joined
+                (portRef D (instanceRef f0_wr_addr_0))
+                (portRef Q (instanceRef f0_Result_0_2_FRB_renamed_376))
+                (portRef I (instanceRef f0_Mcount_wr_addr_lut_0__INV_0))
+              )
+            )
+            (net (rename f0_Result_12_1_FRB "f0/Result<12>1_FRB")
+              (joined
+                (portRef D (instanceRef f0_rd_addr_12))
+                (portRef Q (instanceRef f0_Result_12_1_FRB_renamed_401))
+                (portRef I0 (instanceRef f0_Mcount_rd_addr_xor_12__rt_renamed_254))
+                (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_12__INV_0))
+              )
+            )
+            (net (rename f0_Result_11_1_FRB "f0/Result<11>1_FRB")
+              (joined
+                (portRef D (instanceRef f0_rd_addr_11))
+                (portRef Q (instanceRef f0_Result_11_1_FRB_renamed_400))
+                (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_11__rt_renamed_220))
+                (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_11__INV_0))
+              )
+            )
+            (net (rename f0_Result_10_1_FRB "f0/Result<10>1_FRB")
+              (joined
+                (portRef D (instanceRef f0_rd_addr_10))
+                (portRef Q (instanceRef f0_Result_10_1_FRB_renamed_399))
+                (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_10__rt_renamed_221))
+                (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_10__INV_0))
+              )
+            )
+            (net (rename f0_Result_9_1_FRB "f0/Result<9>1_FRB")
+              (joined
+                (portRef D (instanceRef f0_rd_addr_9))
+                (portRef Q (instanceRef f0_Result_9_1_FRB_renamed_398))
+                (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_9__rt_renamed_222))
+                (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_9__INV_0))
+              )
+            )
+            (net (rename f0_Result_8_1_FRB "f0/Result<8>1_FRB")
+              (joined
+                (portRef D (instanceRef f0_rd_addr_8))
+                (portRef Q (instanceRef f0_Result_8_1_FRB_renamed_397))
+                (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_8__rt_renamed_223))
+                (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_8__INV_0))
+              )
+            )
+            (net (rename f0_Result_7_1_FRB "f0/Result<7>1_FRB")
+              (joined
+                (portRef D (instanceRef f0_rd_addr_7))
+                (portRef Q (instanceRef f0_Result_7_1_FRB_renamed_396))
+                (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_7__rt_renamed_224))
+                (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_7__INV_0))
+              )
+            )
+            (net (rename f0_Result_6_1_FRB "f0/Result<6>1_FRB")
+              (joined
+                (portRef D (instanceRef f0_rd_addr_6))
+                (portRef Q (instanceRef f0_Result_6_1_FRB_renamed_395))
+                (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_6__rt_renamed_225))
+                (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_6__INV_0))
+              )
+            )
+            (net (rename f0_Result_5_1_FRB "f0/Result<5>1_FRB")
+              (joined
+                (portRef D (instanceRef f0_rd_addr_5))
+                (portRef Q (instanceRef f0_Result_5_1_FRB_renamed_394))
+                (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_5__rt_renamed_226))
+                (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_5__INV_0))
+              )
+            )
+            (net (rename f0_Result_4_1_FRB "f0/Result<4>1_FRB")
+              (joined
+                (portRef D (instanceRef f0_rd_addr_4))
+                (portRef Q (instanceRef f0_Result_4_1_FRB_renamed_393))
+                (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_4__rt_renamed_227))
+                (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_4__INV_0))
+              )
+            )
+            (net (rename f0_Result_3_1_FRB "f0/Result<3>1_FRB")
+              (joined
+                (portRef D (instanceRef f0_rd_addr_3))
+                (portRef Q (instanceRef f0_Result_3_1_FRB_renamed_392))
+                (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_3__rt_renamed_228))
+                (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_3__INV_0))
+              )
+            )
+            (net (rename f0_Result_2_1_FRB "f0/Result<2>1_FRB")
+              (joined
+                (portRef D (instanceRef f0_rd_addr_2))
+                (portRef Q (instanceRef f0_Result_2_1_FRB_renamed_391))
+                (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_2__rt_renamed_229))
+                (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_2__INV_0))
+              )
+            )
+            (net (rename f0_Result_1_1_FRB "f0/Result<1>1_FRB")
+              (joined
+                (portRef D (instanceRef f0_rd_addr_1))
+                (portRef Q (instanceRef f0_Result_1_1_FRB_renamed_390))
+                (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_1__rt_renamed_230))
+                (portRef I0 (instanceRef f0_Msub_dont_write_past_me_cy_1__rt_renamed_242))
+              )
+            )
+            (net (rename f0_Result_0_1_FRB "f0/Result<0>1_FRB")
+              (joined
+                (portRef D (instanceRef f0_rd_addr_0))
+                (portRef Q (instanceRef f0_Result_0_1_FRB_renamed_389))
+                (portRef I0 (instanceRef f0_Msub_dont_write_past_me_cy_0__rt_renamed_243))
+                (portRef I (instanceRef f0_Mcount_rd_addr_lut_0__INV_0))
+              )
+            )
+            (net (rename f0__n0161_inv "f0/_n0161_inv")
+              (joined
+                (portRef CE (instanceRef f0_rd_addr_1))
+                (portRef CE (instanceRef f0_rd_addr_2))
+                (portRef CE (instanceRef f0_rd_addr_3))
+                (portRef CE (instanceRef f0_rd_addr_4))
+                (portRef CE (instanceRef f0_rd_addr_5))
+                (portRef CE (instanceRef f0_rd_addr_6))
+                (portRef CE (instanceRef f0_rd_addr_7))
+                (portRef CE (instanceRef f0_rd_addr_8))
+                (portRef CE (instanceRef f0_rd_addr_9))
+                (portRef CE (instanceRef f0_rd_addr_10))
+                (portRef CE (instanceRef f0_rd_addr_11))
+                (portRef CE (instanceRef f0_rd_addr_12))
+                (portRef CE (instanceRef f0_rd_addr_0))
+                (portRef CE (instanceRef f0_Result_0_1_FRB_renamed_389))
+                (portRef CE (instanceRef f0_Result_1_1_FRB_renamed_390))
+                (portRef CE (instanceRef f0_Result_2_1_FRB_renamed_391))
+                (portRef CE (instanceRef f0_Result_3_1_FRB_renamed_392))
+                (portRef CE (instanceRef f0_Result_4_1_FRB_renamed_393))
+                (portRef CE (instanceRef f0_Result_5_1_FRB_renamed_394))
+                (portRef CE (instanceRef f0_Result_6_1_FRB_renamed_395))
+                (portRef CE (instanceRef f0_Result_7_1_FRB_renamed_396))
+                (portRef CE (instanceRef f0_Result_8_1_FRB_renamed_397))
+                (portRef CE (instanceRef f0_Result_9_1_FRB_renamed_398))
+                (portRef CE (instanceRef f0_Result_10_1_FRB_renamed_399))
+                (portRef CE (instanceRef f0_Result_11_1_FRB_renamed_400))
+                (portRef CE (instanceRef f0_Result_12_1_FRB_renamed_401))
+                (portRef CE (instanceRef f0_dont_write_past_me_0__FRB_renamed_402))
+                (portRef CE (instanceRef f0_dont_write_past_me_1__FRB_renamed_403))
+                (portRef CE (instanceRef f0_dont_write_past_me_2__FRB_renamed_404))
+                (portRef CE (instanceRef f0_dont_write_past_me_3__FRB_renamed_405))
+                (portRef CE (instanceRef f0_dont_write_past_me_4__FRB_renamed_406))
+                (portRef CE (instanceRef f0_dont_write_past_me_5__FRB_renamed_407))
+                (portRef CE (instanceRef f0_dont_write_past_me_6__FRB_renamed_408))
+                (portRef CE (instanceRef f0_dont_write_past_me_7__FRB_renamed_409))
+                (portRef CE (instanceRef f0_dont_write_past_me_8__FRB_renamed_410))
+                (portRef CE (instanceRef f0_dont_write_past_me_9__FRB_renamed_411))
+                (portRef CE (instanceRef f0_dont_write_past_me_10__FRB_renamed_412))
+                (portRef CE (instanceRef f0_dont_write_past_me_11__FRB_renamed_413))
+                (portRef CE (instanceRef f0_dont_write_past_me_12__FRB_renamed_414))
+                (portRef O (instanceRef f0__n0161_inv1_cy1))
+              )
+            )
+            (net (rename f0_becoming_full "f0/becoming_full")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_becoming_full_cy_4__))
+                (portRef I1 (instanceRef f0_full_reg_glue_set_renamed_538))
+              )
+            )
+            (net (rename f0_rd_addr_12__wr_addr_12__equal_11_o "f0/rd_addr[12]_wr_addr[12]_equal_11_o")
+              (joined
+                (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__))
+                (portRef CI (instanceRef f0__n0161_inv1_cy))
+                (portRef I2 (instanceRef f0_read_state_FSM_FFd1_In111))
+                (portRef I1 (instanceRef f0_read_state_FSM_FFd2_In1))
+              )
+            )
+            (net (rename f0_dont_write_past_me_0__FRB "f0/dont_write_past_me<0>_FRB")
+              (joined
+                (portRef I1 (instanceRef f0_Mcompar_becoming_full_lut_0__))
+                (portRef Q (instanceRef f0_dont_write_past_me_0__FRB_renamed_402))
+              )
+            )
+            (net (rename f0_dont_write_past_me_1__FRB "f0/dont_write_past_me<1>_FRB")
+              (joined
+                (portRef I3 (instanceRef f0_Mcompar_becoming_full_lut_0__))
+                (portRef Q (instanceRef f0_dont_write_past_me_1__FRB_renamed_403))
+              )
+            )
+            (net (rename f0_dont_write_past_me_2__FRB "f0/dont_write_past_me<2>_FRB")
+              (joined
+                (portRef I5 (instanceRef f0_Mcompar_becoming_full_lut_0__))
+                (portRef Q (instanceRef f0_dont_write_past_me_2__FRB_renamed_404))
+              )
+            )
+            (net (rename f0_dont_write_past_me_3__FRB "f0/dont_write_past_me<3>_FRB")
+              (joined
+                (portRef I1 (instanceRef f0_Mcompar_becoming_full_lut_1__))
+                (portRef Q (instanceRef f0_dont_write_past_me_3__FRB_renamed_405))
+              )
+            )
+            (net (rename f0_dont_write_past_me_4__FRB "f0/dont_write_past_me<4>_FRB")
+              (joined
+                (portRef I3 (instanceRef f0_Mcompar_becoming_full_lut_1__))
+                (portRef Q (instanceRef f0_dont_write_past_me_4__FRB_renamed_406))
+              )
+            )
+            (net (rename f0_dont_write_past_me_5__FRB "f0/dont_write_past_me<5>_FRB")
+              (joined
+                (portRef I5 (instanceRef f0_Mcompar_becoming_full_lut_1__))
+                (portRef Q (instanceRef f0_dont_write_past_me_5__FRB_renamed_407))
+              )
+            )
+            (net (rename f0_dont_write_past_me_6__FRB "f0/dont_write_past_me<6>_FRB")
+              (joined
+                (portRef I1 (instanceRef f0_Mcompar_becoming_full_lut_2__))
+                (portRef Q (instanceRef f0_dont_write_past_me_6__FRB_renamed_408))
+              )
+            )
+            (net (rename f0_dont_write_past_me_7__FRB "f0/dont_write_past_me<7>_FRB")
+              (joined
+                (portRef I3 (instanceRef f0_Mcompar_becoming_full_lut_2__))
+                (portRef Q (instanceRef f0_dont_write_past_me_7__FRB_renamed_409))
+              )
+            )
+            (net (rename f0_dont_write_past_me_8__FRB "f0/dont_write_past_me<8>_FRB")
+              (joined
+                (portRef I5 (instanceRef f0_Mcompar_becoming_full_lut_2__))
+                (portRef Q (instanceRef f0_dont_write_past_me_8__FRB_renamed_410))
+              )
+            )
+            (net (rename f0_dont_write_past_me_9__FRB "f0/dont_write_past_me<9>_FRB")
+              (joined
+                (portRef I1 (instanceRef f0_Mcompar_becoming_full_lut_3__))
+                (portRef Q (instanceRef f0_dont_write_past_me_9__FRB_renamed_411))
+              )
+            )
+            (net (rename f0_dont_write_past_me_10__FRB "f0/dont_write_past_me<10>_FRB")
+              (joined
+                (portRef I3 (instanceRef f0_Mcompar_becoming_full_lut_3__))
+                (portRef Q (instanceRef f0_dont_write_past_me_10__FRB_renamed_412))
+              )
+            )
+            (net (rename f0_dont_write_past_me_11__FRB "f0/dont_write_past_me<11>_FRB")
+              (joined
+                (portRef I5 (instanceRef f0_Mcompar_becoming_full_lut_3__))
+                (portRef Q (instanceRef f0_dont_write_past_me_11__FRB_renamed_413))
+              )
+            )
+            (net (rename f0_dont_write_past_me_12__FRB "f0/dont_write_past_me<12>_FRB")
+              (joined
+                (portRef I1 (instanceRef f0_Mcompar_becoming_full_lut_4__))
+                (portRef Q (instanceRef f0_dont_write_past_me_12__FRB_renamed_414))
+              )
+            )
+            (net (rename f0_GND_14_o_read_OR_37_o "f0/GND_14_o_read_OR_37_o")
+              (joined
+                (portRef O (instanceRef f0_GND_14_o_read_OR_37_o1))
+                (portRef ENBRDEN (instanceRef f0_ram_Mram_ram33))
+                (portRef ENB (instanceRef f0_ram_Mram_ram31))
+                (portRef ENB (instanceRef f0_ram_Mram_ram30))
+                (portRef ENB (instanceRef f0_ram_Mram_ram32))
+                (portRef ENB (instanceRef f0_ram_Mram_ram28))
+                (portRef ENB (instanceRef f0_ram_Mram_ram27))
+                (portRef ENB (instanceRef f0_ram_Mram_ram29))
+                (portRef ENB (instanceRef f0_ram_Mram_ram25))
+                (portRef ENB (instanceRef f0_ram_Mram_ram24))
+                (portRef ENB (instanceRef f0_ram_Mram_ram26))
+                (portRef ENB (instanceRef f0_ram_Mram_ram22))
+                (portRef ENB (instanceRef f0_ram_Mram_ram21))
+                (portRef ENB (instanceRef f0_ram_Mram_ram23))
+                (portRef ENB (instanceRef f0_ram_Mram_ram19))
+                (portRef ENB (instanceRef f0_ram_Mram_ram18))
+                (portRef ENB (instanceRef f0_ram_Mram_ram20))
+                (portRef ENB (instanceRef f0_ram_Mram_ram16))
+                (portRef ENB (instanceRef f0_ram_Mram_ram15))
+                (portRef ENB (instanceRef f0_ram_Mram_ram17))
+                (portRef ENB (instanceRef f0_ram_Mram_ram14))
+                (portRef ENB (instanceRef f0_ram_Mram_ram13))
+                (portRef ENB (instanceRef f0_ram_Mram_ram12))
+                (portRef ENB (instanceRef f0_ram_Mram_ram11))
+                (portRef ENB (instanceRef f0_ram_Mram_ram9))
+                (portRef ENB (instanceRef f0_ram_Mram_ram8))
+                (portRef ENB (instanceRef f0_ram_Mram_ram10))
+                (portRef ENB (instanceRef f0_ram_Mram_ram6))
+                (portRef ENB (instanceRef f0_ram_Mram_ram5))
+                (portRef ENB (instanceRef f0_ram_Mram_ram7))
+                (portRef ENB (instanceRef f0_ram_Mram_ram3))
+                (portRef ENB (instanceRef f0_ram_Mram_ram2))
+                (portRef ENB (instanceRef f0_ram_Mram_ram4))
+                (portRef ENB (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_write "f0/write")
+              (joined
+                (portRef CE (instanceRef f0_wr_addr_1))
+                (portRef CE (instanceRef f0_wr_addr_2))
+                (portRef CE (instanceRef f0_wr_addr_3))
+                (portRef CE (instanceRef f0_wr_addr_4))
+                (portRef CE (instanceRef f0_wr_addr_5))
+                (portRef CE (instanceRef f0_wr_addr_6))
+                (portRef CE (instanceRef f0_wr_addr_7))
+                (portRef CE (instanceRef f0_wr_addr_8))
+                (portRef CE (instanceRef f0_wr_addr_9))
+                (portRef CE (instanceRef f0_wr_addr_10))
+                (portRef CE (instanceRef f0_wr_addr_11))
+                (portRef CE (instanceRef f0_wr_addr_12))
+                (portRef CE (instanceRef f0_wr_addr_0))
+                (portRef O (instanceRef f0_write11))
+                (portRef CE (instanceRef f0_Result_0_2_FRB_renamed_376))
+                (portRef CE (instanceRef f0_Result_1_2_FRB_renamed_377))
+                (portRef CE (instanceRef f0_Result_2_2_FRB_renamed_378))
+                (portRef CE (instanceRef f0_Result_3_2_FRB_renamed_379))
+                (portRef CE (instanceRef f0_Result_4_2_FRB_renamed_380))
+                (portRef CE (instanceRef f0_Result_5_2_FRB_renamed_381))
+                (portRef CE (instanceRef f0_Result_6_2_FRB_renamed_382))
+                (portRef CE (instanceRef f0_Result_7_2_FRB_renamed_383))
+                (portRef CE (instanceRef f0_Result_8_2_FRB_renamed_384))
+                (portRef CE (instanceRef f0_Result_9_2_FRB_renamed_385))
+                (portRef CE (instanceRef f0_Result_10_2_FRB_renamed_386))
+                (portRef CE (instanceRef f0_Result_11_2_FRB_renamed_387))
+                (portRef CE (instanceRef f0_Result_12_2_FRB_renamed_388))
+                (portRef (member WEAWEL 1) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member WEAWEL 0) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram1))
+                (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram1))
+                (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram1))
+                (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_wr_addr_0_ "f0/wr_addr<0>")
+              (joined
+                (portRef Q (instanceRef f0_wr_addr_0))
+                (portRef I1 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef I0 (instanceRef f0_Mcompar_becoming_full_lut_0__))
+                (portRef (member ADDRAWRADDR 12) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_wr_addr_1_ "f0/wr_addr<1>")
+              (joined
+                (portRef Q (instanceRef f0_wr_addr_1))
+                (portRef I3 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef I2 (instanceRef f0_Mcompar_becoming_full_lut_0__))
+                (portRef (member ADDRAWRADDR 11) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_wr_addr_2_ "f0/wr_addr<2>")
+              (joined
+                (portRef Q (instanceRef f0_wr_addr_2))
+                (portRef I5 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef I4 (instanceRef f0_Mcompar_becoming_full_lut_0__))
+                (portRef (member ADDRAWRADDR 10) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_wr_addr_3_ "f0/wr_addr<3>")
+              (joined
+                (portRef Q (instanceRef f0_wr_addr_3))
+                (portRef I1 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef I0 (instanceRef f0_Mcompar_becoming_full_lut_1__))
+                (portRef (member ADDRAWRADDR 9) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_wr_addr_4_ "f0/wr_addr<4>")
+              (joined
+                (portRef Q (instanceRef f0_wr_addr_4))
+                (portRef I3 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef I2 (instanceRef f0_Mcompar_becoming_full_lut_1__))
+                (portRef (member ADDRAWRADDR 8) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_wr_addr_5_ "f0/wr_addr<5>")
+              (joined
+                (portRef Q (instanceRef f0_wr_addr_5))
+                (portRef I5 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef I4 (instanceRef f0_Mcompar_becoming_full_lut_1__))
+                (portRef (member ADDRAWRADDR 7) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_wr_addr_6_ "f0/wr_addr<6>")
+              (joined
+                (portRef Q (instanceRef f0_wr_addr_6))
+                (portRef I1 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef I0 (instanceRef f0_Mcompar_becoming_full_lut_2__))
+                (portRef (member ADDRAWRADDR 6) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_wr_addr_7_ "f0/wr_addr<7>")
+              (joined
+                (portRef Q (instanceRef f0_wr_addr_7))
+                (portRef I3 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef I2 (instanceRef f0_Mcompar_becoming_full_lut_2__))
+                (portRef (member ADDRAWRADDR 5) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_wr_addr_8_ "f0/wr_addr<8>")
+              (joined
+                (portRef Q (instanceRef f0_wr_addr_8))
+                (portRef I5 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef I4 (instanceRef f0_Mcompar_becoming_full_lut_2__))
+                (portRef (member ADDRAWRADDR 4) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_wr_addr_9_ "f0/wr_addr<9>")
+              (joined
+                (portRef Q (instanceRef f0_wr_addr_9))
+                (portRef I1 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef I0 (instanceRef f0_Mcompar_becoming_full_lut_3__))
+                (portRef (member ADDRAWRADDR 3) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_wr_addr_10_ "f0/wr_addr<10>")
+              (joined
+                (portRef Q (instanceRef f0_wr_addr_10))
+                (portRef I3 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef I2 (instanceRef f0_Mcompar_becoming_full_lut_3__))
+                (portRef (member ADDRAWRADDR 2) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_wr_addr_11_ "f0/wr_addr<11>")
+              (joined
+                (portRef Q (instanceRef f0_wr_addr_11))
+                (portRef I5 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef I4 (instanceRef f0_Mcompar_becoming_full_lut_3__))
+                (portRef (member ADDRAWRADDR 1) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_wr_addr_12_ "f0/wr_addr<12>")
+              (joined
+                (portRef Q (instanceRef f0_wr_addr_12))
+                (portRef I1 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__))
+                (portRef I0 (instanceRef f0_Mcompar_becoming_full_lut_4__))
+                (portRef (member ADDRAWRADDR 0) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_rd_addr_0_ "f0/rd_addr<0>")
+              (joined
+                (portRef Q (instanceRef f0_rd_addr_0))
+                (portRef I0 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef (member ADDRBRDADDR 12) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_rd_addr_1_ "f0/rd_addr<1>")
+              (joined
+                (portRef Q (instanceRef f0_rd_addr_1))
+                (portRef I2 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef (member ADDRBRDADDR 11) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_rd_addr_2_ "f0/rd_addr<2>")
+              (joined
+                (portRef Q (instanceRef f0_rd_addr_2))
+                (portRef I4 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__))
+                (portRef (member ADDRBRDADDR 10) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_rd_addr_3_ "f0/rd_addr<3>")
+              (joined
+                (portRef Q (instanceRef f0_rd_addr_3))
+                (portRef I0 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef (member ADDRBRDADDR 9) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_rd_addr_4_ "f0/rd_addr<4>")
+              (joined
+                (portRef Q (instanceRef f0_rd_addr_4))
+                (portRef I2 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef (member ADDRBRDADDR 8) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_rd_addr_5_ "f0/rd_addr<5>")
+              (joined
+                (portRef Q (instanceRef f0_rd_addr_5))
+                (portRef I4 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__))
+                (portRef (member ADDRBRDADDR 7) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_rd_addr_6_ "f0/rd_addr<6>")
+              (joined
+                (portRef Q (instanceRef f0_rd_addr_6))
+                (portRef I0 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef (member ADDRBRDADDR 6) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_rd_addr_7_ "f0/rd_addr<7>")
+              (joined
+                (portRef Q (instanceRef f0_rd_addr_7))
+                (portRef I2 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef (member ADDRBRDADDR 5) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_rd_addr_8_ "f0/rd_addr<8>")
+              (joined
+                (portRef Q (instanceRef f0_rd_addr_8))
+                (portRef I4 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__))
+                (portRef (member ADDRBRDADDR 4) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_rd_addr_9_ "f0/rd_addr<9>")
+              (joined
+                (portRef Q (instanceRef f0_rd_addr_9))
+                (portRef I0 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef (member ADDRBRDADDR 3) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_rd_addr_10_ "f0/rd_addr<10>")
+              (joined
+                (portRef Q (instanceRef f0_rd_addr_10))
+                (portRef I2 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef (member ADDRBRDADDR 2) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_rd_addr_11_ "f0/rd_addr<11>")
+              (joined
+                (portRef Q (instanceRef f0_rd_addr_11))
+                (portRef I4 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__))
+                (portRef (member ADDRBRDADDR 1) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_rd_addr_12_ "f0/rd_addr<12>")
+              (joined
+                (portRef Q (instanceRef f0_rd_addr_12))
+                (portRef I0 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__))
+                (portRef (member ADDRBRDADDR 0) (instanceRef f0_ram_Mram_ram33))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram31))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram30))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram32))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram28))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram27))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram29))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram25))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram24))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram26))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram22))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram21))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram23))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram19))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram18))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram20))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram16))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram15))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram17))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram14))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram13))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram12))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram11))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram9))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram8))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram10))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram6))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram5))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram7))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram3))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram2))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram4))
+                (portRef (member ADDRB 0) (instanceRef f0_ram_Mram_ram1))
+              )
+            )
+            (net (rename f0_full_reg "f0/full_reg")
+              (joined
+                (portRef I1 (instanceRef f0_write11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0))
+                (portRef Q (instanceRef f0_full_reg_renamed_117))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_renamed_418))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set_renamed_420))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+                (portRef D (instanceRef slave_fifo32_debug1_16_BRB0_renamed_497))
+                (portRef I4 (instanceRef f0_read_state_FSM_FFd2_In1))
+                (portRef I4 (instanceRef f0_full_reg_glue_set_renamed_538))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_renamed_53))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111))
+              )
+            )
+            (net (rename f0_read_state_FSM_FFd1 "f0/read_state_FSM_FFd1")
+              (joined
+                (portRef Q (instanceRef f0_read_state_FSM_FFd1_renamed_31))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111))
+                (portRef I1 (instanceRef f0__n0161_inv1_lut_renamed_509))
+                (portRef I1 (instanceRef f0__n0161_inv1_lut1_renamed_510))
+                (portRef I0 (instanceRef f0_GND_14_o_read_OR_37_o1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_write1))
+                (portRef I0 (instanceRef f0_read_state_FSM_FFd1_In111))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_renamed_526))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_renamed_531))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_renamed_536))
+                (portRef I0 (instanceRef f0_read_state_FSM_FFd2_In1))
+                (portRef I3 (instanceRef f0_full_reg_glue_set_renamed_538))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_inv")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1_renamed_502))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1))
+              )
+            )
+            (net N0
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_renamed_33))
+              )
+            )
+            (net N2
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read_renamed_34))
+              )
+            )
+            (net N4
+              (joined
+                (portRef O (instanceRef slave_fifo32__n0258_inv_SW0))
+                (portRef I2 (instanceRef slave_fifo32_wr_one_rstpot_renamed_512))
+              )
+            )
+            (net N6
+              (joined
+                (portRef O (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0))
+                (portRef I5 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1))
+              )
+            )
+            (net N8
+              (joined
+                (portRef O (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0))
+                (portRef I5 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1))
+                (portRef I3 (instanceRef slave_fifo32_state_FSM_FFd1_In2_renamed_36))
+              )
+            )
+            (net N10
+              (joined
+                (portRef O (instanceRef slave_fifo32__n0279_inv_SW0))
+                (portRef I3 (instanceRef slave_fifo32__n0279_inv_renamed_35))
+              )
+            )
+            (net (rename slave_fifo32_state_FSM_FFd1_In3 "slave_fifo32/state_FSM_FFd1-In3")
+              (joined
+                (portRef O (instanceRef slave_fifo32_state_FSM_FFd1_In3_renamed_543))
+                (portRef I0 (instanceRef slave_fifo32_state_FSM_FFd1_In4))
+              )
+            )
+            (net (rename slave_fifo32_state_FSM_FFd2_In1 "slave_fifo32/state_FSM_FFd2-In1")
+              (joined
+                (portRef O (instanceRef slave_fifo32_state_FSM_FFd2_In1_renamed_37))
+                (portRef I2 (instanceRef slave_fifo32_state_FSM_FFd2_In2_renamed_38))
+              )
+            )
+            (net (rename slave_fifo32_state_FSM_FFd2_In2 "slave_fifo32/state_FSM_FFd2-In2")
+              (joined
+                (portRef O (instanceRef slave_fifo32_state_FSM_FFd2_In2_renamed_38))
+                (portRef I2 (instanceRef slave_fifo32_state_FSM_FFd2_In3))
+              )
+            )
+            (net N14
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_renamed_525))
+              )
+            )
+            (net N18
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_renamed_526))
+              )
+            )
+            (net N22
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0))
+              )
+            )
+            (net N24
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1))
+              )
+            )
+            (net N26
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1))
+              )
+            )
+            (net N30
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0))
+              )
+            )
+            (net N34
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1))
+              )
+            )
+            (net N38
+              (joined
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_renamed_516))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set_renamed_426))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_renamed_527))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01217_SW0))
+              )
+            )
+            (net N40
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set_renamed_419))
+              )
+            )
+            (net N42
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_renamed_39))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01212")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212_renamed_40))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01214_renamed_41))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01213")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213_renamed_429))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01214_renamed_41))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01214 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01214")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01214_renamed_41))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01219))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01215")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215_renamed_517))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01219))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01216 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01216")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01216_renamed_42))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01219))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01217")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217_renamed_427))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01219))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01218")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218_renamed_519))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01219))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012112")
+              (joined
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114_renamed_44))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111_renamed_424))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012113")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114_renamed_44))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112_renamed_500))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012114")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113_renamed_43))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114_renamed_44))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB_renamed_459))
+              )
+            )
+            (net N50
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_481))
+              )
+            )
+            (net N52
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1))
+              )
+            )
+            (net N54
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_renamed_45))
+              )
+            )
+            (net N56
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_renamed_46))
+              )
+            )
+            (net N58
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+              )
+            )
+            (net N60
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int1")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_47))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int11")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14_renamed_48))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int14")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv4")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4_renamed_49))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot_renamed_433))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+              )
+            )
+            (net N62
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In3")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31_renamed_50))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In31")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32_renamed_51))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In32")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In1")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In11))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In11")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12_renamed_52))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In12")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_read1))
+                (portRef rd_en (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net N64
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set_renamed_420))
+              )
+            )
+            (net N66
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_renamed_53))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214_renamed_55))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01213")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213_renamed_430))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214_renamed_55))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01214")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214_renamed_55))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01215")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215_renamed_518))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01216")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216_renamed_56))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01217")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217_renamed_428))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01218")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218_renamed_520))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012112")
+              (joined
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111_renamed_425))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012113")
+              (joined
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112_renamed_501))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012114")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113_renamed_57))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB")
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB_renamed_460))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_renamed_423))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01217")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217_renamed_524))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218")
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219_renamed_59))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_renamed_431))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01219")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219_renamed_59))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0))
+              )
+            )
+            (net N76
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0))
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_487))
+              )
+            )
+            (net N78
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1))
+              )
+            )
+            (net N80
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_renamed_60))
+              )
+            )
+            (net N82
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_renamed_61))
+              )
+            )
+            (net N84
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+              )
+            )
+            (net N86
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int1")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_62))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int11")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int12")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv2")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2_renamed_415))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv5")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5_renamed_64))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211")
+              (joined
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+              )
+            )
+            (net N88
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1))
+                (portRef I2
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In3")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In31")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In32")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34))
+              )
+            )
+            (net N90
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In1")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11_renamed_67))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In11")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12_renamed_68))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In12")
+              (joined
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1))
+                (portRef rd_en (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In1")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13))
+              )
+            )
+            (net cat_miso
+              (joined
+                (portRef cat_miso)
+                (portRef I (instanceRef cat_miso_IBUF_renamed_69))
+              )
+            )
+            (net fx3_ce
+              (joined
+                (portRef fx3_ce)
+                (portRef I (instanceRef fx3_ce_IBUF_renamed_70))
+              )
+            )
+            (net fx3_mosi
+              (joined
+                (portRef fx3_mosi)
+                (portRef I (instanceRef fx3_mosi_IBUF_renamed_71))
+              )
+            )
+            (net fx3_sclk
+              (joined
+                (portRef fx3_sclk)
+                (portRef I (instanceRef fx3_sclk_IBUF_renamed_72))
+              )
+            )
+            (net GPIF_CTL4
+              (joined
+                (portRef GPIF_CTL4)
+                (portRef I (instanceRef GPIF_CTL4_IBUF_renamed_73))
+              )
+            )
+            (net GPIF_CTL5
+              (joined
+                (portRef GPIF_CTL5)
+                (portRef I (instanceRef GPIF_CTL5_IBUF_renamed_74))
+              )
+            )
+            (net GPIF_CTL9
+              (joined
+                (portRef GPIF_CTL9)
+                (portRef I (instanceRef GPIF_CTL9_IBUF_renamed_75))
+              )
+            )
+            (net N96
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_31))
+                (portRef O (instanceRef GPIF_D_31_IOBUF))
+              )
+            )
+            (net N97
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_30))
+                (portRef O (instanceRef GPIF_D_30_IOBUF))
+              )
+            )
+            (net N98
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_29))
+                (portRef O (instanceRef GPIF_D_29_IOBUF))
+              )
+            )
+            (net N99
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_28))
+                (portRef O (instanceRef GPIF_D_28_IOBUF))
+              )
+            )
+            (net N100
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_27))
+                (portRef O (instanceRef GPIF_D_27_IOBUF))
+              )
+            )
+            (net N101
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_26))
+                (portRef O (instanceRef GPIF_D_26_IOBUF))
+              )
+            )
+            (net N102
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_25))
+                (portRef O (instanceRef GPIF_D_25_IOBUF))
+              )
+            )
+            (net N103
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_24))
+                (portRef O (instanceRef GPIF_D_24_IOBUF))
+              )
+            )
+            (net N104
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_23))
+                (portRef O (instanceRef GPIF_D_23_IOBUF))
+              )
+            )
+            (net N105
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_22))
+                (portRef O (instanceRef GPIF_D_22_IOBUF))
+              )
+            )
+            (net N106
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_21))
+                (portRef O (instanceRef GPIF_D_21_IOBUF))
+              )
+            )
+            (net N107
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_20))
+                (portRef O (instanceRef GPIF_D_20_IOBUF))
+              )
+            )
+            (net N108
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_19))
+                (portRef O (instanceRef GPIF_D_19_IOBUF))
+              )
+            )
+            (net N109
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_18))
+                (portRef O (instanceRef GPIF_D_18_IOBUF))
+              )
+            )
+            (net N110
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_17))
+                (portRef O (instanceRef GPIF_D_17_IOBUF))
+              )
+            )
+            (net N111
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_16))
+                (portRef O (instanceRef GPIF_D_16_IOBUF))
+              )
+            )
+            (net N112
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_15))
+                (portRef O (instanceRef GPIF_D_15_IOBUF))
+              )
+            )
+            (net N113
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_14))
+                (portRef O (instanceRef GPIF_D_14_IOBUF))
+              )
+            )
+            (net N114
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_13))
+                (portRef O (instanceRef GPIF_D_13_IOBUF))
+              )
+            )
+            (net N115
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_12))
+                (portRef O (instanceRef GPIF_D_12_IOBUF))
+              )
+            )
+            (net N116
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_11))
+                (portRef O (instanceRef GPIF_D_11_IOBUF))
+              )
+            )
+            (net N117
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_10))
+                (portRef O (instanceRef GPIF_D_10_IOBUF))
+              )
+            )
+            (net N118
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_9))
+                (portRef O (instanceRef GPIF_D_9_IOBUF))
+              )
+            )
+            (net N119
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_8))
+                (portRef O (instanceRef GPIF_D_8_IOBUF))
+              )
+            )
+            (net N120
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_7))
+                (portRef O (instanceRef GPIF_D_7_IOBUF))
+              )
+            )
+            (net N121
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_6))
+                (portRef O (instanceRef GPIF_D_6_IOBUF))
+              )
+            )
+            (net N122
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_5))
+                (portRef O (instanceRef GPIF_D_5_IOBUF))
+              )
+            )
+            (net N123
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_4))
+                (portRef O (instanceRef GPIF_D_4_IOBUF))
+              )
+            )
+            (net N124
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_3))
+                (portRef O (instanceRef GPIF_D_3_IOBUF))
+              )
+            )
+            (net N125
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_2))
+                (portRef O (instanceRef GPIF_D_2_IOBUF))
+              )
+            )
+            (net N126
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_1))
+                (portRef O (instanceRef GPIF_D_1_IOBUF))
+              )
+            )
+            (net N127
+              (joined
+                (portRef D (instanceRef slave_fifo32_gpif_data_in_0))
+                (portRef O (instanceRef GPIF_D_0_IOBUF))
+              )
+            )
+            (net (rename codec_ctrl_in_3_ "codec_ctrl_in<3>")
+              (joined
+                (portRef (member codec_ctrl_in 0))
+                (portRef O (instanceRef codec_ctrl_in_3_OBUF))
+              )
+            )
+            (net (rename codec_ctrl_in_2_ "codec_ctrl_in<2>")
+              (joined
+                (portRef (member codec_ctrl_in 1))
+                (portRef O (instanceRef codec_ctrl_in_2_OBUF))
+              )
+            )
+            (net (rename codec_ctrl_in_1_ "codec_ctrl_in<1>")
+              (joined
+                (portRef (member codec_ctrl_in 2))
+                (portRef O (instanceRef codec_ctrl_in_1_OBUF))
+              )
+            )
+            (net (rename codec_ctrl_in_0_ "codec_ctrl_in<0>")
+              (joined
+                (portRef (member codec_ctrl_in 3))
+                (portRef O (instanceRef codec_ctrl_in_0_OBUF))
+              )
+            )
+            (net (rename tx_codec_d_11_ "tx_codec_d<11>")
+              (joined
+                (portRef (member tx_codec_d 0))
+                (portRef O (instanceRef tx_codec_d_11_OBUF_renamed_76))
+              )
+            )
+            (net (rename tx_codec_d_10_ "tx_codec_d<10>")
+              (joined
+                (portRef (member tx_codec_d 1))
+                (portRef O (instanceRef tx_codec_d_10_OBUF_renamed_77))
+              )
+            )
+            (net (rename tx_codec_d_9_ "tx_codec_d<9>")
+              (joined
+                (portRef (member tx_codec_d 2))
+                (portRef O (instanceRef tx_codec_d_9_OBUF_renamed_78))
+              )
+            )
+            (net (rename tx_codec_d_8_ "tx_codec_d<8>")
+              (joined
+                (portRef (member tx_codec_d 3))
+                (portRef O (instanceRef tx_codec_d_8_OBUF_renamed_79))
+              )
+            )
+            (net (rename tx_codec_d_7_ "tx_codec_d<7>")
+              (joined
+                (portRef (member tx_codec_d 4))
+                (portRef O (instanceRef tx_codec_d_7_OBUF_renamed_80))
+              )
+            )
+            (net (rename tx_codec_d_6_ "tx_codec_d<6>")
+              (joined
+                (portRef (member tx_codec_d 5))
+                (portRef O (instanceRef tx_codec_d_6_OBUF_renamed_81))
+              )
+            )
+            (net (rename tx_codec_d_5_ "tx_codec_d<5>")
+              (joined
+                (portRef (member tx_codec_d 6))
+                (portRef O (instanceRef tx_codec_d_5_OBUF_renamed_82))
+              )
+            )
+            (net (rename tx_codec_d_4_ "tx_codec_d<4>")
+              (joined
+                (portRef (member tx_codec_d 7))
+                (portRef O (instanceRef tx_codec_d_4_OBUF_renamed_83))
+              )
+            )
+            (net (rename tx_codec_d_3_ "tx_codec_d<3>")
+              (joined
+                (portRef (member tx_codec_d 8))
+                (portRef O (instanceRef tx_codec_d_3_OBUF_renamed_84))
+              )
+            )
+            (net (rename tx_codec_d_2_ "tx_codec_d<2>")
+              (joined
+                (portRef (member tx_codec_d 9))
+                (portRef O (instanceRef tx_codec_d_2_OBUF_renamed_85))
+              )
+            )
+            (net (rename tx_codec_d_1_ "tx_codec_d<1>")
+              (joined
+                (portRef (member tx_codec_d 10))
+                (portRef O (instanceRef tx_codec_d_1_OBUF_renamed_86))
+              )
+            )
+            (net (rename tx_codec_d_0_ "tx_codec_d<0>")
+              (joined
+                (portRef (member tx_codec_d 11))
+                (portRef O (instanceRef tx_codec_d_0_OBUF_renamed_87))
+              )
+            )
+            (net (rename debug_31_ "debug<31>")
+              (joined
+                (portRef (member debug 0))
+                (portRef O (instanceRef debug_31_OBUF))
+              )
+            )
+            (net (rename debug_30_ "debug<30>")
+              (joined
+                (portRef (member debug 1))
+                (portRef O (instanceRef debug_30_OBUF))
+              )
+            )
+            (net (rename debug_29_ "debug<29>")
+              (joined
+                (portRef (member debug 2))
+                (portRef O (instanceRef debug_29_OBUF))
+              )
+            )
+            (net (rename debug_28_ "debug<28>")
+              (joined
+                (portRef (member debug 3))
+                (portRef O (instanceRef debug_28_OBUF))
+              )
+            )
+            (net (rename debug_27_ "debug<27>")
+              (joined
+                (portRef (member debug 4))
+                (portRef O (instanceRef debug_27_OBUF))
+              )
+            )
+            (net (rename debug_26_ "debug<26>")
+              (joined
+                (portRef (member debug 5))
+                (portRef O (instanceRef debug_26_OBUF))
+              )
+            )
+            (net (rename debug_25_ "debug<25>")
+              (joined
+                (portRef (member debug 6))
+                (portRef O (instanceRef debug_25_OBUF))
+              )
+            )
+            (net (rename debug_24_ "debug<24>")
+              (joined
+                (portRef (member debug 7))
+                (portRef O (instanceRef debug_24_OBUF))
+              )
+            )
+            (net (rename debug_23_ "debug<23>")
+              (joined
+                (portRef (member debug 8))
+                (portRef O (instanceRef debug_23_OBUF))
+              )
+            )
+            (net (rename debug_22_ "debug<22>")
+              (joined
+                (portRef (member debug 9))
+                (portRef O (instanceRef debug_22_OBUF))
+              )
+            )
+            (net (rename debug_21_ "debug<21>")
+              (joined
+                (portRef (member debug 10))
+                (portRef O (instanceRef debug_21_OBUF))
+              )
+            )
+            (net (rename debug_20_ "debug<20>")
+              (joined
+                (portRef (member debug 11))
+                (portRef O (instanceRef debug_20_OBUF))
+              )
+            )
+            (net (rename debug_19_ "debug<19>")
+              (joined
+                (portRef (member debug 12))
+                (portRef O (instanceRef debug_19_OBUF))
+              )
+            )
+            (net (rename debug_18_ "debug<18>")
+              (joined
+                (portRef (member debug 13))
+                (portRef O (instanceRef debug_18_OBUF))
+              )
+            )
+            (net (rename debug_17_ "debug<17>")
+              (joined
+                (portRef (member debug 14))
+                (portRef O (instanceRef debug_17_OBUF))
+              )
+            )
+            (net (rename debug_16_ "debug<16>")
+              (joined
+                (portRef (member debug 15))
+                (portRef O (instanceRef debug_16_OBUF))
+              )
+            )
+            (net (rename debug_15_ "debug<15>")
+              (joined
+                (portRef (member debug 16))
+                (portRef O (instanceRef debug_15_OBUF))
+              )
+            )
+            (net (rename debug_14_ "debug<14>")
+              (joined
+                (portRef (member debug 17))
+                (portRef O (instanceRef debug_14_OBUF))
+              )
+            )
+            (net (rename debug_13_ "debug<13>")
+              (joined
+                (portRef (member debug 18))
+                (portRef O (instanceRef debug_13_OBUF))
+              )
+            )
+            (net (rename debug_12_ "debug<12>")
+              (joined
+                (portRef (member debug 19))
+                (portRef O (instanceRef debug_12_OBUF))
+              )
+            )
+            (net (rename debug_11_ "debug<11>")
+              (joined
+                (portRef (member debug 20))
+                (portRef O (instanceRef debug_11_OBUF))
+              )
+            )
+            (net (rename debug_10_ "debug<10>")
+              (joined
+                (portRef (member debug 21))
+                (portRef O (instanceRef debug_10_OBUF))
+              )
+            )
+            (net (rename debug_9_ "debug<9>")
+              (joined
+                (portRef (member debug 22))
+                (portRef O (instanceRef debug_9_OBUF))
+              )
+            )
+            (net (rename debug_8_ "debug<8>")
+              (joined
+                (portRef (member debug 23))
+                (portRef O (instanceRef debug_8_OBUF))
+              )
+            )
+            (net (rename debug_7_ "debug<7>")
+              (joined
+                (portRef (member debug 24))
+                (portRef O (instanceRef debug_7_OBUF))
+              )
+            )
+            (net (rename debug_6_ "debug<6>")
+              (joined
+                (portRef (member debug 25))
+                (portRef O (instanceRef debug_6_OBUF))
+              )
+            )
+            (net (rename debug_5_ "debug<5>")
+              (joined
+                (portRef (member debug 26))
+                (portRef O (instanceRef debug_5_OBUF))
+              )
+            )
+            (net (rename debug_4_ "debug<4>")
+              (joined
+                (portRef (member debug 27))
+                (portRef O (instanceRef debug_4_OBUF))
+              )
+            )
+            (net (rename debug_3_ "debug<3>")
+              (joined
+                (portRef (member debug 28))
+                (portRef O (instanceRef debug_3_OBUF))
+              )
+            )
+            (net (rename debug_2_ "debug<2>")
+              (joined
+                (portRef (member debug 29))
+                (portRef O (instanceRef debug_2_OBUF))
+              )
+            )
+            (net (rename debug_1_ "debug<1>")
+              (joined
+                (portRef (member debug 30))
+                (portRef O (instanceRef debug_1_OBUF))
+              )
+            )
+            (net (rename debug_0_ "debug<0>")
+              (joined
+                (portRef (member debug 31))
+                (portRef O (instanceRef debug_0_OBUF))
+              )
+            )
+            (net (rename debug_clk_1_ "debug_clk<1>")
+              (joined
+                (portRef (member debug_clk 0))
+                (portRef O (instanceRef debug_clk_1_OBUF_renamed_88))
+              )
+            )
+            (net (rename debug_clk_0_ "debug_clk<0>")
+              (joined
+                (portRef (member debug_clk 1))
+                (portRef O (instanceRef debug_clk_0_OBUF))
+              )
+            )
+            (net cat_ce
+              (joined
+                (portRef cat_ce)
+                (portRef O (instanceRef cat_ce_OBUF))
+              )
+            )
+            (net cat_mosi
+              (joined
+                (portRef cat_mosi)
+                (portRef O (instanceRef cat_mosi_OBUF_renamed_89))
+              )
+            )
+            (net cat_sclk
+              (joined
+                (portRef cat_sclk)
+                (portRef O (instanceRef cat_sclk_OBUF_renamed_90))
+              )
+            )
+            (net fx3_miso
+              (joined
+                (portRef fx3_miso)
+                (portRef O (instanceRef fx3_miso_OBUF_renamed_91))
+              )
+            )
+            (net pll_ce
+              (joined
+                (portRef pll_ce)
+                (portRef O (instanceRef pll_ce_OBUF))
+              )
+            )
+            (net pll_mosi
+              (joined
+                (portRef pll_mosi)
+                (portRef O (instanceRef pll_mosi_OBUF))
+              )
+            )
+            (net pll_sclk
+              (joined
+                (portRef pll_sclk)
+                (portRef O (instanceRef pll_sclk_OBUF))
+              )
+            )
+            (net codec_enable
+              (joined
+                (portRef codec_enable)
+                (portRef O (instanceRef codec_enable_OBUF))
+              )
+            )
+            (net codec_en_agc
+              (joined
+                (portRef codec_en_agc)
+                (portRef O (instanceRef codec_en_agc_OBUF))
+              )
+            )
+            (net codec_reset
+              (joined
+                (portRef codec_reset)
+                (portRef O (instanceRef codec_reset_OBUF))
+              )
+            )
+            (net codec_sync
+              (joined
+                (portRef codec_sync)
+                (portRef O (instanceRef codec_sync_OBUF))
+              )
+            )
+            (net codec_txrx
+              (joined
+                (portRef codec_txrx)
+                (portRef O (instanceRef codec_txrx_OBUF))
+              )
+            )
+            (net codec_fb_clk_p
+              (joined
+                (portRef codec_fb_clk_p)
+                (portRef O (instanceRef codec_fb_clk_p_OBUF_renamed_92))
+              )
+            )
+            (net tx_frame_p
+              (joined
+                (portRef tx_frame_p)
+                (portRef O (instanceRef tx_frame_p_OBUF_renamed_93))
+              )
+            )
+            (net IFCLK
+              (joined
+                (portRef IFCLK)
+                (portRef O (instanceRef IFCLK_OBUF_renamed_94))
+              )
+            )
+            (net FX3_EXTINT
+              (joined
+                (portRef FX3_EXTINT)
+                (portRef O (instanceRef FX3_EXTINT_OBUF))
+              )
+            )
+            (net GPIF_CTL0
+              (joined
+                (portRef GPIF_CTL0)
+                (portRef O (instanceRef GPIF_CTL0_OBUF))
+              )
+            )
+            (net GPIF_CTL1
+              (joined
+                (portRef GPIF_CTL1)
+                (portRef O (instanceRef GPIF_CTL1_OBUF))
+              )
+            )
+            (net GPIF_CTL2
+              (joined
+                (portRef GPIF_CTL2)
+                (portRef O (instanceRef GPIF_CTL2_OBUF))
+              )
+            )
+            (net GPIF_CTL3
+              (joined
+                (portRef GPIF_CTL3)
+                (portRef O (instanceRef GPIF_CTL3_OBUF))
+              )
+            )
+            (net GPIF_CTL7
+              (joined
+                (portRef GPIF_CTL7)
+                (portRef O (instanceRef GPIF_CTL7_OBUF))
+              )
+            )
+            (net GPIF_CTL11
+              (joined
+                (portRef GPIF_CTL11)
+                (portRef O (instanceRef GPIF_CTL11_OBUF))
+              )
+            )
+            (net GPIF_CTL12
+              (joined
+                (portRef GPIF_CTL12)
+                (portRef O (instanceRef GPIF_CTL12_OBUF))
+              )
+            )
+            (net gps_out_enable
+              (joined
+                (portRef gps_out_enable)
+                (portRef O (instanceRef gps_out_enable_OBUF))
+              )
+            )
+            (net gps_ref_enable
+              (joined
+                (portRef gps_ref_enable)
+                (portRef O (instanceRef gps_ref_enable_OBUF))
+              )
+            )
+            (net LED_RX1
+              (joined
+                (portRef LED_RX1)
+                (portRef O (instanceRef LED_RX1_OBUF))
+              )
+            )
+            (net LED_RX2
+              (joined
+                (portRef LED_RX2)
+                (portRef O (instanceRef LED_RX2_OBUF))
+              )
+            )
+            (net LED_TXRX1_RX
+              (joined
+                (portRef LED_TXRX1_RX)
+                (portRef O (instanceRef LED_TXRX1_RX_OBUF))
+              )
+            )
+            (net LED_TXRX1_TX
+              (joined
+                (portRef LED_TXRX1_TX)
+                (portRef O (instanceRef LED_TXRX1_TX_OBUF))
+              )
+            )
+            (net LED_TXRX2_RX
+              (joined
+                (portRef LED_TXRX2_RX)
+                (portRef O (instanceRef LED_TXRX2_RX_OBUF))
+              )
+            )
+            (net LED_TXRX2_TX
+              (joined
+                (portRef LED_TXRX2_TX)
+                (portRef O (instanceRef LED_TXRX2_TX_OBUF))
+              )
+            )
+            (net ext_ref_enable
+              (joined
+                (portRef ext_ref_enable)
+                (portRef O (instanceRef ext_ref_enable_OBUF))
+              )
+            )
+            (net pps_fpga_out_enable
+              (joined
+                (portRef pps_fpga_out_enable)
+                (portRef O (instanceRef pps_fpga_out_enable_OBUF))
+              )
+            )
+            (net SFDX1_RX
+              (joined
+                (portRef SFDX1_RX)
+                (portRef O (instanceRef SFDX1_RX_OBUF))
+              )
+            )
+            (net SFDX1_TX
+              (joined
+                (portRef SFDX1_TX)
+                (portRef O (instanceRef SFDX1_TX_OBUF))
+              )
+            )
+            (net SFDX2_RX
+              (joined
+                (portRef SFDX2_RX)
+                (portRef O (instanceRef SFDX2_RX_OBUF))
+              )
+            )
+            (net SFDX2_TX
+              (joined
+                (portRef SFDX2_TX)
+                (portRef O (instanceRef SFDX2_TX_OBUF))
+              )
+            )
+            (net SRX1_RX
+              (joined
+                (portRef SRX1_RX)
+                (portRef O (instanceRef SRX1_RX_OBUF))
+              )
+            )
+            (net SRX1_TX
+              (joined
+                (portRef SRX1_TX)
+                (portRef O (instanceRef SRX1_TX_OBUF))
+              )
+            )
+            (net SRX2_RX
+              (joined
+                (portRef SRX2_RX)
+                (portRef O (instanceRef SRX2_RX_OBUF))
+              )
+            )
+            (net SRX2_TX
+              (joined
+                (portRef SRX2_TX)
+                (portRef O (instanceRef SRX2_TX_OBUF))
+              )
+            )
+            (net tx_bandsel_a
+              (joined
+                (portRef tx_bandsel_a)
+                (portRef O (instanceRef tx_bandsel_a_OBUF))
+              )
+            )
+            (net tx_bandsel_b
+              (joined
+                (portRef tx_bandsel_b)
+                (portRef O (instanceRef tx_bandsel_b_OBUF))
+              )
+            )
+            (net tx_enable1
+              (joined
+                (portRef tx_enable1)
+                (portRef O (instanceRef tx_enable1_OBUF))
+              )
+            )
+            (net tx_enable2
+              (joined
+                (portRef tx_enable2)
+                (portRef O (instanceRef tx_enable2_OBUF))
+              )
+            )
+            (net rx_bandsel_a
+              (joined
+                (portRef rx_bandsel_a)
+                (portRef O (instanceRef rx_bandsel_a_OBUF))
+              )
+            )
+            (net rx_bandsel_b
+              (joined
+                (portRef rx_bandsel_b)
+                (portRef O (instanceRef rx_bandsel_b_OBUF))
+              )
+            )
+            (net rx_bandsel_c
+              (joined
+                (portRef rx_bandsel_c)
+                (portRef O (instanceRef rx_bandsel_c_OBUF_renamed_95))
+              )
+            )
+            (net (rename slave_fifo32_sloe_1 "slave_fifo32/sloe_1")
+              (joined
+                (portRef I (instanceRef GPIF_CTL2_OBUF))
+                (portRef Q (instanceRef slave_fifo32_sloe_1_renamed_259))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_renamed_96))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set_renamed_528))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_renamed_97))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set_renamed_529))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_renamed_98))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_renamed_530))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_renamed_99))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_renamed_535))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_renamed_100))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_renamed_531))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty_glue_rst")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_renamed_101))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_renamed_536))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_renamed_102))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set_renamed_523))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/full_reg_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_renamed_103))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set_renamed_426))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_renamed_104))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_renamed_417))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_renamed_105))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set_renamed_419))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/state_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_renamed_106))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_glue_set_renamed_513))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_renamed_107))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set_renamed_434))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_renamed_108))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_renamed_109))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set_renamed_432))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_renamed_110))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_renamed_418))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_renamed_111))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set_renamed_420))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_renamed_112))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set_renamed_514))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_renamed_113))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set_renamed_435))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/full_reg_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_renamed_114))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set_renamed_421))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump_glue_set")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_renamed_115))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set_renamed_422))
+              )
+            )
+            (net (rename f1_full_reg_glue_set "f1/full_reg_glue_set")
+              (joined
+                (portRef D (instanceRef f1_full_reg_renamed_116))
+                (portRef O (instanceRef f1_full_reg_glue_set_renamed_537))
+              )
+            )
+            (net (rename f0_full_reg_glue_set "f0/full_reg_glue_set")
+              (joined
+                (portRef D (instanceRef f0_full_reg_renamed_117))
+                (portRef O (instanceRef f0_full_reg_glue_set_renamed_538))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<1>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__rt_renamed_118))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<0>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0__rt_renamed_119))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<11>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__rt_renamed_120))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_11__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<10>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10__rt_renamed_121))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_10__))
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<7>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__rt_renamed_180))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt_renamed_181))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_6__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__rt_renamed_182))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_5__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt_renamed_183))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt_renamed_184))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt_renamed_185))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt_renamed_186))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt_renamed_187))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt_renamed_188))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<6>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__rt_renamed_189))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_6__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt_renamed_190))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt_renamed_191))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt_renamed_192))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_3__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<2>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__rt_renamed_193))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_2__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt_renamed_194))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_1__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt_renamed_195))
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_0__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_cy_11__rt "f1/Mcount_rd_addr_cy<11>_rt")
+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_11__rt_renamed_196))
+                (portRef S (instanceRef f1_Mcount_rd_addr_cy_11__))
+                (portRef LI (instanceRef f1_Mcount_rd_addr_xor_11__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_cy_10__rt "f1/Mcount_rd_addr_cy<10>_rt")
+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_10__rt_renamed_197))
+                (portRef S (instanceRef f1_Mcount_rd_addr_cy_10__))
+                (portRef LI (instanceRef f1_Mcount_rd_addr_xor_10__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_cy_9__rt "f1/Mcount_rd_addr_cy<9>_rt")
+              (joined
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+                (portRef S (instanceRef f1_Mcount_rd_addr_cy_9__))
+                (portRef LI (instanceRef f1_Mcount_rd_addr_xor_9__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_cy_8__rt "f1/Mcount_rd_addr_cy<8>_rt")
+              (joined
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+                (portRef S (instanceRef f1_Mcount_rd_addr_cy_8__))
+                (portRef LI (instanceRef f1_Mcount_rd_addr_xor_8__))
+              )
+            )
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+              (joined
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+                (portRef S (instanceRef f1_Mcount_rd_addr_cy_7__))
+                (portRef LI (instanceRef f1_Mcount_rd_addr_xor_7__))
+              )
+            )
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+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_6__rt_renamed_201))
+                (portRef S (instanceRef f1_Mcount_rd_addr_cy_6__))
+                (portRef LI (instanceRef f1_Mcount_rd_addr_xor_6__))
+              )
+            )
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+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_5__rt_renamed_202))
+                (portRef S (instanceRef f1_Mcount_rd_addr_cy_5__))
+                (portRef LI (instanceRef f1_Mcount_rd_addr_xor_5__))
+              )
+            )
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+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_4__rt_renamed_203))
+                (portRef S (instanceRef f1_Mcount_rd_addr_cy_4__))
+                (portRef LI (instanceRef f1_Mcount_rd_addr_xor_4__))
+              )
+            )
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+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_3__rt_renamed_204))
+                (portRef S (instanceRef f1_Mcount_rd_addr_cy_3__))
+                (portRef LI (instanceRef f1_Mcount_rd_addr_xor_3__))
+              )
+            )
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+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_2__rt_renamed_205))
+                (portRef S (instanceRef f1_Mcount_rd_addr_cy_2__))
+                (portRef LI (instanceRef f1_Mcount_rd_addr_xor_2__))
+              )
+            )
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+              (joined
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+                (portRef S (instanceRef f1_Mcount_rd_addr_cy_1__))
+                (portRef LI (instanceRef f1_Mcount_rd_addr_xor_1__))
+              )
+            )
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+              (joined
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+                (portRef S (instanceRef f1_Mcount_wr_addr_cy_11__))
+                (portRef LI (instanceRef f1_Mcount_wr_addr_xor_11__))
+              )
+            )
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+              (joined
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+                (portRef S (instanceRef f1_Mcount_wr_addr_cy_10__))
+                (portRef LI (instanceRef f1_Mcount_wr_addr_xor_10__))
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+              (joined
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+              (joined
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+                (portRef LI (instanceRef f1_Mcount_wr_addr_xor_8__))
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+              (joined
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+                (portRef S (instanceRef f1_Mcount_wr_addr_cy_6__))
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+                (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_1__))
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+                (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_0__))
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+                (portRef S (instanceRef f0_Mcount_wr_addr_cy_1__))
+                (portRef LI (instanceRef f0_Mcount_wr_addr_xor_1__))
+              )
+            )
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+              (joined
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+                (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_1__))
+                (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_1__))
+              )
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+            (net (rename f0_Msub_dont_write_past_me_cy_0__rt "f0/Msub_dont_write_past_me_cy<0>_rt")
+              (joined
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+                (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_0__))
+                (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_0__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<12>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12__rt_renamed_244))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_12__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<12>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_12__rt_renamed_245))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_12__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>_rt")
+              (joined
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+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>_rt")
+              (joined
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+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<8>_rt")
+              (joined
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+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<8>_rt")
+              (joined
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+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<8>_rt")
+              (joined
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+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<8>_rt")
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__rt_renamed_251))
+                (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__))
+              )
+            )
+            (net (rename f1_Mcount_rd_addr_xor_12__rt "f1/Mcount_rd_addr_xor<12>_rt")
+              (joined
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+                (portRef LI (instanceRef f1_Mcount_rd_addr_xor_12__))
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+            )
+            (net (rename f1_Mcount_wr_addr_xor_12__rt "f1/Mcount_wr_addr_xor<12>_rt")
+              (joined
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+                (portRef LI (instanceRef f1_Mcount_wr_addr_xor_12__))
+              )
+            )
+            (net (rename f0_Mcount_rd_addr_xor_12__rt "f0/Mcount_rd_addr_xor<12>_rt")
+              (joined
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+                (portRef LI (instanceRef f0_Mcount_rd_addr_xor_12__))
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+            )
+            (net (rename f0_Mcount_wr_addr_xor_12__rt "f0/Mcount_wr_addr_xor<12>_rt")
+              (joined
+                (portRef O (instanceRef f0_Mcount_wr_addr_xor_12__rt_renamed_255))
+                (portRef LI (instanceRef f0_Mcount_wr_addr_xor_12__))
+              )
+            )
+            (net (rename slave_fifo32_wr_one_rstpot "slave_fifo32/wr_one_rstpot")
+              (joined
+                (portRef D (instanceRef slave_fifo32_wr_one_renamed_256))
+                (portRef O (instanceRef slave_fifo32_wr_one_rstpot_renamed_512))
+              )
+            )
+            (net (rename slave_fifo32_slrd_rstpot "slave_fifo32/slrd_rstpot")
+              (joined
+                (portRef D (instanceRef slave_fifo32_slrd_renamed_257))
+                (portRef O (instanceRef slave_fifo32_slrd_rstpot_renamed_515))
+                (portRef D (instanceRef slave_fifo32_slrd_1_renamed_550))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot")
+              (joined
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+              )
+            )
+            (net (rename slave_fifo32_sloe_1_rstpot "slave_fifo32/sloe_1_rstpot")
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+              )
+            )
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+              )
+            )
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+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2__))
+              )
+            )
+            (net N237
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB_renamed_331))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_3__))
+              )
+            )
+            (net N238
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr4_FRB_renamed_332))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4__))
+              )
+            )
+            (net N239
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr5_FRB_renamed_333))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_5__))
+              )
+            )
+            (net N240
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB_renamed_334))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_6__))
+              )
+            )
+            (net N241
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr7_FRB_renamed_335))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7__))
+              )
+            )
+            (net N242
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__))
+              )
+            )
+            (net N243
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB_renamed_336))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__))
+              )
+            )
+            (net N244
+              (joined
+                (portRef D (instanceRef f1_Result_0_2_FRB_renamed_337))
+                (portRef O (instanceRef f1_Mcount_wr_addr_xor_0__))
+              )
+            )
+            (net N245
+              (joined
+                (portRef D (instanceRef f1_Result_1_2_FRB_renamed_338))
+                (portRef O (instanceRef f1_Mcount_wr_addr_xor_1__))
+              )
+            )
+            (net N246
+              (joined
+                (portRef D (instanceRef f1_Result_2_2_FRB_renamed_339))
+                (portRef O (instanceRef f1_Mcount_wr_addr_xor_2__))
+              )
+            )
+            (net N247
+              (joined
+                (portRef D (instanceRef f1_Result_3_2_FRB_renamed_340))
+                (portRef O (instanceRef f1_Mcount_wr_addr_xor_3__))
+              )
+            )
+            (net N248
+              (joined
+                (portRef D (instanceRef f1_Result_4_2_FRB_renamed_341))
+                (portRef O (instanceRef f1_Mcount_wr_addr_xor_4__))
+              )
+            )
+            (net N249
+              (joined
+                (portRef D (instanceRef f1_Result_5_2_FRB_renamed_342))
+                (portRef O (instanceRef f1_Mcount_wr_addr_xor_5__))
+              )
+            )
+            (net N250
+              (joined
+                (portRef D (instanceRef f1_Result_6_2_FRB_renamed_343))
+                (portRef O (instanceRef f1_Mcount_wr_addr_xor_6__))
+              )
+            )
+            (net N251
+              (joined
+                (portRef D (instanceRef f1_Result_7_2_FRB_renamed_344))
+                (portRef O (instanceRef f1_Mcount_wr_addr_xor_7__))
+              )
+            )
+            (net N252
+              (joined
+                (portRef D (instanceRef f1_Result_8_2_FRB_renamed_345))
+                (portRef O (instanceRef f1_Mcount_wr_addr_xor_8__))
+              )
+            )
+            (net N253
+              (joined
+                (portRef D (instanceRef f1_Result_9_2_FRB_renamed_346))
+                (portRef O (instanceRef f1_Mcount_wr_addr_xor_9__))
+              )
+            )
+            (net N254
+              (joined
+                (portRef D (instanceRef f1_Result_10_2_FRB_renamed_347))
+                (portRef O (instanceRef f1_Mcount_wr_addr_xor_10__))
+              )
+            )
+            (net N255
+              (joined
+                (portRef D (instanceRef f1_Result_11_2_FRB_renamed_348))
+                (portRef O (instanceRef f1_Mcount_wr_addr_xor_11__))
+              )
+            )
+            (net N256
+              (joined
+                (portRef O (instanceRef f1_Mcount_wr_addr_cy_11__))
+                (portRef CI (instanceRef f1_Mcount_wr_addr_xor_12__))
+              )
+            )
+            (net N257
+              (joined
+                (portRef D (instanceRef f1_Result_12_2_FRB_renamed_349))
+                (portRef O (instanceRef f1_Mcount_wr_addr_xor_12__))
+              )
+            )
+            (net N258
+              (joined
+                (portRef D (instanceRef f1_Result_0_1_FRB_renamed_350))
+                (portRef O (instanceRef f1_Mcount_rd_addr_xor_0__))
+              )
+            )
+            (net N259
+              (joined
+                (portRef D (instanceRef f1_Result_1_1_FRB_renamed_351))
+                (portRef O (instanceRef f1_Mcount_rd_addr_xor_1__))
+              )
+            )
+            (net N260
+              (joined
+                (portRef D (instanceRef f1_Result_2_1_FRB_renamed_352))
+                (portRef O (instanceRef f1_Mcount_rd_addr_xor_2__))
+              )
+            )
+            (net N261
+              (joined
+                (portRef D (instanceRef f1_Result_3_1_FRB_renamed_353))
+                (portRef O (instanceRef f1_Mcount_rd_addr_xor_3__))
+              )
+            )
+            (net N262
+              (joined
+                (portRef D (instanceRef f1_Result_4_1_FRB_renamed_354))
+                (portRef O (instanceRef f1_Mcount_rd_addr_xor_4__))
+              )
+            )
+            (net N263
+              (joined
+                (portRef D (instanceRef f1_Result_5_1_FRB_renamed_355))
+                (portRef O (instanceRef f1_Mcount_rd_addr_xor_5__))
+              )
+            )
+            (net N264
+              (joined
+                (portRef D (instanceRef f1_Result_6_1_FRB_renamed_356))
+                (portRef O (instanceRef f1_Mcount_rd_addr_xor_6__))
+              )
+            )
+            (net N265
+              (joined
+                (portRef D (instanceRef f1_Result_7_1_FRB_renamed_357))
+                (portRef O (instanceRef f1_Mcount_rd_addr_xor_7__))
+              )
+            )
+            (net N266
+              (joined
+                (portRef D (instanceRef f1_Result_8_1_FRB_renamed_358))
+                (portRef O (instanceRef f1_Mcount_rd_addr_xor_8__))
+              )
+            )
+            (net N267
+              (joined
+                (portRef D (instanceRef f1_Result_9_1_FRB_renamed_359))
+                (portRef O (instanceRef f1_Mcount_rd_addr_xor_9__))
+              )
+            )
+            (net N268
+              (joined
+                (portRef D (instanceRef f1_Result_10_1_FRB_renamed_360))
+                (portRef O (instanceRef f1_Mcount_rd_addr_xor_10__))
+              )
+            )
+            (net N269
+              (joined
+                (portRef D (instanceRef f1_Result_11_1_FRB_renamed_361))
+                (portRef O (instanceRef f1_Mcount_rd_addr_xor_11__))
+              )
+            )
+            (net N270
+              (joined
+                (portRef O (instanceRef f1_Mcount_rd_addr_cy_11__))
+                (portRef CI (instanceRef f1_Mcount_rd_addr_xor_12__))
+              )
+            )
+            (net N271
+              (joined
+                (portRef D (instanceRef f1_Result_12_1_FRB_renamed_362))
+                (portRef O (instanceRef f1_Mcount_rd_addr_xor_12__))
+              )
+            )
+            (net N272
+              (joined
+                (portRef D (instanceRef f1_dont_write_past_me_0__FRB_renamed_363))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_xor_0__))
+              )
+            )
+            (net N273
+              (joined
+                (portRef D (instanceRef f1_dont_write_past_me_1__FRB_renamed_364))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_xor_1__))
+              )
+            )
+            (net N274
+              (joined
+                (portRef D (instanceRef f1_dont_write_past_me_2__FRB_renamed_365))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_xor_2__))
+              )
+            )
+            (net N275
+              (joined
+                (portRef D (instanceRef f1_dont_write_past_me_3__FRB_renamed_366))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_xor_3__))
+              )
+            )
+            (net N276
+              (joined
+                (portRef D (instanceRef f1_dont_write_past_me_4__FRB_renamed_367))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_xor_4__))
+              )
+            )
+            (net N277
+              (joined
+                (portRef D (instanceRef f1_dont_write_past_me_5__FRB_renamed_368))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_xor_5__))
+              )
+            )
+            (net N278
+              (joined
+                (portRef D (instanceRef f1_dont_write_past_me_6__FRB_renamed_369))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_xor_6__))
+              )
+            )
+            (net N279
+              (joined
+                (portRef D (instanceRef f1_dont_write_past_me_7__FRB_renamed_370))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_xor_7__))
+              )
+            )
+            (net N280
+              (joined
+                (portRef D (instanceRef f1_dont_write_past_me_8__FRB_renamed_371))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_xor_8__))
+              )
+            )
+            (net N281
+              (joined
+                (portRef D (instanceRef f1_dont_write_past_me_9__FRB_renamed_372))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_xor_9__))
+              )
+            )
+            (net N282
+              (joined
+                (portRef D (instanceRef f1_dont_write_past_me_10__FRB_renamed_373))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_xor_10__))
+              )
+            )
+            (net N283
+              (joined
+                (portRef D (instanceRef f1_dont_write_past_me_11__FRB_renamed_374))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_xor_11__))
+              )
+            )
+            (net N284
+              (joined
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_11__))
+                (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_12__))
+              )
+            )
+            (net N285
+              (joined
+                (portRef D (instanceRef f1_dont_write_past_me_12__FRB_renamed_375))
+                (portRef O (instanceRef f1_Msub_dont_write_past_me_xor_12__))
+              )
+            )
+            (net N286
+              (joined
+                (portRef D (instanceRef f0_Result_0_2_FRB_renamed_376))
+                (portRef O (instanceRef f0_Mcount_wr_addr_xor_0__))
+              )
+            )
+            (net N287
+              (joined
+                (portRef D (instanceRef f0_Result_1_2_FRB_renamed_377))
+                (portRef O (instanceRef f0_Mcount_wr_addr_xor_1__))
+              )
+            )
+            (net N288
+              (joined
+                (portRef D (instanceRef f0_Result_2_2_FRB_renamed_378))
+                (portRef O (instanceRef f0_Mcount_wr_addr_xor_2__))
+              )
+            )
+            (net N289
+              (joined
+                (portRef D (instanceRef f0_Result_3_2_FRB_renamed_379))
+                (portRef O (instanceRef f0_Mcount_wr_addr_xor_3__))
+              )
+            )
+            (net N290
+              (joined
+                (portRef D (instanceRef f0_Result_4_2_FRB_renamed_380))
+                (portRef O (instanceRef f0_Mcount_wr_addr_xor_4__))
+              )
+            )
+            (net N291
+              (joined
+                (portRef D (instanceRef f0_Result_5_2_FRB_renamed_381))
+                (portRef O (instanceRef f0_Mcount_wr_addr_xor_5__))
+              )
+            )
+            (net N292
+              (joined
+                (portRef D (instanceRef f0_Result_6_2_FRB_renamed_382))
+                (portRef O (instanceRef f0_Mcount_wr_addr_xor_6__))
+              )
+            )
+            (net N293
+              (joined
+                (portRef D (instanceRef f0_Result_7_2_FRB_renamed_383))
+                (portRef O (instanceRef f0_Mcount_wr_addr_xor_7__))
+              )
+            )
+            (net N294
+              (joined
+                (portRef D (instanceRef f0_Result_8_2_FRB_renamed_384))
+                (portRef O (instanceRef f0_Mcount_wr_addr_xor_8__))
+              )
+            )
+            (net N295
+              (joined
+                (portRef D (instanceRef f0_Result_9_2_FRB_renamed_385))
+                (portRef O (instanceRef f0_Mcount_wr_addr_xor_9__))
+              )
+            )
+            (net N296
+              (joined
+                (portRef D (instanceRef f0_Result_10_2_FRB_renamed_386))
+                (portRef O (instanceRef f0_Mcount_wr_addr_xor_10__))
+              )
+            )
+            (net N297
+              (joined
+                (portRef D (instanceRef f0_Result_11_2_FRB_renamed_387))
+                (portRef O (instanceRef f0_Mcount_wr_addr_xor_11__))
+              )
+            )
+            (net N298
+              (joined
+                (portRef O (instanceRef f0_Mcount_wr_addr_cy_11__))
+                (portRef CI (instanceRef f0_Mcount_wr_addr_xor_12__))
+              )
+            )
+            (net N299
+              (joined
+                (portRef D (instanceRef f0_Result_12_2_FRB_renamed_388))
+                (portRef O (instanceRef f0_Mcount_wr_addr_xor_12__))
+              )
+            )
+            (net N300
+              (joined
+                (portRef D (instanceRef f0_Result_0_1_FRB_renamed_389))
+                (portRef O (instanceRef f0_Mcount_rd_addr_xor_0__))
+              )
+            )
+            (net N301
+              (joined
+                (portRef D (instanceRef f0_Result_1_1_FRB_renamed_390))
+                (portRef O (instanceRef f0_Mcount_rd_addr_xor_1__))
+              )
+            )
+            (net N302
+              (joined
+                (portRef D (instanceRef f0_Result_2_1_FRB_renamed_391))
+                (portRef O (instanceRef f0_Mcount_rd_addr_xor_2__))
+              )
+            )
+            (net N303
+              (joined
+                (portRef D (instanceRef f0_Result_3_1_FRB_renamed_392))
+                (portRef O (instanceRef f0_Mcount_rd_addr_xor_3__))
+              )
+            )
+            (net N304
+              (joined
+                (portRef D (instanceRef f0_Result_4_1_FRB_renamed_393))
+                (portRef O (instanceRef f0_Mcount_rd_addr_xor_4__))
+              )
+            )
+            (net N305
+              (joined
+                (portRef D (instanceRef f0_Result_5_1_FRB_renamed_394))
+                (portRef O (instanceRef f0_Mcount_rd_addr_xor_5__))
+              )
+            )
+            (net N306
+              (joined
+                (portRef D (instanceRef f0_Result_6_1_FRB_renamed_395))
+                (portRef O (instanceRef f0_Mcount_rd_addr_xor_6__))
+              )
+            )
+            (net N307
+              (joined
+                (portRef D (instanceRef f0_Result_7_1_FRB_renamed_396))
+                (portRef O (instanceRef f0_Mcount_rd_addr_xor_7__))
+              )
+            )
+            (net N308
+              (joined
+                (portRef D (instanceRef f0_Result_8_1_FRB_renamed_397))
+                (portRef O (instanceRef f0_Mcount_rd_addr_xor_8__))
+              )
+            )
+            (net N309
+              (joined
+                (portRef D (instanceRef f0_Result_9_1_FRB_renamed_398))
+                (portRef O (instanceRef f0_Mcount_rd_addr_xor_9__))
+              )
+            )
+            (net N310
+              (joined
+                (portRef D (instanceRef f0_Result_10_1_FRB_renamed_399))
+                (portRef O (instanceRef f0_Mcount_rd_addr_xor_10__))
+              )
+            )
+            (net N311
+              (joined
+                (portRef D (instanceRef f0_Result_11_1_FRB_renamed_400))
+                (portRef O (instanceRef f0_Mcount_rd_addr_xor_11__))
+              )
+            )
+            (net N312
+              (joined
+                (portRef O (instanceRef f0_Mcount_rd_addr_cy_11__))
+                (portRef CI (instanceRef f0_Mcount_rd_addr_xor_12__))
+              )
+            )
+            (net N313
+              (joined
+                (portRef D (instanceRef f0_Result_12_1_FRB_renamed_401))
+                (portRef O (instanceRef f0_Mcount_rd_addr_xor_12__))
+              )
+            )
+            (net N314
+              (joined
+                (portRef D (instanceRef f0_dont_write_past_me_0__FRB_renamed_402))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_xor_0__))
+              )
+            )
+            (net N315
+              (joined
+                (portRef D (instanceRef f0_dont_write_past_me_1__FRB_renamed_403))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_xor_1__))
+              )
+            )
+            (net N316
+              (joined
+                (portRef D (instanceRef f0_dont_write_past_me_2__FRB_renamed_404))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_xor_2__))
+              )
+            )
+            (net N317
+              (joined
+                (portRef D (instanceRef f0_dont_write_past_me_3__FRB_renamed_405))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_xor_3__))
+              )
+            )
+            (net N318
+              (joined
+                (portRef D (instanceRef f0_dont_write_past_me_4__FRB_renamed_406))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_xor_4__))
+              )
+            )
+            (net N319
+              (joined
+                (portRef D (instanceRef f0_dont_write_past_me_5__FRB_renamed_407))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_xor_5__))
+              )
+            )
+            (net N320
+              (joined
+                (portRef D (instanceRef f0_dont_write_past_me_6__FRB_renamed_408))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_xor_6__))
+              )
+            )
+            (net N321
+              (joined
+                (portRef D (instanceRef f0_dont_write_past_me_7__FRB_renamed_409))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_xor_7__))
+              )
+            )
+            (net N322
+              (joined
+                (portRef D (instanceRef f0_dont_write_past_me_8__FRB_renamed_410))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_xor_8__))
+              )
+            )
+            (net N323
+              (joined
+                (portRef D (instanceRef f0_dont_write_past_me_9__FRB_renamed_411))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_xor_9__))
+              )
+            )
+            (net N324
+              (joined
+                (portRef D (instanceRef f0_dont_write_past_me_10__FRB_renamed_412))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_xor_10__))
+              )
+            )
+            (net N325
+              (joined
+                (portRef D (instanceRef f0_dont_write_past_me_11__FRB_renamed_413))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_xor_11__))
+              )
+            )
+            (net N326
+              (joined
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_11__))
+                (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_12__))
+              )
+            )
+            (net N327
+              (joined
+                (portRef D (instanceRef f0_dont_write_past_me_12__FRB_renamed_414))
+                (portRef O (instanceRef f0_Msub_dont_write_past_me_xor_12__))
+              )
+            )
+            (net N328
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+              )
+            )
+            (net N329
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1))
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+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut1")
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+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+              )
+            )
+            (net N445
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+              )
+            )
+            (net N447
+              (joined
+                (portRef I4
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218_SW0_FRB")
+              (joined
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_renamed_431))
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB_renamed_463))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_0_rstpot")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot_renamed_433))
+              )
+            )
+            (net N451
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+              )
+            )
+            (net N453
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot_renamed_433))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>_inv")
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3_renamed_503))
+                (portRef O
+ (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv_INV_0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0_lut")
+              (joined
+                (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut_renamed_436))
+              )
+            )
+            (net N455
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut_renamed_436))
+              )
+            )
+            (net N457
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_FRB_renamed_437))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_0__))
+              )
+            )
+            (net N458
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB_renamed_438))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_1__))
+              )
+            )
+            (net N459
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr2_FRB_renamed_439))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_2__))
+              )
+            )
+            (net N460
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr3_FRB_renamed_440))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_3__))
+              )
+            )
+            (net N461
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr4_FRB_renamed_441))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_4__))
+              )
+            )
+            (net N462
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB_renamed_442))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_5__))
+              )
+            )
+            (net N463
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB_renamed_443))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_6__))
+              )
+            )
+            (net N464
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr7_FRB_renamed_444))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_7__))
+              )
+            )
+            (net N465
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8__))
+              )
+            )
+            (net N466
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr8_FRB_renamed_445))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8__))
+              )
+            )
+            (net N467
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB_renamed_446))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_0__))
+              )
+            )
+            (net N468
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB_renamed_447))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_1__))
+              )
+            )
+            (net N469
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB_renamed_448))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_2__))
+              )
+            )
+            (net N470
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB_renamed_449))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_3__))
+              )
+            )
+            (net N471
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB_renamed_450))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4__))
+              )
+            )
+            (net N472
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB_renamed_451))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5__))
+              )
+            )
+            (net N473
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr6_FRB_renamed_452))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_6__))
+              )
+            )
+            (net N474
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB_renamed_453))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7__))
+              )
+            )
+            (net N475
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__))
+                (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__))
+              )
+            )
+            (net N476
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB_renamed_454))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__))
+              )
+            )
+            (net N477
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421_FRB_renamed_455))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421))
+              )
+            )
+            (net N478
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411_FRB_renamed_456))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411))
+              )
+            )
+            (net N479
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB_renamed_457))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421))
+              )
+            )
+            (net N480
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB_renamed_458))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411))
+              )
+            )
+            (net N481
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB_renamed_459))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0))
+              )
+            )
+            (net N482
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB_renamed_460))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0))
+              )
+            )
+            (net N483
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB_renamed_461))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621))
+              )
+            )
+            (net N484
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB_renamed_462))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621))
+              )
+            )
+            (net N485
+              (joined
+                (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB_renamed_463))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB0")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0_renamed_464))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1_renamed_465))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_13_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1_renamed_466))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_14_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_14_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_14_BRB1_renamed_467))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_15_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15_BRB1_renamed_468))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB0")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0_renamed_469))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13__))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1_renamed_470))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_13_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1_renamed_471))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_14_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1_renamed_472))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_15_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1_renamed_473))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd2_BRB0")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB0_renamed_474))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_GND_50_o_read_OR_57_o1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0144_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd2_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB1_renamed_475))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_GND_50_o_read_OR_57_o1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In11))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0144_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB0")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0_renamed_476))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1_renamed_477))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_478))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1_renamed_479))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2_renamed_480))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_481))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4_renamed_482))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5_renamed_483))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_484))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1_renamed_485))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2_renamed_486))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_487))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4_renamed_488))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5_renamed_489))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_11_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_BRB1_renamed_490))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_11_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1_renamed_491))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_10_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1_renamed_492))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_10_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1_renamed_493))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_9_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1_renamed_494))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_9_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1_renamed_495))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__))
+              )
+            )
+            (net (rename slave_fifo32_debug1_17_BRB0 "slave_fifo32/debug1_17_BRB0")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_17_BRB0_renamed_496))
+                (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_o_tvalid1_INV_0))
+              )
+            )
+            (net (rename slave_fifo32_debug1_16_BRB0 "slave_fifo32/debug1_16_BRB0")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_debug1_16_BRB0_renamed_497))
+                (portRef I (instanceRef f0_i_tready1_INV_0))
+              )
+            )
+            (net (rename slave_fifo32_rd_one_BRB0 "slave_fifo32/rd_one_BRB0")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_rd_one_BRB0_renamed_498))
+                (portRef I0 (instanceRef slave_fifo32_rd_one_rstpot))
+                (portRef I1 (instanceRef slave_fifo32_state_FSM_FFd1_In3_G))
+              )
+            )
+            (net (rename slave_fifo32_rd_one_BRB1 "slave_fifo32/rd_one_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_rd_one_BRB1_renamed_499))
+                (portRef I1 (instanceRef slave_fifo32_rd_one_rstpot))
+                (portRef I3 (instanceRef slave_fifo32_state_FSM_FFd1_In3_G))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1_renamed_502))
+                (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB3")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3_renamed_503))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB4")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4_renamed_504))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+              )
+            )
+            (net N543
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6))
+              )
+            )
+            (net (rename f1__n0161_inv1_lut "f1/_n0161_inv1_lut")
+              (joined
+                (portRef O (instanceRef f1__n0161_inv1_lut_renamed_507))
+                (portRef S (instanceRef f1__n0161_inv1_cy))
+              )
+            )
+            (net (rename f1_rd_addr_12__wr_addr_12__equal_11_o_l1 "f1/rd_addr[12]_wr_addr[12]_equal_11_o_l1")
+              (joined
+                (portRef O (instanceRef f1__n0161_inv1_cy))
+                (portRef CI (instanceRef f1__n0161_inv1_cy1))
+              )
+            )
+            (net (rename f1__n0161_inv1_lut1 "f1/_n0161_inv1_lut1")
+              (joined
+                (portRef O (instanceRef f1__n0161_inv1_lut1_renamed_508))
+                (portRef S (instanceRef f1__n0161_inv1_cy1))
+              )
+            )
+            (net (rename f0__n0161_inv1_lut "f0/_n0161_inv1_lut")
+              (joined
+                (portRef O (instanceRef f0__n0161_inv1_lut_renamed_509))
+                (portRef S (instanceRef f0__n0161_inv1_cy))
+              )
+            )
+            (net (rename f0_rd_addr_12__wr_addr_12__equal_11_o_l1 "f0/rd_addr[12]_wr_addr[12]_equal_11_o_l1")
+              (joined
+                (portRef O (instanceRef f0__n0161_inv1_cy))
+                (portRef CI (instanceRef f0__n0161_inv1_cy1))
+              )
+            )
+            (net (rename f0__n0161_inv1_lut1 "f0/_n0161_inv1_lut1")
+              (joined
+                (portRef O (instanceRef f0__n0161_inv1_lut1_renamed_510))
+                (portRef S (instanceRef f0__n0161_inv1_cy1))
+              )
+            )
+            (net N545
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2))
+              )
+            )
+            (net N546
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2))
+              )
+            )
+            (net N547
+              (joined
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F))
+              )
+            )
+            (net N548
+              (joined
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0))
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G))
+              )
+            )
+            (net N549
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0))
+              )
+            )
+            (net N550
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0))
+              )
+            )
+            (net N551
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1))
+              )
+            )
+            (net N552
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1))
+              )
+            )
+            (net N553
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1))
+              )
+            )
+            (net N554
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1))
+              )
+            )
+            (net N559
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_renamed_535))
+              )
+            )
+            (net N561
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_SW0))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_renamed_536))
+              )
+            )
+            (net N563
+              (joined
+                (portRef O (instanceRef slave_fifo32_slrd_rstpot_SW0))
+                (portRef I1 (instanceRef slave_fifo32_slrd_rstpot_renamed_515))
+              )
+            )
+            (net N565
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_renamed_516))
+              )
+            )
+            (net N567
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_SW0))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_renamed_527))
+              )
+            )
+            (net N569
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+              )
+            )
+            (net N571
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+              )
+            )
+            (net N573
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1_SW0))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1))
+              )
+            )
+            (net N575
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_SW1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_renamed_530))
+              )
+            )
+            (net N577
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_SW1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_renamed_531))
+              )
+            )
+            (net N579
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1))
+              )
+            )
+            (net N581
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1))
+                (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1))
+              )
+            )
+            (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2_1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1_renamed_539))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_47))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14_renamed_48))
+              )
+            )
+            (net (rename slave_fifo32_sloe_rstpot "slave_fifo32/sloe_rstpot")
+              (joined
+                (portRef O (instanceRef slave_fifo32_sloe_rstpot_renamed_541))
+                (portRef D (instanceRef slave_fifo32_sloe_renamed_540))
+                (portRef D (instanceRef slave_fifo32_sloe_33_renamed_554))
+                (portRef D (instanceRef slave_fifo32_sloe_32_renamed_555))
+                (portRef D (instanceRef slave_fifo32_sloe_31_renamed_556))
+                (portRef D (instanceRef slave_fifo32_sloe_30_renamed_557))
+                (portRef D (instanceRef slave_fifo32_sloe_29_renamed_558))
+                (portRef D (instanceRef slave_fifo32_sloe_28_renamed_559))
+                (portRef D (instanceRef slave_fifo32_sloe_27_renamed_560))
+                (portRef D (instanceRef slave_fifo32_sloe_26_renamed_561))
+                (portRef D (instanceRef slave_fifo32_sloe_25_renamed_562))
+                (portRef D (instanceRef slave_fifo32_sloe_24_renamed_563))
+                (portRef D (instanceRef slave_fifo32_sloe_23_renamed_564))
+                (portRef D (instanceRef slave_fifo32_sloe_22_renamed_565))
+                (portRef D (instanceRef slave_fifo32_sloe_21_renamed_566))
+                (portRef D (instanceRef slave_fifo32_sloe_20_renamed_567))
+                (portRef D (instanceRef slave_fifo32_sloe_19_renamed_568))
+                (portRef D (instanceRef slave_fifo32_sloe_18_renamed_569))
+                (portRef D (instanceRef slave_fifo32_sloe_17_renamed_570))
+                (portRef D (instanceRef slave_fifo32_sloe_16_renamed_571))
+                (portRef D (instanceRef slave_fifo32_sloe_15_renamed_572))
+                (portRef D (instanceRef slave_fifo32_sloe_14_renamed_573))
+                (portRef D (instanceRef slave_fifo32_sloe_13_renamed_574))
+                (portRef D (instanceRef slave_fifo32_sloe_12_renamed_575))
+                (portRef D (instanceRef slave_fifo32_sloe_11_renamed_576))
+                (portRef D (instanceRef slave_fifo32_sloe_10_renamed_577))
+                (portRef D (instanceRef slave_fifo32_sloe_9_renamed_578))
+                (portRef D (instanceRef slave_fifo32_sloe_8_renamed_579))
+                (portRef D (instanceRef slave_fifo32_sloe_7_renamed_580))
+                (portRef D (instanceRef slave_fifo32_sloe_6_renamed_581))
+                (portRef D (instanceRef slave_fifo32_sloe_5_renamed_582))
+                (portRef D (instanceRef slave_fifo32_sloe_4_renamed_583))
+                (portRef D (instanceRef slave_fifo32_sloe_3_renamed_584))
+                (portRef D (instanceRef slave_fifo32_sloe_2_renamed_585))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_31_rstpot "slave_fifo32/gpif_data_out_31_rstpot")
+              (joined
+                (portRef O (instanceRef slave_fifo32_gpif_data_out_31_rstpot_renamed_542))
+                (portRef D (instanceRef slave_fifo32_gpif_data_out_31_1_renamed_547))
+                (portRef D (instanceRef slave_fifo32_gpif_data_out_31))
+              )
+            )
+            (net N583
+              (joined
+                (portRef O (instanceRef slave_fifo32_state_FSM_FFd1_In3_F))
+                (portRef I0 (instanceRef slave_fifo32_state_FSM_FFd1_In3_renamed_543))
+              )
+            )
+            (net N584
+              (joined
+                (portRef O (instanceRef slave_fifo32_state_FSM_FFd1_In3_G))
+                (portRef I1 (instanceRef slave_fifo32_state_FSM_FFd1_In3_renamed_543))
+              )
+            )
+            (net N585
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14))
+              )
+            )
+            (net N586
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14))
+              )
+            )
+            (net N587
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1))
+              )
+            )
+            (net N588
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1))
+              )
+            )
+            (net N589
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F))
+                (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2))
+              )
+            )
+            (net N590
+              (joined
+                (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2))
+              )
+            )
+            (net (rename slave_fifo32_slrd2_1 "slave_fifo32/slrd2_1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_slrd2_1_renamed_544))
+                (portRef D (instanceRef slave_fifo32_slrd3_renamed_8))
+                (portRef (member DIPA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+                (portRef (member DIPA 3) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+              )
+            )
+            (net (rename slave_fifo32_EP_WMARK1_1 "slave_fifo32/EP_WMARK1_1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_EP_WMARK1_1_renamed_545))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0))
+                (portRef I5 (instanceRef slave_fifo32_slrd_rstpot_renamed_515))
+                (portRef I1 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0))
+              )
+            )
+            (net (rename slave_fifo32_EP_READY1_1 "slave_fifo32/EP_READY1_1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_EP_READY1_1_renamed_546))
+                (portRef I3 (instanceRef slave_fifo32__n0290_inv1))
+                (portRef I2 (instanceRef slave_fifo32__n0258_inv_SW0))
+                (portRef I4 (instanceRef slave_fifo32__n0279_inv_renamed_35))
+                (portRef I4 (instanceRef slave_fifo32_state_FSM_FFd2_In2_renamed_38))
+                (portRef I0 (instanceRef slave_fifo32_slrd_rstpot_SW0))
+                (portRef I1 (instanceRef slave_fifo32_sloe_1_rstpot_renamed_534))
+                (portRef I2 (instanceRef slave_fifo32_state_FSM_FFd1_In3_F))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_31_1 "slave_fifo32/gpif_data_out_31_1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_31_1_renamed_547))
+                (portRef I1 (instanceRef slave_fifo32_gpif_data_out_31_rstpot_renamed_542))
+              )
+            )
+            (net (rename slave_fifo32_slwr_1 "slave_fifo32/slwr_1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_slwr_1_renamed_548))
+                (portRef D (instanceRef slave_fifo32_debug1_29))
+              )
+            )
+            (net (rename slave_fifo32_sloe_34 "slave_fifo32/sloe_34")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_34_renamed_549))
+                (portRef D (instanceRef slave_fifo32_debug1_31))
+                (portRef I0 (instanceRef slave_fifo32_sloe_1_rstpot_renamed_534))
+              )
+            )
+            (net (rename slave_fifo32_slrd_1 "slave_fifo32/slrd_1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_slrd_1_renamed_550))
+                (portRef D (instanceRef slave_fifo32_slrd1_renamed_10))
+                (portRef I0 (instanceRef slave_fifo32_slrd_rstpot_renamed_515))
+              )
+            )
+            (net (rename slave_fifo32_pktend_1 "slave_fifo32/pktend_1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_pktend_1_renamed_551))
+                (portRef D (instanceRef slave_fifo32_debug1_28))
+              )
+            )
+            (net (rename slave_fifo32_fifoadr_1_1 "slave_fifo32/fifoadr_1_1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifoadr_1_1_renamed_552))
+                (portRef D (instanceRef slave_fifo32_debug1_27))
+                (portRef I0 (instanceRef slave_fifo32_Mcount_fifoadr_xor_1_11))
+                (portRef I1 (instanceRef slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT171))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT181))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT211))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT41))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT51))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT61))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT71))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT81))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT91))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1))
+                (portRef I0 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_write1))
+                (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1))
+                (portRef I1 (instanceRef slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1))
+                (portRef I3 (instanceRef slave_fifo32_ctrl_tx_tvalid1))
+                (portRef I3 (instanceRef slave_fifo32_data_tx_tvalid1))
+                (portRef I0 (instanceRef slave_fifo32_state_FSM_FFd1_In2_renamed_36))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1))
+              )
+            )
+            (net (rename slave_fifo32_fifoadr_0_1 "slave_fifo32/fifoadr_0_1")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_fifoadr_0_1_renamed_553))
+                (portRef D (instanceRef slave_fifo32_debug1_26))
+                (portRef I1 (instanceRef slave_fifo32_Mcount_fifoadr_xor_1_11))
+                (portRef I0 (instanceRef slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT171))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT181))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT211))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT41))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT51))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT61))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT71))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT81))
+                (portRef I3 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT91))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0))
+                (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_write1))
+                (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1))
+                (portRef I0 (instanceRef slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1))
+                (portRef I (instanceRef slave_fifo32_Mcount_fifoadr_xor_0_11_INV_0))
+                (portRef I2 (instanceRef slave_fifo32_ctrl_tx_tvalid1))
+                (portRef I2 (instanceRef slave_fifo32_data_tx_tvalid1))
+                (portRef I2 (instanceRef slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0))
+              )
+            )
+            (net (rename slave_fifo32_sloe_33 "slave_fifo32/sloe_33")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_33_renamed_554))
+                (portRef T (instanceRef GPIF_D_31_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_31_ "slave_fifo32/gpif_data_out<31>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_31))
+                (portRef I (instanceRef GPIF_D_31_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_32 "slave_fifo32/sloe_32")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_32_renamed_555))
+                (portRef T (instanceRef GPIF_D_30_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_30_ "slave_fifo32/gpif_data_out<30>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_30))
+                (portRef I (instanceRef GPIF_D_30_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_31 "slave_fifo32/sloe_31")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_31_renamed_556))
+                (portRef T (instanceRef GPIF_D_29_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_29_ "slave_fifo32/gpif_data_out<29>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_29))
+                (portRef I (instanceRef GPIF_D_29_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_30 "slave_fifo32/sloe_30")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_30_renamed_557))
+                (portRef T (instanceRef GPIF_D_28_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_28_ "slave_fifo32/gpif_data_out<28>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_28))
+                (portRef I (instanceRef GPIF_D_28_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_29 "slave_fifo32/sloe_29")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_29_renamed_558))
+                (portRef T (instanceRef GPIF_D_27_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_27_ "slave_fifo32/gpif_data_out<27>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_27))
+                (portRef I (instanceRef GPIF_D_27_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_28 "slave_fifo32/sloe_28")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_28_renamed_559))
+                (portRef T (instanceRef GPIF_D_26_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_26_ "slave_fifo32/gpif_data_out<26>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_26))
+                (portRef I (instanceRef GPIF_D_26_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_27 "slave_fifo32/sloe_27")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_27_renamed_560))
+                (portRef T (instanceRef GPIF_D_25_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_25_ "slave_fifo32/gpif_data_out<25>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_25))
+                (portRef I (instanceRef GPIF_D_25_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_26 "slave_fifo32/sloe_26")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_26_renamed_561))
+                (portRef T (instanceRef GPIF_D_24_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_24_ "slave_fifo32/gpif_data_out<24>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_24))
+                (portRef I (instanceRef GPIF_D_24_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_25 "slave_fifo32/sloe_25")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_25_renamed_562))
+                (portRef T (instanceRef GPIF_D_23_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_23_ "slave_fifo32/gpif_data_out<23>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_23))
+                (portRef I (instanceRef GPIF_D_23_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_24 "slave_fifo32/sloe_24")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_24_renamed_563))
+                (portRef T (instanceRef GPIF_D_22_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_22_ "slave_fifo32/gpif_data_out<22>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_22))
+                (portRef I (instanceRef GPIF_D_22_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_23 "slave_fifo32/sloe_23")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_23_renamed_564))
+                (portRef T (instanceRef GPIF_D_21_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_21_ "slave_fifo32/gpif_data_out<21>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_21))
+                (portRef I (instanceRef GPIF_D_21_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_22 "slave_fifo32/sloe_22")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_22_renamed_565))
+                (portRef T (instanceRef GPIF_D_20_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_20_ "slave_fifo32/gpif_data_out<20>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_20))
+                (portRef I (instanceRef GPIF_D_20_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_21 "slave_fifo32/sloe_21")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_21_renamed_566))
+                (portRef T (instanceRef GPIF_D_19_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_19_ "slave_fifo32/gpif_data_out<19>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_19))
+                (portRef I (instanceRef GPIF_D_19_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_20 "slave_fifo32/sloe_20")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_20_renamed_567))
+                (portRef T (instanceRef GPIF_D_18_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_18_ "slave_fifo32/gpif_data_out<18>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_18))
+                (portRef I (instanceRef GPIF_D_18_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_19 "slave_fifo32/sloe_19")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_19_renamed_568))
+                (portRef T (instanceRef GPIF_D_17_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_17_ "slave_fifo32/gpif_data_out<17>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_17))
+                (portRef I (instanceRef GPIF_D_17_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_18 "slave_fifo32/sloe_18")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_18_renamed_569))
+                (portRef T (instanceRef GPIF_D_16_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_16_ "slave_fifo32/gpif_data_out<16>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_16))
+                (portRef I (instanceRef GPIF_D_16_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_17 "slave_fifo32/sloe_17")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_17_renamed_570))
+                (portRef T (instanceRef GPIF_D_15_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_15_ "slave_fifo32/gpif_data_out<15>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_15))
+                (portRef I (instanceRef GPIF_D_15_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_16 "slave_fifo32/sloe_16")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_16_renamed_571))
+                (portRef T (instanceRef GPIF_D_14_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_14_ "slave_fifo32/gpif_data_out<14>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_14))
+                (portRef I (instanceRef GPIF_D_14_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_15 "slave_fifo32/sloe_15")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_15_renamed_572))
+                (portRef T (instanceRef GPIF_D_13_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_13_ "slave_fifo32/gpif_data_out<13>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_13))
+                (portRef I (instanceRef GPIF_D_13_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_14 "slave_fifo32/sloe_14")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_14_renamed_573))
+                (portRef T (instanceRef GPIF_D_12_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_12_ "slave_fifo32/gpif_data_out<12>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_12))
+                (portRef I (instanceRef GPIF_D_12_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_13 "slave_fifo32/sloe_13")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_13_renamed_574))
+                (portRef T (instanceRef GPIF_D_11_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_11_ "slave_fifo32/gpif_data_out<11>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_11))
+                (portRef I (instanceRef GPIF_D_11_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_12 "slave_fifo32/sloe_12")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_12_renamed_575))
+                (portRef T (instanceRef GPIF_D_10_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_10_ "slave_fifo32/gpif_data_out<10>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_10))
+                (portRef I (instanceRef GPIF_D_10_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_11 "slave_fifo32/sloe_11")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_11_renamed_576))
+                (portRef T (instanceRef GPIF_D_9_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_9_ "slave_fifo32/gpif_data_out<9>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_9))
+                (portRef I (instanceRef GPIF_D_9_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_10 "slave_fifo32/sloe_10")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_10_renamed_577))
+                (portRef T (instanceRef GPIF_D_8_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_8_ "slave_fifo32/gpif_data_out<8>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_8))
+                (portRef I (instanceRef GPIF_D_8_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_9 "slave_fifo32/sloe_9")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_9_renamed_578))
+                (portRef T (instanceRef GPIF_D_7_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_7_ "slave_fifo32/gpif_data_out<7>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_7))
+                (portRef I (instanceRef GPIF_D_7_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_8 "slave_fifo32/sloe_8")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_8_renamed_579))
+                (portRef T (instanceRef GPIF_D_6_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_6_ "slave_fifo32/gpif_data_out<6>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_6))
+                (portRef I (instanceRef GPIF_D_6_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_7 "slave_fifo32/sloe_7")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_7_renamed_580))
+                (portRef T (instanceRef GPIF_D_5_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_5_ "slave_fifo32/gpif_data_out<5>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_5))
+                (portRef I (instanceRef GPIF_D_5_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_6 "slave_fifo32/sloe_6")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_6_renamed_581))
+                (portRef T (instanceRef GPIF_D_4_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_4_ "slave_fifo32/gpif_data_out<4>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_4))
+                (portRef I (instanceRef GPIF_D_4_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_5 "slave_fifo32/sloe_5")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_5_renamed_582))
+                (portRef T (instanceRef GPIF_D_3_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_3_ "slave_fifo32/gpif_data_out<3>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_3))
+                (portRef I (instanceRef GPIF_D_3_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_4 "slave_fifo32/sloe_4")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_4_renamed_583))
+                (portRef T (instanceRef GPIF_D_2_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_2_ "slave_fifo32/gpif_data_out<2>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_2))
+                (portRef I (instanceRef GPIF_D_2_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_3 "slave_fifo32/sloe_3")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_3_renamed_584))
+                (portRef T (instanceRef GPIF_D_1_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_1_ "slave_fifo32/gpif_data_out<1>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_1))
+                (portRef I (instanceRef GPIF_D_1_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_sloe_2 "slave_fifo32/sloe_2")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_sloe_2_renamed_585))
+                (portRef T (instanceRef GPIF_D_0_IOBUF))
+              )
+            )
+            (net (rename slave_fifo32_gpif_data_out_0_ "slave_fifo32/gpif_data_out<0>")
+              (joined
+                (portRef Q (instanceRef slave_fifo32_gpif_data_out_0))
+                (portRef I (instanceRef GPIF_D_0_IOBUF))
+              )
+            )
+          )
+      )
+    )
+  )
+
+  (design b200
+    (cellRef b200
+      (libraryRef b200_lib)
+    )
+    (property PART (string "xc6slx75-3-fgg484") (owner "Xilinx"))
+  )
+)
+
diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/constrs_1/fileset.xml b/fpga/usrp3/top/b200/planahead/planahead.data/constrs_1/fileset.xml
new file mode 100644
index 000000000..6234dfdc5
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.data/constrs_1/fileset.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PSRCDIR/constrs_1/imports/b200/b200.ucf">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../b200.ucf"/>
+        <Attr Name="ImportTime" Val="1358988004"/>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/constrs_1/imports/b200/timing.ucf">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../timing.ucf"/>
+        <Attr Name="ImportTime" Val="1359506480"/>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="ConstrsType" Val="UCF"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1.psg b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1.psg
new file mode 100644
index 000000000..147f3a950
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1.psg
@@ -0,0 +1,20 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+	<StratHandle Name="ISE Defaults" Flow="ISE14">
+		<Desc>ISE Defaults, including packing registers in IOs off</Desc>
+	</StratHandle>
+	<Step Id="ngdbuild">
+	</Step>
+	<Step Id="map">
+		<Option Id="FFPackEnum">3</Option>
+	</Step>
+	<Step Id="par">
+	</Step>
+	<Step Id="trce">
+	</Step>
+	<Step Id="xdl">
+	</Step>
+	<Step Id="bitgen">
+	</Step>
+</Strategy>
+
diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_in.xml b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_in.xml
new file mode 100644
index 000000000..d7d32c943
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_in.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PSRCDIR/constrs_1/imports/b200/b200.ucf">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../b200.ucf"/>
+        <Attr Name="ImportTime" Val="1358988004"/>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/constrs_1/imports/b200/timing.ucf">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../timing.ucf"/>
+        <Attr Name="ImportTime" Val="1359506480"/>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="ConstrsType" Val="UCF"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_out.xml b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_out.xml
new file mode 100644
index 000000000..4d152cf5b
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_out.xml
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="constrs_out" Type="Constrs" RelSrcDir="$PRUNDIR/impl_1/.constrs">
+    <File Path="$PRUNDIR/impl_1/.constrs/b200.ucf">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PRUNDIR/impl_1/.constrs/timing.ucf">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="ConstrsType" Val="UCF"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/impl_1.psg b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/impl_1.psg
new file mode 100644
index 000000000..147f3a950
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/impl_1.psg
@@ -0,0 +1,20 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+	<StratHandle Name="ISE Defaults" Flow="ISE14">
+		<Desc>ISE Defaults, including packing registers in IOs off</Desc>
+	</StratHandle>
+	<Step Id="ngdbuild">
+	</Step>
+	<Step Id="map">
+		<Option Id="FFPackEnum">3</Option>
+	</Step>
+	<Step Id="par">
+	</Step>
+	<Step Id="trce">
+	</Step>
+	<Step Id="xdl">
+	</Step>
+	<Step Id="bitgen">
+	</Step>
+</Strategy>
+
diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/sources.xml b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/sources.xml
new file mode 100644
index 000000000..1ebdc052b
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/sources.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PSRCDIR/sources_1/imports/build/b200.ngc">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../build/b200.ngc"/>
+        <Attr Name="ImportTime" Val="1359508205"/>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="b200"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/runs.xml b/fpga/usrp3/top/b200/planahead/planahead.data/runs/runs.xml
new file mode 100644
index 000000000..b8f171cc0
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/runs.xml
@@ -0,0 +1,30 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="8">
+	<Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc6slx75fgg484-3" LaunchPart="xc6slx75fgg484-3" ConstrsSet="constrs_1" Description="Imported on Tue Jan 29 17:25:57 2013" State="current" Dir="$PRUNDIR/impl_1" LaunchTime="1359509156" Reconstructed="TRUE">
+		<File Type="MAP-PSR" Name="b200.psr"/>
+		<File Type="PA-EDIF" Name="b200.edf"/>
+		<File Type="PAR-NCD" Name="b200.ncd"/>
+		<File Type="PA-UCF" Name="b200.ucf"/>
+		<File Type="PAR-PAD" Name="b200_routed_pad.txt"/>
+		<File Type="PAR-PAR" Name="b200_routed.par"/>
+		<File Type="PAR-UNR" Name="b200_routed.unroutes"/>
+		<File Type="BG-BIT" Name="b200.bit"/>
+		<File Type="BG-DRC" Name="b200.drc"/>
+		<File Type="PA-CONSTRSDIR" Name=".constrs"/>
+		<File Type="BG-BGN" Name="b200.bgn"/>
+		<File Type="TRCE-TWR" Name="b200.twr"/>
+		<File Type="TRCE-TWX" Name="b200.twx"/>
+		<File Type="XDL-XDL" Name="b200.xdl"/>
+		<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+		<File Type="WBT-LOG" Name="webtalk.log"/>
+		<File Type="RUN-SRCS" Name="$PDATADIR/runs/impl_1/sources.xml"/>
+		<File Type="RUN-CONSTRS" Name="$PDATADIR/runs/impl_1/constrs_in.xml"/>
+		<File Type="RUN-STRAT" Name="$PDATADIR/runs/impl_1/impl_1.psg"/>
+		<File Type="NGDB-NGD" Name="b200.ngd"/>
+		<File Type="NGDB-BLD" Name="b200.bld"/>
+		<File Type="MAP-NCD" Name="b200.ncd"/>
+		<File Type="MAP-MRP" Name="b200.mrp"/>
+		<File Type="MAP-MAP" Name="b200.map"/>
+	</Run>
+</Runs>
+
diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/sim_1/fileset.xml b/fpga/usrp3/top/b200/planahead/planahead.data/sim_1/fileset.xml
new file mode 100644
index 000000000..65babe32f
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.data/sim_1/fileset.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+      <Option Name="SrcSet" Val="sources_1"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml b/fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml
new file mode 100644
index 000000000..b0421e4c2
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PSRCDIR/sources_1/imports/build/b200.ngc">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../build/b200.ngc"/>
+        <Attr Name="ImportTime" Val="1359508205"/>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/imports/coregen/fifo_4k_2clk.ngc">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../coregen/fifo_4k_2clk.ngc"/>
+        <Attr Name="ImportTime" Val="1359144134"/>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="GateLvl"/>
+      <Option Name="TopModule" Val="b200"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/wt/java_command_handlers.wdf b/fpga/usrp3/top/b200/planahead/planahead.data/wt/java_command_handlers.wdf
new file mode 100644
index 000000000..d32729c6c
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.data/wt/java_command_handlers.wdf
@@ -0,0 +1,12 @@
+version:1
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464737263:31:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697466696e64:32:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697470726f70657274696573:31:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:66696c6565786974:31:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f67676c657a6f6f6d617265616d6f6465:32:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7a6f6f6d666974:31:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7a6f6f6d696e:3133:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7a6f6f6d6f7574:3137:00:00
+eof:1108508211
diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/wt/project.wpc b/fpga/usrp3/top/b200/planahead/planahead.data/wt/project.wpc
new file mode 100644
index 000000000..9b3420931
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.data/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+eof:
diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/wt/webtalk_pa.xml b/fpga/usrp3/top/b200/planahead/planahead.data/wt/webtalk_pa.xml
new file mode 100644
index 000000000..4c889614e
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.data/wt/webtalk_pa.xml
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Tue Jan 29 17:42:17 2013">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="a2486f6b8cdf4e77be535de080ad1097" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="GateLvl" type="DesignMode"/>
+<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="AddSrc" value="1" type="JavaHandler"/>
+<property name="EditFind" value="2" type="JavaHandler"/>
+<property name="EditProperties" value="1" type="JavaHandler"/>
+<property name="FileExit" value="1" type="JavaHandler"/>
+<property name="NewProject" value="1" type="JavaHandler"/>
+<property name="ToggleZoomAreaMode" value="2" type="JavaHandler"/>
+<property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
+<property name="ZoomFit" value="1" type="JavaHandler"/>
+<property name="ZoomIn" value="13" type="JavaHandler"/>
+<property name="ZoomOut" value="17" type="JavaHandler"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="1" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="0" type="TclMode"/>
+<property name="ISEMode" value="0" type="ISEMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/fpga/usrp3/top/b200/planahead/planahead.ppr b/fpga/usrp3/top/b200/planahead/planahead.ppr
new file mode 100644
index 000000000..706cfae4b
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.ppr
@@ -0,0 +1,28 @@
+<?xml version="1.0"?>
+<!--Product Version: PlanAhead v14.4 (64-bit)-->
+<Project Version="4" Minor="36">
+	<FileSet Dir="sources_1" File="fileset.xml"/>
+	<FileSet Dir="constrs_1" File="fileset.xml"/>
+	<FileSet Dir="sim_1" File="fileset.xml"/>
+	<RunSet Dir="runs" File="runs.xml"/>
+	<DefaultLaunch Dir="$PRUNDIR"/>
+	<DefaultPromote Dir="$PROMOTEDIR"/>
+	<Config>
+		<Option Name="Id" Val="0f51201731ac4b37b508a9b552ac0aac"/>
+		<Option Name="Part" Val="xc6slx75fgg484-3"/>
+		<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+		<Option Name="TargetLanguage" Val="Verilog"/>
+		<Option Name="TargetSimulator" Val="ISim"/>
+		<Option Name="Board" Val=""/>
+		<Option Name="SourceMgmtMode" Val="All"/>
+		<Option Name="ActiveSimSet" Val="sim_1"/>
+		<Option Name="CxlOverwriteLibs" Val="1"/>
+		<Option Name="CxlFuncsim" Val="1"/>
+		<Option Name="CxlTimesim" Val="1"/>
+		<Option Name="CxlCore" Val="1"/>
+		<Option Name="CxlEdk" Val="0"/>
+		<Option Name="CxlExcludeCores" Val="1"/>
+		<Option Name="CxlExcludeSubLibs" Val="0"/>
+	</Config>
+</Project>
+
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.bat b/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.bat
new file mode 100644
index 000000000..f95ac9bd2
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.bat
@@ -0,0 +1,21 @@
+@echo off
+
+rem  PlanAhead(TM)
+rem  launch.bat: a PlanAhead-generated ExploreAhead Script
+rem  Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
+
+
+setlocal
+
+set HD_LDIR=%~dp0
+
+rem *** Create Queue Clues
+set HD_RUNDIR=%HD_LDIR%\../impl_1
+if exist "%HD_RUNDIR%" echo. > "%HD_RUNDIR%/.ISE.queue.rst"
+
+
+rem *** Launch Runs (one at a time)
+set HD_RUNBAT=%HD_LDIR%\../impl_1\runme.bat
+if exist "%HD_RUNBAT%" call "%HD_RUNBAT%" %*
+
+
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.sh b/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.sh
new file mode 100755
index 000000000..48861c686
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.sh
@@ -0,0 +1,26 @@
+#!/bin/sh
+
+# 
+# PlanAhead(TM)
+# launch.sh: a PlanAhead-generated ExploreAhead Script for UNIX
+# Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
+# 
+
+HD_LDIR=`dirname "$0"`
+
+# *** Create Queue Clues
+HD_RUNDIR="$HD_LDIR/../impl_1"
+if [ -d "$HD_RUNDIR" ]
+then
+/bin/touch "$HD_RUNDIR/.ISE.queue.rst"
+fi
+
+
+# *** Launch Runs (one at a time)
+HD_RUNSH="$HD_LDIR/../impl_1/runme.sh"
+if [ -f "$HD_RUNSH" ]
+then
+"$HD_RUNSH"
+fi
+
+
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/b200.ucf b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/b200.ucf
new file mode 100644
index 000000000..665f5d76c
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/b200.ucf
@@ -0,0 +1,317 @@
+## SPI Nets
+
+NET "cat_ce" LOC = Y1;
+NET "cat_ce" IOSTANDARD = LVCMOS18;
+NET "cat_miso" LOC = V1;
+NET "cat_miso" IOSTANDARD = LVCMOS18;
+NET "cat_mosi" LOC = T4;
+NET "cat_mosi" IOSTANDARD = LVCMOS18;
+NET "cat_sclk" LOC = P7;
+NET "cat_sclk" IOSTANDARD = LVCMOS18;
+
+NET "fx3_ce" LOC = H20;
+NET "fx3_miso" LOC = G20;
+NET "fx3_mosi" LOC = AA20;
+NET "fx3_sclk" LOC = Y21;
+
+NET "pll_ce" LOC = W11;
+NET "pll_mosi" LOC = AB11;
+NET "pll_sclk" LOC = Y12;
+
+NET "FPGA_RXD0" LOC = AB8;
+NET "FPGA_TXD0" LOC = AB7;
+
+NET "SCL_FPGA" LOC = P21;
+NET "SDA_FPGA" LOC = W22;
+
+## Catalina Controls
+
+NET "codec_enable" LOC = J6;
+NET "codec_enable" IOSTANDARD = LVCMOS18;
+NET "codec_en_agc" LOC = P6;
+NET "codec_en_agc" IOSTANDARD = LVCMOS18;
+NET "codec_reset" LOC = Y2;
+NET "codec_reset" IOSTANDARD = LVCMOS18;
+NET "codec_sync" LOC = M3;
+NET "codec_sync" IOSTANDARD = LVCMOS18;
+NET "codec_txrx" LOC = M7;
+NET "codec_txrx" IOSTANDARD = LVCMOS18;
+
+NET "codec_ctrl_in[0]" LOC = E3;
+NET "codec_ctrl_in[0]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_in[1]" LOC = F2;
+NET "codec_ctrl_in[1]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_in[2]" LOC = F1;
+NET "codec_ctrl_in[2]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_in[3]" LOC = E1;
+NET "codec_ctrl_in[3]" IOSTANDARD = LVCMOS18;
+
+NET "codec_ctrl_out[0]" LOC = D1;
+NET "codec_ctrl_out[0]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out[1]" LOC = C1;
+NET "codec_ctrl_out[1]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out[2]" LOC = H3;
+NET "codec_ctrl_out[2]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out[3]" LOC = F3;
+NET "codec_ctrl_out[3]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out[4]" LOC = P1;
+NET "codec_ctrl_out[4]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out[5]" LOC = J1;
+NET "codec_ctrl_out[5]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out[6]" LOC = B1;
+NET "codec_ctrl_out[6]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out[7]" LOC = H2;
+NET "codec_ctrl_out[7]" IOSTANDARD = LVCMOS18;
+
+## Catalina Data RX
+
+NET "rx_codec_d[0]" LOC = T2;
+NET "rx_codec_d[0]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[0]" DRIVE = 4;
+NET "rx_codec_d[1]" LOC = R1;
+NET "rx_codec_d[1]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[1]" DRIVE = 4;
+NET "rx_codec_d[2]" LOC = V2;
+NET "rx_codec_d[2]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[2]" DRIVE = 4;
+NET "rx_codec_d[3]" LOC = N1;
+NET "rx_codec_d[3]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[3]" DRIVE = 4;
+NET "rx_codec_d[4]" LOC = V3;
+NET "rx_codec_d[4]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[4]" DRIVE = 4;
+NET "rx_codec_d[5]" LOC = T1;
+NET "rx_codec_d[5]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[5]" DRIVE = 4;
+NET "rx_codec_d[6]" LOC = W1;
+NET "rx_codec_d[6]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[6]" DRIVE = 4;
+NET "rx_codec_d[7]" LOC = U1;
+NET "rx_codec_d[7]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[7]" DRIVE = 4;
+NET "rx_codec_d[8]" LOC = W3;
+NET "rx_codec_d[8]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[8]" DRIVE = 4;
+NET "rx_codec_d[9]" LOC = U3;
+NET "rx_codec_d[9]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[9]" DRIVE = 4;
+NET "rx_codec_d[10]" LOC = P2;
+NET "rx_codec_d[10]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[10]" DRIVE = 4;
+NET "rx_codec_d[11]" LOC = R3;
+NET "rx_codec_d[11]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[11]" DRIVE = 4;
+
+## Catalina Data TX
+
+NET "tx_codec_d[0]" LOC = M1;
+NET "tx_codec_d[0]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[0]" DRIVE = 4;
+NET "tx_codec_d[1]" LOC = K1;
+NET "tx_codec_d[1]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[1]" DRIVE = 4;
+NET "tx_codec_d[2]" LOC = L3;
+NET "tx_codec_d[2]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[2]" DRIVE = 4;
+NET "tx_codec_d[3]" LOC = K2;
+NET "tx_codec_d[3]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[3]" DRIVE = 4;
+NET "tx_codec_d[4]" LOC = M4;
+NET "tx_codec_d[4]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[4]" DRIVE = 4;
+NET "tx_codec_d[5]" LOC = J4;
+NET "tx_codec_d[5]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[5]" DRIVE = 4;
+NET "tx_codec_d[6]" LOC = L4;
+NET "tx_codec_d[6]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[6]" DRIVE = 4;
+NET "tx_codec_d[7]" LOC = H1;
+NET "tx_codec_d[7]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[7]" DRIVE = 4;
+NET "tx_codec_d[8]" LOC = M2;
+NET "tx_codec_d[8]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[8]" DRIVE = 4;
+NET "tx_codec_d[9]" LOC = G1;
+NET "tx_codec_d[9]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[9]" DRIVE = 4;
+NET "tx_codec_d[10]" LOC = N3;
+NET "tx_codec_d[10]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[10]" DRIVE = 4;
+NET "tx_codec_d[11]" LOC = G3;
+NET "tx_codec_d[11]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[11]" DRIVE = 4;
+
+## Catalina Clocks
+
+NET "cat_clkout_fpga" LOC = J3;
+NET "cat_clkout_fpga" IOSTANDARD = LVCMOS18;
+NET "codec_data_clk_p" LOC = K3;
+NET "codec_data_clk_p" IOSTANDARD = LVCMOS18;
+NET "codec_fb_clk_p" LOC = P3;
+NET "codec_fb_clk_p" IOSTANDARD = LVCMOS18;
+#  | IOSTANDARD = LVCMOS18;
+NET "codec_main_clk_p" LOC = K5;
+#  | IOSTANDARD = LVCMOS18;
+NET "codec_main_clk_n" LOC = K4;
+
+NET "rx_frame_p" LOC = U4;
+NET "rx_frame_p" IOSTANDARD = LVCMOS18;
+NET "tx_frame_p" LOC = T3;
+NET "tx_frame_p" IOSTANDARD = LVCMOS18;
+
+## Debug Bus
+
+NET "debug[0]" LOC = C14;
+NET "debug[1]" LOC = F15;
+NET "debug[2]" LOC = A18;
+NET "debug[3]" LOC = A17;
+NET "debug[4]" LOC = E14;
+NET "debug[5]" LOC = G13;
+NET "debug[6]" LOC = D13;
+NET "debug[7]" LOC = F13;
+NET "debug[8]" LOC = D8;
+NET "debug[9]" LOC = A6;
+NET "debug[10]" LOC = D7;
+NET "debug[11]" LOC = A5;
+NET "debug[12]" LOC = B6;
+NET "debug[13]" LOC = A3;
+NET "debug[14]" LOC = A7;
+NET "debug[15]" LOC = A8;
+NET "debug[16]" LOC = B18;
+NET "debug[17]" LOC = C17;
+NET "debug[18]" LOC = H13;
+NET "debug[19]" LOC = D12;
+NET "debug[20]" LOC = H14;
+NET "debug[21]" LOC = C10;
+NET "debug[22]" LOC = D10;
+NET "debug[23]" LOC = C8;
+NET "debug[24]" LOC = D9;
+NET "debug[25]" LOC = C5;
+NET "debug[26]" LOC = A9;
+NET "debug[27]" LOC = B8;
+NET "debug[28]" LOC = A4;
+NET "debug[29]" LOC = C7;
+NET "debug[30]" LOC = C6;
+NET "debug[31]" LOC = D6;
+
+NET "debug_clk[0]" LOC = A12;
+NET "debug_clk[1]" LOC = C12;
+
+## GPIF
+
+NET "IFCLK" LOC = H21;
+NET "FX3_EXTINT" LOC = U20;
+
+NET "GPIF_CTL0" LOC = V20;
+NET "GPIF_CTL1" LOC = T22;
+NET "GPIF_CTL2" LOC = R22;
+NET "GPIF_CTL3" LOC = U22;
+NET "GPIF_CTL4" LOC = P19;
+NET "GPIF_CTL5" LOC = N22;
+NET "GPIF_CTL6" LOC = T21;
+NET "GPIF_CTL7" LOC = V21;
+NET "GPIF_CTL8" LOC = K18;
+NET "GPIF_CTL9" LOC = R20;
+##GPIF_CTL10 is "FPGA_CFG_DONE", defined later.
+NET "GPIF_CTL11" LOC = P22;
+NET "GPIF_CTL12" LOC = M20;
+
+NET "GPIF_D[0]" LOC = T17;
+NET "GPIF_D[1]" LOC = U14;
+NET "GPIF_D[2]" LOC = U13;
+NET "GPIF_D[3]" LOC = AA6;
+NET "GPIF_D[4]" LOC = AB6;
+NET "GPIF_D[5]" LOC = Y3;
+NET "GPIF_D[6]" LOC = AB3;
+NET "GPIF_D[7]" LOC = AA4;
+NET "GPIF_D[8]" LOC = AA2;
+NET "GPIF_D[9]" LOC = AB2;
+NET "GPIF_D[10]" LOC = AB19;
+NET "GPIF_D[11]" LOC = AA18;
+NET "GPIF_D[12]" LOC = AB18;
+NET "GPIF_D[13]" LOC = Y13;
+NET "GPIF_D[14]" LOC = AA12;
+NET "GPIF_D[15]" LOC = AB12;
+NET "GPIF_D[16]" LOC = N20;
+NET "GPIF_D[17]" LOC = L20;
+NET "GPIF_D[18]" LOC = N19;
+NET "GPIF_D[19]" LOC = M22;
+NET "GPIF_D[20]" LOC = L19;
+NET "GPIF_D[21]" LOC = M21;
+NET "GPIF_D[22]" LOC = M19;
+NET "GPIF_D[23]" LOC = K22;
+NET "GPIF_D[24]" LOC = J20;
+NET "GPIF_D[25]" LOC = L22;
+NET "GPIF_D[26]" LOC = K19;
+NET "GPIF_D[27]" LOC = H22;
+NET "GPIF_D[28]" LOC = J22;
+NET "GPIF_D[29]" LOC = K20;
+NET "GPIF_D[30]" LOC = G22;
+NET "GPIF_D[31]" LOC = F22;
+
+## GPS
+
+NET "gps_lock" LOC = Y17;
+NET "gps_out_enable" LOC = V22;
+NET "gps_ref_enable" LOC = AB13;
+NET "gps_rxd" LOC = AB14;
+NET "gps_txd" LOC = W12;
+NET "gps_txd_nmea" LOC = AA14;
+
+## LEDS
+
+NET "LED_RX1" LOC = C22;
+NET "LED_RX2" LOC = L15;
+NET "LED_TXRX1_TX" LOC = C20;
+NET "LED_TXRX2_RX" LOC = D21;
+NET "LED_TXRX1_RX" LOC = K16;
+NET "LED_TXRX2_TX" LOC = D22;
+
+## Misc Hardware Control
+
+NET "ext_ref_enable" LOC = Y15;
+NET "pll_lock" LOC = AB10;
+NET "AUX_PWR_ON" LOC = AA21;
+#NET "RFUSE"  LOC = "P15"  ;
+
+## PPS
+
+NET "pps_fpga_out_enable" LOC = AB15;
+NET "PPS_IN_EXT" LOC = AB16;
+NET "PPS_IN_INT" LOC = AB21;
+NET "pps_out" LOC = AB17;
+
+## RF Hardware Control
+
+NET "SFDX1_RX" LOC = W4;
+NET "SFDX1_TX" LOC = T18;
+NET "SFDX2_RX" LOC = F18;
+NET "SFDX2_TX" LOC = H17;
+NET "SRX1_RX" LOC = Y7;
+NET "SRX1_TX" LOC = AA8;
+NET "SRX2_RX" LOC = J17;
+NET "SRX2_TX" LOC = F19;
+NET "tx_bandsel_a" LOC = N16;
+NET "tx_bandsel_b" LOC = M16;
+NET "tx_enable1" LOC = Y4;
+NET "tx_enable2" LOC = R19;
+NET "rx_bandsel_a" LOC = T20;
+NET "rx_bandsel_b" LOC = U19;
+NET "rx_bandsel_c" LOC = P20;
+
+## FPGA Config Pins
+
+#NET "FPGA_CFG_INIT_B"  LOC = "T6"  ;
+#NET "FPGA_CFG_DONE"  LOC = "Y22"  ;
+#NET "FPGA_CFG_M0"  LOC = "AA22"  ;
+#NET "FPGA_CFG_M1"  LOC = "U15"  ;
+#NET "FPGA_CFG_PROG_B"  LOC = "AA1"  ;
+
+## Special Pins
+
+#NET "VFS"  LOC = "P16"  ;
+#NET "TMS"  LOC = "C18"  ;
+#NET "TDO"  LOC = "A19"  ;
+#NET "TDI"  LOC = "E18"  ;
+#NET "TCK"  LOC = "G15"  ;
+#NET "GND"  LOC = "N15"  ;
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/timing.ucf b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/timing.ucf
new file mode 100644
index 000000000..907b97539
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/timing.ucf
@@ -0,0 +1,85 @@
+
+# codec_main_clk is 40 MHz main tcxo clock
+NET "codec_main_clk*" TNM_NET = "codec_main_clk";
+TIMESPEC TS_codec_main_clk = PERIOD "codec_main_clk" 25000 ps HIGH 50 %;
+
+
+# IFCLK is 100 MHz GPIF clock
+NET "IFCLK" TNM_NET = "IFCLK";
+TIMESPEC TS_IFCLK = PERIOD "IFCLK" 10000 ps HIGH 50 %;
+
+
+# codec_data_clk is the data clock from catalina, sample rate dependent
+# this clock equals sample rate in CMOS DDR 1R1T mode
+# this clock is double the sample rate in CMOS DDR 2R2T mode
+# Max clock rate is 61.44 MHz
+NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p";
+TIMESPEC TS_codec_data_clk_p = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %;
+
+
+#always use IOB for GPIF pins for awesome timing
+INST "GPIF_D_9_IOBUF" IOB =TRUE;
+INST "GPIF_D_8_IOBUF" IOB =TRUE;
+INST "GPIF_D_7_IOBUF" IOB =TRUE;
+INST "GPIF_D_6_IOBUF" IOB =TRUE;
+INST "GPIF_D_5_IOBUF" IOB =TRUE;
+INST "GPIF_D_4_IOBUF" IOB =TRUE;
+INST "GPIF_D_3_IOBUF" IOB =TRUE;
+INST "GPIF_D_31_IOBUF" IOB =TRUE;
+INST "GPIF_D_30_IOBUF" IOB =TRUE;
+INST "GPIF_D_2_IOBUF" IOB =TRUE;
+INST "GPIF_D_29_IOBUF" IOB =TRUE;
+INST "GPIF_D_28_IOBUF" IOB =TRUE;
+INST "GPIF_D_27_IOBUF" IOB =TRUE;
+INST "GPIF_D_26_IOBUF" IOB =TRUE;
+INST "GPIF_D_25_IOBUF" IOB =TRUE;
+INST "GPIF_D_24_IOBUF" IOB =TRUE;
+INST "GPIF_D_23_IOBUF" IOB =TRUE;
+INST "GPIF_D_22_IOBUF" IOB =TRUE;
+INST "GPIF_D_21_IOBUF" IOB =TRUE;
+INST "GPIF_D_20_IOBUF" IOB =TRUE;
+INST "GPIF_D_1_IOBUF" IOB =TRUE;
+INST "GPIF_CTL0_OBUF" IOB =TRUE;
+INST "GPIF_CTL11_OBUF" IOB =TRUE;
+INST "GPIF_CTL12_OBUF" IOB =TRUE;
+INST "GPIF_CTL1_OBUF" IOB =TRUE;
+INST "GPIF_CTL2_OBUF" IOB =TRUE;
+INST "GPIF_CTL3_OBUF" IOB =TRUE;
+INST "GPIF_CTL4_IBUF" IOB =TRUE;
+INST "GPIF_CTL5_IBUF" IOB =TRUE;
+INST "GPIF_CTL7_OBUF" IOB =TRUE;
+INST "GPIF_CTL9_IBUF" IOB =TRUE;
+INST "GPIF_D_0_IOBUF" IOB =TRUE;
+INST "GPIF_D_10_IOBUF" IOB =TRUE;
+INST "GPIF_D_11_IOBUF" IOB =TRUE;
+INST "GPIF_D_12_IOBUF" IOB =TRUE;
+INST "GPIF_D_13_IOBUF" IOB =TRUE;
+INST "GPIF_D_14_IOBUF" IOB =TRUE;
+INST "GPIF_D_15_IOBUF" IOB =TRUE;
+INST "GPIF_D_16_IOBUF" IOB =TRUE;
+INST "GPIF_D_17_IOBUF" IOB =TRUE;
+INST "GPIF_D_18_IOBUF" IOB =TRUE;
+INST "GPIF_D_19_IOBUF" IOB =TRUE;
+
+# TODO not working... constraints ignored
+
+#constrain FX3 IO
+INST "GPIF_D[*]" TNM = "gpif_net_out";
+INST "GPIF_D[*]" TNM = "gpif_net_in";
+INST "GPIF_CTL0" TNM = "gpif_net_out";
+INST "GPIF_CTL1" TNM = "gpif_net_out";
+INST "GPIF_CTL2" TNM = "gpif_net_out";
+INST "GPIF_CTL3" TNM = "gpif_net_out";
+INST "GPIF_CTL4" TNM = "gpif_net_in";
+INST "GPIF_CTL5" TNM = "gpif_net_in";
+INST "GPIF_CTL6" TNM = gpif_net_in;
+INST "GPIF_CTL7" TNM = "gpif_net_out";
+INST "GPIF_CTL8" TNM = gpif_net_in;
+INST "GPIF_CTL11" TNM = "gpif_net_out";
+INST "GPIF_CTL12" TNM = "gpif_net_out";
+
+#NET "gpif_clk" TNM_NET = "TNM_gpif_clk";
+#OFFSET = OUT 5 ns AFTER "gpif_clk";
+#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %;
+#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING;
+#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING;
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.map.begin.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.map.begin.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.map.end.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.map.end.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.ngdbuild.begin.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.ngdbuild.begin.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.ngdbuild.end.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.ngdbuild.end.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.par.begin.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.par.begin.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.par.end.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.par.end.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.trce.begin.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.trce.begin.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.trce.end.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.trce.end.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.xdl.begin.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.xdl.begin.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.xdl.end.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.xdl.end.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.js b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.js
new file mode 100644
index 000000000..72d04e50d
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.js
@@ -0,0 +1,196 @@
+//
+//  PlanAhead(TM)
+//  ISEWrap.js: ExploreAhead Script for WSH 5.1/5.6
+//  Copyright 1986-1999, 2001-2010 Xilinx, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+	       ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+			    "\" Owner=\"" + ISEUser + 
+			    "\" Host=\"" + ISEHost + 
+			    "\" Pid=\"" + ISEPid +
+			    "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  return ISEFileSys.OpenTextFile( ISEFullPath, 8, true );
+}
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.sh b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.sh
new file mode 100755
index 000000000..4ebc95977
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.sh
@@ -0,0 +1,62 @@
+#!/bin/sh
+
+#
+#  PlanAhead(TM)
+#  ISEWrap.sh: ExploreAhead Script for UNIX
+#  Copyright 1986-1999, 2001-2010 Xilinx, Inc. All Rights Reserved. 
+#
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+if [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+ISE_USER=$USER
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.edf b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.edf
new file mode 100644
index 000000000..6fe23b7b5
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.edf
@@ -0,0 +1,51815 @@
+(edif b200
+  (edifversion 2 0 0)
+  (edifLevel 0)
+  (keywordmap (keywordlevel 0))
+(status
+ (written
+  (timeStamp 2013 01 29 17 25 56)
+  (program "PlanAhead" (version "14.4"))
+  (comment "Built on 'Tue Dec 18 05:17:28 MST 2012'")
+  (comment "Built by 'xbuild'")
+ )
+)
+  (Library hdi_primitives
+    (edifLevel 0)
+    (technology (numberDefinition ))
+   (cell FDRE (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port Q (direction OUTPUT))
+        (port C (direction INPUT))
+        (port CE (direction INPUT))
+        (port D (direction INPUT))
+        (port R (direction INPUT))
+       )
+     )
+   )
+   (cell MUXCY (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port O (direction OUTPUT))
+        (port CI (direction INPUT))
+        (port DI (direction INPUT))
+        (port S (direction INPUT))
+       )
+     )
+   )
+   (cell LUT2 (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port O (direction OUTPUT))
+        (port I0 (direction INPUT))
+        (port I1 (direction INPUT))
+       )
+     )
+   )
+   (cell LUT3 (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port O (direction OUTPUT))
+        (port I0 (direction INPUT))
+        (port I1 (direction INPUT))
+        (port I2 (direction INPUT))
+       )
+     )
+   )
+   (cell SRLC32E (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port Q (direction OUTPUT))
+        (port Q31 (direction OUTPUT))
+        (port CE (direction INPUT))
+        (port CLK (direction INPUT))
+        (port D (direction INPUT))
+        (port (array (rename A "A[4:0]") 5) (direction INPUT))
+       )
+     )
+   )
+   (cell XORCY (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port O (direction OUTPUT))
+        (port CI (direction INPUT))
+        (port LI (direction INPUT))
+       )
+     )
+   )
+   (cell OBUF (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port O (direction OUTPUT))
+        (port I (direction INPUT))
+       )
+     )
+   )
+   (cell FD (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port Q (direction OUTPUT))
+        (port C (direction INPUT))
+        (port D (direction INPUT))
+       )
+     )
+   )
+   (cell ODDR2 (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port Q (direction OUTPUT))
+        (port C0 (direction INPUT))
+        (port C1 (direction INPUT))
+        (port CE (direction INPUT))
+        (port D0 (direction INPUT))
+        (port D1 (direction INPUT))
+        (port R (direction INPUT))
+        (port S (direction INPUT))
+       )
+     )
+   )
+   (cell IOBUF (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port O (direction OUTPUT))
+        (port I (direction INPUT))
+        (port T (direction INPUT))
+        (port IO (direction INOUT))
+       )
+     )
+   )
+   (cell LUT6 (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port O (direction OUTPUT))
+        (port I0 (direction INPUT))
+        (port I1 (direction INPUT))
+        (port I2 (direction INPUT))
+        (port I3 (direction INPUT))
+        (port I4 (direction INPUT))
+        (port I5 (direction INPUT))
+       )
+     )
+   )
+   (cell RAMB16BWER (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port CLKA (direction INPUT))
+        (port CLKB (direction INPUT))
+        (port ENA (direction INPUT))
+        (port ENB (direction INPUT))
+        (port REGCEA (direction INPUT))
+        (port REGCEB (direction INPUT))
+        (port RSTA (direction INPUT))
+        (port RSTB (direction INPUT))
+        (port (array (rename DOA "DOA[31:0]") 32) (direction OUTPUT))
+        (port (array (rename DOB "DOB[31:0]") 32) (direction OUTPUT))
+        (port (array (rename DOPA "DOPA[3:0]") 4) (direction OUTPUT))
+        (port (array (rename DOPB "DOPB[3:0]") 4) (direction OUTPUT))
+        (port (array (rename ADDRA "ADDRA[13:0]") 14) (direction INPUT))
+        (port (array (rename ADDRB "ADDRB[13:0]") 14) (direction INPUT))
+        (port (array (rename DIA "DIA[31:0]") 32) (direction INPUT))
+        (port (array (rename DIB "DIB[31:0]") 32) (direction INPUT))
+        (port (array (rename DIPA "DIPA[3:0]") 4) (direction INPUT))
+        (port (array (rename DIPB "DIPB[3:0]") 4) (direction INPUT))
+        (port (array (rename WEA "WEA[3:0]") 4) (direction INPUT))
+        (port (array (rename WEB "WEB[3:0]") 4) (direction INPUT))
+       )
+     )
+   )
+   (cell LUT1 (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port O (direction OUTPUT))
+        (port I0 (direction INPUT))
+       )
+     )
+   )
+   (cell FDSE (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port Q (direction OUTPUT))
+        (port C (direction INPUT))
+        (port CE (direction INPUT))
+        (port D (direction INPUT))
+        (port S (direction INPUT))
+       )
+     )
+   )
+   (cell LUT4 (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port O (direction OUTPUT))
+        (port I0 (direction INPUT))
+        (port I1 (direction INPUT))
+        (port I2 (direction INPUT))
+        (port I3 (direction INPUT))
+       )
+     )
+   )
+   (cell LUT5 (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port O (direction OUTPUT))
+        (port I0 (direction INPUT))
+        (port I1 (direction INPUT))
+        (port I2 (direction INPUT))
+        (port I3 (direction INPUT))
+        (port I4 (direction INPUT))
+       )
+     )
+   )
+   (cell FDR (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port Q (direction OUTPUT))
+        (port C (direction INPUT))
+        (port D (direction INPUT))
+        (port R (direction INPUT))
+       )
+     )
+   )
+   (cell FDE (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port Q (direction OUTPUT))
+        (port C (direction INPUT))
+        (port CE (direction INPUT))
+        (port D (direction INPUT))
+       )
+     )
+   )
+   (cell IBUFG (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port O (direction OUTPUT))
+        (port I (direction INPUT))
+       )
+     )
+   )
+   (cell MUXF7 (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port O (direction OUTPUT))
+        (port I0 (direction INPUT))
+        (port I1 (direction INPUT))
+        (port S (direction INPUT))
+       )
+     )
+   )
+   (cell RAMB8BWER (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port CLKAWRCLK (direction INPUT))
+        (port CLKBRDCLK (direction INPUT))
+        (port ENAWREN (direction INPUT))
+        (port ENBRDEN (direction INPUT))
+        (port REGCEA (direction INPUT))
+        (port REGCEBREGCE (direction INPUT))
+        (port RSTA (direction INPUT))
+        (port RSTBRST (direction INPUT))
+        (port (array (rename DOADO "DOADO[15:0]") 16) (direction OUTPUT))
+        (port (array (rename DOBDO "DOBDO[15:0]") 16) (direction OUTPUT))
+        (port (array (rename DOPADOP "DOPADOP[1:0]") 2) (direction OUTPUT))
+        (port (array (rename DOPBDOP "DOPBDOP[1:0]") 2) (direction OUTPUT))
+        (port (array (rename ADDRAWRADDR "ADDRAWRADDR[12:0]") 13) (direction INPUT))
+        (port (array (rename ADDRBRDADDR "ADDRBRDADDR[12:0]") 13) (direction INPUT))
+        (port (array (rename DIADI "DIADI[15:0]") 16) (direction INPUT))
+        (port (array (rename DIBDI "DIBDI[15:0]") 16) (direction INPUT))
+        (port (array (rename DIPADIP "DIPADIP[1:0]") 2) (direction INPUT))
+        (port (array (rename DIPBDIP "DIPBDIP[1:0]") 2) (direction INPUT))
+        (port (array (rename WEAWEL "WEAWEL[1:0]") 2) (direction INPUT))
+        (port (array (rename WEBWEU "WEBWEU[1:0]") 2) (direction INPUT))
+       )
+     )
+   )
+   (cell BUFG (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port O (direction OUTPUT))
+        (port I (direction INPUT))
+       )
+     )
+   )
+   (cell IBUFGDS (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port O (direction OUTPUT))
+        (port I (direction INPUT))
+        (port IB (direction INPUT))
+       )
+     )
+   )
+   (cell FDS (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port Q (direction OUTPUT))
+        (port C (direction INPUT))
+        (port D (direction INPUT))
+        (port S (direction INPUT))
+       )
+     )
+   )
+   (cell FDP (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port Q (direction OUTPUT))
+        (port C (direction INPUT))
+        (port D (direction INPUT))
+        (port PRE (direction INPUT))
+       )
+     )
+   )
+   (cell GND (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port G (direction OUTPUT))
+       )
+     )
+   )
+   (cell IBUF (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port O (direction OUTPUT))
+        (port I (direction INPUT))
+       )
+     )
+   )
+   (cell VCC (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port P (direction OUTPUT))
+       )
+     )
+   )
+   (cell DCM_SP (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface 
+        (port CLK0 (direction OUTPUT))
+        (port CLK180 (direction OUTPUT))
+        (port CLK270 (direction OUTPUT))
+        (port CLK2X (direction OUTPUT))
+        (port CLK2X180 (direction OUTPUT))
+        (port CLK90 (direction OUTPUT))
+        (port CLKDV (direction OUTPUT))
+        (port CLKFX (direction OUTPUT))
+        (port CLKFX180 (direction OUTPUT))
+        (port LOCKED (direction OUTPUT))
+        (port PSDONE (direction OUTPUT))
+        (port CLKFB (direction INPUT))
+        (port CLKIN (direction INPUT))
+        (port DSSEN (direction INPUT))
+        (port PSCLK (direction INPUT))
+        (port PSEN (direction INPUT))
+        (port PSINCDEC (direction INPUT))
+        (port RST (direction INPUT))
+        (port (array (rename STATUS "STATUS[7:0]") 8) (direction OUTPUT))
+       )
+     )
+   )
+   (cell INV (celltype GENERIC)
+     (view netlist (viewtype NETLIST)
+       (interface
+         (port I (direction INPUT))
+         (port O (direction OUTPUT))
+       )
+     )
+   )
+  )
+  (Library b200_lib
+    (edifLevel 0)
+    (technology (numberDefinition ))
+   (cell fifo_4k_2clk (celltype GENERIC)
+     (view view_1 (viewtype NETLIST)
+       (interface 
+        (port rst (direction INPUT))
+        (port wr_clk (direction INPUT))
+        (port rd_clk (direction INPUT))
+        (port wr_en (direction INPUT))
+        (port rd_en (direction INPUT))
+        (port full (direction OUTPUT))
+        (port empty (direction OUTPUT))
+        (port (array (rename din "din[71:0]") 72) (direction INPUT))
+        (port (array (rename dout "dout[71:0]") 72) (direction OUTPUT))
+        (port (array (rename rd_data_count "rd_data_count[9:0]") 10) (direction OUTPUT))
+        (port (array (rename wr_data_count "wr_data_count[9:0]") 10) (direction OUTPUT))
+       )
+     )
+   )
+   (cell b200 (celltype GENERIC)
+     (view view_1 (viewtype NETLIST)
+       (interface 
+        (port cat_miso (direction INPUT))
+        (port fx3_ce (direction INPUT))
+        (port fx3_mosi (direction INPUT))
+        (port fx3_sclk (direction INPUT))
+        (port FPGA_RXD0 (direction INPUT))
+        (port FPGA_TXD0 (direction INPUT))
+        (port SCL_FPGA (direction INPUT))
+        (port SDA_FPGA (direction INPUT))
+        (port codec_data_clk_p (direction INPUT))
+        (port rx_frame_p (direction INPUT))
+        (port cat_clkout_fpga (direction INPUT))
+        (port codec_main_clk_p (direction INPUT))
+        (port codec_main_clk_n (direction INPUT))
+        (port GPIF_CTL4 (direction INPUT))
+        (port GPIF_CTL5 (direction INPUT))
+        (port GPIF_CTL6 (direction INPUT))
+        (port GPIF_CTL8 (direction INPUT))
+        (port GPIF_CTL9 (direction INPUT))
+        (port gps_lock (direction INPUT))
+        (port gps_rxd (direction INPUT))
+        (port gps_txd (direction INPUT))
+        (port gps_txd_nmea (direction INPUT))
+        (port pll_lock (direction INPUT))
+        (port FPGA_CFG_CS (direction INPUT))
+        (port AUX_PWR_ON (direction INPUT))
+        (port PPS_IN_EXT (direction INPUT))
+        (port PPS_IN_INT (direction INPUT))
+        (port pps_out (direction INPUT))
+        (port cat_ce (direction OUTPUT))
+        (port cat_mosi (direction OUTPUT))
+        (port cat_sclk (direction OUTPUT))
+        (port fx3_miso (direction OUTPUT))
+        (port pll_ce (direction OUTPUT))
+        (port pll_mosi (direction OUTPUT))
+        (port pll_sclk (direction OUTPUT))
+        (port codec_enable (direction OUTPUT))
+        (port codec_en_agc (direction OUTPUT))
+        (port codec_reset (direction OUTPUT))
+        (port codec_sync (direction OUTPUT))
+        (port codec_txrx (direction OUTPUT))
+        (port codec_fb_clk_p (direction OUTPUT))
+        (port tx_frame_p (direction OUTPUT))
+        (port IFCLK (direction OUTPUT))
+        (port FX3_EXTINT (direction OUTPUT))
+        (port GPIF_CTL0 (direction OUTPUT))
+        (port GPIF_CTL1 (direction OUTPUT))
+        (port GPIF_CTL2 (direction OUTPUT))
+        (port GPIF_CTL3 (direction OUTPUT))
+        (port GPIF_CTL7 (direction OUTPUT))
+        (port GPIF_CTL11 (direction OUTPUT))
+        (port GPIF_CTL12 (direction OUTPUT))
+        (port gps_out_enable (direction OUTPUT))
+        (port gps_ref_enable (direction OUTPUT))
+        (port LED_RX1 (direction OUTPUT))
+        (port LED_RX2 (direction OUTPUT))
+        (port LED_TXRX1_RX (direction OUTPUT))
+        (port LED_TXRX1_TX (direction OUTPUT))
+        (port LED_TXRX2_RX (direction OUTPUT))
+        (port LED_TXRX2_TX (direction OUTPUT))
+        (port ext_ref_enable (direction OUTPUT))
+        (port pps_fpga_out_enable (direction OUTPUT))
+        (port SFDX1_RX (direction OUTPUT))
+        (port SFDX1_TX (direction OUTPUT))
+        (port SFDX2_RX (direction OUTPUT))
+        (port SFDX2_TX (direction OUTPUT))
+        (port SRX1_RX (direction OUTPUT))
+        (port SRX1_TX (direction OUTPUT))
+        (port SRX2_RX (direction OUTPUT))
+        (port SRX2_TX (direction OUTPUT))
+        (port tx_bandsel_a (direction OUTPUT))
+        (port tx_bandsel_b (direction OUTPUT))
+        (port tx_enable1 (direction OUTPUT))
+        (port tx_enable2 (direction OUTPUT))
+        (port rx_bandsel_a (direction OUTPUT))
+        (port rx_bandsel_b (direction OUTPUT))
+        (port rx_bandsel_c (direction OUTPUT))
+        (port (array (rename codec_ctrl_out "codec_ctrl_out[7:0]") 8) (direction INPUT))
+        (port (array (rename rx_codec_d "rx_codec_d[11:0]") 12) (direction INPUT))
+        (port (array (rename codec_ctrl_in "codec_ctrl_in[3:0]") 4) (direction OUTPUT))
+        (port (array (rename tx_codec_d "tx_codec_d[11:0]") 12) (direction OUTPUT))
+        (port (array (rename debug "debug[31:0]") 32) (direction OUTPUT))
+        (port (array (rename debug_clk "debug_clk[1:0]") 2) (direction OUTPUT))
+        (port (array (rename GPIF_D "GPIF_D[31:0]") 32) (direction INOUT))
+       )
+       (contents
+         (instance (rename f1_Result_7_2_FRB "f1/Result<7>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Result_11_2_FRB "f1/Result<11>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcompar_becoming_full_cy_2_ "f1/Mcompar_becoming_full_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___120___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata341 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata341") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___111___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata291"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata291 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata291") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___111___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata291"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[20].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[15].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[43].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[38].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Mcompar_becoming_full_cy_3_ "f1/Mcompar_becoming_full_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata401 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata401") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___108___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata510"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata351 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata351") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___85___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata351"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance debug_23_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance debug_18_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata410 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata410") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___109___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata410"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename f1_Mcompar_becoming_full_cy_4_ "f1/Mcompar_becoming_full_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata411 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___107___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata65"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata361 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata361") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___84___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata361"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_GND_14_o_read_OR_37_o1 "f1/GND_14_o_read_OR_37_o1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___31___f1/GND_14_o_read_OR_37_o1"))
+           (property INIT (string "8'h72"))
+         )
+         (instance (rename slave_fifo32_debug1_0 "slave_fifo32/debug1_0") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_wr_addr_xor_10_ "f0/Mcount_wr_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_debug1_1 "slave_fifo32/debug1_1") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata421 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata421") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___106___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata71"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata371 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata371") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___110___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata210"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_debug1_2 "slave_fifo32/debug1_2") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_debug1_3 "slave_fifo32/debug1_3") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug1_4 "slave_fifo32/debug1_4") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug1_5 "slave_fifo32/debug1_5") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_wr_addr_xor_11_ "f0/Mcount_wr_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_debug1_6 "slave_fifo32/debug1_6") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata431 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata431") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___105___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata81"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata381 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata381") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___82___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata310"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_debug1_7 "slave_fifo32/debug1_7") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_debug1_8 "slave_fifo32/debug1_8") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug1_9 "slave_fifo32/debug1_9") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[17].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[22].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f0_Mcount_wr_addr_xor_12_ "f0/Mcount_wr_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata391 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata391") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___109___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata410"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata441 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata441") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___104___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata91"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename catgen_gen_pins_4__oddr2 "catgen/gen_pins[4].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "C0"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata501 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata501") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___98___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata151"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata451 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata451") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___103___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata301"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___134___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata510 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata510") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___108___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata510"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata461 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata461") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___102___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata101"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___169___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11"))
+           (property INIT (string "8'hC8"))
+         )
+         (instance (rename f1_dont_write_past_me_1__FRB "f1/dont_write_past_me<1>_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata511 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata511") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___97___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata161"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_1_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_sloe_rstpot "slave_fifo32/sloe_rstpot") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_debug2_0 "slave_fifo32/debug2_0") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___134___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_debug2_1 "slave_fifo32/debug2_1") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In12_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In12_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___47___slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/read1"))
+           (property INIT (string "4'hD"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata521 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata521") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___96___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata171"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata471 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata471") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___101___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata111"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[18].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[23].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_debug2_2 "slave_fifo32/debug2_2") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[46].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[51].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_debug2_3 "slave_fifo32/debug2_3") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_debug2_4 "slave_fifo32/debug2_4") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug2_5 "slave_fifo32/debug2_5") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___133___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug2_6 "slave_fifo32/debug2_6") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata531 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata531") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___95___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata181"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata481 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata481") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___100___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata131"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug2_7 "slave_fifo32/debug2_7") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_Mcount_fifoadr_xor_1_11 "slave_fifo32/Mcount_fifoadr_xor<1>11") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___42___slave_fifo32/Mcount_fifoadr_xor<1>11"))
+           (property INIT (string "4'h6"))
+         )
+         (instance (rename slave_fifo32_debug2_8 "slave_fifo32/debug2_8") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug2_9 "slave_fifo32/debug2_9") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT131") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___133___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata541 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata541") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___94___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata191"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata491 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata491") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___99___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata141"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_read_ready_go "slave_fifo32/read_ready_go") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_sloe_1_rstpot "slave_fifo32/sloe_1_rstpot") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAAAA2AAAAAAAFFAA"))
+         )
+         (instance debug_19_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance debug_24_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tready1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0111111111111111"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___132___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata601 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata601") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___88___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata251"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata551 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata551") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___93___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata201"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_13") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_14") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___117___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11"))
+           (property INIT (string "8'h69"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_15") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT151") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___132___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata561 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata561") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___92___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata311"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata611 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata611") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___87___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata321"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[25].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[30].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT161") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata571 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata571") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___91___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata211"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata621 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata621") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___86___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata331"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram3") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
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+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram4") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram5") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram6") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_lut_5__INV_0 "f1/Msub_dont_write_past_me_lut<5>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram7") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata631 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata631") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___85___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata351"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata581 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata581") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___90___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata221"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram8") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram9") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata591 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata591") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___89___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata241"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata641 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata641") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___84___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata361"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___38___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1"))
+           (property INIT (string "4'h6"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[26].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[31].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[54].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[49].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_dont_write_past_me_2__FRB "f1/dont_write_past_me<2>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFBFBFBFFFB00FB00"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[33].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[28].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance debug_30_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance debug_25_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<3>1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h6"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[34].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[29].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[57].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[62].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_EP_READY1 "slave_fifo32/EP_READY1") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<5>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_dont_write_past_me_3__FRB "f1/dont_write_past_me<3>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_EP_READY "slave_fifo32/EP_READY") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_cy_0__rt "f1/Msub_dont_write_past_me_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[36].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9CCC9CC6CCCCCCC6"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[41].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_i_tready1 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/i_tready1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___170___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/i_tready1"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___119___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set"))
+           (property INIT (string "16'hFFA2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[1].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance debug_26_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance debug_31_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_i_tvalid_int1_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'h8000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<5>1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h999A999999959999"))
+         )
+         (instance (rename f0_Result_8_2_FRB "f0/Result<8>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv1_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[37].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[42].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<10>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<11>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f1_dont_write_past_me_4__FRB "f1/dont_write_past_me<4>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___16___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1"))
+           (property INIT (string "16'h5400"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<12>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[39].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata65 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata65") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___75___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata65"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[44].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata71 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___74___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata71"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_6_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<6>1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h6"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0001FFFF00007FFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[4].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata81 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___73___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata81"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<2>11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___11___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11"))
+           (property INIT (string "16'h6AA9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata91 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata91") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___72___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata91"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___46___slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1"))
+           (property INIT (string "16'h0455"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[45].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance debug_27_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[50].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_20_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_15_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv6_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___124___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0"))
+           (property INIT (string "16'hEEEF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_rd_addr_0 "f1/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_rd_addr_1 "f1/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_rd_addr_2 "f1/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_rd_addr_3 "f1/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_rd_addr_4 "f1/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_lut_8__INV_0 "f0/Msub_dont_write_past_me_lut<8>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_rd_addr_5 "f1/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_rd_addr_6 "f1/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_rd_addr_7 "f1/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___4___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1"))
+           (property INIT (string "16'h0455"))
+         )
+         (instance (rename f1_rd_addr_8 "f1/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_rd_addr_9 "f1/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr10_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr10_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_10__rt "f0/Mcount_wr_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[52].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance SRX1_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[47].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[7].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_dont_write_past_me_5__FRB "f1/dont_write_past_me<5>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_1__rt "f1/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAAAAAAAAAAAAAAA9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h01FE00FF00FF807F"))
+         )
+         (instance (rename f1_Mcount_wr_addr_xor_12__rt "f1/Mcount_wr_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/GND_56_o_read_OR_123_o1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___171___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Result_8_2_FRB "f1/Result<8>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance cat_sclk_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/fifo_4k_2clk") (viewref view_1 (cellref fifo_4k_2clk (libraryref b200_lib)))
+           (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>"))
+         )
+         (instance (rename f1_Result_12_2_FRB "f1/Result<12>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[53].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[48].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance debug_28_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[2].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFF7FFFFFFFFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_5__rt "f0/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance ODDR2_ifclk_dbg (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "NONE"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[55].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[60].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_Mcount_idle_cycles_xor_0_11 "slave_fifo32/Mcount_idle_cycles_xor<0>11") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___177___slave_fifo32/Mcount_idle_cycles_xor<0>11"))
+           (property INIT (string "4'h1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0000000000000001"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<10>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB4BBBBBBB4BBB4B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___130___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename f1_Mcount_wr_addr_xor_10_ "f1/Mcount_wr_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_dont_write_past_me_6__FRB "f1/dont_write_past_me<6>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance SRX2_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<11>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB4BBBBBBB4BBB4B"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_6__rt "f1/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance GPIF_D_2_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[56].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[61].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___130___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename f1_Mcount_wr_addr_xor_11_ "f1/Mcount_wr_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_cy_10_ "f1/Msub_dont_write_past_me_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<12>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB4BBBBBBB4BBB4B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram3") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___129___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram4") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_Mcount_wr_addr_xor_12_ "f1/Mcount_wr_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram5") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_cy_11_ "f1/Msub_dont_write_past_me_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<13>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB4BBBBBBB4BBB4B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram6") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram7") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram8") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram9") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT131") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___129___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_0_ "f0/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[5].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB4BBBBBBB4BBB4B"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_11__rt "f1/Mcount_wr_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance debug_29_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___128___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_1_ "f0/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<15>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB4BBBBBBB4BBB4B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata101 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata101") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___146___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata101"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[58].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT151") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___128___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[63].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32__n0223_inv1 "slave_fifo32/_n0223_inv1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___21___slave_fifo32/_n0223_inv1"))
+           (property INIT (string "8'h82"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_2_ "f0/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata110") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___151___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata110"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata111 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata111") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___146___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata101"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT161") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_3_ "f0/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata121 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata121") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___145___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata121"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hAC"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_4_ "f0/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9CCC9CC6CCCCCCC6"))
+         )
+         (instance (rename slave_fifo32__n0279_inv_SW0 "slave_fifo32/_n0279_inv_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___121___slave_fifo32/_n0258_inv_SW0"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<3>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h00400000AAEAAAAA"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata131 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata131") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___145___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata121"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hAC"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_5_ "f0/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[59].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[64].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata141 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata141") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___144___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata141"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___11___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11"))
+           (property INIT (string "32'h6AAAAAA9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<0>11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_6_ "f0/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_dont_write_past_me_7__FRB "f1/dont_write_past_me<7>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata151 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata151") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___144___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata141"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata201 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata201") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___141___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata201"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_slrd1 "slave_fifo32/slrd1") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_slrd2 "slave_fifo32/slrd2") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_slrd3 "slave_fifo32/slrd3") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_7_ "f0/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata210 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata210") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___151___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata110"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata161 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata161") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___143___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata161"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata211 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata211") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___141___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata201"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_o_tlast1 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/o_tlast1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___170___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/i_tready1"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[8].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_8_ "f0/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata171 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata171") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___143___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata161"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_0 "slave_fifo32/gpif_data_out_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata221 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata221") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___140___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata221"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_1 "slave_fifo32/gpif_data_out_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_2 "slave_fifo32/gpif_data_out_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_9_ "f0/Mcount_rd_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_3 "slave_fifo32/gpif_data_out_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_4 "slave_fifo32/gpif_data_out_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata231 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata231") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___140___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata221"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_5 "slave_fifo32/gpif_data_out_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename f0__n0161_inv1_cy1 "f0/_n0161_inv1_cy1") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata181 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata181") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___142___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata181"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_6 "slave_fifo32/gpif_data_out_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_7 "slave_fifo32/gpif_data_out_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT33") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_8 "slave_fifo32/gpif_data_out_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___7___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0"))
+           (property INIT (string "32'hFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32__n0279_inv "slave_fifo32/_n0279_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0020202008282828"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_9 "slave_fifo32/gpif_data_out_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata191 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata191") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___142___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata181"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata241 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata241") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___139___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata241"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT41 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT41") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata251 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata251") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___139___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata241"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata301 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata301") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___147___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata91"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT51 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT51") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___32___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata261 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata261") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___138___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata261"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___32___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0"))
+           (property INIT (string "16'hF110"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata311 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata311") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___136___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata311"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT61 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT61") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata321 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata321") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___136___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata311"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata271 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata271") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___138___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata261"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT71 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT71") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata281 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata281") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___137___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata281"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT81 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT81") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<1>11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h69"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata291 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata291") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___137___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata281"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f1_dont_write_past_me_8__FRB "f1/dont_write_past_me<8>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT91 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT91") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___42___slave_fifo32/Mcount_fifoadr_xor<1>11"))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_cy") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_10__rt "f1/Mcount_rd_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_dont_write_past_me_10__FRB "f1/dont_write_past_me<10>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[10].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32__n0230_inv1 "slave_fifo32/_n0230_inv1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___48___slave_fifo32/_n0230_inv1"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int16_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'hEFFF"))
+         )
+         (instance (rename f0_Result_9_2_FRB "f0/Result<9>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_GND_14_o_read_OR_37_o1 "f0/GND_14_o_read_OR_37_o1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___30___f0/GND_14_o_read_OR_37_o1"))
+           (property INIT (string "8'h72"))
+         )
+         (instance (rename slave_fifo32_Mcount_idle_cycles_xor_1_11 "slave_fifo32/Mcount_idle_cycles_xor<1>11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___23___slave_fifo32/Mcount_idle_cycles_xor<2>11"))
+           (property INIT (string "8'h14"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_full_reg "f1/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_rd_addr_xor_12__rt "f0/Mcount_rd_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___2___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0"))
+           (property INIT (string "16'hFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/GND_66_o_read_OR_144_o1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___169___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename catgen_gen_pins_7__oddr2 "catgen/gen_pins[7].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "C0"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_dont_write_past_me_9__FRB "f1/dont_write_past_me<9>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0004FFFF00040004"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_lut_12__INV_0 "f0/Msub_dont_write_past_me_lut<12>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[13].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_dont_write_past_me_11__FRB "f1/dont_write_past_me<11>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'hD"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_0") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd2_BRB0") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance GPIF_D_21_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_16_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd2_BRB1") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_2") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_3") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_4") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_5") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_6") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<4>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h6AAAAAAAAAAAAAA9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_7") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_8") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h8000000000000000"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_lut_8__INV_0 "f1/Msub_dont_write_past_me_lut<8>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename f0__n0161_inv1_lut1 "f0/_n0161_inv1_lut1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'hD"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAAAA2A22FFAA7F22"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[16].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hA2AAA6A6F7FFA6A6"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[21].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty_glue_rst_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFE"))
+         )
+         (instance (rename f1_Result_9_2_FRB "f1/Result<9>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_3__rt "f0/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_dont_write_past_me_12__FRB "f1/dont_write_past_me<12>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tready_int1_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h2F"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_0_ "f1/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_3__rt "f1/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_1_ "f1/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename f1_rd_addr_10 "f1/rd_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_rd_addr_11 "f1/rd_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_2_ "f1/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_rd_addr_12 "f1/rd_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___20___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11"))
+           (property INIT (string "16'h6AA9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance LED_TXRX2_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_3_ "f1/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/clear_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFE"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_4_ "f1/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[19].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[24].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance gps_out_enable_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_5_ "f1/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<8>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_6_ "f1/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance GPIF_D_3_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_0_ "f1/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_7_ "f1/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_8__rt "f0/Mcount_wr_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tlast1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0C0C0C0C0C0D0C0C"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_1_ "f1/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_8_ "f1/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_Mcount_idle_cycles_xor_2_11 "slave_fifo32/Mcount_idle_cycles_xor<2>11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___23___slave_fifo32/Mcount_idle_cycles_xor<2>11"))
+           (property INIT (string "16'h1444"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_2_ "f1/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_9_ "f1/Mcount_rd_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_3_ "f1/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_8__rt "f1/Mcount_wr_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_4_ "f1/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01212") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0010001000000010"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01213") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9090900000900000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01214 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01214") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h99900000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01215") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0220000000000220"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[32].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01216 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01216") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[27].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_5_ "f1/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01217") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0080000000000080"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01218") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___116___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921"))
+           (property INIT (string "16'h0440"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01219 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01219") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFAF8AA0000000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFEFFFF"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_6_ "f1/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr9_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_7_ "f1/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance FX3_EXTINT_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_cy_0_ "f1/Msub_dont_write_past_me_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_8_ "f1/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_31_1 "slave_fifo32/gpif_data_out_31_1") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance codec_data_clk_bufg (viewref netlist (cellref IBUFG (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+           (property IBUF_DELAY_VALUE (string "0"))
+           (property IBUF_LOW_PWR (boolean (true)))
+           (property IOSTANDARD (string "DEFAULT"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_cy_1_ "f1/Msub_dont_write_past_me_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_9_ "f1/Mcount_wr_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01212111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr9_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_cy_2_ "f1/Msub_dont_write_past_me_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tvalid11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___127___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tvalid11"))
+           (property INIT (string "8'hE0"))
+         )
+         (instance (rename f0_read_state_FSM_FFd2_In1 "f0/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFDFDFDFFA8A8A8FF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_cy_3_ "f1/Msub_dont_write_past_me_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_cy_4_ "f1/Msub_dont_write_past_me_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0021FFFF00FFFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_i_tready "slave_fifo32/fifo64_to_gpmc32_ctrl/i_tready") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[40].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[35].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_cy_5_ "f1/Msub_dont_write_past_me_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_read_state_FSM_FFd2_In1 "f1/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFDFDFDFFA8A8A8FF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h1"))
+         )
+         (instance (rename f0__n0161_inv1_lut "f0/_n0161_inv1_lut") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11_SW1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h01"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_cy_6_ "f1/Msub_dont_write_past_me_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_cy_7_ "f1/Msub_dont_write_past_me_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_cy_8_ "f1/Msub_dont_write_past_me_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_slrd2_1 "slave_fifo32/slrd2_1") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1-In111") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___10___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1"))
+           (property INIT (string "16'h7F2A"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_cy_9_ "f1/Msub_dont_write_past_me_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1 "slave_fifo32/ctrl_tx_tready_data_tx_tready_OR_55_o1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'h5410"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_cy_1__rt "f0/Msub_dont_write_past_me_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1 "slave_fifo32/Mmux_state[1]_wr_fifo_eof_Mux_22_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h2A7F7F7FFFFFFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01216_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFF6FFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[43].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[38].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<3>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___20___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11"))
+           (property INIT (string "32'h6AAAAAA9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<12>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h2002000000002002"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012112") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h8822228C80202084"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012113") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename f0_ram_Mram_ram10 "f0/ram/Mram_ram10") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___29___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111"))
+           (property INIT (string "32'hFFAEFFFF"))
+         )
+         (instance (rename f0_Mcount_wr_addr_xor_0_ "f0/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_lut_3__INV_0 "f0/Msub_dont_write_past_me_lut<3>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename f0_ram_Mram_ram11 "f0/ram/Mram_ram11") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___8___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In11"))
+           (property INIT (string "32'h8A8ADF8A"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012114") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB33A820A820A820"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_ram_Mram_ram12 "f0/ram/Mram_ram12") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0000000023003300"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_ram_Mram_ram13 "f0/ram/Mram_ram13") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram14 "f0/ram/Mram_ram14") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv5") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hFB"))
+         )
+         (instance (rename f0_ram_Mram_ram15 "f0/ram/Mram_ram15") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram20 "f0/ram/Mram_ram20") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_Mcount_wr_addr_xor_1_ "f0/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_ram_Mram_ram16 "f0/ram/Mram_ram16") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram21 "f0/ram/Mram_ram21") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFF0C080C0C0C0C"))
+         )
+         (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename f0_ram_Mram_ram17 "f0/ram/Mram_ram17") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram22 "f0/ram/Mram_ram22") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_ram_Mram_ram18 "f0/ram/Mram_ram18") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram23 "f0/ram/Mram_ram23") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_EP_READY1_1 "slave_fifo32/EP_READY1_1") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_ram_Mram_ram24 "f0/ram/Mram_ram24") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram19 "f0/ram/Mram_ram19") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram30 "f0/ram/Mram_ram30") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram25 "f0/ram/Mram_ram25") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_10 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_ram_Mram_ram26 "f0/ram/Mram_ram26") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram31 "f0/ram/Mram_ram31") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_Mcount_wr_addr_xor_2_ "f0/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_ram_Mram_ram27 "f0/ram/Mram_ram27") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram32 "f0/ram/Mram_ram32") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_12 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_ram_Mram_ram28 "f0/ram/Mram_ram28") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram33 "f0/ram/Mram_ram33") (viewref netlist (cellref RAMB8BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "16:OUTPUT:DOBDO<15:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 1))
+           (property DATA_WIDTH_B (integer 1))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "18'h00000"))
+           (property INIT_B (string "18'h00000"))
+           (property RAM_MODE (string "TDP"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "18'h00000"))
+           (property SRVAL_B (string "18'h00000"))
+           (property INIT_FILE (string "NONE"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_ram_Mram_ram29 "f0/ram/Mram_ram29") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_Mcount_wr_addr_xor_3_ "f0/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_wr_addr_xor_4_ "f0/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_wr_addr_xor_5_ "f0/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[51].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[46].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_wr_addr_xor_6_ "f0/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance rx_bandsel_a_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1 "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/read1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___47___slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/read1"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___37___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0154_inv1"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename f0_Mcount_wr_addr_xor_7_ "f0/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_wr_addr_xor_8_ "f0/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___173___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename f0_Mcount_wr_addr_xor_9_ "f0/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_22_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_17_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/read") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0111111111111111"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<6>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance SRX1_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[54].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[49].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h00000001FFFFFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename f1_ram_Mram_ram10 "f1/ram/Mram_ram10") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance rx_bandsel_b_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f1_ram_Mram_ram11 "f1/ram/Mram_ram11") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_ram_Mram_ram12 "f1/ram/Mram_ram12") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_i_tready "slave_fifo32/fifo64_to_gpmc32_tx/i_tready") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_ram_Mram_ram13 "f1/ram/Mram_ram13") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_ram_Mram_ram14 "f1/ram/Mram_ram14") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h5140514055555140"))
+         )
+         (instance (rename f1_ram_Mram_ram15 "f1/ram/Mram_ram15") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_ram_Mram_ram20 "f1/ram/Mram_ram20") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_ram_Mram_ram21 "f1/ram/Mram_ram21") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_ram_Mram_ram16 "f1/ram/Mram_ram16") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_12_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_ram_Mram_ram17 "f1/ram/Mram_ram17") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_ram_Mram_ram22 "f1/ram/Mram_ram22") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_Mcount_rd_addr_xor_12__rt "f1/Mcount_rd_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_ram_Mram_ram23 "f1/ram/Mram_ram23") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_ram_Mram_ram18 "f1/ram/Mram_ram18") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_ram_Mram_ram24 "f1/ram/Mram_ram24") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_ram_Mram_ram19 "f1/ram/Mram_ram19") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_ram_Mram_ram30 "f1/ram/Mram_ram30") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_ram_Mram_ram25 "f1/ram/Mram_ram25") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_ram_Mram_ram31 "f1/ram/Mram_ram31") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_ram_Mram_ram26 "f1/ram/Mram_ram26") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_ram_Mram_ram27 "f1/ram/Mram_ram27") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_ram_Mram_ram32 "f1/ram/Mram_ram32") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_ram_Mram_ram28 "f1/ram/Mram_ram28") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_ram_Mram_ram33 "f1/ram/Mram_ram33") (viewref netlist (cellref RAMB8BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "16:OUTPUT:DOBDO<15:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 1))
+           (property DATA_WIDTH_B (integer 1))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "18'h00000"))
+           (property INIT_B (string "18'h00000"))
+           (property RAM_MODE (string "TDP"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "18'h00000"))
+           (property SRVAL_B (string "18'h00000"))
+           (property INIT_FILE (string "NONE"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+         )
+         (instance (rename f1_ram_Mram_ram29 "f1/ram/Mram_ram29") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32__n0237_inv1 "slave_fifo32/_n0237_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0000000100000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1__n0161_inv1_cy1 "f1/_n0161_inv1_cy1") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_pktend "slave_fifo32/pktend") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+           (property IOB (string "TRUE"))
+         )
+         (instance fx3_miso1 (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___180___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[57].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[62].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 18))
+           (property DATA_WIDTH_B (integer 18))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 18))
+           (property DATA_WIDTH_B (integer 18))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_Mcount_rd_addr_xor_0_ "f1/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___22___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511"))
+           (property INIT (string "32'hBF4040BF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_4_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<4>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h6AAAAAAAAAAAAAA9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___14___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31"))
+           (property INIT (string "32'hFFFF4B44"))
+         )
+         (instance (rename f1_Mcount_rd_addr_xor_1_ "f1/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hE178E1E1E1E1E1E1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance rx_bandsel_c_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_rd_one_rstpot "slave_fifo32/rd_one_rstpot") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f1_Mcount_rd_addr_xor_2_ "f1/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___36___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111"))
+           (property INIT (string "32'h9AAAAAA6"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_9_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_rd_addr_xor_3_ "f1/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAAAA9AAAA6A696A6"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tvalid11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0000FFFF0000FEFF"))
+         )
+         (instance (rename slave_fifo32_slrd_rstpot "slave_fifo32/slrd_rstpot") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAA2AAAFAAA2AFAFA"))
+         )
+         (instance (rename f1_Mcount_rd_addr_xor_4_ "f1/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT61") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h99AA99A6AAAAAAA6"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[0].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Mcount_rd_addr_xor_5_ "f1/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcount_rd_addr_xor_6_ "f1/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFF0040BFBF4000FF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_cy_1__rt "f1/Msub_dont_write_past_me_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_Mcount_rd_addr_xor_7_ "f1/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___4___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1"))
+           (property INIT (string "32'hDFDDFFFF"))
+         )
+         (instance LED_RX1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In12") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFBEEEA55514440"))
+         )
+         (instance (rename f1_Mcount_rd_addr_xor_8_ "f1/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Result_0_1_FRB "f0/Result<0>1_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In14") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAAAAAAAA2A080808"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFC55FC54FF55FF55"))
+         )
+         (instance (rename f1_Mcount_rd_addr_xor_9_ "f1/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___126___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0"))
+           (property INIT (string "16'hCCC9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In31") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In32") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In33") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'hFDFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In34") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFB"))
+         )
+         (instance (rename catgen_gen_pins_10__oddr2 "catgen/gen_pins[10].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "C0"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<11>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_debug1_16_BRB0 "slave_fifo32/debug1_16_BRB0") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[3].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_9_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___124___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0"))
+           (property INIT (string "4'h6"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAAAAAAAAAAAAAAA9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata101 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata101") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___70___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata101"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata110") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___81___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata110"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata111 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___69___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata111"))
+           (property INIT (string "4'h8"))
+         )
+         (instance pll_ce_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata121 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata121") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___80___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata121"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full411") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___19___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421"))
+           (property INIT (string "16'hFEEE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata131 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata131") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___68___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata131"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___19___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421"))
+           (property INIT (string "16'h0111"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___118___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11"))
+           (property INIT (string "16'hFFF9"))
+         )
+         (instance LED_RX2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename catgen_gen_pins_2__oddr2 "catgen/gen_pins[2].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "C0"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata141 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata141") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___67___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata141"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In13") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAA3B8819AA2A8808"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1 "slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h777FF7FFFFFFFFFF"))
+         )
+         (instance (rename slave_fifo32_state_FSM_FFd1 "slave_fifo32/state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_state_FSM_FFd2 "slave_fifo32/state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01212211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h8020401008020401"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata201 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata201") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___61___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata201"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata151 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata151") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___66___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata151"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[11].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_space_xor<3>111_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata210 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata210") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___78___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata210"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata161 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata161") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___65___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata161"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata211 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata211") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___59___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata211"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_Mcount_fifoadr_xor_0_11_INV_0 "slave_fifo32/Mcount_fifoadr_xor<0>11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename gen_clks_clkout1_buf "gen_clks/clkout1_buf") (viewref netlist (cellref BUFG (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[6].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata171 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata171") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___64___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata171"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata221 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata221") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___58___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata221"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_debug1_17_BRB0 "slave_fifo32/debug1_17_BRB0") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_1__rt "f0/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata181 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata181") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___63___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata181"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata231 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata231") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___51___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata231"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<12>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr11_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr11_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata191 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata191") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___62___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata191"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata241 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata241") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___57___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata241"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_11__rt "f0/Mcount_wr_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_10_ "f0/Mcount_rd_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<13>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata251 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata251") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___56___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata251"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata301 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata301") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___71___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata301"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f1_Result_0_1_FRB "f1/Result<0>1_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_11_ "f0/Mcount_rd_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<14>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata310 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata310") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___50___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata310"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata261 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata261") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___81___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata110"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata311 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata311") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___60___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata311"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_2__rt "f1/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_lut_3__INV_0 "f1/Msub_dont_write_past_me_lut<3>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata271 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata271") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___80___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata121"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata321 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata321") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___55___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata321"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[14].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata281 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata281") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___51___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata231"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata331 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata331") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___54___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata331"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full621") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFEFEFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[2].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata291 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata291") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___79___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata291"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata341 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata341") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___79___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata291"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[9].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance tx_enable1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr10_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr10_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata351 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata351") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___53___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata351"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata401 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata401") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___76___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata510"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata410 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata410") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___77___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata410"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata361 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata361") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___52___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata361"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata411 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___75___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata65"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_6__rt "f0/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata421 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata421") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___74___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata71"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata371 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata371") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___78___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata210"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_wr_one "slave_fifo32/wr_one") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata431 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata431") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___73___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata81"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata381 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata381") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___50___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata310"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename gen_clks_clkin1_buf "gen_clks/clkin1_buf") (viewref netlist (cellref IBUFGDS (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+           (property IOSTANDARD (string "DEFAULT"))
+           (property IBUF_DELAY_VALUE (string "0"))
+           (property IBUF_LOW_PWR (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata441 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata441") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___72___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata91"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata391 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata391") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___77___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata410"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance LED_TXRX1_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___45___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1"))
+           (property INIT (string "4'h4"))
+         )
+         (instance GPIF_D_23_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_18_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata501 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata501") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___66___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata151"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata451 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata451") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___71___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata301"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[22].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_write11 "f1/write11") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___123___f1/write11"))
+           (property INIT (string "4'h1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[17].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_7__rt "f1/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata510 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata510") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___76___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata510"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata461 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata461") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___70___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata101"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata511 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata511") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___65___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata161"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[5].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'h9996"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata471 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata471") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___69___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata111"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata521 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata521") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___64___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata171"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<3>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hA9A9A9A9FF0000FF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata481 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata481") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___68___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata131"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata531 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata531") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___63___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata181"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_xor_10_ "f0/Msub_dont_write_past_me_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance tx_enable2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata491 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata491") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___67___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata141"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata541 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata541") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___62___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata191"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_xor_11_ "f0/Msub_dont_write_past_me_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/write1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0001000000000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT52") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hC9C9C9C900FFFF00"))
+         )
+         (instance (rename slave_fifo32_sloe_1 "slave_fifo32/sloe_1") (viewref netlist (cellref FDS (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata601 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata601") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___56___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata251"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata551 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata551") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___61___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata201"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_sloe_2 "slave_fifo32/sloe_2") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_xor_12_ "f0/Msub_dont_write_past_me_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_sloe_3 "slave_fifo32/sloe_3") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_4 "slave_fifo32/sloe_4") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_sloe_5 "slave_fifo32/sloe_5") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata561 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata561") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___60___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata311"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_sloe_6 "slave_fifo32/sloe_6") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata611 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata611") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___55___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata321"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_sloe_7 "slave_fifo32/sloe_7") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_10__rt "f0/Mcount_rd_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_sloe_8 "slave_fifo32/sloe_8") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_9 "slave_fifo32/sloe_9") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0EE00FF00FF00FF0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata571 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata571") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___59___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata211"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata621 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata621") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___54___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata331"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFF0000FFFF1000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[30].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hF0F0F0F08877EE11"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[25].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata581 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata581") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___58___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata221"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata631 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata631") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___53___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata351"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full921 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___116___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921"))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[8].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata641 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata641") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___52___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata361"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata591 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata591") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___57___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata241"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_0_ "f0/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___41___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFF1110FFFFFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance LED_TXRX2_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_1_ "f0/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_2_ "f0/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename f1__n0161_inv1_lut "f1/_n0161_inv1_lut") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_3_ "f0/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/GND_56_o_read_OR_123_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h11101110FFFF1110"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0 "slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___24___slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0"))
+           (property INIT (string "8'hD0"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_4_ "f0/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_5_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0144_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0144_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___8___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In11"))
+           (property INIT (string "32'h00440F44"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_5_ "f0/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_lut_12__INV_0 "f1/Msub_dont_write_past_me_lut<12>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[10].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr9_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_6_ "f0/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[33].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[28].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_7_ "f0/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_8_ "f0/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_9_ "f0/Mcount_wr_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT21") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_lut_6__INV_0 "f0/Msub_dont_write_past_me_lut<6>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT17") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h56555656"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAAAAAAAAAAAAAAA9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[12].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT31") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_11__rt "f1/Mcount_rd_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___33___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11"))
+           (property INIT (string "8'h54"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT41") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename f0_Result_1_1_FRB "f0/Result<1>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT51") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state_glue_set") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___28___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111"))
+           (property INIT (string "8'hA9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<13>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[13].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0121211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h8282414141418228"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[41].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[36].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<14>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<15>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<9>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAAAAAAB9AAAAAAA8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___135___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT91") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___135___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___35___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0"))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h7"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[20].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[15].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty") (viewref netlist (cellref FDS (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1 "slave_fifo32/ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hA8A8A88820202000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[16].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[21].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/full_reg_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFF008C008C008C"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[44].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<9>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[39].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___44___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0"))
+           (property INIT (string "8'hBF"))
+         )
+         (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[23].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_SW1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full_glue_set_SW1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___5___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0"))
+           (property INIT (string "32'hFFFF7FFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[18].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_Result_1_1_FRB "f1/Result<1>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/fifo_4k_2clk") (viewref view_1 (cellref fifo_4k_2clk (libraryref b200_lib)))
+           (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11_SW1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[24].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[19].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[47].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[52].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_4__rt "f0/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_xor_0_ "f1/Msub_dont_write_past_me_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/GND_63_o_space[15]_LessThan_2_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFF55555554"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_xor_1_ "f1/Msub_dont_write_past_me_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_4__rt "f1/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full411_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_xor_2_ "f1/Msub_dont_write_past_me_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[31].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[26].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_0 "slave_fifo32/gpif_data_in_0") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_1 "slave_fifo32/gpif_data_in_1") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_2 "slave_fifo32/gpif_data_in_2") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0000FFFB0004FFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_3 "slave_fifo32/gpif_data_in_3") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_xor_3_ "f1/Msub_dont_write_past_me_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_4 "slave_fifo32/gpif_data_in_4") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance ODDR2_ifclk (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "NONE"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_5 "slave_fifo32/gpif_data_in_5") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_full_reg_glue_set "f1/full_reg_glue_set") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___123___f1/write11"))
+           (property INIT (string "32'hF0FF4044"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_6 "slave_fifo32/gpif_data_in_6") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_7 "slave_fifo32/gpif_data_in_7") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h350035F0"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_8 "slave_fifo32/gpif_data_in_8") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAA8AAA8AFFCFAA8A"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01217") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h999F999699999990"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_xor_4_ "f1/Msub_dont_write_past_me_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_slrd_rstpot_SW0 "slave_fifo32/slrd_rstpot_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h4141414141411441"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_9 "slave_fifo32/gpif_data_in_9") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01219") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAA08880800008008"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_xor_5_ "f1/Msub_dont_write_past_me_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[27].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[32].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_24_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_19_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[55].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[60].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_xor_6_ "f1/Msub_dont_write_past_me_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_xor_7_ "f1/Msub_dont_write_past_me_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1__n0161_inv1_lut1 "f1/_n0161_inv1_lut1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'hD"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance IFCLK_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_9__rt "f0/Mcount_wr_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_xor_8_ "f1/Msub_dont_write_past_me_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename catgen_oddr2_frame "catgen/oddr2_frame") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "C0"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_xor_9_ "f1/Msub_dont_write_past_me_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[34].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[29].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_10 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_o_tlast1 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/o_tlast1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___172___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/o_tlast1"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_12 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_9__rt "f1/Mcount_wr_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full411_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[40].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h1111000111111111"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[35].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[58].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[63].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_rd_addr_0 "f0/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___34___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111"))
+           (property INIT (string "4'h7"))
+         )
+         (instance (rename f0_rd_addr_1 "f0/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0_cy") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_i_tready1 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/i_tready1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___172___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/o_tlast1"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename f0_rd_addr_2 "f0/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_rd_addr_3 "f0/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_rd_addr_4 "f0/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_rd_addr_5 "f0/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_rd_addr_6 "f0/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_rd_addr_7 "f0/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_rd_addr_8 "f0/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_rd_addr_9 "f0/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[37].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFF66FF69FFFFFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[42].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/state_glue_set") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___16___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1"))
+           (property INIT (string "16'hA2A6"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename catgen_gen_pins_5__oddr2 "catgen/gen_pins[5].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "C0"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0000000000000001"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___3___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0"))
+           (property INIT (string "16'hFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[2].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_lut_10__INV_0 "f0/Msub_dont_write_past_me_lut<10>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0004FFFF00040004"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_6_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_xor_10_ "f1/Msub_dont_write_past_me_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_xor_11_ "f1/Msub_dont_write_past_me_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_0__inv1_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state<0>_inv1_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[38].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[43].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<13>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_xor_12_ "f1/Msub_dont_write_past_me_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<14>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1-In111") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___13___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1"))
+           (property INIT (string "16'h7F2A"))
+         )
+         (instance (rename f1_Mcount_rd_addr_xor_10_ "f1/Mcount_rd_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___5___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0"))
+           (property INIT (string "32'hFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<15>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_rd_addr_xor_11_ "f1/Mcount_rd_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_rd_addr_xor_12_ "f1/Mcount_rd_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[45].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[50].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg") (viewref netlist (cellref FDS (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_pktend_1 "slave_fifo32/pktend_1") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_lut_6__INV_0 "f1/Msub_dont_write_past_me_lut<6>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[5].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename gpif_sync_reset_int "gpif_sync/reset_int") (viewref netlist (cellref FDP (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01217_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01217_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'hA521"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Result_10_1_FRB "f0/Result<10>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Result_2_1_FRB "f0/Result<2>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[46].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[51].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_EP_WMARK "slave_fifo32/EP_WMARK") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance ext_ref_enable_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance codec_reset_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[0].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[48].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[53].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[8].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv31 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___14___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31"))
+           (property INIT (string "16'h4500"))
+         )
+         (instance (rename slave_fifo32_slrd_1 "slave_fifo32/slrd_1") (viewref netlist (cellref FDS (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>111_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[49].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<10>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[54].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<6>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___1___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0"))
+           (property INIT (string "16'hFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty") (viewref netlist (cellref FDS (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<11>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___1___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0"))
+           (property INIT (string "16'h8000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance cat_sclk1 (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___178___cat_mosi1"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<12>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[3].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<12>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<13>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename f1_Mcount_wr_addr_lut_0__INV_0 "f1/Mcount_wr_addr_lut<0>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_cy1") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename f1_Mcount_rd_addr_lut_0__INV_0 "f1/Mcount_rd_addr_lut<0>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<13>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<14>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[56].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[61].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<14>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<15>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename f0_write11 "f0/write11") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___122___f0/write11"))
+           (property INIT (string "4'h1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename f1_Result_2_1_FRB "f1/Result<2>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_10__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<10>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[57].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___22___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511"))
+           (property INIT (string "8'hBF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[62].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f0_read_state_FSM_FFd1 "f0/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_read_state_FSM_FFd2 "f0/read_state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___12___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31"))
+           (property INIT (string "16'h4500"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full1021 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___43___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021"))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_10_ "f1/Mcount_wr_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___3___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0"))
+           (property INIT (string "16'h8000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[6].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_11_ "f1/Mcount_wr_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0102_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___117___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11"))
+           (property INIT (string "16'hFF57"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0102_SW1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___27___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0"))
+           (property INIT (string "8'h80"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[59].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hCCCCCCCCF0550FAA"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[64].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_dont_write_past_me_10__FRB "f0/dont_write_past_me<10>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<0>11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAAAA8AAAAAAABAAA"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h00400000AAEAAAAA"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2_1") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance LED_TXRX1_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance GPIF_D_30_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_25_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_11__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<11>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_lut_9__INV_0 "f0/Msub_dont_write_past_me_lut<9>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[9].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance XST_GND (viewref netlist (cellref GND (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_dont_write_past_me_11__FRB "f0/dont_write_past_me<11>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_state_FSM_FFd1_In2 "slave_fifo32/state_FSM_FFd1-In2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h2700050022000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_state_FSM_FFd1_In3 "slave_fifo32/state_FSM_FFd1-In3") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_state_FSM_FFd1_In4 "slave_fifo32/state_FSM_FFd1-In4") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___176___slave_fifo32/state_FSM_FFd1-In4"))
+           (property INIT (string "4'hE"))
+         )
+         (instance cat_miso_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+           (property IBUF_DELAY_VALUE (string "0"))
+           (property IFD_DELAY_VALUE (string "AUTO"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_full_reg_glue_set "f0/full_reg_glue_set") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___122___f0/write11"))
+           (property INIT (string "32'hF0FF4044"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<10>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_wr_one_rstpot "slave_fifo32/wr_one_rstpot") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___48___slave_fifo32/_n0230_inv1"))
+           (property INIT (string "32'hEEAAA2AA"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Result_0_2_FRB "f0/Result<0>2_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_12__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<12>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0__n0161_inv1_cy "f0/_n0161_inv1_cy") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename gpif_sync_reset_out "gpif_sync/reset_out") (viewref netlist (cellref FDP (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata33 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata33") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___150___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata33"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid31") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___125___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11"))
+           (property INIT (string "8'hE0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[11].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata41 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata41") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___150___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata33"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hA8A8FDA8A8A8A8A8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata51 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata51") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___149___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata51"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance GPIF_D_7_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata61 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata61") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___149___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata51"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f0_dont_write_past_me_12__FRB "f0/dont_write_past_me<12>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid61") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFF0001FFFE0000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata71 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata71") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___148___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata71"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata81 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata81") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___148___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata71"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_rd_one_BRB0 "slave_fifo32/rd_one_BRB0") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_rd_one_BRB1 "slave_fifo32/rd_one_BRB1") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata91 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata91") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___147___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata91"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance SFDX2_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename gen_clks_clkout2_buf "gen_clks/clkout2_buf") (viewref netlist (cellref BUFG (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[14].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<4>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename f0_Result_11_1_FRB "f0/Result<11>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance codec_enable_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_2__rt "f0/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f0_Result_3_1_FRB "f0/Result<3>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") (viewref netlist (cellref FDS (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___13___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1"))
+           (property INIT (string "16'h2E22"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr12_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr12_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_ctrl_tx_tvalid1 "slave_fifo32/ctrl_tx_tvalid1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h01000000"))
+         )
+         (instance (rename f1_Result_0_2_FRB "f1/Result<0>2_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_rstpot") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFF0FFFFFF80FF80"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In12_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In12_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___46___slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1"))
+           (property INIT (string "4'hD"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_0") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_3__rt "f1/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1__n0161_inv1_cy "f1/_n0161_inv1_cy") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hA8A8A8A8A8A8B9A8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[22].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[17].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr11_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr11_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h55555504FFFFFF5D"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1 "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFF55555554"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_7__rt "f0/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h8421000000000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<13>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<14>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_8__rt "f1/Mcount_rd_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tready1_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h80000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<15>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tready1_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h80000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0000FAFB00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[30].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[25].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f1_Result_3_1_FRB "f1/Result<3>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_11__rt "f0/Mcount_rd_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename catgen_gen_pins_8__oddr2 "catgen/gen_pins[8].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "C0"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance fx3_ce_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+           (property IBUF_DELAY_VALUE (string "0"))
+           (property IFD_DELAY_VALUE (string "AUTO"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1_SW1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___118___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11"))
+           (property INIT (string "8'h04"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFAAAAFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1_G") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hFB"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[33].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[28].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___120___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set"))
+           (property INIT (string "16'hFFA2"))
+         )
+         (instance (rename f0_Mcount_rd_addr_xor_10_ "f0/Mcount_rd_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr9_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_rd_addr_xor_11_ "f0/Mcount_rd_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_31_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_26_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_rd_addr_xor_12_ "f0/Mcount_rd_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_idle_cycles_0 "slave_fifo32/idle_cycles_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_idle_cycles_1 "slave_fifo32/idle_cycles_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___171___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11"))
+           (property INIT (string "8'hC8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename catgen_gen_pins_0__oddr2 "catgen/gen_pins[0].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "C0"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_o_tready_int11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h3333333333323333"))
+         )
+         (instance (rename slave_fifo32_idle_cycles_2 "slave_fifo32/idle_cycles_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_lut_9__INV_0 "f1/Msub_dont_write_past_me_lut<9>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_i_tvalid_int1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h1555555555555555"))
+         )
+         (instance gps_ref_enable_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[36].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[41].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata65 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata65") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___107___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata65"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full621_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata71 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___106___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata71"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___179___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata81 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___105___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata81"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_0_rstpot") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h6AAA595566AA5555"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata91 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata91") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___104___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata91"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Result_1_2_FRB "f0/Result<1>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218_SW0_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/read") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0111111111111111"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<12>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty_glue_rst") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFC55FC54FF55FF55"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[44].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[39].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<13>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<9>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<14>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance tx_codec_d_0_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance GPIF_D_8_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT101") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_0__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<0>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT110") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT111") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0146_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___0___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot"))
+           (property INIT (string "32'hFFFF8D88"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full621_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_rd_addr_xor_0_ "f0/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT121") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_rd_addr_xor_1_ "f0/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT131") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename f0_Mcount_rd_addr_xor_2_ "f0/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifoadr_0_1 "slave_fifo32/fifoadr_0_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT141") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0121111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___174___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename f0_Mcount_rd_addr_xor_3_ "f0/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT201") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT151") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[47].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[52].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_rd_addr_xor_4_ "f0/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT210") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_tlast1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0C0C0C0C0C0C0D0C"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT161") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT211 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT211") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Result_12_1_FRB "f0/Result<12>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_rd_addr_xor_5_ "f0/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT171 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT171") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename f0_Result_4_1_FRB "f0/Result<4>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT221") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") (viewref netlist (cellref FDS (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_rd_addr_xor_6_ "f0/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT231") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance XST_VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT181 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT181") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_wr_addr_10 "f0/wr_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifoadr_1_1 "slave_fifo32/fifoadr_1_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance tx_codec_d_1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_rd_addr_xor_7_ "f0/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_wr_addr_11 "f0/wr_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_wr_addr_12 "f0/wr_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT241") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT191") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h1"))
+         )
+         (instance (rename f1_Result_1_2_FRB "f1/Result<1>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_1__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<1>_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_read_state_FSM_FFd1_In111 "f0/read_state_FSM_FFd1-In111") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___30___f0/GND_14_o_read_OR_37_o1"))
+           (property INIT (string "16'hFDA8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_rd_addr_xor_8_ "f0/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT251") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT301") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance cat_ce_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_rd_addr_xor_9_ "f0/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT261") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT311") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_5__rt "f0/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo_rst_gpif_rst_OR_155_o1 "slave_fifo32/fifo64_to_gpmc32_resp/fifo_rst_gpif_rst_OR_155_o1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___175___slave_fifo32/fifo64_to_gpmc32_resp/fifo_rst_gpif_rst_OR_155_o1"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT271") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32__n0258_inv_SW0 "slave_fifo32/_n0258_inv_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___121___slave_fifo32/_n0258_inv_SW0"))
+           (property INIT (string "8'hBF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___115___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11"))
+           (property INIT (string "8'h69"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT321") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_i_tvalid_int1_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'h8000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tready_int1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hC000000080000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[60].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT281") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[55].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<10>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_5__rt "f1/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT291") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA8880888"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___12___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31"))
+           (property INIT (string "32'hFFFF4B44"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hEFEFEFEEEEEEEEEE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<11>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f0_Mcompar_becoming_full_cy_0_ "f0/Mcompar_becoming_full_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_space_xor<3>111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hEFEFEFEEEEEEEEEE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<12>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f0_Mcompar_becoming_full_cy_1_ "f0/Mcompar_becoming_full_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f0_Mcompar_becoming_full_cy_2_ "f0/Mcompar_becoming_full_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance tx_codec_d_2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f0_Mcompar_becoming_full_cy_3_ "f0/Mcompar_becoming_full_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_2__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<2>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_lut_10__INV_0 "f1/Msub_dont_write_past_me_lut<10>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f0_Mcompar_becoming_full_cy_4_ "f0/Mcompar_becoming_full_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o41") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[58].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_data_tx_tvalid1 "slave_fifo32/data_tx_tvalid1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h00010000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[63].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In12") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFAAB9"))
+         )
+         (instance (rename slave_fifo32__n0290_inv1 "slave_fifo32/_n0290_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___21___slave_fifo32/_n0223_inv1"))
+           (property INIT (string "32'h20002222"))
+         )
+         (instance (rename f1_Result_4_1_FRB "f1/Result<4>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___174___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111"))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_lut_4__INV_0 "f0/Msub_dont_write_past_me_lut<4>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In31") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o1_SW1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'hFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0102_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___115___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11"))
+           (property INIT (string "16'hFF57"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In32") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0102_SW1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___26___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0"))
+           (property INIT (string "8'h80"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In33") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'hFDFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0000000000000001"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In34") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFB"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full611 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full611") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0000000100010001"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAAAAAAAAA9AAAAAA"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_10 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_10") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h04040000FF04FF00"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_11") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_12 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_12") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hE1E1E1E10FF0F00F"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full621") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFEFEFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_13 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_13") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance tx_codec_d_3_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_14 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_14") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[1].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_15 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_15") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_20 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_20") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_16 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_16") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_21") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_17 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_17") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_3__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<3>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_22 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_22") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_18 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_18") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_23 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_23") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_19 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_19") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_24 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_24") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_25") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_30") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_26") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0154_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0154_inv1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___37___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0154_inv1"))
+           (property INIT (string "8'hDC"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_31") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_27") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_28") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT52") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hA9A9A9A9AA5555AA"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_29") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h8000000000000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___39___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h54A855AA55AA55AA"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFF9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFF00FFE8FF17FFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In13") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAA3B8819AA2A8808"))
+         )
+         (instance GPIF_D_27_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hCCCCCCCCF50A05FA"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0404040404040504"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o41") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFF7FFFFFFFFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFE"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_cy_10_ "f0/Msub_dont_write_past_me_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<7>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_cy_11_ "f0/Msub_dont_write_past_me_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[4].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_10_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0_lut") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h1111111011111111"))
+         )
+         (instance tx_codec_d_4_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0010001000000010"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01213") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9090900000900000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<2>11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___9___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11"))
+           (property INIT (string "16'h6AA9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_4__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<4>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01214") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h99900000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01215") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0220000000000220"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01216") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01217") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0080000000000080"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01218") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___114___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921"))
+           (property INIT (string "16'h0440"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01219") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFAF8AA0000000000"))
+         )
+         (instance SFDX1_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f0_Result_10_2_FRB "f0/Result<10>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Result_2_2_FRB "f0/Result<2>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h00000001FFFFFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[12].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f0_Mcompar_becoming_full_lut_0_ "f0/Mcompar_becoming_full_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[0].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f0_Mcompar_becoming_full_lut_1_ "f0/Mcompar_becoming_full_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[7].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_SW1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set_SW1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___7___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0"))
+           (property INIT (string "32'hFFFF7FFF"))
+         )
+         (instance debug_0_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance codec_fb_clk_p_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f0_Mcompar_becoming_full_lut_2_ "f0/Mcompar_becoming_full_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename f0_Mcompar_becoming_full_lut_3_ "f0/Mcompar_becoming_full_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_11_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcompar_becoming_full_lut_4_ "f0/Mcompar_becoming_full_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance GPIF_D_9_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance tx_codec_d_5_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/i_tvalid_o_tready_AND_73_o1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___127___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tvalid11"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_5__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<5>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_write1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/write1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0000000100000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hCCCCCCCCF05A0F5A"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[15].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[20].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_state_FSM_FFd1_In3_F "slave_fifo32/state_FSM_FFd1-In3_F") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h80808000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_state_FSM_FFd1_In3_G "slave_fifo32/state_FSM_FFd1-In3_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h04155555FFFFFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hCCCCCCCC0F5AF05A"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance SFDX2_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[3].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h8421000000000000"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_10 "slave_fifo32/gpif_data_in_10") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_11 "slave_fifo32/gpif_data_in_11") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_12 "slave_fifo32/gpif_data_in_12") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_13 "slave_fifo32/gpif_data_in_13") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_14 "slave_fifo32/gpif_data_in_14") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_15 "slave_fifo32/gpif_data_in_15") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_20 "slave_fifo32/gpif_data_in_20") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_16 "slave_fifo32/gpif_data_in_16") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'h0001"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_21 "slave_fifo32/gpif_data_in_21") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21_SW1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h01"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_17 "slave_fifo32/gpif_data_in_17") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_22 "slave_fifo32/gpif_data_in_22") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_18 "slave_fifo32/gpif_data_in_18") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_23 "slave_fifo32/gpif_data_in_23") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_19 "slave_fifo32/gpif_data_in_19") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_24 "slave_fifo32/gpif_data_in_24") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_25 "slave_fifo32/gpif_data_in_25") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_30 "slave_fifo32/gpif_data_in_30") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_26 "slave_fifo32/gpif_data_in_26") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_31 "slave_fifo32/gpif_data_in_31") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance debug_1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_27 "slave_fifo32/gpif_data_in_27") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_28 "slave_fifo32/gpif_data_in_28") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_in_29 "slave_fifo32/gpif_data_in_29") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename f0_Result_5_1_FRB "f0/Result<5>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAA8AAA8AFFCFAA8A"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB0") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance tx_codec_d_6_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f1_Result_2_2_FRB "f1/Result<2>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212_SW1_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___168___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021"))
+           (property INIT (string "8'hEA"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_6__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<6>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename catgen_gen_pins_11__oddr2 "catgen/gen_pins[11].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "C0"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<12>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[23].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[18].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f0_i_tready1_INV_0 "f0/i_tready1_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[6].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_wr_addr_0 "f1/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_wr_addr_1 "f1/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_wr_addr_2 "f1/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_wr_addr_3 "f1/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_wr_addr_4 "f1/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance GPIF_CTL4_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+           (property IBUF_DELAY_VALUE (string "0"))
+           (property IFD_DELAY_VALUE (string "AUTO"))
+         )
+         (instance (rename f1_wr_addr_5 "f1/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_wr_addr_6 "f1/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_wr_addr_7 "f1/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_wr_addr_8 "f1/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0144_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___6___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11"))
+           (property INIT (string "32'h00440F44"))
+         )
+         (instance (rename f1_wr_addr_9 "f1/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance debug_clk_0_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance debug_2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename catgen_gen_pins_3__oddr2 "catgen/gen_pins[3].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "C0"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o41") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___9___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11"))
+           (property INIT (string "32'h6AAAAAA9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_o_tvalid11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h5555555555545555"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h00FBFB0005FBFB05"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_13_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFF5455FFFF5657"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[31].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[26].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___173___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111"))
+           (property INIT (string "4'h9"))
+         )
+         (instance tx_codec_d_7_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_7__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<7>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[9].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[10].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename f1_Result_5_1_FRB "f1/Result<5>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance GPIF_CTL5_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+           (property IBUF_DELAY_VALUE (string "0"))
+           (property IFD_DELAY_VALUE (string "AUTO"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_lut_4__INV_0 "f1/Msub_dont_write_past_me_lut<4>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance debug_clk_1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_state_FSM_FFd2_In1 "slave_fifo32/state_FSM_FFd2-In1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___177___slave_fifo32/Mcount_idle_cycles_xor<0>11"))
+           (property INIT (string "16'h8000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[11].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance debug_3_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_state_FSM_FFd2_In2 "slave_fifo32/state_FSM_FFd2-In2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h1054101010101010"))
+         )
+         (instance (rename slave_fifo32_state_FSM_FFd2_In3 "slave_fifo32/state_FSM_FFd2-In3") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___176___slave_fifo32/state_FSM_FFd1-In4"))
+           (property INIT (string "16'hFFF4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/fifo_4k_2clk") (viewref view_1 (cellref fifo_4k_2clk (libraryref b200_lib)))
+           (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[34].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[29].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA6AAA6A6"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_14_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance tx_codec_d_8_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h1111000111111111"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_8__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<8>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAAAAAAAAAAAAAAA9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<2>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance tx_bandsel_a_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[13].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance reset_global_locked_OR_1_o1 (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___179___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1"))
+           (property INIT (string "4'hD"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance GPIF_D_28_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram10") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram11") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[14].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram12") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<6>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram13") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[42].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram14") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt__n0074_inv1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/_n0074_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hC60ACC000A0A0000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[37].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram15") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram16") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___28___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111"))
+           (property INIT (string "32'hFFAEFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram17") (viewref netlist (cellref RAMB8BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "16:OUTPUT:DOBDO<15:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 1))
+           (property DATA_WIDTH_B (integer 1))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "18'h00000"))
+           (property INIT_B (string "18'h00000"))
+           (property RAM_MODE (string "TDP"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "18'h00000"))
+           (property SRVAL_B (string "18'h00000"))
+           (property INIT_FILE (string "NONE"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_write_AND_42_o_inv2") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'hDFCF"))
+         )
+         (instance debug_4_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___35___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0"))
+           (property INIT (string "16'hCCC9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<4>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFBF8FFFFFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<9>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB4BBBBBBB4BBB4B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hAABAAAAA"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_15_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance tx_codec_d_9_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___119___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[16].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[21].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_9__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<9>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance tx_bandsel_b_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename gen_clks_clkout3_buf "gen_clks/clkout3_buf") (viewref netlist (cellref BUFG (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB1") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFE"))
+         )
+         (instance (rename f0_Result_11_2_FRB "f0/Result<11>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB3") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB4") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_3__rt "f0/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[17].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f0_Result_3_2_FRB "f0/Result<3>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[22].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[50].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[45].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<4>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h6AAAAAAAAAAAAAA9"))
+         )
+         (instance (rename f1_ram_Mram_ram1 "f1/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFEFFFFFFFFFFF"))
+         )
+         (instance (rename f1_ram_Mram_ram2 "f1/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_ram_Mram_ram3 "f1/ram/Mram_ram3") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/GND_50_o_read_OR_57_o1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'h2272"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hEEFFFEFFFFFFFFFF"))
+         )
+         (instance (rename f1_ram_Mram_ram4 "f1/ram/Mram_ram4") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_ram_Mram_ram5 "f1/ram/Mram_ram5") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance debug_5_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f1_ram_Mram_ram6 "f1/ram/Mram_ram6") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_4__rt "f1/Mcount_rd_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_ram_Mram_ram7 "f1/ram/Mram_ram7") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_ram_Mram_ram8 "f1/ram/Mram_ram8") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_GND_50_o_read_OR_57_o1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/GND_50_o_read_OR_57_o1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'h2272"))
+         )
+         (instance (rename f1_ram_Mram_ram9 "f1/ram/Mram_ram9") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[19].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[24].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr12_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr12_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hEEFFEFFFFFFFFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFEFFFFFFFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[25].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[30].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[48].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[53].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_8__rt "f0/Mcount_rd_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance GPIF_D_10_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_lut_7__INV_0 "f0/Msub_dont_write_past_me_lut<7>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_Mcount_wr_addr_xor_0_ "f1/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[27].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[32].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_0") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>_inv_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_9__rt "f1/Mcount_rd_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance debug_6_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f1_Mcount_wr_addr_xor_1_ "f1/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_2 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_2") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_3 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_3") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_4 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_4") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Result_6_1_FRB "f0/Result<6>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_5 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_5") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_6 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_6") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_wr_addr_xor_2_ "f1/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_7 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_7") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_dont_write_past_me_0__FRB "f0/dont_write_past_me<0>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_8 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_8") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance pll_mosi_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_9 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_9") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv4") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___33___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11"))
+           (property INIT (string "8'hA8"))
+         )
+         (instance fx3_mosi_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+           (property IBUF_DELAY_VALUE (string "0"))
+           (property IFD_DELAY_VALUE (string "AUTO"))
+         )
+         (instance (rename f1_Mcount_wr_addr_xor_3_ "f1/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h4000FBFF4400FFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[28].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Result_3_2_FRB "f1/Result<3>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[33].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Mcount_wr_addr_xor_4_ "f1/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[61].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[56].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Mcount_wr_addr_xor_5_ "f1/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_Mcount_wr_addr_xor_6_ "f1/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_wr_addr_xor_7_ "f1/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___27___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0"))
+           (property INIT (string "32'hFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/read_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h80000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[35].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[40].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Mcount_wr_addr_xor_8_ "f1/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_CTL9_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+           (property IBUF_DELAY_VALUE (string "0"))
+           (property IFD_DELAY_VALUE (string "AUTO"))
+         )
+         (instance (rename f1_Mcount_wr_addr_xor_9_ "f1/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[0].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance debug_7_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h5599665556955695"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_0") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv1_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state<0>_inv1_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_2") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_3") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_0") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_4") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_dont_write_past_me_1__FRB "f0/dont_write_past_me<1>_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[41].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[36].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_5") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_2") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_6") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[64].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[59].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_3") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_7") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_4") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_8") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<0>11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_5") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_9") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_6") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_7") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_8") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_rd_addr_10 "f0/rd_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int14_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFF55FF01FF55FF55"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_rd_addr_11 "f0/rd_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int14_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFF55FF00FF55FF54"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_rd_addr_12 "f0/rd_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[43].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[38].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance codec_en_agc_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h5140514055555140"))
+         )
+         (instance tx_codec_d_10_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[3].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Result_6_1_FRB "f1/Result<6>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Result_10_1_FRB "f1/Result<10>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW3") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h04040000FF04FF00"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<2>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[39].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[44].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance debug_8_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f0_dont_write_past_me_2__FRB "f0/dont_write_past_me<2>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_slwr_1 "slave_fifo32/slwr_1") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hA8A8A8A8A8A8B9A8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___39___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11"))
+           (property INIT (string "32'hFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 18))
+           (property DATA_WIDTH_B (integer 18))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 18))
+           (property DATA_WIDTH_B (integer 18))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[46].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[51].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hF2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int12") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0000000000010005"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int14") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'h010F"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int15") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h7FFFFFFFFFFFFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[6].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int16") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h00F7000000F7F7F7"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_13") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_14") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance tx_codec_d_11_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_15") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance GPIF_D_29_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[47].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[52].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance cat_mosi1 (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___178___cat_mosi1"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tready1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0111111111111111"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance debug_9_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFF0D2F087F"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[1].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___15___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1"))
+           (property INIT (string "16'h5400"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_1__rt "f0/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f0_dont_write_past_me_3__FRB "f0/dont_write_past_me<3>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[49].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[54].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___38___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1"))
+           (property INIT (string "16'hA8EA"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_i_tvalid_int1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h1555555555555555"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___41___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11"))
+           (property INIT (string "32'hFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[9].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_1__rt "f1/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_10 "slave_fifo32/gpif_data_out_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_11 "slave_fifo32/gpif_data_out_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_12 "slave_fifo32/gpif_data_out_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_13 "slave_fifo32/gpif_data_out_13") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_14 "slave_fifo32/gpif_data_out_14") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_15 "slave_fifo32/gpif_data_out_15") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_20 "slave_fifo32/gpif_data_out_20") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance SFDX1_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance GPIF_CTL11_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_21 "slave_fifo32/gpif_data_out_21") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_16 "slave_fifo32/gpif_data_out_16") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename f0_Result_12_2_FRB "f0/Result<12>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_17 "slave_fifo32/gpif_data_out_17") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_22 "slave_fifo32/gpif_data_out_22") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[55].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_18 "slave_fifo32/gpif_data_out_18") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_23 "slave_fifo32/gpif_data_out_23") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[60].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_24 "slave_fifo32/gpif_data_out_24") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_19 "slave_fifo32/gpif_data_out_19") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_25 "slave_fifo32/gpif_data_out_25") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_30 "slave_fifo32/gpif_data_out_30") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename f0_Result_4_2_FRB "f0/Result<4>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_31 "slave_fifo32/gpif_data_out_31") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_26 "slave_fifo32/gpif_data_out_26") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_27 "slave_fifo32/gpif_data_out_27") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_28 "slave_fifo32/gpif_data_out_28") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_29 "slave_fifo32/gpif_data_out_29") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename catgen_oddr2_clk "catgen/oddr2_clk") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "C0"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[4].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n012110_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h00008400"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[57].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/GND_66_o_read_OR_144_o1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___44___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[62].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename catgen_gen_pins_6__oddr2 "catgen/gen_pins[6].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "C0"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_6__rt "f0/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f0_dont_write_past_me_4__FRB "f0/dont_write_past_me<4>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_lut_11__INV_0 "f0/Msub_dont_write_past_me_lut<11>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_6__rt "f1/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[58].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[63].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance GPIF_CTL12_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance GPIF_D_11_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[7].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full411") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___17___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421"))
+           (property INIT (string "16'hFEEE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___17___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421"))
+           (property INIT (string "16'h0111"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_lut_7__INV_0 "f1/Msub_dont_write_past_me_lut<7>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/GND_63_o_space[15]_LessThan_2_o1_SW1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'hFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0146_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hFFB8FF88"))
+         )
+         (instance (rename f0_Result_7_1_FRB "f0/Result<7>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_dont_write_past_me_5__FRB "f0/dont_write_past_me<5>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_gpif_data_out_31_rstpot "slave_fifo32/gpif_data_out_31_rstpot") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f1_Result_4_2_FRB "f1/Result<4>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance pps_fpga_out_enable_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hA8A8FDA8A8A8A8A8"))
+         )
+         (instance (rename f1_Mcompar_becoming_full_lut_0_ "f1/Mcompar_becoming_full_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full621") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFEFEFE"))
+         )
+         (instance (rename f1_Mcompar_becoming_full_lut_1_ "f1/Mcompar_becoming_full_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0000000000000001"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<7>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state_glue_set") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___29___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111"))
+           (property INIT (string "8'hA9"))
+         )
+         (instance (rename f1_Mcompar_becoming_full_lut_2_ "f1/Mcompar_becoming_full_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename f0_dont_write_past_me_6__FRB "f0/dont_write_past_me<6>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/state") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcompar_becoming_full_lut_3_ "f1/Mcompar_becoming_full_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000009009"))
+         )
+         (instance (rename f0_full_reg "f0/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcompar_becoming_full_lut_4_ "f1/Mcompar_becoming_full_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___0___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot"))
+           (property INIT (string "32'hFFFF7222"))
+         )
+         (instance fx3_miso_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int16_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hEEEEFEEE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_12_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[12].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Result_7_1_FRB "f1/Result<7>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Result_11_1_FRB "f1/Result<11>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance tx_frame_p_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata101 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata101") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___162___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata101"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata110") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___167___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata110"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata111 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata111") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___162___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata101"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full611") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0000000100010001"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata121 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata121") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___161___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata121"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f0_dont_write_past_me_7__FRB "f0/dont_write_past_me<7>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full621") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFEFEFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata131 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata131") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___161___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata121"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFF5554"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___10___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1"))
+           (property INIT (string "16'h2E22"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata141 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata141") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___160___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata141"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1_G") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata201 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata201") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___157___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata201"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata151 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata151") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___160___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata141"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[20].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[15].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata210 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata210") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___167___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata110"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata161 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata161") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___159___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata161"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata211 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata211") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___157___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata201"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full921 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___114___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921"))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata171 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata171") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___159___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata161"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata221 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata221") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___156___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata221"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata231 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata231") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___156___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata221"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata181 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata181") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___158___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata181"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifoadr_0 "slave_fifo32/fifoadr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___40___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write1"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifoadr_1 "slave_fifo32/fifoadr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata241 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata241") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___155___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata241"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata191 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata191") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___158___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata181"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/full_reg_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h4C4CFF4C4C4C4C4C"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT21") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata251 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata251") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___155___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata241"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<9>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAAAAAAB9AAAAAAA8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT17") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___175___slave_fifo32/fifo64_to_gpmc32_resp/fifo_rst_gpif_rst_OR_155_o1"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata301 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata301") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___163___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata91"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0154_inv1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hDC"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT31") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance GPIF_CTL0_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata261 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata261") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___154___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata261"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata311 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata311") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___152___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata311"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f0_dont_write_past_me_8__FRB "f0/dont_write_past_me<8>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<13>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT41") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata321 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata321") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___152___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata311"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata271 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata271") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___154___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata261"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<14>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT51") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata281 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata281") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___153___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata281"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[23].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[18].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_15_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<15>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata291 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata291") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___153___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata281"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<11>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___131___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Result_5_2_FRB "f0/Result<5>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_lut_2__INV_0 "f0/Msub_dont_write_past_me_lut<2>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT91") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___131___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81"))
+           (property INIT (string "4'hE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_EP_WMARK1 "slave_fifo32/EP_WMARK1") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h00000000DD09C000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance GPIF_CTL1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0020000002200200"))
+         )
+         (instance (rename f0_dont_write_past_me_9__FRB "f0/dont_write_past_me<9>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance codec_sync_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___126___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0"))
+           (property INIT (string "4'hD"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[31].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[26].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance GPIF_D_12_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance cat_mosi_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<5>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[34].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[29].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Result_8_1_FRB "f0/Result<8>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance GPIF_CTL2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0303CFCF0203DFCF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/fifo_4k_2clk") (viewref view_1 (cellref fifo_4k_2clk (libraryref b200_lib)))
+           (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFBFBFBFFFB00FB00"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Result_5_2_FRB "f1/Result<5>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_read_state_FSM_FFd1_In111 "f1/read_state_FSM_FFd1-In111") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___31___f1/GND_14_o_read_OR_37_o1"))
+           (property INIT (string "16'hFDA8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_debug1_10 "slave_fifo32/debug1_10") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_debug1_11 "slave_fifo32/debug1_11") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug1_12 "slave_fifo32/debug1_12") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug1_13 "slave_fifo32/debug1_13") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug1_14 "slave_fifo32/debug1_14") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug1_15 "slave_fifo32/debug1_15") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_debug1_21 "slave_fifo32/debug1_21") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug1_22 "slave_fifo32/debug1_22") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_o_tvalid1_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/o_tvalid1_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<1>11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h69"))
+         )
+         (instance (rename slave_fifo32_debug1_18 "slave_fifo32/debug1_18") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug1_23 "slave_fifo32/debug1_23") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug1_19 "slave_fifo32/debug1_19") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_debug1_26 "slave_fifo32/debug1_26") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug1_31 "slave_fifo32/debug1_31") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug1_27 "slave_fifo32/debug1_27") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug1_28 "slave_fifo32/debug1_28") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug1_29 "slave_fifo32/debug1_29") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_xor_0_ "f0/Msub_dont_write_past_me_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[42].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[37].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_xor_1_ "f0/Msub_dont_write_past_me_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_xor_2_ "f0/Msub_dont_write_past_me_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg_glue_set") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___45___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1"))
+           (property INIT (string "32'h5540FFC0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hEFEEEFEEEFEEFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h54555454FCFFFCFC"))
+         )
+         (instance GPIF_CTL3_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_xor_3_ "f0/Msub_dont_write_past_me_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/ram/Mram_ram") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 36))
+           (property DATA_WIDTH_B (integer 36))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_xor_4_ "f0/Msub_dont_write_past_me_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h2002000000002002"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___180___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012112") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h8822228C80202084"))
+         )
+         (instance (rename bus_sync_reset_int "bus_sync/reset_int") (viewref netlist (cellref FDP (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012113") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_xor_5_ "f0/Msub_dont_write_past_me_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012114") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB33A820A820A820"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_xor_6_ "f0/Msub_dont_write_past_me_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_xor_7_ "f0/Msub_dont_write_past_me_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___36___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111"))
+           (property INIT (string "4'h7"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_xor_8_ "f0/Msub_dont_write_past_me_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[45].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[50].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Result_8_1_FRB "f1/Result<8>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_xor_9_ "f0/Msub_dont_write_past_me_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Result_12_1_FRB "f1/Result<12>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_read1 "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/read1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_cy_0_ "f0/Msub_dont_write_past_me_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename catgen_gen_pins_9__oddr2 "catgen/gen_pins[9].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "C0"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_cy_1_ "f0/Msub_dont_write_past_me_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/ram/Mram_ram") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 36))
+           (property DATA_WIDTH_B (integer 36))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_4__rt "f0/Mcount_rd_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_cy_2_ "f0/Msub_dont_write_past_me_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<10>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_cy_3_ "f0/Msub_dont_write_past_me_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[53].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[48].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_cy_4_ "f0/Msub_dont_write_past_me_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance debug_10_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_cy_5_ "f0/Msub_dont_write_past_me_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_5__rt "f1/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_cy_6_ "f0/Msub_dont_write_past_me_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___26___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0"))
+           (property INIT (string "32'hFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_cy_7_ "f0/Msub_dont_write_past_me_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_10__rt "f1/Mcount_wr_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_cy_8_ "f0/Msub_dont_write_past_me_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename catgen_gen_pins_1__oddr2 "catgen/gen_pins[1].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property DDR_ALIGNMENT (string "C0"))
+           (property SRTYPE (string "ASYNC"))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_cy_9_ "f0/Msub_dont_write_past_me_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_sloe "slave_fifo32/sloe") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_debug2_10 "slave_fifo32/debug2_10") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h7FFF7F7F2AFF2A2A"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_debug2_11 "slave_fifo32/debug2_11") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_debug2_12 "slave_fifo32/debug2_12") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename f0_Mcount_rd_addr_cy_9__rt "f0/Mcount_rd_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_debug2_13 "slave_fifo32/debug2_13") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_debug2_14 "slave_fifo32/debug2_14") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_debug2_15 "slave_fifo32/debug2_15") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[61].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[56].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_debug2_16 "slave_fifo32/debug2_16") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_debug2_21 "slave_fifo32/debug2_21") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_debug2_17 "slave_fifo32/debug2_17") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___18___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11"))
+           (property INIT (string "16'h6AA9"))
+         )
+         (instance (rename slave_fifo32_debug2_22 "slave_fifo32/debug2_22") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_debug2_18 "slave_fifo32/debug2_18") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_slrd "slave_fifo32/slrd") (viewref netlist (cellref FDS (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_debug2_23 "slave_fifo32/debug2_23") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_debug2_19 "slave_fifo32/debug2_19") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_debug2_26 "slave_fifo32/debug2_26") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_debug2_31 "slave_fifo32/debug2_31") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_debug2_27 "slave_fifo32/debug2_27") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_debug2_28 "slave_fifo32/debug2_28") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_debug2_29 "slave_fifo32/debug2_29") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance debug_11_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_write_AND_42_o_inv2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_write_AND_42_o_inv2") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'hDFCF"))
+         )
+         (instance (rename f0_Result_6_2_FRB "f0/Result<6>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1011 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___49___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011"))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hFE"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_lut_2__INV_0 "f1/Msub_dont_write_past_me_lut<2>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1021 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___168___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021"))
+           (property INIT (string "4'h9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_10 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_10") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_11 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_11") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_12 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_12") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_13 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_13") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___25___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511"))
+           (property INIT (string "32'hBF4040BF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_14 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_14") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFD"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_20 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_20") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2_G") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_15 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_15") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_21 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_21") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0121211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0121211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h8282414141418228"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_16 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_16") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_17 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_17") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB0") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_22 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_22") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_18 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_18") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hE178E1E1E1E1E1E1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB1") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_23 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_23") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_19 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_19") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_24 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_24") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_25 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_25") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_30 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_30") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_31 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_31") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_26 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_26") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_27 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_27") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_28 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_28") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___34___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111"))
+           (property INIT (string "32'h9AAAAAA6"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[59].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[64].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_29 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_29") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<0>11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_slwr "slave_fifo32/slwr") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hAAAA9AAAA6A696A6"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___40___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write1"))
+           (property INIT (string "16'hEFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT61") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h99AA99A6AAAAAAA6"))
+         )
+         (instance (rename slave_fifo32_sloe_10 "slave_fifo32/sloe_10") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance codec_ctrl_in_0_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA9AAA9A9"))
+         )
+         (instance (rename slave_fifo32_sloe_11 "slave_fifo32/sloe_11") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_sloe_12 "slave_fifo32/sloe_12") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01211_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFF05FF04FF"))
+         )
+         (instance (rename slave_fifo32_sloe_13 "slave_fifo32/sloe_13") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_14 "slave_fifo32/sloe_14") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_20 "slave_fifo32/sloe_20") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_15 "slave_fifo32/sloe_15") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFB0400FFFA0500"))
+         )
+         (instance (rename slave_fifo32_sloe_16 "slave_fifo32/sloe_16") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_21 "slave_fifo32/sloe_21") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_sloe_17 "slave_fifo32/sloe_17") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_22 "slave_fifo32/sloe_22") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_23 "slave_fifo32/sloe_23") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_18 "slave_fifo32/sloe_18") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance debug_12_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_sloe_19 "slave_fifo32/sloe_19") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_24 "slave_fifo32/sloe_24") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFF0040BFBF4000FF"))
+         )
+         (instance (rename slave_fifo32_sloe_25 "slave_fifo32/sloe_25") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_30 "slave_fifo32/sloe_30") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA6AAA6A6"))
+         )
+         (instance (rename slave_fifo32_sloe_26 "slave_fifo32/sloe_26") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_31 "slave_fifo32/sloe_31") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_sloe_27 "slave_fifo32/sloe_27") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_32 "slave_fifo32/sloe_32") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_33 "slave_fifo32/sloe_33") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_28 "slave_fifo32/sloe_28") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_sloe_34 "slave_fifo32/sloe_34") (viewref netlist (cellref FDS (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_sloe_29 "slave_fifo32/sloe_29") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+           (property IOB (string "TRUE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_13_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_read_state_FSM_FFd1 "f1/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_read_state_FSM_FFd2 "f1/read_state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<2>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[2].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_10_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<12>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<3>1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA9AAA9A9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state_glue_set") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___15___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1"))
+           (property INIT (string "16'hA2A6"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<2>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata33 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata33") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___166___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata33"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<10>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<13>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata41 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata41") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___166___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata33"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Result_9_1_FRB "f0/Result<9>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance GPIF_CTL7_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<11>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<14>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata51 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata51") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___165___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata51"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<12>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<6>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata61 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata61") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___165___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata51"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_Result_6_2_FRB "f1/Result<6>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<13>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename bus_sync_reset_out "bus_sync/reset_out") (viewref netlist (cellref FDP (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h9009000000000000"))
+         )
+         (instance codec_ctrl_in_1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance (rename f1_Result_10_2_FRB "f1/Result<10>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata71 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata71") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___164___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata71"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'h0307"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int12") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h7FFFFFFFFFFFFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<14>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFDBFDDBFDFFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int13") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "16'hF700"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___43___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021"))
+           (property INIT (string "16'hEFFF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<4>1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA9AAA9A9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h59555959"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFCBFFBEFFC7FF7DF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata81 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata81") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___164___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata71"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[10].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int16") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hF0E4D8CC00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<15>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'h1B"))
+         )
+         (instance debug_13_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance pll_sclk_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<9>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB4BBBBBBB4BBB4B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata91 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata91") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___163___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata91"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance fx3_sclk_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+           (property IBUF_DELAY_VALUE (string "0"))
+           (property IFD_DELAY_VALUE (string "AUTO"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[5].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram10") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram11") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram12") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_10_ "f0/Mcount_wr_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram13") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_11_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram14") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram15") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram16") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram17") (viewref netlist (cellref RAMB8BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "16:OUTPUT:DOBDO<15:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 1))
+           (property DATA_WIDTH_B (integer 1))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "18'h00000"))
+           (property INIT_B (string "18'h00000"))
+           (property RAM_MODE (string "TDP"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "18'h00000"))
+           (property SRVAL_B (string "18'h00000"))
+           (property INIT_FILE (string "NONE"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_11_ "f0/Mcount_wr_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<5>1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'hA9AAA9A9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<3>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___18___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11"))
+           (property INIT (string "32'h6AAAAAA9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance SRX2_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance GPIF_D_0_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance codec_txrx_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[13].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Msub_dont_write_past_me_lut_11__INV_0 "f1/Msub_dont_write_past_me_lut<11>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_EP_WMARK1_1 "slave_fifo32/EP_WMARK1_1") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance codec_ctrl_in_2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[1].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[8].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance debug_14_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f0_wr_addr_0 "f0/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_wr_addr_1 "f0/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_wr_addr_2 "f0/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_wr_addr_3 "f0/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty") (viewref netlist (cellref FDS (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename f0_wr_addr_4 "f0/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Result_9_1_FRB "f1/Result<9>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_2__rt "f0/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f0_wr_addr_5 "f0/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_lut_5__INV_0 "f0/Msub_dont_write_past_me_lut<5>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename f0_wr_addr_6 "f0/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_wr_addr_7 "f0/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_wr_addr_8 "f0/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/_n0074_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hC60ACC000A0A0000"))
+         )
+         (instance (rename f0_wr_addr_9 "f0/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB0") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_2__rt "f1/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty") (viewref netlist (cellref FDS (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[16].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[21].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[4].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance codec_ctrl_in_3_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename f0_ram_Mram_ram1 "f0/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram2 "f0/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_ram_Mram_ram3 "f0/ram/Mram_ram3") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram4 "f0/ram/Mram_ram4") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram5 "f0/ram/Mram_ram5") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram6 "f0/ram/Mram_ram6") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram7 "f0/ram/Mram_ram7") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram8 "f0/ram/Mram_ram8") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance (rename f0_ram_Mram_ram9 "f0/ram/Mram_ram9") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "32:INPUT:DIA<31:0>"))
+           (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property WRITE_MODE_A (string "READ_FIRST"))
+           (property WRITE_MODE_B (string "WRITE_FIRST"))
+           (property DATA_WIDTH_A (integer 2))
+           (property DATA_WIDTH_B (integer 2))
+           (property DOA_REG (integer 0))
+           (property DOB_REG (integer 0))
+           (property EN_RSTRAM_A (boolean (true)))
+           (property EN_RSTRAM_B (boolean (true)))
+           (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000"))
+           (property INIT_A (string "36'h000000000"))
+           (property INIT_B (string "36'h000000000"))
+           (property RST_PRIORITY_A (string "CE"))
+           (property RST_PRIORITY_B (string "CE"))
+           (property RSTTYPE (string "SYNC"))
+           (property SRVAL_A (string "36'h000000000"))
+           (property SRVAL_B (string "36'h000000000"))
+           (property SIM_COLLISION_CHECK (string "ALL"))
+           (property SIM_DEVICE (string "SPARTAN6"))
+           (property INIT_FILE (string "NONE"))
+         )
+         (instance debug_20_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance debug_15_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0155115501111111"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_wr_addr_cy_7__rt "f0/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename gen_clks_dcm_sp_inst "gen_clks/dcm_sp_inst") (viewref netlist (cellref DCM_SP (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "8:OUTPUT:STATUS<7:0>"))
+           (property CLKIN_DIVIDE_BY_2 (boolean (false)))
+           (property CLKOUT_PHASE_SHIFT (string "NONE"))
+           (property CLK_FEEDBACK (string "1X"))
+           (property DESKEW_ADJUST (string "SYSTEM_SYNCHRONOUS"))
+           (property DFS_FREQUENCY_MODE (string "LOW"))
+           (property DLL_FREQUENCY_MODE (string "LOW"))
+           (property DSS_MODE (string "NONE"))
+           (property DUTY_CYCLE_CORRECTION (boolean (true)))
+           (property FACTORY_JF (string "16'hC080"))
+           (property STARTUP_WAIT (boolean (false)))
+           (property CLKFX_DIVIDE (integer 2))
+           (property CLKFX_MULTIPLY (integer 5))
+           (property PHASE_SHIFT (integer 0))
+           (property CLKDV_DIVIDE (string "2.000000"))
+           (property CLKIN_PERIOD (string "25.000000"))
+           (property VERY_HIGH_FREQUENCY (string "FALSE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_13_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/clear_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hFFFFFFFFFFFFFFFE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[24].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[19].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f1_Mcount_wr_addr_cy_7__rt "f1/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___6___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11"))
+           (property INIT (string "32'h8A8ADF8A"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<8>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[7].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___25___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511"))
+           (property INIT (string "8'hBF"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_12__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_10_ "f1/Mcount_rd_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___2___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0"))
+           (property INIT (string "16'h8000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_Mcount_rd_addr_cy_11_ "f1/Mcount_rd_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance debug_21_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance debug_16_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/read_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "32'h80000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Result_7_2_FRB "f0/Result<7>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcount_wr_addr_xor_12__rt "f0/Mcount_wr_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<4>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h6AAAAAAAAAAAAAA9"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[32].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[27].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_write_ready_go "slave_fifo32/write_ready_go") (viewref netlist (cellref FD (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata101 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata101") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___102___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata101"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_14_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_14_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0 "slave_fifo32/Mmux_state[1]_wr_fifo_eof_Mux_22_o1_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___24___slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0"))
+           (property INIT (string "32'h80008080"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata110") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___113___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata110"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata111 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___101___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata111"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata121 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata121") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___112___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata121"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/i_tvalid_o_tready_AND_73_o1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___125___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11"))
+           (property INIT (string "4'h4"))
+         )
+         (instance (rename f0_Mcount_wr_addr_lut_0__INV_0 "f0/Mcount_wr_addr_lut<0>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcount_rd_addr_lut_0__INV_0 "f0/Mcount_rd_addr_lut<0>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h1"))
+           (property XILINX_LEGACY_PRIM (string "INV"))
+           (property XILINX_REPORT_XFORM (string "INV"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata131 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata131") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___100___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata131"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<10>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB4BBBBBBB4BBB4B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[11].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata141 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata141") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___99___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata141"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<11>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB4BBBBBBB4BBB4B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tready_int1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h00000C0000000800"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata151 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata151") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___98___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata151"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<12>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB4BBBBBBB4BBB4B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata201 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata201") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___93___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata201"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename f1_wr_addr_10 "f1/wr_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f1_wr_addr_11 "f1/wr_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "8'hFB"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_wr_addr_12 "f1/wr_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata210 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata210") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___110___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata210"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata161 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata161") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___97___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata161"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<13>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB4BBBBBBB4BBB4B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h0000000100000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata211 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata211") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___91___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata211"))
+           (property INIT (string "4'h8"))
+         )
+         (instance debug_22_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance debug_17_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property CAPACITANCE (string "DONT_CARE"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[12].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB4BBBBBBB4BBB4B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'h7FFF7F7F2AFF2A2A"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata221 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata221") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___90___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata221"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata171 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata171") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___96___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata171"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[40].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[35].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance GPIF_D_14_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives)))
+           (property XILINX_REPORT_XFORM (string "IOBUF"))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Msub_dont_write_past_me_cy_0__rt "f0/Msub_dont_write_past_me_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<15>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "64'hBB4BBBBBBB4BBB4B"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata231 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata231") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___83___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata231"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata181 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata181") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___95___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata181"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___49___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011"))
+           (property INIT (string "8'h9F"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata241 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata241") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___89___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata241"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata191 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata191") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___94___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata191"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_15_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b0"))
+         )
+         (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata301 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata301") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___103___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata301"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata251 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata251") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___88___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata251"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata310 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata310") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___82___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata310"))
+           (property INIT (string "4'h8"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[14].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property BUS_INFO (string "5:INPUT:A<4:0>"))
+           (property INIT (string "32'h00000000"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata311 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata311") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___92___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata311"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata261 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata261") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___113___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata110"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename f1_dont_write_past_me_0__FRB "f1/dont_write_past_me<0>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "1'b1"))
+         )
+         (instance (rename f1_Mcompar_becoming_full_cy_0_ "f1/Mcompar_becoming_full_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata321 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata321") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___87___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata321"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata271 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata271") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___112___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata121"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property INIT (string "2'h2"))
+         )
+         (instance (rename f1_Mcompar_becoming_full_cy_1_ "f1/Mcompar_becoming_full_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata331 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata331") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___86___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata331"))
+           (property INIT (string "8'hE4"))
+         )
+         (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata281 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata281") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
+           (property XSTLIB (boolean (true)))
+           (property PK_HLUTNM (string "___XLNM___83___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata231"))
+           (property INIT (string "8'hE4"))
+         )
+         (net codec_main_clk_n (joined
+          (portref IB (instanceref gen_clks_clkin1_buf))
+          (portref codec_main_clk_n)
+          )
+
+           (property DIFF_TERM (boolean (false)))
+         )
+         (net codec_main_clk_p (joined
+          (portref I (instanceref gen_clks_clkin1_buf))
+          (portref codec_main_clk_p)
+          )
+
+           (property DIFF_TERM (boolean (false)))
+         )
+         (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[0]") (joined
+          (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref S (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1_))
+          )
+         )
+         (net (rename f0_Result_7_1_FRB "f0/Result<7>1_FRB") (joined
+          (portref D (instanceref f0_rd_addr_7))
+          (portref Q (instanceref f0_Result_7_1_FRB))
+          (portref I0 (instanceref f0_Mcount_rd_addr_cy_7__rt))
+          (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_7__INV_0))
+          )
+         )
+         (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[1]") (joined
+          (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref S (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2_))
+          )
+         )
+         (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[2]") (joined
+          (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref S (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3_))
+          )
+         )
+         (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[3]") (joined
+          (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref S (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4_))
+          )
+         )
+         (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[4]") (joined
+          (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_))
+          (portref S (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i64_tready "slave_fifo32/fifo64_to_gpmc32_rx/i64_tready") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_i_tready1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo_rst_gpif_rst_OR_155_o "slave_fifo32/fifo64_to_gpmc32_resp/fifo_rst_gpif_rst_OR_155_o") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo_rst_gpif_rst_OR_155_o1))
+          (portref rst (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref rst (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref rst (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          (portref rst (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<8>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<1>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[9]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_10_))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_9__rt "f1/Mcount_rd_addr_cy<9>_rt") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_9__rt))
+          (portref S (instanceref f1_Mcount_rd_addr_cy_9_))
+          (portref LI (instanceref f1_Mcount_rd_addr_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__rt))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9_))
+          )
+         )
+         (net (rename f0_rd_addr_12__wr_addr_12__equal_11_o_l1 "f0/rd_addr[12]_wr_addr[12]_equal_11_o_l1") (joined
+          (portref O (instanceref f0__n0161_inv1_cy))
+          (portref CI (instanceref f0__n0161_inv1_cy1))
+          )
+         )
+         (net (rename slave_fifo32_Mcount_idle_cycles1 "slave_fifo32/Mcount_idle_cycles1") (joined
+          (portref D (instanceref slave_fifo32_idle_cycles_1))
+          (portref O (instanceref slave_fifo32_Mcount_idle_cycles_xor_1_11))
+          )
+         )
+         (net (rename slave_fifo32_Mcount_idle_cycles2 "slave_fifo32/Mcount_idle_cycles2") (joined
+          (portref D (instanceref slave_fifo32_idle_cycles_2))
+          (portref O (instanceref slave_fifo32_Mcount_idle_cycles_xor_2_11))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_5__rt "f0/Mcount_rd_addr_cy<5>_rt") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_5__rt))
+          (portref S (instanceref f0_Mcount_rd_addr_cy_5_))
+          (portref LI (instanceref f0_Mcount_rd_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst))
+          )
+         )
+         (net (rename f0_wr_addr_0_ "f0/wr_addr[0]") (joined
+          (portref Q (instanceref f0_wr_addr_0))
+          (portref I1 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref I0 (instanceref f0_Mcompar_becoming_full_lut_0_))
+          (portref (member ADDRAWRADDR 12) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f0_wr_addr_1_ "f0/wr_addr[1]") (joined
+          (portref Q (instanceref f0_wr_addr_1))
+          (portref I3 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref I2 (instanceref f0_Mcompar_becoming_full_lut_0_))
+          (portref (member ADDRAWRADDR 11) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_10__rt "f0/Mcount_rd_addr_cy<10>_rt") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_10__rt))
+          (portref S (instanceref f0_Mcount_rd_addr_cy_10_))
+          (portref LI (instanceref f0_Mcount_rd_addr_xor_10_))
+          )
+         )
+         (net (rename f0_wr_addr_2_ "f0/wr_addr[2]") (joined
+          (portref Q (instanceref f0_wr_addr_2))
+          (portref I5 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref I4 (instanceref f0_Mcompar_becoming_full_lut_0_))
+          (portref (member ADDRAWRADDR 10) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f0_wr_addr_3_ "f0/wr_addr[3]") (joined
+          (portref Q (instanceref f0_wr_addr_3))
+          (portref I1 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref I0 (instanceref f0_Mcompar_becoming_full_lut_1_))
+          (portref (member ADDRAWRADDR 9) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f0_wr_addr_4_ "f0/wr_addr[4]") (joined
+          (portref Q (instanceref f0_wr_addr_4))
+          (portref I3 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref I2 (instanceref f0_Mcompar_becoming_full_lut_1_))
+          (portref (member ADDRAWRADDR 8) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f0_wr_addr_5_ "f0/wr_addr[5]") (joined
+          (portref Q (instanceref f0_wr_addr_5))
+          (portref I5 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref I4 (instanceref f0_Mcompar_becoming_full_lut_1_))
+          (portref (member ADDRAWRADDR 7) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f0_wr_addr_6_ "f0/wr_addr[6]") (joined
+          (portref Q (instanceref f0_wr_addr_6))
+          (portref I1 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref I0 (instanceref f0_Mcompar_becoming_full_lut_2_))
+          (portref (member ADDRAWRADDR 6) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f0_Result_5_2_FRB "f0/Result<5>2_FRB") (joined
+          (portref D (instanceref f0_wr_addr_5))
+          (portref Q (instanceref f0_Result_5_2_FRB))
+          (portref I0 (instanceref f0_Mcount_wr_addr_cy_5__rt))
+          )
+         )
+         (net (rename f0_wr_addr_7_ "f0/wr_addr[7]") (joined
+          (portref Q (instanceref f0_wr_addr_7))
+          (portref I3 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref I2 (instanceref f0_Mcompar_becoming_full_lut_2_))
+          (portref (member ADDRAWRADDR 5) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f0_wr_addr_8_ "f0/wr_addr[8]") (joined
+          (portref Q (instanceref f0_wr_addr_8))
+          (portref I5 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref I4 (instanceref f0_Mcompar_becoming_full_lut_2_))
+          (portref (member ADDRAWRADDR 4) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f0_wr_addr_9_ "f0/wr_addr[9]") (joined
+          (portref Q (instanceref f0_wr_addr_9))
+          (portref I1 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref I0 (instanceref f0_Mcompar_becoming_full_lut_3_))
+          (portref (member ADDRAWRADDR 3) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<8>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__rt))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net (rename f0_rd_addr_10_ "f0/rd_addr[10]") (joined
+          (portref Q (instanceref f0_rd_addr_10))
+          (portref I2 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref (member ADDRBRDADDR 2) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f1_Result_11_1_FRB "f1/Result<11>1_FRB") (joined
+          (portref D (instanceref f1_rd_addr_11))
+          (portref Q (instanceref f1_Result_11_1_FRB))
+          (portref I0 (instanceref f1_Mcount_rd_addr_cy_11__rt))
+          (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_11__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14))
+          )
+         )
+         (net (rename f0_rd_addr_11_ "f0/rd_addr[11]") (joined
+          (portref Q (instanceref f0_rd_addr_11))
+          (portref I4 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref (member ADDRBRDADDR 1) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f0_rd_addr_12_ "f0/rd_addr[12]") (joined
+          (portref Q (instanceref f0_rd_addr_12))
+          (portref I0 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_))
+          (portref (member ADDRBRDADDR 0) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01216))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full921))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9__rt))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_write "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/write") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_write1))
+          (portref wr_en (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[3]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_3))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename f0_dont_write_past_me_10__FRB "f0/dont_write_past_me<10>_FRB") (joined
+          (portref I3 (instanceref f0_Mcompar_becoming_full_lut_3_))
+          (portref Q (instanceref f0_dont_write_past_me_10__FRB))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_6__rt "f1/Mcount_wr_addr_cy<6>_rt") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_6__rt))
+          (portref S (instanceref f1_Mcount_wr_addr_cy_6_))
+          (portref LI (instanceref f1_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[4]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_4))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+          )
+         )
+         (net (rename slave_fifo32__n0230_inv "slave_fifo32/_n0230_inv") (joined
+          (portref CE (instanceref slave_fifo32_idle_cycles_0))
+          (portref CE (instanceref slave_fifo32_idle_cycles_1))
+          (portref CE (instanceref slave_fifo32_idle_cycles_2))
+          (portref O (instanceref slave_fifo32__n0230_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[5]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_5))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[6]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_6))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0121111))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61))
+          )
+         )
+         (net (rename f1_Result_3_1_FRB "f1/Result<3>1_FRB") (joined
+          (portref D (instanceref f1_rd_addr_3))
+          (portref Q (instanceref f1_Result_3_1_FRB))
+          (portref I0 (instanceref f1_Mcount_rd_addr_cy_3__rt))
+          (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_3__INV_0))
+          )
+         )
+         (net (rename f1_read_state_FSM_FFd1_In1 "f1/read_state_FSM_FFd1-In1") (joined
+          (portref D (instanceref f1_read_state_FSM_FFd1))
+          (portref O (instanceref f1_read_state_FSM_FFd1_In111))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[7]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_7))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr10") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_10_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr11") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_11_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr12") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_12_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_10__rt "f0/Mcount_wr_addr_cy<10>_rt") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_10__rt))
+          (portref S (instanceref f0_Mcount_wr_addr_cy_10_))
+          (portref LI (instanceref f0_Mcount_wr_addr_xor_10_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0121 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01219))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_10_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[10]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata210))
+          (portref (member din 61) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_11_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[11]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata33))
+          (portref (member din 60) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_12_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[12]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata41))
+          (portref (member din 59) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_13_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[13]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata51))
+          (portref (member din 58) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_14_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[14]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata61))
+          (portref (member din 57) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f1__n0161_inv "f1/_n0161_inv") (joined
+          (portref CE (instanceref f1_rd_addr_1))
+          (portref CE (instanceref f1_rd_addr_2))
+          (portref CE (instanceref f1_rd_addr_3))
+          (portref CE (instanceref f1_rd_addr_4))
+          (portref CE (instanceref f1_rd_addr_5))
+          (portref CE (instanceref f1_rd_addr_6))
+          (portref CE (instanceref f1_rd_addr_7))
+          (portref CE (instanceref f1_rd_addr_8))
+          (portref CE (instanceref f1_rd_addr_9))
+          (portref CE (instanceref f1_rd_addr_10))
+          (portref CE (instanceref f1_rd_addr_11))
+          (portref CE (instanceref f1_rd_addr_12))
+          (portref CE (instanceref f1_rd_addr_0))
+          (portref CE (instanceref f1_Result_0_1_FRB))
+          (portref CE (instanceref f1_Result_1_1_FRB))
+          (portref CE (instanceref f1_Result_2_1_FRB))
+          (portref CE (instanceref f1_Result_3_1_FRB))
+          (portref CE (instanceref f1_Result_4_1_FRB))
+          (portref CE (instanceref f1_Result_5_1_FRB))
+          (portref CE (instanceref f1_Result_6_1_FRB))
+          (portref CE (instanceref f1_Result_7_1_FRB))
+          (portref CE (instanceref f1_Result_8_1_FRB))
+          (portref CE (instanceref f1_Result_9_1_FRB))
+          (portref CE (instanceref f1_Result_10_1_FRB))
+          (portref CE (instanceref f1_Result_11_1_FRB))
+          (portref CE (instanceref f1_Result_12_1_FRB))
+          (portref CE (instanceref f1_dont_write_past_me_0__FRB))
+          (portref CE (instanceref f1_dont_write_past_me_1__FRB))
+          (portref CE (instanceref f1_dont_write_past_me_2__FRB))
+          (portref CE (instanceref f1_dont_write_past_me_3__FRB))
+          (portref CE (instanceref f1_dont_write_past_me_4__FRB))
+          (portref CE (instanceref f1_dont_write_past_me_5__FRB))
+          (portref CE (instanceref f1_dont_write_past_me_6__FRB))
+          (portref CE (instanceref f1_dont_write_past_me_7__FRB))
+          (portref CE (instanceref f1_dont_write_past_me_8__FRB))
+          (portref CE (instanceref f1_dont_write_past_me_9__FRB))
+          (portref CE (instanceref f1_dont_write_past_me_10__FRB))
+          (portref CE (instanceref f1_dont_write_past_me_11__FRB))
+          (portref CE (instanceref f1_dont_write_past_me_12__FRB))
+          (portref O (instanceref f1__n0161_inv1_cy1))
+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata131))
+          (portref (member din 51) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata71))
+          (portref (member din 56) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata141))
+          (portref (member din 50) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata81))
+          (portref (member din 55) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
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+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_1__rt "f0/Mcount_wr_addr_cy<1>_rt") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_1__rt))
+          (portref S (instanceref f0_Mcount_wr_addr_cy_1_))
+          (portref LI (instanceref f0_Mcount_wr_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_0))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_1))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_))
+          )
+         )
+         (net (rename slave_fifo32_idle_cycles_0_ "slave_fifo32/idle_cycles[0]") (joined
+          (portref Q (instanceref slave_fifo32_idle_cycles_0))
+          (portref I1 (instanceref slave_fifo32_Mcount_idle_cycles_xor_0_11))
+          (portref I2 (instanceref slave_fifo32_Mcount_idle_cycles_xor_2_11))
+          (portref I1 (instanceref slave_fifo32_Mcount_idle_cycles_xor_1_11))
+          (portref I0 (instanceref slave_fifo32__n0237_inv1))
+          (portref I2 (instanceref slave_fifo32_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_2))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_))
+          )
+         )
+         (net (rename slave_fifo32_idle_cycles_1_ "slave_fifo32/idle_cycles[1]") (joined
+          (portref Q (instanceref slave_fifo32_idle_cycles_1))
+          (portref I3 (instanceref slave_fifo32_Mcount_idle_cycles_xor_2_11))
+          (portref I2 (instanceref slave_fifo32_Mcount_idle_cycles_xor_1_11))
+          (portref I1 (instanceref slave_fifo32__n0237_inv1))
+          (portref I3 (instanceref slave_fifo32_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[3]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_))
+          )
+         )
+         (net (rename slave_fifo32_idle_cycles_2_ "slave_fifo32/idle_cycles[2]") (joined
+          (portref Q (instanceref slave_fifo32_idle_cycles_2))
+          (portref I1 (instanceref slave_fifo32_Mcount_idle_cycles_xor_2_11))
+          (portref I2 (instanceref slave_fifo32__n0237_inv1))
+          (portref I0 (instanceref slave_fifo32_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_))
+          (portref (member ADDRAWRADDR 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[4]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_4))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0154_inv1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_))
+          (portref (member ADDRAWRADDR 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net N0 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[5]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_5))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_))
+          )
+         )
+         (net N2 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read))
+          )
+         )
+         (net N4 (joined
+          (portref O (instanceref slave_fifo32__n0258_inv_SW0))
+          (portref I2 (instanceref slave_fifo32_wr_one_rstpot))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_2))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_))
+          (portref (member ADDRAWRADDR 10) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
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+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[9]") (joined
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_3_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[3]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_3_))
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 68) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename tx_tdata_0_ "tx_tdata[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[11]") (joined
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11_))
+          (portref (member DIA 20) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F))
+          (portref (member dout 60) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr[6]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_6))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_))
+          (portref (member ADDRAWRADDR 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_4_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[4]") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_4_))
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member dout 67) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename tx_tdata_1_ "tx_tdata[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[12]") (joined
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12_))
+          (portref (member DIA 19) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F))
+          (portref (member dout 59) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_0))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__rt))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr[7]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_7))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_))
+          (portref (member ADDRAWRADDR 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_5_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[5]") (joined
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_5_))
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW1))
+          (portref (member dout 66) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename tx_tdata_2_ "tx_tdata[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[13]") (joined
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13_))
+          (portref (member DIA 18) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31))
+          (portref (member dout 58) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr[8]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_8))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_))
+          (portref (member ADDRAWRADDR 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr1_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_1))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr[10]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_10))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_))
+          (portref (member ADDRAWRADDR 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_6_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[6]") (joined
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_6_))
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21))
+          (portref (member dout 65) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename tx_tdata_3_ "tx_tdata[3]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[14]") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14_))
+          (portref (member DIA 17) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F))
+          (portref (member dout 57) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr[9]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_9))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_))
+          (portref (member ADDRAWRADDR 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[0]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr[11]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_11))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_))
+          (portref (member ADDRAWRADDR 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_7_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[7]") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_7_))
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21))
+          (portref (member dout 64) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename tx_tdata_4_ "tx_tdata[4]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram3))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_20_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[20]") (joined
+          (portref (member DIA 29) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 51) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[15]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15_))
+          (portref (member DIA 16) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F))
+          (portref (member dout 56) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[1]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full1021))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW1))
+          )
+         )
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+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_12))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4_))
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+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
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+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
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+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_8_))
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member dout 63) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename tx_tdata_5_ "tx_tdata[5]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram3))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_16_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[16]") (joined
+          (portref (member DIPA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 55) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_21_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[21]") (joined
+          (portref (member DIA 28) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 50) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[2]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_9_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[9]") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_9_))
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1))
+          (portref (member dout 62) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename tx_tdata_6_ "tx_tdata[6]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_22_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[22]") (joined
+          (portref (member DIA 27) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 49) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_17_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[17]") (joined
+          (portref (member DIPA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 54) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[3]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211))
+          )
+         )
+         (net (rename tx_tdata_7_ "tx_tdata[7]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_23_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[23]") (joined
+          (portref (member DIA 26) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 48) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_18_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[18]") (joined
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 53) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32__n0290_inv "slave_fifo32/_n0290_inv") (joined
+          (portref O (instanceref slave_fifo32__n0290_inv1))
+          (portref I0 (instanceref slave_fifo32_sloe_rstpot))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[4]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr5_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_5))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr5_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5__rt))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621))
+          )
+         )
+         (net (rename tx_tdata_8_ "tx_tdata[8]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram5))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_19_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[19]") (joined
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 52) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_24_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[24]") (joined
+          (portref (member DIA 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 47) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f0_Result_9_1_FRB "f0/Result<9>1_FRB") (joined
+          (portref D (instanceref f0_rd_addr_9))
+          (portref Q (instanceref f0_Result_9_1_FRB))
+          (portref I0 (instanceref f0_Mcount_rd_addr_cy_9__rt))
+          (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_9__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[5]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211))
+          )
+         )
+         (net (rename tx_tdata_9_ "tx_tdata[9]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram5))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/read") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read))
+          (portref rd_en (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_30_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[30]") (joined
+          (portref (member DIA 19) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 41) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_25_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[25]") (joined
+          (portref (member DIA 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 46) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[6]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_31_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[31]") (joined
+          (portref (member DIA 18) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 40) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_26_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[26]") (joined
+          (portref (member DIA 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 45) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[7]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_27_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[27]") (joined
+          (portref (member DIA 22) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 44) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_32_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[32]") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G))
+          (portref (member dout 39) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[8]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tlast "slave_fifo32/fifo64_to_gpmc32_resp/i32_tlast") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_o_tlast1))
+          (portref (member din 39) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_28_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[28]") (joined
+          (portref (member DIA 21) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 43) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[9]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[29]") (joined
+          (portref (member DIA 20) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 42) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tvalid "slave_fifo32/data_rx_tvalid") (joined
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1))
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tvalid11))
+          (portref I5 (instanceref slave_fifo32_state_FSM_FFd1_In2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_10_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[10]") (joined
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10_))
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member dout 61) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_11_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[11]") (joined
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11_))
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member dout 60) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_12_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[12]") (joined
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12_))
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member dout 59) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write1))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member WEAWEL 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member WEAWEL 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_13_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[13]") (joined
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F))
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW1))
+          (portref (member dout 58) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_14_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[14]") (joined
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F))
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW1))
+          (portref (member dout 57) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg_glue_set") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set))
+          )
+         )
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+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_4))
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+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt))
+          )
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+          )
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+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F))
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW1))
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+          )
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+          )
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+          (portref (member dout 55) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212))
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+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421_FRB))
+          )
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+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB))
+          )
+         )
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+          )
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+          )
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+          )
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+          )
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+          )
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+          )
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+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr4_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621))
+          )
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+          )
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+          )
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+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata210))
+          )
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+          )
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+          )
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+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata33))
+          )
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+          )
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+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          (portref (member dout 39) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0003_12_ "slave_fifo32/fifo64_to_gpmc32_rx/n0003[12]") (joined
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+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata41))
+          )
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+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_10_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0))
+          )
+         )
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+          (portref (member dout 43) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata51))
+          )
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+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_11_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0))
+          )
+         )
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+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB0))
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+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_))
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+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_))
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+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_write_AND_42_o_inv2))
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+          (portref (member dout 42) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_10_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_11_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_12_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_10_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_11_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_12_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][4]") (joined
+          (portref (member DOB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member din 67) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv3") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv31))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01214))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_full "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/full") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_GND_50_o_read_OR_57_o1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_write1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv31))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0144_inv1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_write_AND_42_o_inv2))
+          (portref full (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][5]") (joined
+          (portref (member DOB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member din 66) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][6]") (joined
+          (portref (member DOB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member din 65) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][7]") (joined
+          (portref (member DOB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member din 64) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][8]") (joined
+          (portref (member DOB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member din 63) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][9]") (joined
+          (portref (member DOB 22) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member din 62) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f1_Result_11_2_FRB "f1/Result<11>2_FRB") (joined
+          (portref D (instanceref f1_wr_addr_11))
+          (portref Q (instanceref f1_Result_11_2_FRB))
+          (portref I0 (instanceref f1_Mcount_wr_addr_cy_11__rt))
+          )
+         )
+         (net fx3_miso (joined
+          (portref O (instanceref fx3_miso_OBUF))
+          (portref fx3_miso)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state_glue_set") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set))
+          )
+         )
+         (net tx_tlast (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref (member DIADI 15) (instanceref f1_ram_Mram_ram33))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_empty "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/empty") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_read1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In12_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14))
+          (portref empty (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_7__rt "f1/Mcount_wr_addr_cy<7>_rt") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_7__rt))
+          (portref S (instanceref f1_Mcount_wr_addr_cy_7_))
+          (portref LI (instanceref f1_Mcount_wr_addr_xor_7_))
+          )
+         )
+         (net (rename f1_Result_3_2_FRB "f1/Result<3>2_FRB") (joined
+          (portref D (instanceref f1_wr_addr_3))
+          (portref Q (instanceref f1_Result_3_2_FRB))
+          (portref I0 (instanceref f1_Mcount_wr_addr_cy_3__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1_))
+          )
+         )
+         (net (rename gen_clks_clk0 "gen_clks/clk0") (joined
+          (portref I (instanceref gen_clks_clkout1_buf))
+          (portref CLK0 (instanceref gen_clks_dcm_sp_inst))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_11__rt "f0/Mcount_wr_addr_cy<11>_rt") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_11__rt))
+          (portref S (instanceref f0_Mcount_wr_addr_cy_11_))
+          (portref LI (instanceref f0_Mcount_wr_addr_xor_11_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_0_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[0]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata110))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata261))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_11_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_))
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+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9_))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_cy_1__rt "f0/Msub_dont_write_past_me_cy<1>_rt") (joined
+          (portref O (instanceref f0_Msub_dont_write_past_me_cy_1__rt))
+          (portref S (instanceref f0_Msub_dont_write_past_me_cy_1_))
+          (portref LI (instanceref f0_Msub_dont_write_past_me_xor_1_))
+          )
+         )
+         (net fx3_mosi (joined
+          (portref I (instanceref fx3_mosi_IBUF))
+          (portref fx3_mosi)
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_10_ "f1/Mcount_wr_addr_cy[10]") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_10_))
+          (portref CI (instanceref f1_Mcount_wr_addr_cy_11_))
+          (portref CI (instanceref f1_Mcount_wr_addr_xor_11_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>_inv") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_13_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_))
+          )
+         )
+         (net (rename f1_rd_addr_12__wr_addr_12__equal_11_o_l1 "f1/rd_addr[12]_wr_addr[12]_equal_11_o_l1") (joined
+          (portref O (instanceref f1__n0161_inv1_cy))
+          (portref CI (instanceref f1__n0161_inv1_cy1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_0))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state_glue_set") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/read") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read))
+          (portref rd_en (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv))
+          )
+         )
+         (net (rename bus_sync_reset_int "bus_sync/reset_int") (joined
+          (portref Q (instanceref bus_sync_reset_int))
+          (portref D (instanceref bus_sync_reset_out))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full92 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full92") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full921))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr3_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_3))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr3_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__rt))
+          )
+         )
+         (net tx_codec_d_3_OBUF (joined
+          (portref Q (instanceref catgen_gen_pins_3__oddr2))
+          (portref I (instanceref tx_codec_d_3_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr8_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_8))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_2__rt "f0/Mcount_wr_addr_cy<2>_rt") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_2__rt))
+          (portref S (instanceref f0_Mcount_wr_addr_cy_2_))
+          (portref LI (instanceref f0_Mcount_wr_addr_xor_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[0]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_0_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_0_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[1]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_1_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[2]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_2_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_2_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__rt))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[3]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_3_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_3_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full411_FRB") (joined
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_i_tvalid_int "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/i_tvalid_int") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[4]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_4_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[5]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_5_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[6]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_6_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_15_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[7]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_7_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[8]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_8_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_8_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_dont_write_past_me_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/dont_write_past_me[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1-In1") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[9]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_9_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_9_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full621_FRB") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0121111))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid_bdd2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid_bdd2") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid_bdd8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid_bdd8") (joined
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_o_tready_int "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/o_tready_int") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr2_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_2))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__rt))
+          )
+         )
+         (net tx_codec_d_5_OBUF (joined
+          (portref Q (instanceref catgen_gen_pins_5__oddr2))
+          (portref I (instanceref tx_codec_d_5_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[0]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRAWRADDR 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[1]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRAWRADDR 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr6_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_6))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr6_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6__rt))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[2]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRAWRADDR 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename f0_Result_9_2_FRB "f0/Result<9>2_FRB") (joined
+          (portref D (instanceref f0_wr_addr_9))
+          (portref Q (instanceref f0_Result_9_2_FRB))
+          (portref I0 (instanceref f0_Mcount_wr_addr_cy_9__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[3]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRAWRADDR 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[4]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRAWRADDR 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_4_))
+          )
+         )
+         (net tx_frame_p_OBUF (joined
+          (portref Q (instanceref catgen_oddr2_frame))
+          (portref I (instanceref tx_frame_p_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[5]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRAWRADDR 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_inv") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1))
+          )
+         )
+         (net IFCLK (joined
+          (portref O (instanceref IFCLK_OBUF))
+          (portref IFCLK)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[6]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRAWRADDR 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[7]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRAWRADDR 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[8]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRAWRADDR 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[9]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRAWRADDR 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename bus_sync_reset_out "bus_sync/reset_out") (joined
+          (portref Q (instanceref bus_sync_reset_out))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_5))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_6))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_7))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_8))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_9))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_11))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9))
+          (portref R (instanceref f1_read_state_FSM_FFd2))
+          (portref R (instanceref f0_read_state_FSM_FFd2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7))
+          (portref R (instanceref f1_wr_addr_9))
+          (portref R (instanceref f1_wr_addr_8))
+          (portref R (instanceref f1_wr_addr_7))
+          (portref R (instanceref f1_wr_addr_6))
+          (portref R (instanceref f1_wr_addr_5))
+          (portref R (instanceref f1_wr_addr_4))
+          (portref R (instanceref f1_wr_addr_3))
+          (portref R (instanceref f1_wr_addr_2))
+          (portref R (instanceref f1_wr_addr_12))
+          (portref R (instanceref f1_wr_addr_11))
+          (portref R (instanceref f1_wr_addr_10))
+          (portref R (instanceref f1_wr_addr_1))
+          (portref R (instanceref f1_wr_addr_0))
+          (portref R (instanceref f1_rd_addr_9))
+          (portref R (instanceref f1_rd_addr_8))
+          (portref R (instanceref f1_rd_addr_7))
+          (portref R (instanceref f1_rd_addr_6))
+          (portref R (instanceref f1_rd_addr_5))
+          (portref R (instanceref f1_rd_addr_4))
+          (portref R (instanceref f1_rd_addr_3))
+          (portref R (instanceref f1_rd_addr_2))
+          (portref R (instanceref f1_rd_addr_12))
+          (portref R (instanceref f1_rd_addr_11))
+          (portref R (instanceref f1_rd_addr_10))
+          (portref R (instanceref f1_rd_addr_1))
+          (portref R (instanceref f1_rd_addr_0))
+          (portref R (instanceref f1_read_state_FSM_FFd1))
+          (portref R (instanceref f0_wr_addr_9))
+          (portref R (instanceref f0_wr_addr_8))
+          (portref R (instanceref f0_wr_addr_7))
+          (portref R (instanceref f0_wr_addr_6))
+          (portref R (instanceref f0_wr_addr_5))
+          (portref R (instanceref f0_wr_addr_4))
+          (portref R (instanceref f0_wr_addr_3))
+          (portref R (instanceref f0_wr_addr_2))
+          (portref R (instanceref f0_wr_addr_12))
+          (portref R (instanceref f0_wr_addr_11))
+          (portref R (instanceref f0_wr_addr_10))
+          (portref R (instanceref f0_wr_addr_1))
+          (portref R (instanceref f0_wr_addr_0))
+          (portref R (instanceref f0_rd_addr_9))
+          (portref R (instanceref f0_rd_addr_8))
+          (portref R (instanceref f0_rd_addr_7))
+          (portref R (instanceref f0_rd_addr_6))
+          (portref R (instanceref f0_rd_addr_5))
+          (portref R (instanceref f0_rd_addr_4))
+          (portref R (instanceref f0_rd_addr_3))
+          (portref R (instanceref f0_rd_addr_2))
+          (portref R (instanceref f0_rd_addr_12))
+          (portref R (instanceref f0_rd_addr_11))
+          (portref R (instanceref f0_rd_addr_10))
+          (portref R (instanceref f0_rd_addr_1))
+          (portref R (instanceref f0_rd_addr_0))
+          (portref R (instanceref f0_read_state_FSM_FFd1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo_rst_gpif_rst_OR_155_o1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump))
+          (portref R (instanceref f1_full_reg))
+          (portref R (instanceref f0_full_reg))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg))
+          (portref S (instanceref f1_Result_0_2_FRB))
+          (portref R (instanceref f1_Result_1_2_FRB))
+          (portref R (instanceref f1_Result_2_2_FRB))
+          (portref R (instanceref f1_Result_3_2_FRB))
+          (portref R (instanceref f1_Result_4_2_FRB))
+          (portref R (instanceref f1_Result_5_2_FRB))
+          (portref R (instanceref f1_Result_6_2_FRB))
+          (portref R (instanceref f1_Result_7_2_FRB))
+          (portref R (instanceref f1_Result_8_2_FRB))
+          (portref R (instanceref f1_Result_9_2_FRB))
+          (portref R (instanceref f1_Result_10_2_FRB))
+          (portref R (instanceref f1_Result_11_2_FRB))
+          (portref R (instanceref f1_Result_12_2_FRB))
+          (portref S (instanceref f1_Result_0_1_FRB))
+          (portref R (instanceref f1_Result_1_1_FRB))
+          (portref R (instanceref f1_Result_2_1_FRB))
+          (portref R (instanceref f1_Result_3_1_FRB))
+          (portref R (instanceref f1_Result_4_1_FRB))
+          (portref R (instanceref f1_Result_5_1_FRB))
+          (portref R (instanceref f1_Result_6_1_FRB))
+          (portref R (instanceref f1_Result_7_1_FRB))
+          (portref R (instanceref f1_Result_8_1_FRB))
+          (portref R (instanceref f1_Result_9_1_FRB))
+          (portref R (instanceref f1_Result_10_1_FRB))
+          (portref R (instanceref f1_Result_11_1_FRB))
+          (portref R (instanceref f1_Result_12_1_FRB))
+          (portref S (instanceref f1_dont_write_past_me_0__FRB))
+          (portref R (instanceref f1_dont_write_past_me_1__FRB))
+          (portref S (instanceref f1_dont_write_past_me_2__FRB))
+          (portref S (instanceref f1_dont_write_past_me_3__FRB))
+          (portref S (instanceref f1_dont_write_past_me_4__FRB))
+          (portref S (instanceref f1_dont_write_past_me_5__FRB))
+          (portref S (instanceref f1_dont_write_past_me_6__FRB))
+          (portref S (instanceref f1_dont_write_past_me_7__FRB))
+          (portref S (instanceref f1_dont_write_past_me_8__FRB))
+          (portref S (instanceref f1_dont_write_past_me_9__FRB))
+          (portref S (instanceref f1_dont_write_past_me_10__FRB))
+          (portref S (instanceref f1_dont_write_past_me_11__FRB))
+          (portref S (instanceref f1_dont_write_past_me_12__FRB))
+          (portref S (instanceref f0_Result_0_2_FRB))
+          (portref R (instanceref f0_Result_1_2_FRB))
+          (portref R (instanceref f0_Result_2_2_FRB))
+          (portref R (instanceref f0_Result_3_2_FRB))
+          (portref R (instanceref f0_Result_4_2_FRB))
+          (portref R (instanceref f0_Result_5_2_FRB))
+          (portref R (instanceref f0_Result_6_2_FRB))
+          (portref R (instanceref f0_Result_7_2_FRB))
+          (portref R (instanceref f0_Result_8_2_FRB))
+          (portref R (instanceref f0_Result_9_2_FRB))
+          (portref R (instanceref f0_Result_10_2_FRB))
+          (portref R (instanceref f0_Result_11_2_FRB))
+          (portref R (instanceref f0_Result_12_2_FRB))
+          (portref S (instanceref f0_Result_0_1_FRB))
+          (portref R (instanceref f0_Result_1_1_FRB))
+          (portref R (instanceref f0_Result_2_1_FRB))
+          (portref R (instanceref f0_Result_3_1_FRB))
+          (portref R (instanceref f0_Result_4_1_FRB))
+          (portref R (instanceref f0_Result_5_1_FRB))
+          (portref R (instanceref f0_Result_6_1_FRB))
+          (portref R (instanceref f0_Result_7_1_FRB))
+          (portref R (instanceref f0_Result_8_1_FRB))
+          (portref R (instanceref f0_Result_9_1_FRB))
+          (portref R (instanceref f0_Result_10_1_FRB))
+          (portref R (instanceref f0_Result_11_1_FRB))
+          (portref R (instanceref f0_Result_12_1_FRB))
+          (portref S (instanceref f0_dont_write_past_me_0__FRB))
+          (portref R (instanceref f0_dont_write_past_me_1__FRB))
+          (portref S (instanceref f0_dont_write_past_me_2__FRB))
+          (portref S (instanceref f0_dont_write_past_me_3__FRB))
+          (portref S (instanceref f0_dont_write_past_me_4__FRB))
+          (portref S (instanceref f0_dont_write_past_me_5__FRB))
+          (portref S (instanceref f0_dont_write_past_me_6__FRB))
+          (portref S (instanceref f0_dont_write_past_me_7__FRB))
+          (portref S (instanceref f0_dont_write_past_me_8__FRB))
+          (portref S (instanceref f0_dont_write_past_me_9__FRB))
+          (portref S (instanceref f0_dont_write_past_me_10__FRB))
+          (portref S (instanceref f0_dont_write_past_me_11__FRB))
+          (portref S (instanceref f0_dont_write_past_me_12__FRB))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1))
+          )
+         )
+         (net (rename f0_Result_11_1_FRB "f0/Result<11>1_FRB") (joined
+          (portref D (instanceref f0_rd_addr_11))
+          (portref Q (instanceref f0_Result_11_1_FRB))
+          (portref I0 (instanceref f0_Mcount_rd_addr_cy_11__rt))
+          (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_11__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[10]") (joined
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[11]") (joined
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[12]") (joined
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[13]") (joined
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_7))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_8))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB0") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[14]") (joined
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr5_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_5))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt))
+          )
+         )
+         (net (rename f1_Result_7_1_FRB "f1/Result<7>1_FRB") (joined
+          (portref D (instanceref f1_rd_addr_7))
+          (portref Q (instanceref f1_Result_7_1_FRB))
+          (portref I0 (instanceref f1_Mcount_rd_addr_cy_7__rt))
+          (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_7__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0_ "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e))
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+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_1_11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_3_11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_SW1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_0_11_INV_0))
+          )
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+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1))
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+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11))
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+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_SW0))
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+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2))
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+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr5_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr5_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__rt))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<12>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12__rt))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12_))
+          )
+         )
+         (net (rename ctrl_tdata_0_ "ctrl_tdata[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename ctrl_tdata_1_ "ctrl_tdata[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a1") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_0_11_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a2 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a2") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a3 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a3") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11))
+          )
+         )
+         (net (rename ctrl_tdata_2_ "ctrl_tdata[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a4 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a4") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a5 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a5") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11))
+          )
+         )
+         (net (rename ctrl_tdata_3_ "ctrl_tdata[3]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/full_reg_glue_set") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set))
+          )
+         )
+         (net (rename ctrl_tdata_4_ "ctrl_tdata[4]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram3))
+          )
+         )
+         (net (rename ctrl_tdata_5_ "ctrl_tdata[5]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram3))
+          )
+         )
+         (net (rename ctrl_tdata_6_ "ctrl_tdata[6]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram4))
+          )
+         )
+         (net (rename ctrl_tdata_7_ "ctrl_tdata[7]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write1))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_0_ "slave_fifo32/ctrl_rx_tdata[0]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename ctrl_tdata_8_ "ctrl_tdata[8]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram5))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_2_))
+          )
+         )
+         (net GPIF_CTL5_IBUF (joined
+          (portref D (instanceref slave_fifo32_EP_WMARK))
+          (portref O (instanceref GPIF_CTL5_IBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/GND_56_o_read_OR_123_o") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref ENBRDEN (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_1_ "slave_fifo32/ctrl_rx_tdata[1]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename ctrl_tdata_9_ "ctrl_tdata[9]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram5))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_2_ "slave_fifo32/ctrl_rx_tdata[2]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231))
+          (portref (member DOB 29) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a1") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_0_11_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a2 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a2") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_1_11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0154_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0154_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_6))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr6_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a3 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a3") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11))
+          )
+         )
+         (net (rename f1_GND_14_o_read_OR_37_o "f1/GND_14_o_read_OR_37_o") (joined
+          (portref O (instanceref f1_GND_14_o_read_OR_37_o1))
+          (portref ENBRDEN (instanceref f1_ram_Mram_ram33))
+          (portref ENB (instanceref f1_ram_Mram_ram31))
+          (portref ENB (instanceref f1_ram_Mram_ram30))
+          (portref ENB (instanceref f1_ram_Mram_ram32))
+          (portref ENB (instanceref f1_ram_Mram_ram28))
+          (portref ENB (instanceref f1_ram_Mram_ram27))
+          (portref ENB (instanceref f1_ram_Mram_ram29))
+          (portref ENB (instanceref f1_ram_Mram_ram25))
+          (portref ENB (instanceref f1_ram_Mram_ram24))
+          (portref ENB (instanceref f1_ram_Mram_ram26))
+          (portref ENB (instanceref f1_ram_Mram_ram22))
+          (portref ENB (instanceref f1_ram_Mram_ram21))
+          (portref ENB (instanceref f1_ram_Mram_ram23))
+          (portref ENB (instanceref f1_ram_Mram_ram19))
+          (portref ENB (instanceref f1_ram_Mram_ram18))
+          (portref ENB (instanceref f1_ram_Mram_ram20))
+          (portref ENB (instanceref f1_ram_Mram_ram16))
+          (portref ENB (instanceref f1_ram_Mram_ram15))
+          (portref ENB (instanceref f1_ram_Mram_ram17))
+          (portref ENB (instanceref f1_ram_Mram_ram14))
+          (portref ENB (instanceref f1_ram_Mram_ram13))
+          (portref ENB (instanceref f1_ram_Mram_ram12))
+          (portref ENB (instanceref f1_ram_Mram_ram11))
+          (portref ENB (instanceref f1_ram_Mram_ram9))
+          (portref ENB (instanceref f1_ram_Mram_ram8))
+          (portref ENB (instanceref f1_ram_Mram_ram10))
+          (portref ENB (instanceref f1_ram_Mram_ram6))
+          (portref ENB (instanceref f1_ram_Mram_ram5))
+          (portref ENB (instanceref f1_ram_Mram_ram7))
+          (portref ENB (instanceref f1_ram_Mram_ram3))
+          (portref ENB (instanceref f1_ram_Mram_ram2))
+          (portref ENB (instanceref f1_ram_Mram_ram4))
+          (portref ENB (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_4))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_5))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_6))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_7))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_8))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_9))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_3_ "slave_fifo32/ctrl_rx_tdata[3]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261))
+          (portref (member DOB 28) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a4 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a4") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_3_11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a5 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a5") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_4_ "slave_fifo32/ctrl_rx_tdata[4]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271))
+          (portref (member DOB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_slrd_rstpot "slave_fifo32/slrd_rstpot") (joined
+          (portref D (instanceref slave_fifo32_slrd))
+          (portref O (instanceref slave_fifo32_slrd_rstpot))
+          (portref D (instanceref slave_fifo32_slrd_1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_5_ "slave_fifo32/ctrl_rx_tdata[5]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281))
+          (portref (member DOB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<3>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_3_))
+          )
+         )
+         (net tx_codec_d_11_OBUF (joined
+          (portref Q (instanceref catgen_gen_pins_11__oddr2))
+          (portref I (instanceref tx_codec_d_11_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[10]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_6_ "slave_fifo32/ctrl_rx_tdata[6]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291))
+          (portref (member DOB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[11]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_7_ "slave_fifo32/ctrl_rx_tdata[7]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301))
+          (portref (member DOB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net tx_codec_d_9_OBUF (joined
+          (portref Q (instanceref catgen_gen_pins_9__oddr2))
+          (portref I (instanceref tx_codec_d_9_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[12]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_empty "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/empty") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1))
+          (portref empty (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_8_ "slave_fifo32/ctrl_rx_tdata[8]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311))
+          (portref (member DOB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[13]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_9_ "slave_fifo32/ctrl_rx_tdata[9]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321))
+          (portref (member DOB 22) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[14]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_0__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<0>_FRB") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_0__FRB))
+          )
+         )
+         (net (rename f1_Result_5_2_FRB "f1/Result<5>2_FRB") (joined
+          (portref D (instanceref f1_wr_addr_5))
+          (portref Q (instanceref f1_Result_5_2_FRB))
+          (portref I0 (instanceref f1_Mcount_wr_addr_cy_5__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_write "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_write1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<1>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_write "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/write") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_write1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_4))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_5))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_6))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_7))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_8))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_9))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr2_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr3_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_eof_Mux_22_o "slave_fifo32/state[1]_wr_fifo_eof_Mux_22_o") (joined
+          (portref D (instanceref slave_fifo32_pktend))
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1))
+          (portref D (instanceref slave_fifo32_pktend_1))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_7__rt "f0/Mcount_rd_addr_cy<7>_rt") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_7__rt))
+          (portref S (instanceref f0_Mcount_rd_addr_cy_7_))
+          (portref LI (instanceref f0_Mcount_rd_addr_xor_7_))
+          )
+         )
+         (net (rename f0_Result_0_1_FRB "f0/Result<0>1_FRB") (joined
+          (portref D (instanceref f0_rd_addr_0))
+          (portref Q (instanceref f0_Result_0_1_FRB))
+          (portref I0 (instanceref f0_Msub_dont_write_past_me_cy_0__rt))
+          (portref I0 (instanceref f0_Mcount_rd_addr_lut_0__INV_0))
+          )
+         )
+         (net fx3_sclk (joined
+          (portref I (instanceref fx3_sclk_IBUF))
+          (portref fx3_sclk)
+          )
+         )
+         (net GPIF_CTL11 (joined
+          (portref O (instanceref GPIF_CTL11_OBUF))
+          (portref GPIF_CTL11)
+          )
+         )
+         (net GPIF_CTL12 (joined
+          (portref O (instanceref GPIF_CTL12_OBUF))
+          (portref GPIF_CTL12)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3210 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3210") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_10_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3211") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_11_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3212 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3212") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In_bdd1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In_bdd1") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3213 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3213") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13))
+          )
+         )
+         (net (rename slave_fifo32_read_ready_go "slave_fifo32/read_ready_go") (joined
+          (portref Q (instanceref slave_fifo32_read_ready_go))
+          (portref I2 (instanceref slave_fifo32__n0290_inv1))
+          (portref I0 (instanceref slave_fifo32__n0258_inv_SW0))
+          (portref I1 (instanceref slave_fifo32__n0279_inv_SW0))
+          (portref I3 (instanceref slave_fifo32_state_FSM_FFd2_In2))
+          (portref I1 (instanceref slave_fifo32_slrd_rstpot_SW0))
+          (portref I2 (instanceref slave_fifo32_sloe_1_rstpot))
+          (portref I3 (instanceref slave_fifo32_state_FSM_FFd1_In3_F))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3214 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3214") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_14_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3215 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3215") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15))
+          )
+         )
+         (net (rename slave_fifo32_state_FSM_FFd1_In2 "slave_fifo32/state_FSM_FFd1-In2") (joined
+          (portref O (instanceref slave_fifo32_state_FSM_FFd1_In2))
+          (portref I1 (instanceref slave_fifo32_state_FSM_FFd1_In4))
+          (portref I3 (instanceref slave_fifo32_state_FSM_FFd2_In3))
+          )
+         )
+         (net (rename slave_fifo32_state_FSM_FFd1_In3 "slave_fifo32/state_FSM_FFd1-In3") (joined
+          (portref O (instanceref slave_fifo32_state_FSM_FFd1_In3))
+          (portref I0 (instanceref slave_fifo32_state_FSM_FFd1_In4))
+          )
+         )
+         (net (rename codec_ctrl_in_0_ "codec_ctrl_in[0]") (joined
+          (portref O (instanceref codec_ctrl_in_0_OBUF))
+          (portref (member codec_ctrl_in 3))
+          )
+         )
+         (net (rename codec_ctrl_in_1_ "codec_ctrl_in[1]") (joined
+          (portref O (instanceref codec_ctrl_in_1_OBUF))
+          (portref (member codec_ctrl_in 2))
+          )
+         )
+         (net (rename codec_ctrl_in_2_ "codec_ctrl_in[2]") (joined
+          (portref O (instanceref codec_ctrl_in_2_OBUF))
+          (portref (member codec_ctrl_in 1))
+          )
+         )
+         (net (rename codec_ctrl_in_3_ "codec_ctrl_in[3]") (joined
+          (portref O (instanceref codec_ctrl_in_3_OBUF))
+          (portref (member codec_ctrl_in 0))
+          )
+         )
+         (net codec_sync (joined
+          (portref O (instanceref codec_sync_OBUF))
+          (portref codec_sync)
+          )
+         )
+         (net (rename tx_tdata_10_ "tx_tdata[10]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram6))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1))
+          )
+         )
+         (net (rename tx_tdata_11_ "tx_tdata[11]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram6))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_1_))
+          )
+         )
+         (net (rename tx_tdata_12_ "tx_tdata[12]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram7))
+          )
+         )
+         (net ctrl_tlast (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref (member DIADI 15) (instanceref f0_ram_Mram_ram33))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_2__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<2>_FRB") (joined
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_2__FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_write "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/write") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_write1))
+          (portref wr_en (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename tx_tdata_13_ "tx_tdata[13]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram7))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_0))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_4_))
+          )
+         )
+         (net (rename tx_tdata_14_ "tx_tdata[14]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram8))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<0>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_5_))
+          )
+         )
+         (net (rename tx_tdata_20_ "tx_tdata[20]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram11))
+          )
+         )
+         (net (rename tx_tdata_15_ "tx_tdata[15]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram8))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_debug1_0_ "slave_fifo32/debug1[0]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_0))
+          (portref D (instanceref slave_fifo32_debug2_0))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_8__rt "f1/Mcount_wr_addr_cy<8>_rt") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_8__rt))
+          (portref S (instanceref f1_Mcount_wr_addr_cy_8_))
+          (portref LI (instanceref f1_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net (rename tx_tdata_16_ "tx_tdata[16]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram9))
+          )
+         )
+         (net (rename tx_tdata_21_ "tx_tdata[21]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_debug1_1_ "slave_fifo32/debug1[1]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_1))
+          (portref D (instanceref slave_fifo32_debug2_1))
+          )
+         )
+         (net (rename tx_tdata_22_ "tx_tdata[22]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram12))
+          )
+         )
+         (net (rename tx_tdata_17_ "tx_tdata[17]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram9))
+          )
+         )
+         (net (rename f1_rd_addr_10_ "f1/rd_addr[10]") (joined
+          (portref Q (instanceref f1_rd_addr_10))
+          (portref I2 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref (member ADDRBRDADDR 2) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_debug1_2_ "slave_fifo32/debug1[2]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_2))
+          (portref D (instanceref slave_fifo32_debug2_2))
+          )
+         )
+         (net (rename tx_tdata_23_ "tx_tdata[23]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram12))
+          )
+         )
+         (net (rename tx_tdata_18_ "tx_tdata[18]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram10))
+          )
+         )
+         (net (rename f1_rd_addr_11_ "f1/rd_addr[11]") (joined
+          (portref Q (instanceref f1_rd_addr_11))
+          (portref I4 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref (member ADDRBRDADDR 1) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_debug1_3_ "slave_fifo32/debug1[3]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_3))
+          (portref D (instanceref slave_fifo32_debug2_3))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full_glue_set") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set))
+          )
+         )
+         (net (rename tx_tdata_24_ "tx_tdata[24]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram13))
+          )
+         )
+         (net (rename tx_tdata_19_ "tx_tdata[19]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram10))
+          )
+         )
+         (net (rename f1_rd_addr_12_ "f1/rd_addr[12]") (joined
+          (portref Q (instanceref f1_rd_addr_12))
+          (portref I0 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_))
+          (portref (member ADDRBRDADDR 0) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[9]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_10_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2_))
+          )
+         )
+         (net (rename slave_fifo32_debug1_4_ "slave_fifo32/debug1[4]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_4))
+          (portref D (instanceref slave_fifo32_debug2_4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[10]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_11_))
+          )
+         )
+         (net (rename tx_tdata_30_ "tx_tdata[30]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram16))
+          )
+         )
+         (net (rename tx_tdata_25_ "tx_tdata[25]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram13))
+          )
+         )
+         (net (rename slave_fifo32_debug1_5_ "slave_fifo32/debug1[5]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_5))
+          (portref D (instanceref slave_fifo32_debug2_5))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[11]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_12_))
+          )
+         )
+         (net (rename tx_tdata_31_ "tx_tdata[31]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram16))
+          )
+         )
+         (net (rename tx_tdata_26_ "tx_tdata[26]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram14))
+          )
+         )
+         (net (rename slave_fifo32_debug1_6_ "slave_fifo32/debug1[6]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_6))
+          (portref D (instanceref slave_fifo32_debug2_6))
+          )
+         )
+         (net (rename tx_tdata_32_ "tx_tdata[32]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram17))
+          )
+         )
+         (net (rename tx_tdata_27_ "tx_tdata[27]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram14))
+          )
+         )
+         (net GPIF_CTL9_IBUF (joined
+          (portref RST (instanceref gen_clks_dcm_sp_inst))
+          (portref I1 (instanceref reset_global_locked_OR_1_o1))
+          (portref O (instanceref GPIF_CTL9_IBUF))
+          )
+         )
+         (net (rename slave_fifo32_debug1_7_ "slave_fifo32/debug1[7]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_7))
+          (portref D (instanceref slave_fifo32_debug2_7))
+          )
+         )
+         (net (rename tx_tdata_33_ "tx_tdata[33]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram17))
+          )
+         )
+         (net (rename tx_tdata_28_ "tx_tdata[28]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram15))
+          )
+         )
+         (net (rename slave_fifo32_debug1_8_ "slave_fifo32/debug1[8]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_8))
+          (portref D (instanceref slave_fifo32_debug2_8))
+          )
+         )
+         (net (rename tx_tdata_34_ "tx_tdata[34]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram18))
+          )
+         )
+         (net (rename tx_tdata_29_ "tx_tdata[29]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram15))
+          )
+         )
+         (net (rename slave_fifo32_debug1_9_ "slave_fifo32/debug1[9]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_9))
+          (portref D (instanceref slave_fifo32_debug2_9))
+          )
+         )
+         (net (rename tx_tdata_40_ "tx_tdata[40]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram21))
+          )
+         )
+         (net (rename tx_tdata_35_ "tx_tdata[35]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram18))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst))
+          )
+         )
+         (net (rename tx_tdata_41_ "tx_tdata[41]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram21))
+          )
+         )
+         (net (rename tx_tdata_36_ "tx_tdata[36]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram19))
+          )
+         )
+         (net (rename tx_tdata_42_ "tx_tdata[42]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram22))
+          )
+         )
+         (net (rename tx_tdata_37_ "tx_tdata[37]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram19))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set))
+          )
+         )
+         (net (rename tx_tdata_43_ "tx_tdata[43]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram22))
+          )
+         )
+         (net (rename tx_tdata_38_ "tx_tdata[38]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram20))
+          )
+         )
+         (net (rename tx_tdata_39_ "tx_tdata[39]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram20))
+          )
+         )
+         (net (rename tx_tdata_44_ "tx_tdata[44]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram23))
+          )
+         )
+         (net (rename tx_tdata_50_ "tx_tdata[50]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram26))
+          )
+         )
+         (net (rename tx_tdata_45_ "tx_tdata[45]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram23))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[10]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10_))
+          )
+         )
+         (net fx3_sclk_IBUF (joined
+          (portref I1 (instanceref cat_sclk1))
+          (portref O (instanceref fx3_sclk_IBUF))
+          )
+         )
+         (net (rename tx_tdata_51_ "tx_tdata[51]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram26))
+          )
+         )
+         (net (rename tx_tdata_46_ "tx_tdata[46]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram24))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[11]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_4__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<4>_FRB") (joined
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_4__FRB))
+          )
+         )
+         (net (rename tx_tdata_52_ "tx_tdata[52]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram27))
+          )
+         )
+         (net (rename tx_tdata_47_ "tx_tdata[47]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram24))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[12]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_10__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<10>_FRB") (joined
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_10__FRB))
+          )
+         )
+         (net (rename tx_tdata_53_ "tx_tdata[53]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram27))
+          )
+         )
+         (net (rename tx_tdata_48_ "tx_tdata[48]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram25))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[13]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13_))
+          )
+         )
+         (net (rename tx_tdata_54_ "tx_tdata[54]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram28))
+          )
+         )
+         (net (rename tx_tdata_49_ "tx_tdata[49]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram25))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[14]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_4))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt))
+          )
+         )
+         (net (rename tx_tdata_60_ "tx_tdata[60]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram31))
+          )
+         )
+         (net (rename tx_tdata_55_ "tx_tdata[55]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram28))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[15]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_9_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o "slave_fifo32/ctrl_tx_tready_data_tx_tready_OR_55_o") (joined
+          (portref D (instanceref slave_fifo32_read_ready_go))
+          (portref O (instanceref slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1))
+          )
+         )
+         (net (rename tx_tdata_61_ "tx_tdata[61]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram31))
+          )
+         )
+         (net (rename tx_tdata_56_ "tx_tdata[56]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram29))
+          )
+         )
+         (net codec_txrx (joined
+          (portref O (instanceref codec_txrx_OBUF))
+          (portref codec_txrx)
+          )
+         )
+         (net (rename tx_tdata_62_ "tx_tdata[62]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram32))
+          )
+         )
+         (net (rename tx_tdata_57_ "tx_tdata[57]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram29))
+          )
+         )
+         (net (rename tx_tdata_63_ "tx_tdata[63]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram32))
+          )
+         )
+         (net (rename tx_tdata_58_ "tx_tdata[58]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref (member DIA 31) (instanceref f1_ram_Mram_ram30))
+          )
+         )
+         (net (rename tx_tdata_59_ "tx_tdata[59]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref (member DIA 30) (instanceref f1_ram_Mram_ram30))
+          )
+         )
+         (net (rename slave_fifo32_debug2_0_ "slave_fifo32/debug2[0]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_0))
+          (portref I (instanceref debug_0_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_debug2_1_ "slave_fifo32/debug2[1]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_1))
+          (portref I (instanceref debug_1_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_debug2_2_ "slave_fifo32/debug2[2]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_2))
+          (portref I (instanceref debug_2_OBUF))
+          )
+         )
+         (net (rename f0_full_reg "f0/full_reg") (joined
+          (portref I1 (instanceref f0_write11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0))
+          (portref Q (instanceref f0_full_reg))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+          (portref D (instanceref slave_fifo32_debug1_16_BRB0))
+          (portref I4 (instanceref f0_read_state_FSM_FFd2_In1))
+          (portref I4 (instanceref f0_full_reg_glue_set))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111))
+          )
+         )
+         (net (rename slave_fifo32_debug2_3_ "slave_fifo32/debug2[3]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_3))
+          (portref I (instanceref debug_3_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_debug2_4_ "slave_fifo32/debug2[4]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_4))
+          (portref I (instanceref debug_4_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_debug2_5_ "slave_fifo32/debug2[5]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_5))
+          (portref I (instanceref debug_5_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1))
+          )
+         )
+         (net (rename f1_wr_addr_0_ "f1/wr_addr[0]") (joined
+          (portref Q (instanceref f1_wr_addr_0))
+          (portref I1 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref I0 (instanceref f1_Mcompar_becoming_full_lut_0_))
+          (portref (member ADDRAWRADDR 12) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_debug2_6_ "slave_fifo32/debug2[6]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_6))
+          (portref I (instanceref debug_6_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/write") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1))
+          (portref wr_en (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f1_wr_addr_1_ "f1/wr_addr[1]") (joined
+          (portref Q (instanceref f1_wr_addr_1))
+          (portref I3 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref I2 (instanceref f1_Mcompar_becoming_full_lut_0_))
+          (portref (member ADDRAWRADDR 11) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_debug2_7_ "slave_fifo32/debug2[7]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_7))
+          (portref I (instanceref debug_7_OBUF))
+          )
+         )
+         (net (rename f1_wr_addr_2_ "f1/wr_addr[2]") (joined
+          (portref Q (instanceref f1_wr_addr_2))
+          (portref I5 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref I4 (instanceref f1_Mcompar_becoming_full_lut_0_))
+          (portref (member ADDRAWRADDR 10) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_debug2_8_ "slave_fifo32/debug2[8]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_8))
+          (portref I (instanceref debug_8_OBUF))
+          )
+         )
+         (net (rename f1_wr_addr_3_ "f1/wr_addr[3]") (joined
+          (portref Q (instanceref f1_wr_addr_3))
+          (portref I1 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref I0 (instanceref f1_Mcompar_becoming_full_lut_1_))
+          (portref (member ADDRAWRADDR 9) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_debug2_9_ "slave_fifo32/debug2[9]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_9))
+          (portref I (instanceref debug_9_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1))
+          )
+         )
+         (net (rename f1_wr_addr_4_ "f1/wr_addr[4]") (joined
+          (portref Q (instanceref f1_wr_addr_4))
+          (portref I3 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref I2 (instanceref f1_Mcompar_becoming_full_lut_1_))
+          (portref (member ADDRAWRADDR 8) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_10_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[10]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata210))
+          (portref (member din 61) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f1_wr_addr_5_ "f1/wr_addr[5]") (joined
+          (portref Q (instanceref f1_wr_addr_5))
+          (portref I5 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref I4 (instanceref f1_Mcompar_becoming_full_lut_1_))
+          (portref (member ADDRAWRADDR 7) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_6__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<6>_FRB") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_6__FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_11_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[11]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata33))
+          (portref (member din 60) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[10]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_10))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata210))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata371))
+          (portref (member DOB 21) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename f1_wr_addr_6_ "f1/wr_addr[6]") (joined
+          (portref Q (instanceref f1_wr_addr_6))
+          (portref I1 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref I0 (instanceref f1_Mcompar_becoming_full_lut_2_))
+          (portref (member ADDRAWRADDR 6) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_12__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<12>_FRB") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_12__FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_12_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[12]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata41))
+          (portref (member din 59) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[11]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata310))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata381))
+          (portref (member DOB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename f1_wr_addr_7_ "f1/wr_addr[7]") (joined
+          (portref Q (instanceref f1_wr_addr_7))
+          (portref I3 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref I2 (instanceref f1_Mcompar_becoming_full_lut_2_))
+          (portref (member ADDRAWRADDR 5) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_13_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[13]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata51))
+          (portref (member din 58) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[12]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_12))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata410))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata391))
+          (portref (member DOB 19) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr4_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_4))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr4_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4__rt))
+          )
+         )
+         (net (rename f1_wr_addr_8_ "f1/wr_addr[8]") (joined
+          (portref Q (instanceref f1_wr_addr_8))
+          (portref I5 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref I4 (instanceref f1_Mcompar_becoming_full_lut_2_))
+          (portref (member ADDRAWRADDR 4) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRA 4) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_14_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[14]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata61))
+          (portref (member din 57) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[13]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_13))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata510))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata401))
+          (portref (member DOB 18) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename f1_wr_addr_9_ "f1/wr_addr[9]") (joined
+          (portref Q (instanceref f1_wr_addr_9))
+          (portref I1 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref I0 (instanceref f1_Mcompar_becoming_full_lut_3_))
+          (portref (member ADDRAWRADDR 3) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRA 3) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_20_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[20]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata131))
+          (portref (member din 51) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_15_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[15]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata71))
+          (portref (member din 56) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[14]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_14))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata65))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata411))
+          (portref (member DOB 17) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr1") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr2") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr9_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_9))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr3") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_21_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[21]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata141))
+          (portref (member din 50) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_16_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[16]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata81))
+          (portref (member din 55) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_3__rt "f0/Mcount_wr_addr_cy<3>_rt") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_3__rt))
+          (portref S (instanceref f0_Mcount_wr_addr_cy_3_))
+          (portref LI (instanceref f0_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_20_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[20]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_20))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata131))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata481))
+          (portref (member DOB 29) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[15]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_15))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata71))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata421))
+          (portref (member DOB 16) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr4") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr5") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_10_ "f0/Mcount_wr_addr_cy[10]") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_10_))
+          (portref CI (instanceref f0_Mcount_wr_addr_cy_11_))
+          (portref CI (instanceref f0_Mcount_wr_addr_xor_11_))
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+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[29]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata221))
+          (portref (member din 42) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_28_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[28]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata211))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata571))
+          (portref (member DOB 21) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_15_ "slave_fifo32/data_rx_tdata[15]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT71))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_20_ "slave_fifo32/data_rx_tdata[20]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tlast "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tlast") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set))
+          (portref (member DOB 17) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tvalid11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write1))
+          )
+         )
+         (net (rename f1_Result_9_1_FRB "f1/Result<9>1_FRB") (joined
+          (portref D (instanceref f1_rd_addr_9))
+          (portref Q (instanceref f1_Result_9_1_FRB))
+          (portref I0 (instanceref f1_Mcount_rd_addr_cy_9__rt))
+          (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_9__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[29]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata221))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata581))
+          (portref (member DOB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_16_ "slave_fifo32/data_rx_tdata[16]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT81))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_21_ "slave_fifo32/data_rx_tdata[21]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_17_ "slave_fifo32/data_rx_tdata[17]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT91))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_22_ "slave_fifo32/data_rx_tdata[22]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_18_ "slave_fifo32/data_rx_tdata[18]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_23_ "slave_fifo32/data_rx_tdata[23]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[10]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_19_ "slave_fifo32/data_rx_tdata[19]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_24_ "slave_fifo32/data_rx_tdata[24]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT171))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[11]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_25_ "slave_fifo32/data_rx_tdata[25]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT181))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_30_ "slave_fifo32/data_rx_tdata[30]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[12]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_26_ "slave_fifo32/data_rx_tdata[26]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_31_ "slave_fifo32/data_rx_tdata[31]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_8__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<8>_FRB") (joined
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_8__FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[13]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_27_ "slave_fifo32/data_rx_tdata[27]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr3_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[14]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_28_ "slave_fifo32/data_rx_tdata[28]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT211))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[15]") (joined
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_29_ "slave_fifo32/data_rx_tdata[29]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n012121 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n012121") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0121211))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_SW0))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_0_ "f1/Mcount_rd_addr_cy[0]") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref f1_Mcount_rd_addr_cy_1_))
+          (portref CI (instanceref f1_Mcount_rd_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_6_1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_1_ "f1/Mcount_rd_addr_cy[1]") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_1_))
+          (portref CI (instanceref f1_Mcount_rd_addr_cy_2_))
+          (portref CI (instanceref f1_Mcount_rd_addr_xor_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut1") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1))
+          )
+         )
+         (net (rename slave_fifo32_fifoadr_0_ "slave_fifo32/fifoadr[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifoadr_0))
+          (portref I (instanceref GPIF_CTL12_OBUF))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_2_ "f1/Mcount_rd_addr_cy[2]") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_2_))
+          (portref CI (instanceref f1_Mcount_rd_addr_cy_3_))
+          (portref CI (instanceref f1_Mcount_rd_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr7_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_7))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr7_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7__rt))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_GND_50_o_read_OR_57_o "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/GND_50_o_read_OR_57_o") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_GND_50_o_read_OR_57_o1))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifoadr_1_ "slave_fifo32/fifoadr[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifoadr_1))
+          (portref I (instanceref GPIF_CTL11_OBUF))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_3_ "f1/Mcount_rd_addr_cy[3]") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_3_))
+          (portref CI (instanceref f1_Mcount_rd_addr_cy_4_))
+          (portref CI (instanceref f1_Mcount_rd_addr_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[10]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata210))
+          )
+         )
+         (net (rename f0_rd_addr_0_ "f0/rd_addr[0]") (joined
+          (portref Q (instanceref f0_rd_addr_0))
+          (portref I0 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref (member ADDRBRDADDR 12) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_4_ "f1/Mcount_rd_addr_cy[4]") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_4_))
+          (portref CI (instanceref f1_Mcount_rd_addr_cy_5_))
+          (portref CI (instanceref f1_Mcount_rd_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[11]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata310))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename f0_rd_addr_1_ "f0/rd_addr[1]") (joined
+          (portref Q (instanceref f0_rd_addr_1))
+          (portref I2 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref (member ADDRBRDADDR 11) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_5_ "f1/Mcount_rd_addr_cy[5]") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_5_))
+          (portref CI (instanceref f1_Mcount_rd_addr_cy_6_))
+          (portref CI (instanceref f1_Mcount_rd_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[12]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata410))
+          )
+         )
+         (net (rename f0_rd_addr_2_ "f0/rd_addr[2]") (joined
+          (portref Q (instanceref f0_rd_addr_2))
+          (portref I4 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref (member ADDRBRDADDR 10) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_6_ "f1/Mcount_rd_addr_cy[6]") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_6_))
+          (portref CI (instanceref f1_Mcount_rd_addr_cy_7_))
+          (portref CI (instanceref f1_Mcount_rd_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[13]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata510))
+          )
+         )
+         (net (rename f0_rd_addr_3_ "f0/rd_addr[3]") (joined
+          (portref Q (instanceref f0_rd_addr_3))
+          (portref I0 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref (member ADDRBRDADDR 9) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_7_ "f1/Mcount_rd_addr_cy[7]") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_7_))
+          (portref CI (instanceref f1_Mcount_rd_addr_cy_8_))
+          (portref CI (instanceref f1_Mcount_rd_addr_xor_8_))
+          )
+         )
+         (net codec_enable (joined
+          (portref O (instanceref codec_enable_OBUF))
+          (portref codec_enable)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[14]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata65))
+          )
+         )
+         (net (rename f0_rd_addr_4_ "f0/rd_addr[4]") (joined
+          (portref Q (instanceref f0_rd_addr_4))
+          (portref I2 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref (member ADDRBRDADDR 8) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tlast "slave_fifo32/fifo64_to_gpmc32_tx/o32_tlast") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_glue_set))
+          (portref (member DOBDO 15) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tvalid11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_write1))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_8_ "f1/Mcount_rd_addr_cy[8]") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_8_))
+          (portref CI (instanceref f1_Mcount_rd_addr_cy_9_))
+          (portref CI (instanceref f1_Mcount_rd_addr_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_20_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[20]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata131))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[15]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata71))
+          )
+         )
+         (net (rename f1_dont_write_past_me_1__FRB "f1/dont_write_past_me<1>_FRB") (joined
+          (portref I3 (instanceref f1_Mcompar_becoming_full_lut_0_))
+          (portref Q (instanceref f1_dont_write_past_me_1__FRB))
+          )
+         )
+         (net (rename f0_rd_addr_5_ "f0/rd_addr[5]") (joined
+          (portref Q (instanceref f0_rd_addr_5))
+          (portref I4 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref (member ADDRBRDADDR 7) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_9_ "f1/Mcount_rd_addr_cy[9]") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_9_))
+          (portref CI (instanceref f1_Mcount_rd_addr_cy_10_))
+          (portref CI (instanceref f1_Mcount_rd_addr_xor_10_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_21_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[21]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata141))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_16_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[16]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata81))
+          )
+         )
+         (net (rename f0_rd_addr_6_ "f0/rd_addr[6]") (joined
+          (portref Q (instanceref f0_rd_addr_6))
+          (portref I0 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref (member ADDRBRDADDR 6) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_4))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_22_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[22]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata151))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_17_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[17]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata91))
+          )
+         )
+         (net (rename f0_Result_11_2_FRB "f0/Result<11>2_FRB") (joined
+          (portref D (instanceref f0_wr_addr_11))
+          (portref Q (instanceref f0_Result_11_2_FRB))
+          (portref I0 (instanceref f0_Mcount_wr_addr_cy_11__rt))
+          )
+         )
+         (net (rename f0_rd_addr_7_ "f0/rd_addr[7]") (joined
+          (portref Q (instanceref f0_rd_addr_7))
+          (portref I2 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref (member ADDRBRDADDR 5) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111))
+          (portref I0 (instanceref f1__n0161_inv1_lut))
+          (portref I1 (instanceref f1_GND_14_o_read_OR_37_o1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1))
+          (portref I1 (instanceref f1_read_state_FSM_FFd1_In111))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst))
+          (portref I2 (instanceref f1_read_state_FSM_FFd2_In1))
+          (portref I2 (instanceref f1_full_reg_glue_set))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_23_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[23]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata161))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_18_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[18]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata101))
+          )
+         )
+         (net (rename f0_rd_addr_8_ "f0/rd_addr[8]") (joined
+          (portref Q (instanceref f0_rd_addr_8))
+          (portref I4 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref (member ADDRBRDADDR 4) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[0]") (joined
+          (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref S (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_24_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[24]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata171))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_19_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[19]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata111))
+          )
+         )
+         (net (rename f0_rd_addr_9_ "f0/rd_addr[9]") (joined
+          (portref Q (instanceref f0_rd_addr_9))
+          (portref I0 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref (member ADDRBRDADDR 3) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[1]") (joined
+          (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref S (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_30_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[30]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata241))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_25_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[25]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata181))
+          )
+         )
+         (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[2]") (joined
+          (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref S (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_31_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[31]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata251))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_26_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[26]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata191))
+          )
+         )
+         (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[3]") (joined
+          (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref S (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_27_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[27]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata201))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_32_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[32]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata261))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr6_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_6))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt))
+          )
+         )
+         (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[4]") (joined
+          (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_))
+          (portref S (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_))
+          )
+         )
+         (net (rename f1_Result_7_2_FRB "f1/Result<7>2_FRB") (joined
+          (portref D (instanceref f1_wr_addr_7))
+          (portref Q (instanceref f1_Result_7_2_FRB))
+          (portref I0 (instanceref f1_Mcount_wr_addr_cy_7__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_33_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[33]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata271))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_28_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[28]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata211))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_i_tvalid_int "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/i_tvalid_int") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0154_inv1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[29]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata221))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_34_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[34]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata281))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_40_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[40]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata351))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_35_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[35]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata291))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_2__rt "f1/Mcount_rd_addr_cy<2>_rt") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_2__rt))
+          (portref S (instanceref f1_Mcount_rd_addr_cy_2_))
+          (portref LI (instanceref f1_Mcount_rd_addr_xor_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_cy_1__rt "f1/Msub_dont_write_past_me_cy<1>_rt") (joined
+          (portref O (instanceref f1_Msub_dont_write_past_me_cy_1__rt))
+          (portref S (instanceref f1_Msub_dont_write_past_me_cy_1_))
+          (portref LI (instanceref f1_Msub_dont_write_past_me_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_36_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[36]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata301))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_41_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[41]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata361))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[3]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_37_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[37]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata311))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_42_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[42]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e))
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+          )
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+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0))
+          )
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+          )
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+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4))
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+          (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_2__INV_0))
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+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_))
+          )
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+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5))
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+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_))
+          )
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+          )
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+          )
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+          )
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+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_))
+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata401))
+          )
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+          )
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+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8_))
+          )
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+          )
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+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_7))
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+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_))
+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata411))
+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata471))
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+          (portref (member dout 58) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_8))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1))
+          )
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+          (portref (member dout 57) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161))
+          )
+         )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata431))
+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata491))
+          )
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+          (portref (member dout 51) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          )
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+          (portref Q (instanceref f0_dont_write_past_me_1__FRB))
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+          (portref CE (instanceref f1_Result_10_2_FRB))
+          (portref CE (instanceref f1_Result_11_2_FRB))
+          (portref CE (instanceref f1_Result_12_2_FRB))
+          (portref (member WEAWEL 1) (instanceref f1_ram_Mram_ram33))
+          (portref (member WEAWEL 0) (instanceref f1_ram_Mram_ram33))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram31))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram31))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram31))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram31))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram30))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram30))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram30))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram30))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram32))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram32))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram32))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram32))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram28))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram28))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram28))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram28))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram27))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram27))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram27))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram27))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram29))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram29))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram29))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram29))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram25))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram25))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram25))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram25))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram24))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram24))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram24))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram24))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram26))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram26))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram26))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram26))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram22))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram22))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram22))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram22))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram21))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram21))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram21))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram21))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram23))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram23))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram23))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram23))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram19))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram19))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram19))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram19))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram18))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram18))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram18))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram18))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram20))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram20))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram20))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram20))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram16))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram16))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram16))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram16))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram15))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram15))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram15))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram15))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram17))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram17))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram17))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram17))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram14))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram14))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram14))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram14))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram13))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram13))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram13))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram13))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram12))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram12))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram12))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram12))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram11))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram11))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram11))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram11))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram9))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram9))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram9))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram9))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram8))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram8))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram8))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram8))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram10))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram10))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram10))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram10))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram6))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram6))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram6))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram6))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram5))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram5))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram5))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram5))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram7))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram7))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram7))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram7))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram3))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram3))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram3))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram3))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram2))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram2))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram2))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram2))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram4))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram4))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram4))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram4))
+          (portref (member WEA 3) (instanceref f1_ram_Mram_ram1))
+          (portref (member WEA 2) (instanceref f1_ram_Mram_ram1))
+          (portref (member WEA 1) (instanceref f1_ram_Mram_ram1))
+          (portref (member WEA 0) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_write1))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_13_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_8__rt "f0/Mcount_rd_addr_cy<8>_rt") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_8__rt))
+          (portref S (instanceref f0_Mcount_rd_addr_cy_8_))
+          (portref LI (instanceref f0_Mcount_rd_addr_xor_8_))
+          )
+         )
+         (net (rename f0_Result_0_2_FRB "f0/Result<0>2_FRB") (joined
+          (portref D (instanceref f0_wr_addr_0))
+          (portref Q (instanceref f0_Result_0_2_FRB))
+          (portref I0 (instanceref f0_Mcount_wr_addr_lut_0__INV_0))
+          )
+         )
+         (net (rename f0_dont_write_past_me_3__FRB "f0/dont_write_past_me<3>_FRB") (joined
+          (portref I1 (instanceref f0_Mcompar_becoming_full_lut_1_))
+          (portref Q (instanceref f0_dont_write_past_me_3__FRB))
+          )
+         )
+         (net (rename f1_dont_write_past_me_5__FRB "f1/dont_write_past_me<5>_FRB") (joined
+          (portref I5 (instanceref f1_Mcompar_becoming_full_lut_1_))
+          (portref Q (instanceref f1_dont_write_past_me_5__FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_2_))
+          )
+         )
+         (net (rename f0_GND_14_o_read_OR_37_o "f0/GND_14_o_read_OR_37_o") (joined
+          (portref O (instanceref f0_GND_14_o_read_OR_37_o1))
+          (portref ENBRDEN (instanceref f0_ram_Mram_ram33))
+          (portref ENB (instanceref f0_ram_Mram_ram31))
+          (portref ENB (instanceref f0_ram_Mram_ram30))
+          (portref ENB (instanceref f0_ram_Mram_ram32))
+          (portref ENB (instanceref f0_ram_Mram_ram28))
+          (portref ENB (instanceref f0_ram_Mram_ram27))
+          (portref ENB (instanceref f0_ram_Mram_ram29))
+          (portref ENB (instanceref f0_ram_Mram_ram25))
+          (portref ENB (instanceref f0_ram_Mram_ram24))
+          (portref ENB (instanceref f0_ram_Mram_ram26))
+          (portref ENB (instanceref f0_ram_Mram_ram22))
+          (portref ENB (instanceref f0_ram_Mram_ram21))
+          (portref ENB (instanceref f0_ram_Mram_ram23))
+          (portref ENB (instanceref f0_ram_Mram_ram19))
+          (portref ENB (instanceref f0_ram_Mram_ram18))
+          (portref ENB (instanceref f0_ram_Mram_ram20))
+          (portref ENB (instanceref f0_ram_Mram_ram16))
+          (portref ENB (instanceref f0_ram_Mram_ram15))
+          (portref ENB (instanceref f0_ram_Mram_ram17))
+          (portref ENB (instanceref f0_ram_Mram_ram14))
+          (portref ENB (instanceref f0_ram_Mram_ram13))
+          (portref ENB (instanceref f0_ram_Mram_ram12))
+          (portref ENB (instanceref f0_ram_Mram_ram11))
+          (portref ENB (instanceref f0_ram_Mram_ram9))
+          (portref ENB (instanceref f0_ram_Mram_ram8))
+          (portref ENB (instanceref f0_ram_Mram_ram10))
+          (portref ENB (instanceref f0_ram_Mram_ram6))
+          (portref ENB (instanceref f0_ram_Mram_ram5))
+          (portref ENB (instanceref f0_ram_Mram_ram7))
+          (portref ENB (instanceref f0_ram_Mram_ram3))
+          (portref ENB (instanceref f0_ram_Mram_ram2))
+          (portref ENB (instanceref f0_ram_Mram_ram4))
+          (portref ENB (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_state_FSM_FFd2_In1 "slave_fifo32/state_FSM_FFd2-In1") (joined
+          (portref O (instanceref slave_fifo32_state_FSM_FFd2_In1))
+          (portref I2 (instanceref slave_fifo32_state_FSM_FFd2_In2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_4))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_5))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_6))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_7))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_8))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_14_BRB1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15_BRB1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_BRB1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv1))
+          )
+         )
+         (net (rename slave_fifo32_state_FSM_FFd2_In2 "slave_fifo32/state_FSM_FFd2-In2") (joined
+          (portref O (instanceref slave_fifo32_state_FSM_FFd2_In2))
+          (portref I2 (instanceref slave_fifo32_state_FSM_FFd2_In3))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_10_ "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding[10]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_10))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata371))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4_))
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+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full1021))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo__n0146_inv "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_4))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_5))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_6))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_7))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_8))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_9))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_10))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_11))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_12))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_1__FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_2__FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_3__FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_4__FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_5__FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_6__FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_7__FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_8__FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_9__FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_10__FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_11__FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_12__FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_0__FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr4_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr10_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr11_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr12_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo__n0146_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_0_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_lut_0_ "f1/Mcount_wr_addr_lut[0]") (joined
+          (portref S (instanceref f1_Mcount_wr_addr_cy_0_))
+          (portref LI (instanceref f1_Mcount_wr_addr_xor_0_))
+          (portref O (instanceref f1_Mcount_wr_addr_lut_0__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[2]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[3]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[4]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In_bdd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In_bdd1") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[5]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_5))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[6]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[7]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net rx_bandsel_c_OBUF (joined
+          (portref G (instanceref XST_GND))
+          (portref D (instanceref bus_sync_reset_int))
+          (portref D (instanceref gpif_sync_reset_int))
+          (portref D1 (instanceref ODDR2_ifclk))
+          (portref R (instanceref ODDR2_ifclk))
+          (portref S (instanceref ODDR2_ifclk))
+          (portref D1 (instanceref ODDR2_ifclk_dbg))
+          (portref R (instanceref ODDR2_ifclk_dbg))
+          (portref S (instanceref ODDR2_ifclk_dbg))
+          (portref DSSEN (instanceref gen_clks_dcm_sp_inst))
+          (portref PSCLK (instanceref gen_clks_dcm_sp_inst))
+          (portref PSEN (instanceref gen_clks_dcm_sp_inst))
+          (portref PSINCDEC (instanceref gen_clks_dcm_sp_inst))
+          (portref D0 (instanceref catgen_gen_pins_0__oddr2))
+          (portref D1 (instanceref catgen_gen_pins_0__oddr2))
+          (portref R (instanceref catgen_gen_pins_0__oddr2))
+          (portref S (instanceref catgen_gen_pins_0__oddr2))
+          (portref D0 (instanceref catgen_gen_pins_1__oddr2))
+          (portref D1 (instanceref catgen_gen_pins_1__oddr2))
+          (portref R (instanceref catgen_gen_pins_1__oddr2))
+          (portref S (instanceref catgen_gen_pins_1__oddr2))
+          (portref D0 (instanceref catgen_gen_pins_2__oddr2))
+          (portref D1 (instanceref catgen_gen_pins_2__oddr2))
+          (portref R (instanceref catgen_gen_pins_2__oddr2))
+          (portref S (instanceref catgen_gen_pins_2__oddr2))
+          (portref D0 (instanceref catgen_gen_pins_3__oddr2))
+          (portref D1 (instanceref catgen_gen_pins_3__oddr2))
+          (portref R (instanceref catgen_gen_pins_3__oddr2))
+          (portref S (instanceref catgen_gen_pins_3__oddr2))
+          (portref D0 (instanceref catgen_gen_pins_4__oddr2))
+          (portref D1 (instanceref catgen_gen_pins_4__oddr2))
+          (portref R (instanceref catgen_gen_pins_4__oddr2))
+          (portref S (instanceref catgen_gen_pins_4__oddr2))
+          (portref D0 (instanceref catgen_gen_pins_5__oddr2))
+          (portref D1 (instanceref catgen_gen_pins_5__oddr2))
+          (portref R (instanceref catgen_gen_pins_5__oddr2))
+          (portref S (instanceref catgen_gen_pins_5__oddr2))
+          (portref D0 (instanceref catgen_gen_pins_6__oddr2))
+          (portref D1 (instanceref catgen_gen_pins_6__oddr2))
+          (portref R (instanceref catgen_gen_pins_6__oddr2))
+          (portref S (instanceref catgen_gen_pins_6__oddr2))
+          (portref D0 (instanceref catgen_gen_pins_7__oddr2))
+          (portref D1 (instanceref catgen_gen_pins_7__oddr2))
+          (portref R (instanceref catgen_gen_pins_7__oddr2))
+          (portref S (instanceref catgen_gen_pins_7__oddr2))
+          (portref D0 (instanceref catgen_gen_pins_8__oddr2))
+          (portref D1 (instanceref catgen_gen_pins_8__oddr2))
+          (portref R (instanceref catgen_gen_pins_8__oddr2))
+          (portref S (instanceref catgen_gen_pins_8__oddr2))
+          (portref D0 (instanceref catgen_gen_pins_9__oddr2))
+          (portref D1 (instanceref catgen_gen_pins_9__oddr2))
+          (portref R (instanceref catgen_gen_pins_9__oddr2))
+          (portref S (instanceref catgen_gen_pins_9__oddr2))
+          (portref D0 (instanceref catgen_gen_pins_10__oddr2))
+          (portref D1 (instanceref catgen_gen_pins_10__oddr2))
+          (portref R (instanceref catgen_gen_pins_10__oddr2))
+          (portref S (instanceref catgen_gen_pins_10__oddr2))
+          (portref D0 (instanceref catgen_gen_pins_11__oddr2))
+          (portref D1 (instanceref catgen_gen_pins_11__oddr2))
+          (portref R (instanceref catgen_gen_pins_11__oddr2))
+          (portref S (instanceref catgen_gen_pins_11__oddr2))
+          (portref D0 (instanceref catgen_oddr2_frame))
+          (portref D1 (instanceref catgen_oddr2_frame))
+          (portref R (instanceref catgen_oddr2_frame))
+          (portref S (instanceref catgen_oddr2_frame))
+          (portref D1 (instanceref catgen_oddr2_clk))
+          (portref R (instanceref catgen_oddr2_clk))
+          (portref S (instanceref catgen_oddr2_clk))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_10_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_10_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_11_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_11_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_12_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_10_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_10_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_11_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_11_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_12_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_))
+          (portref DI (instanceref f1_Msub_dont_write_past_me_cy_0_))
+          (portref DI (instanceref f1_Msub_dont_write_past_me_cy_1_))
+          (portref CI (instanceref f1_Mcount_wr_addr_cy_0_))
+          (portref CI (instanceref f1_Mcount_wr_addr_xor_0_))
+          (portref DI (instanceref f1_Mcount_wr_addr_cy_1_))
+          (portref DI (instanceref f1_Mcount_wr_addr_cy_2_))
+          (portref DI (instanceref f1_Mcount_wr_addr_cy_3_))
+          (portref DI (instanceref f1_Mcount_wr_addr_cy_4_))
+          (portref DI (instanceref f1_Mcount_wr_addr_cy_5_))
+          (portref DI (instanceref f1_Mcount_wr_addr_cy_6_))
+          (portref DI (instanceref f1_Mcount_wr_addr_cy_7_))
+          (portref DI (instanceref f1_Mcount_wr_addr_cy_8_))
+          (portref DI (instanceref f1_Mcount_wr_addr_cy_9_))
+          (portref DI (instanceref f1_Mcount_wr_addr_cy_10_))
+          (portref DI (instanceref f1_Mcount_wr_addr_cy_11_))
+          (portref CI (instanceref f1_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref f1_Mcount_rd_addr_xor_0_))
+          (portref DI (instanceref f1_Mcount_rd_addr_cy_1_))
+          (portref DI (instanceref f1_Mcount_rd_addr_cy_2_))
+          (portref DI (instanceref f1_Mcount_rd_addr_cy_3_))
+          (portref DI (instanceref f1_Mcount_rd_addr_cy_4_))
+          (portref DI (instanceref f1_Mcount_rd_addr_cy_5_))
+          (portref DI (instanceref f1_Mcount_rd_addr_cy_6_))
+          (portref DI (instanceref f1_Mcount_rd_addr_cy_7_))
+          (portref DI (instanceref f1_Mcount_rd_addr_cy_8_))
+          (portref DI (instanceref f1_Mcount_rd_addr_cy_9_))
+          (portref DI (instanceref f1_Mcount_rd_addr_cy_10_))
+          (portref DI (instanceref f1_Mcount_rd_addr_cy_11_))
+          (portref DI (instanceref f1_Mcompar_becoming_full_cy_0_))
+          (portref DI (instanceref f1_Mcompar_becoming_full_cy_1_))
+          (portref DI (instanceref f1_Mcompar_becoming_full_cy_2_))
+          (portref DI (instanceref f1_Mcompar_becoming_full_cy_3_))
+          (portref DI (instanceref f1_Mcompar_becoming_full_cy_4_))
+          (portref DI (instanceref f0_Msub_dont_write_past_me_cy_0_))
+          (portref DI (instanceref f0_Msub_dont_write_past_me_cy_1_))
+          (portref CI (instanceref f0_Mcount_wr_addr_cy_0_))
+          (portref CI (instanceref f0_Mcount_wr_addr_xor_0_))
+          (portref DI (instanceref f0_Mcount_wr_addr_cy_1_))
+          (portref DI (instanceref f0_Mcount_wr_addr_cy_2_))
+          (portref DI (instanceref f0_Mcount_wr_addr_cy_3_))
+          (portref DI (instanceref f0_Mcount_wr_addr_cy_4_))
+          (portref DI (instanceref f0_Mcount_wr_addr_cy_5_))
+          (portref DI (instanceref f0_Mcount_wr_addr_cy_6_))
+          (portref DI (instanceref f0_Mcount_wr_addr_cy_7_))
+          (portref DI (instanceref f0_Mcount_wr_addr_cy_8_))
+          (portref DI (instanceref f0_Mcount_wr_addr_cy_9_))
+          (portref DI (instanceref f0_Mcount_wr_addr_cy_10_))
+          (portref DI (instanceref f0_Mcount_wr_addr_cy_11_))
+          (portref CI (instanceref f0_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref f0_Mcount_rd_addr_xor_0_))
+          (portref DI (instanceref f0_Mcount_rd_addr_cy_1_))
+          (portref DI (instanceref f0_Mcount_rd_addr_cy_2_))
+          (portref DI (instanceref f0_Mcount_rd_addr_cy_3_))
+          (portref DI (instanceref f0_Mcount_rd_addr_cy_4_))
+          (portref DI (instanceref f0_Mcount_rd_addr_cy_5_))
+          (portref DI (instanceref f0_Mcount_rd_addr_cy_6_))
+          (portref DI (instanceref f0_Mcount_rd_addr_cy_7_))
+          (portref DI (instanceref f0_Mcount_rd_addr_cy_8_))
+          (portref DI (instanceref f0_Mcount_rd_addr_cy_9_))
+          (portref DI (instanceref f0_Mcount_rd_addr_cy_10_))
+          (portref DI (instanceref f0_Mcount_rd_addr_cy_11_))
+          (portref DI (instanceref f0_Mcompar_becoming_full_cy_0_))
+          (portref DI (instanceref f0_Mcompar_becoming_full_cy_1_))
+          (portref DI (instanceref f0_Mcompar_becoming_full_cy_2_))
+          (portref DI (instanceref f0_Mcompar_becoming_full_cy_3_))
+          (portref DI (instanceref f0_Mcompar_becoming_full_cy_4_))
+          (portref I (instanceref codec_ctrl_in_3_OBUF))
+          (portref I (instanceref codec_ctrl_in_2_OBUF))
+          (portref I (instanceref codec_ctrl_in_1_OBUF))
+          (portref I (instanceref codec_ctrl_in_0_OBUF))
+          (portref I (instanceref debug_20_OBUF))
+          (portref I (instanceref cat_ce_OBUF))
+          (portref I (instanceref pll_ce_OBUF))
+          (portref I (instanceref pll_mosi_OBUF))
+          (portref I (instanceref pll_sclk_OBUF))
+          (portref I (instanceref codec_en_agc_OBUF))
+          (portref I (instanceref codec_sync_OBUF))
+          (portref I (instanceref codec_txrx_OBUF))
+          (portref I (instanceref GPIF_CTL0_OBUF))
+          (portref I (instanceref gps_out_enable_OBUF))
+          (portref I (instanceref gps_ref_enable_OBUF))
+          (portref I (instanceref ext_ref_enable_OBUF))
+          (portref I (instanceref pps_fpga_out_enable_OBUF))
+          (portref I (instanceref tx_bandsel_a_OBUF))
+          (portref I (instanceref tx_bandsel_b_OBUF))
+          (portref I (instanceref rx_bandsel_a_OBUF))
+          (portref I (instanceref rx_bandsel_b_OBUF))
+          (portref I (instanceref rx_bandsel_c_OBUF))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          (portref CI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          (portref DI (instanceref f1__n0161_inv1_cy))
+          (portref CI (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          (portref DI (instanceref f0__n0161_inv1_cy))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref REGCEBREGCE (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref RSTBRST (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref (member WEBWEU 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref (member WEBWEU 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIA 16) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 16) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIPA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIPA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIPB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIPB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIPA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIPA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIPA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIPB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIPB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIPB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref REGCEBREGCE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref RSTBRST (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member WEBWEU 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member WEBWEU 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member DIPA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIPA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIPA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIPB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIPB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIPB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIA 16) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 16) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member DIPA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member DIPA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member DIPB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member DIPB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref REGCEA (instanceref f1_ram_Mram_ram33))
+          (portref REGCEBREGCE (instanceref f1_ram_Mram_ram33))
+          (portref RSTA (instanceref f1_ram_Mram_ram33))
+          (portref RSTBRST (instanceref f1_ram_Mram_ram33))
+          (portref (member WEBWEU 1) (instanceref f1_ram_Mram_ram33))
+          (portref (member WEBWEU 0) (instanceref f1_ram_Mram_ram33))
+          (portref REGCEA (instanceref f1_ram_Mram_ram31))
+          (portref REGCEB (instanceref f1_ram_Mram_ram31))
+          (portref RSTA (instanceref f1_ram_Mram_ram31))
+          (portref RSTB (instanceref f1_ram_Mram_ram31))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram31))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram31))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram31))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram31))
+          (portref REGCEA (instanceref f1_ram_Mram_ram30))
+          (portref REGCEB (instanceref f1_ram_Mram_ram30))
+          (portref RSTA (instanceref f1_ram_Mram_ram30))
+          (portref RSTB (instanceref f1_ram_Mram_ram30))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram30))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram30))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram30))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram30))
+          (portref REGCEA (instanceref f1_ram_Mram_ram32))
+          (portref REGCEB (instanceref f1_ram_Mram_ram32))
+          (portref RSTA (instanceref f1_ram_Mram_ram32))
+          (portref RSTB (instanceref f1_ram_Mram_ram32))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram32))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram32))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram32))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram32))
+          (portref REGCEA (instanceref f1_ram_Mram_ram28))
+          (portref REGCEB (instanceref f1_ram_Mram_ram28))
+          (portref RSTA (instanceref f1_ram_Mram_ram28))
+          (portref RSTB (instanceref f1_ram_Mram_ram28))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram28))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram28))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram28))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram28))
+          (portref REGCEA (instanceref f1_ram_Mram_ram27))
+          (portref REGCEB (instanceref f1_ram_Mram_ram27))
+          (portref RSTA (instanceref f1_ram_Mram_ram27))
+          (portref RSTB (instanceref f1_ram_Mram_ram27))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram27))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram27))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram27))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram27))
+          (portref REGCEA (instanceref f1_ram_Mram_ram29))
+          (portref REGCEB (instanceref f1_ram_Mram_ram29))
+          (portref RSTA (instanceref f1_ram_Mram_ram29))
+          (portref RSTB (instanceref f1_ram_Mram_ram29))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram29))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram29))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram29))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram29))
+          (portref REGCEA (instanceref f1_ram_Mram_ram25))
+          (portref REGCEB (instanceref f1_ram_Mram_ram25))
+          (portref RSTA (instanceref f1_ram_Mram_ram25))
+          (portref RSTB (instanceref f1_ram_Mram_ram25))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram25))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram25))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram25))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram25))
+          (portref REGCEA (instanceref f1_ram_Mram_ram24))
+          (portref REGCEB (instanceref f1_ram_Mram_ram24))
+          (portref RSTA (instanceref f1_ram_Mram_ram24))
+          (portref RSTB (instanceref f1_ram_Mram_ram24))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram24))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram24))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram24))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram24))
+          (portref REGCEA (instanceref f1_ram_Mram_ram26))
+          (portref REGCEB (instanceref f1_ram_Mram_ram26))
+          (portref RSTA (instanceref f1_ram_Mram_ram26))
+          (portref RSTB (instanceref f1_ram_Mram_ram26))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram26))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram26))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram26))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram26))
+          (portref REGCEA (instanceref f1_ram_Mram_ram22))
+          (portref REGCEB (instanceref f1_ram_Mram_ram22))
+          (portref RSTA (instanceref f1_ram_Mram_ram22))
+          (portref RSTB (instanceref f1_ram_Mram_ram22))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram22))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram22))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram22))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram22))
+          (portref REGCEA (instanceref f1_ram_Mram_ram21))
+          (portref REGCEB (instanceref f1_ram_Mram_ram21))
+          (portref RSTA (instanceref f1_ram_Mram_ram21))
+          (portref RSTB (instanceref f1_ram_Mram_ram21))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram21))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram21))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram21))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram21))
+          (portref REGCEA (instanceref f1_ram_Mram_ram23))
+          (portref REGCEB (instanceref f1_ram_Mram_ram23))
+          (portref RSTA (instanceref f1_ram_Mram_ram23))
+          (portref RSTB (instanceref f1_ram_Mram_ram23))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram23))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram23))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram23))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram23))
+          (portref REGCEA (instanceref f1_ram_Mram_ram19))
+          (portref REGCEB (instanceref f1_ram_Mram_ram19))
+          (portref RSTA (instanceref f1_ram_Mram_ram19))
+          (portref RSTB (instanceref f1_ram_Mram_ram19))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram19))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram19))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram19))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram19))
+          (portref REGCEA (instanceref f1_ram_Mram_ram18))
+          (portref REGCEB (instanceref f1_ram_Mram_ram18))
+          (portref RSTA (instanceref f1_ram_Mram_ram18))
+          (portref RSTB (instanceref f1_ram_Mram_ram18))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram18))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram18))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram18))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram18))
+          (portref REGCEA (instanceref f1_ram_Mram_ram20))
+          (portref REGCEB (instanceref f1_ram_Mram_ram20))
+          (portref RSTA (instanceref f1_ram_Mram_ram20))
+          (portref RSTB (instanceref f1_ram_Mram_ram20))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram20))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram20))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram20))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram20))
+          (portref REGCEA (instanceref f1_ram_Mram_ram16))
+          (portref REGCEB (instanceref f1_ram_Mram_ram16))
+          (portref RSTA (instanceref f1_ram_Mram_ram16))
+          (portref RSTB (instanceref f1_ram_Mram_ram16))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram16))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram16))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram16))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram16))
+          (portref REGCEA (instanceref f1_ram_Mram_ram15))
+          (portref REGCEB (instanceref f1_ram_Mram_ram15))
+          (portref RSTA (instanceref f1_ram_Mram_ram15))
+          (portref RSTB (instanceref f1_ram_Mram_ram15))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram15))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram15))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram15))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram15))
+          (portref REGCEA (instanceref f1_ram_Mram_ram17))
+          (portref REGCEB (instanceref f1_ram_Mram_ram17))
+          (portref RSTA (instanceref f1_ram_Mram_ram17))
+          (portref RSTB (instanceref f1_ram_Mram_ram17))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram17))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram17))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram17))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram17))
+          (portref REGCEA (instanceref f1_ram_Mram_ram14))
+          (portref REGCEB (instanceref f1_ram_Mram_ram14))
+          (portref RSTA (instanceref f1_ram_Mram_ram14))
+          (portref RSTB (instanceref f1_ram_Mram_ram14))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram14))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram14))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram14))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram14))
+          (portref REGCEA (instanceref f1_ram_Mram_ram13))
+          (portref REGCEB (instanceref f1_ram_Mram_ram13))
+          (portref RSTA (instanceref f1_ram_Mram_ram13))
+          (portref RSTB (instanceref f1_ram_Mram_ram13))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram13))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram13))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram13))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram13))
+          (portref REGCEA (instanceref f1_ram_Mram_ram12))
+          (portref REGCEB (instanceref f1_ram_Mram_ram12))
+          (portref RSTA (instanceref f1_ram_Mram_ram12))
+          (portref RSTB (instanceref f1_ram_Mram_ram12))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram12))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram12))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram12))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram12))
+          (portref REGCEA (instanceref f1_ram_Mram_ram11))
+          (portref REGCEB (instanceref f1_ram_Mram_ram11))
+          (portref RSTA (instanceref f1_ram_Mram_ram11))
+          (portref RSTB (instanceref f1_ram_Mram_ram11))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram11))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram11))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram11))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram11))
+          (portref REGCEA (instanceref f1_ram_Mram_ram9))
+          (portref REGCEB (instanceref f1_ram_Mram_ram9))
+          (portref RSTA (instanceref f1_ram_Mram_ram9))
+          (portref RSTB (instanceref f1_ram_Mram_ram9))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram9))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram9))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram9))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram9))
+          (portref REGCEA (instanceref f1_ram_Mram_ram8))
+          (portref REGCEB (instanceref f1_ram_Mram_ram8))
+          (portref RSTA (instanceref f1_ram_Mram_ram8))
+          (portref RSTB (instanceref f1_ram_Mram_ram8))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram8))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram8))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram8))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram8))
+          (portref REGCEA (instanceref f1_ram_Mram_ram10))
+          (portref REGCEB (instanceref f1_ram_Mram_ram10))
+          (portref RSTA (instanceref f1_ram_Mram_ram10))
+          (portref RSTB (instanceref f1_ram_Mram_ram10))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram10))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram10))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram10))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram10))
+          (portref REGCEA (instanceref f1_ram_Mram_ram6))
+          (portref REGCEB (instanceref f1_ram_Mram_ram6))
+          (portref RSTA (instanceref f1_ram_Mram_ram6))
+          (portref RSTB (instanceref f1_ram_Mram_ram6))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram6))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram6))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram6))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram6))
+          (portref REGCEA (instanceref f1_ram_Mram_ram5))
+          (portref REGCEB (instanceref f1_ram_Mram_ram5))
+          (portref RSTA (instanceref f1_ram_Mram_ram5))
+          (portref RSTB (instanceref f1_ram_Mram_ram5))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram5))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram5))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram5))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram5))
+          (portref REGCEA (instanceref f1_ram_Mram_ram7))
+          (portref REGCEB (instanceref f1_ram_Mram_ram7))
+          (portref RSTA (instanceref f1_ram_Mram_ram7))
+          (portref RSTB (instanceref f1_ram_Mram_ram7))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram7))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram7))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram7))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram7))
+          (portref REGCEA (instanceref f1_ram_Mram_ram3))
+          (portref REGCEB (instanceref f1_ram_Mram_ram3))
+          (portref RSTA (instanceref f1_ram_Mram_ram3))
+          (portref RSTB (instanceref f1_ram_Mram_ram3))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram3))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram3))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram3))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram3))
+          (portref REGCEA (instanceref f1_ram_Mram_ram2))
+          (portref REGCEB (instanceref f1_ram_Mram_ram2))
+          (portref RSTA (instanceref f1_ram_Mram_ram2))
+          (portref RSTB (instanceref f1_ram_Mram_ram2))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram2))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram2))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram2))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram2))
+          (portref REGCEA (instanceref f1_ram_Mram_ram4))
+          (portref REGCEB (instanceref f1_ram_Mram_ram4))
+          (portref RSTA (instanceref f1_ram_Mram_ram4))
+          (portref RSTB (instanceref f1_ram_Mram_ram4))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram4))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram4))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram4))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram4))
+          (portref REGCEA (instanceref f1_ram_Mram_ram1))
+          (portref REGCEB (instanceref f1_ram_Mram_ram1))
+          (portref RSTA (instanceref f1_ram_Mram_ram1))
+          (portref RSTB (instanceref f1_ram_Mram_ram1))
+          (portref (member WEB 3) (instanceref f1_ram_Mram_ram1))
+          (portref (member WEB 2) (instanceref f1_ram_Mram_ram1))
+          (portref (member WEB 1) (instanceref f1_ram_Mram_ram1))
+          (portref (member WEB 0) (instanceref f1_ram_Mram_ram1))
+          (portref REGCEA (instanceref f0_ram_Mram_ram33))
+          (portref REGCEBREGCE (instanceref f0_ram_Mram_ram33))
+          (portref RSTA (instanceref f0_ram_Mram_ram33))
+          (portref RSTBRST (instanceref f0_ram_Mram_ram33))
+          (portref (member WEBWEU 1) (instanceref f0_ram_Mram_ram33))
+          (portref (member WEBWEU 0) (instanceref f0_ram_Mram_ram33))
+          (portref REGCEA (instanceref f0_ram_Mram_ram31))
+          (portref REGCEB (instanceref f0_ram_Mram_ram31))
+          (portref RSTA (instanceref f0_ram_Mram_ram31))
+          (portref RSTB (instanceref f0_ram_Mram_ram31))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram31))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram31))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram31))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram31))
+          (portref REGCEA (instanceref f0_ram_Mram_ram30))
+          (portref REGCEB (instanceref f0_ram_Mram_ram30))
+          (portref RSTA (instanceref f0_ram_Mram_ram30))
+          (portref RSTB (instanceref f0_ram_Mram_ram30))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram30))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram30))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram30))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram30))
+          (portref REGCEA (instanceref f0_ram_Mram_ram32))
+          (portref REGCEB (instanceref f0_ram_Mram_ram32))
+          (portref RSTA (instanceref f0_ram_Mram_ram32))
+          (portref RSTB (instanceref f0_ram_Mram_ram32))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram32))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram32))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram32))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram32))
+          (portref REGCEA (instanceref f0_ram_Mram_ram28))
+          (portref REGCEB (instanceref f0_ram_Mram_ram28))
+          (portref RSTA (instanceref f0_ram_Mram_ram28))
+          (portref RSTB (instanceref f0_ram_Mram_ram28))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram28))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram28))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram28))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram28))
+          (portref REGCEA (instanceref f0_ram_Mram_ram27))
+          (portref REGCEB (instanceref f0_ram_Mram_ram27))
+          (portref RSTA (instanceref f0_ram_Mram_ram27))
+          (portref RSTB (instanceref f0_ram_Mram_ram27))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram27))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram27))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram27))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram27))
+          (portref REGCEA (instanceref f0_ram_Mram_ram29))
+          (portref REGCEB (instanceref f0_ram_Mram_ram29))
+          (portref RSTA (instanceref f0_ram_Mram_ram29))
+          (portref RSTB (instanceref f0_ram_Mram_ram29))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram29))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram29))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram29))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram29))
+          (portref REGCEA (instanceref f0_ram_Mram_ram25))
+          (portref REGCEB (instanceref f0_ram_Mram_ram25))
+          (portref RSTA (instanceref f0_ram_Mram_ram25))
+          (portref RSTB (instanceref f0_ram_Mram_ram25))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram25))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram25))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram25))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram25))
+          (portref REGCEA (instanceref f0_ram_Mram_ram24))
+          (portref REGCEB (instanceref f0_ram_Mram_ram24))
+          (portref RSTA (instanceref f0_ram_Mram_ram24))
+          (portref RSTB (instanceref f0_ram_Mram_ram24))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram24))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram24))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram24))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram24))
+          (portref REGCEA (instanceref f0_ram_Mram_ram26))
+          (portref REGCEB (instanceref f0_ram_Mram_ram26))
+          (portref RSTA (instanceref f0_ram_Mram_ram26))
+          (portref RSTB (instanceref f0_ram_Mram_ram26))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram26))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram26))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram26))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram26))
+          (portref REGCEA (instanceref f0_ram_Mram_ram22))
+          (portref REGCEB (instanceref f0_ram_Mram_ram22))
+          (portref RSTA (instanceref f0_ram_Mram_ram22))
+          (portref RSTB (instanceref f0_ram_Mram_ram22))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram22))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram22))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram22))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram22))
+          (portref REGCEA (instanceref f0_ram_Mram_ram21))
+          (portref REGCEB (instanceref f0_ram_Mram_ram21))
+          (portref RSTA (instanceref f0_ram_Mram_ram21))
+          (portref RSTB (instanceref f0_ram_Mram_ram21))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram21))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram21))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram21))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram21))
+          (portref REGCEA (instanceref f0_ram_Mram_ram23))
+          (portref REGCEB (instanceref f0_ram_Mram_ram23))
+          (portref RSTA (instanceref f0_ram_Mram_ram23))
+          (portref RSTB (instanceref f0_ram_Mram_ram23))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram23))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram23))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram23))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram23))
+          (portref REGCEA (instanceref f0_ram_Mram_ram19))
+          (portref REGCEB (instanceref f0_ram_Mram_ram19))
+          (portref RSTA (instanceref f0_ram_Mram_ram19))
+          (portref RSTB (instanceref f0_ram_Mram_ram19))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram19))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram19))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram19))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram19))
+          (portref REGCEA (instanceref f0_ram_Mram_ram18))
+          (portref REGCEB (instanceref f0_ram_Mram_ram18))
+          (portref RSTA (instanceref f0_ram_Mram_ram18))
+          (portref RSTB (instanceref f0_ram_Mram_ram18))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram18))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram18))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram18))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram18))
+          (portref REGCEA (instanceref f0_ram_Mram_ram20))
+          (portref REGCEB (instanceref f0_ram_Mram_ram20))
+          (portref RSTA (instanceref f0_ram_Mram_ram20))
+          (portref RSTB (instanceref f0_ram_Mram_ram20))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram20))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram20))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram20))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram20))
+          (portref REGCEA (instanceref f0_ram_Mram_ram16))
+          (portref REGCEB (instanceref f0_ram_Mram_ram16))
+          (portref RSTA (instanceref f0_ram_Mram_ram16))
+          (portref RSTB (instanceref f0_ram_Mram_ram16))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram16))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram16))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram16))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram16))
+          (portref REGCEA (instanceref f0_ram_Mram_ram15))
+          (portref REGCEB (instanceref f0_ram_Mram_ram15))
+          (portref RSTA (instanceref f0_ram_Mram_ram15))
+          (portref RSTB (instanceref f0_ram_Mram_ram15))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram15))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram15))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram15))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram15))
+          (portref REGCEA (instanceref f0_ram_Mram_ram17))
+          (portref REGCEB (instanceref f0_ram_Mram_ram17))
+          (portref RSTA (instanceref f0_ram_Mram_ram17))
+          (portref RSTB (instanceref f0_ram_Mram_ram17))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram17))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram17))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram17))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram17))
+          (portref REGCEA (instanceref f0_ram_Mram_ram14))
+          (portref REGCEB (instanceref f0_ram_Mram_ram14))
+          (portref RSTA (instanceref f0_ram_Mram_ram14))
+          (portref RSTB (instanceref f0_ram_Mram_ram14))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram14))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram14))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram14))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram14))
+          (portref REGCEA (instanceref f0_ram_Mram_ram13))
+          (portref REGCEB (instanceref f0_ram_Mram_ram13))
+          (portref RSTA (instanceref f0_ram_Mram_ram13))
+          (portref RSTB (instanceref f0_ram_Mram_ram13))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram13))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram13))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram13))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram13))
+          (portref REGCEA (instanceref f0_ram_Mram_ram12))
+          (portref REGCEB (instanceref f0_ram_Mram_ram12))
+          (portref RSTA (instanceref f0_ram_Mram_ram12))
+          (portref RSTB (instanceref f0_ram_Mram_ram12))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram12))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram12))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram12))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram12))
+          (portref REGCEA (instanceref f0_ram_Mram_ram11))
+          (portref REGCEB (instanceref f0_ram_Mram_ram11))
+          (portref RSTA (instanceref f0_ram_Mram_ram11))
+          (portref RSTB (instanceref f0_ram_Mram_ram11))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram11))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram11))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram11))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram11))
+          (portref REGCEA (instanceref f0_ram_Mram_ram9))
+          (portref REGCEB (instanceref f0_ram_Mram_ram9))
+          (portref RSTA (instanceref f0_ram_Mram_ram9))
+          (portref RSTB (instanceref f0_ram_Mram_ram9))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram9))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram9))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram9))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram9))
+          (portref REGCEA (instanceref f0_ram_Mram_ram8))
+          (portref REGCEB (instanceref f0_ram_Mram_ram8))
+          (portref RSTA (instanceref f0_ram_Mram_ram8))
+          (portref RSTB (instanceref f0_ram_Mram_ram8))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram8))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram8))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram8))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram8))
+          (portref REGCEA (instanceref f0_ram_Mram_ram10))
+          (portref REGCEB (instanceref f0_ram_Mram_ram10))
+          (portref RSTA (instanceref f0_ram_Mram_ram10))
+          (portref RSTB (instanceref f0_ram_Mram_ram10))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram10))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram10))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram10))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram10))
+          (portref REGCEA (instanceref f0_ram_Mram_ram6))
+          (portref REGCEB (instanceref f0_ram_Mram_ram6))
+          (portref RSTA (instanceref f0_ram_Mram_ram6))
+          (portref RSTB (instanceref f0_ram_Mram_ram6))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram6))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram6))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram6))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram6))
+          (portref REGCEA (instanceref f0_ram_Mram_ram5))
+          (portref REGCEB (instanceref f0_ram_Mram_ram5))
+          (portref RSTA (instanceref f0_ram_Mram_ram5))
+          (portref RSTB (instanceref f0_ram_Mram_ram5))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram5))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram5))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram5))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram5))
+          (portref REGCEA (instanceref f0_ram_Mram_ram7))
+          (portref REGCEB (instanceref f0_ram_Mram_ram7))
+          (portref RSTA (instanceref f0_ram_Mram_ram7))
+          (portref RSTB (instanceref f0_ram_Mram_ram7))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram7))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram7))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram7))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram7))
+          (portref REGCEA (instanceref f0_ram_Mram_ram3))
+          (portref REGCEB (instanceref f0_ram_Mram_ram3))
+          (portref RSTA (instanceref f0_ram_Mram_ram3))
+          (portref RSTB (instanceref f0_ram_Mram_ram3))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram3))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram3))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram3))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram3))
+          (portref REGCEA (instanceref f0_ram_Mram_ram2))
+          (portref REGCEB (instanceref f0_ram_Mram_ram2))
+          (portref RSTA (instanceref f0_ram_Mram_ram2))
+          (portref RSTB (instanceref f0_ram_Mram_ram2))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram2))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram2))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram2))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram2))
+          (portref REGCEA (instanceref f0_ram_Mram_ram4))
+          (portref REGCEB (instanceref f0_ram_Mram_ram4))
+          (portref RSTA (instanceref f0_ram_Mram_ram4))
+          (portref RSTB (instanceref f0_ram_Mram_ram4))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram4))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram4))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram4))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram4))
+          (portref REGCEA (instanceref f0_ram_Mram_ram1))
+          (portref REGCEB (instanceref f0_ram_Mram_ram1))
+          (portref RSTA (instanceref f0_ram_Mram_ram1))
+          (portref RSTB (instanceref f0_ram_Mram_ram1))
+          (portref (member WEB 3) (instanceref f0_ram_Mram_ram1))
+          (portref (member WEB 2) (instanceref f0_ram_Mram_ram1))
+          (portref (member WEB 1) (instanceref f0_ram_Mram_ram1))
+          (portref (member WEB 0) (instanceref f0_ram_Mram_ram1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_))
+          (portref (member din 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 5) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 6) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 7) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 8) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 9) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 10) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 11) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 12) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 13) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 14) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 15) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 16) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 17) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 18) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 19) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 20) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 21) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 22) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 26) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 27) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 28) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 29) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 30) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 31) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 32) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 33) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 34) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 35) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 36) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 37) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 38) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 13) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 14) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 15) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 16) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 17) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 18) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 19) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 20) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 21) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 22) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 23) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 24) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 25) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 26) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 27) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 28) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 29) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 32) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 33) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 34) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 35) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref (member din 36) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
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+          )
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+          )
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+          )
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+          (portref Q (instanceref slave_fifo32_wr_one))
+          (portref I0 (instanceref slave_fifo32_wr_one_rstpot))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0))
+          )
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+         (net (rename slave_fifo32_sloe_1 "slave_fifo32/sloe_1") (joined
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+          (portref Q (instanceref slave_fifo32_sloe_1))
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+         (net (rename slave_fifo32_sloe_2 "slave_fifo32/sloe_2") (joined
+          (portref Q (instanceref slave_fifo32_sloe_2))
+          (portref T (instanceref GPIF_D_0_IOBUF))
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+         (net (rename slave_fifo32_sloe_3 "slave_fifo32/sloe_3") (joined
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+          (portref T (instanceref GPIF_D_1_IOBUF))
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+         )
+         (net (rename slave_fifo32_sloe_4 "slave_fifo32/sloe_4") (joined
+          (portref Q (instanceref slave_fifo32_sloe_4))
+          (portref T (instanceref GPIF_D_2_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_5 "slave_fifo32/sloe_5") (joined
+          (portref Q (instanceref slave_fifo32_sloe_5))
+          (portref T (instanceref GPIF_D_3_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_6 "slave_fifo32/sloe_6") (joined
+          (portref Q (instanceref slave_fifo32_sloe_6))
+          (portref T (instanceref GPIF_D_4_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_7 "slave_fifo32/sloe_7") (joined
+          (portref Q (instanceref slave_fifo32_sloe_7))
+          (portref T (instanceref GPIF_D_5_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_8 "slave_fifo32/sloe_8") (joined
+          (portref Q (instanceref slave_fifo32_sloe_8))
+          (portref T (instanceref GPIF_D_6_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_9 "slave_fifo32/sloe_9") (joined
+          (portref Q (instanceref slave_fifo32_sloe_9))
+          (portref T (instanceref GPIF_D_7_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_empty "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/empty") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In12_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11))
+          (portref empty (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename GPIF_D_10_ "GPIF_D[10]") (joined
+          (portref IO (instanceref GPIF_D_10_IOBUF))
+          (portref (member GPIF_D 21))
+          )
+         )
+         (net (rename GPIF_D_11_ "GPIF_D[11]") (joined
+          (portref IO (instanceref GPIF_D_11_IOBUF))
+          (portref (member GPIF_D 20))
+          )
+         )
+         (net pll_ce (joined
+          (portref O (instanceref pll_ce_OBUF))
+          (portref pll_ce)
+          )
+         )
+         (net (rename GPIF_D_12_ "GPIF_D[12]") (joined
+          (portref IO (instanceref GPIF_D_12_IOBUF))
+          (portref (member GPIF_D 19))
+          )
+         )
+         (net (rename GPIF_D_13_ "GPIF_D[13]") (joined
+          (portref IO (instanceref GPIF_D_13_IOBUF))
+          (portref (member GPIF_D 18))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full102 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full102") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full1021))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+          )
+         )
+         (net (rename GPIF_D_14_ "GPIF_D[14]") (joined
+          (portref IO (instanceref GPIF_D_14_IOBUF))
+          (portref (member GPIF_D 17))
+          )
+         )
+         (net N10 (joined
+          (portref O (instanceref slave_fifo32__n0279_inv_SW0))
+          (portref I3 (instanceref slave_fifo32__n0279_inv))
+          )
+         )
+         (net (rename GPIF_D_20_ "GPIF_D[20]") (joined
+          (portref IO (instanceref GPIF_D_20_IOBUF))
+          (portref (member GPIF_D 11))
+          )
+         )
+         (net (rename GPIF_D_15_ "GPIF_D[15]") (joined
+          (portref IO (instanceref GPIF_D_15_IOBUF))
+          (portref (member GPIF_D 16))
+          )
+         )
+         (net N14 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv))
+          )
+         )
+         (net cat_miso (joined
+          (portref I (instanceref cat_miso_IBUF))
+          (portref cat_miso)
+          )
+         )
+         (net N22 (joined
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0))
+          )
+         )
+         (net N18 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv))
+          )
+         )
+         (net (rename GPIF_D_21_ "GPIF_D[21]") (joined
+          (portref IO (instanceref GPIF_D_21_IOBUF))
+          (portref (member GPIF_D 10))
+          )
+         )
+         (net (rename GPIF_D_16_ "GPIF_D[16]") (joined
+          (portref IO (instanceref GPIF_D_16_IOBUF))
+          (portref (member GPIF_D 15))
+          )
+         )
+         (net N24 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1))
+          )
+         )
+         (net LED_RX1 (joined
+          (portref O (instanceref LED_RX1_OBUF))
+          (portref LED_RX1)
+          )
+         )
+         (net N30 (joined
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0))
+          )
+         )
+         (net LED_RX2 (joined
+          (portref O (instanceref LED_RX2_OBUF))
+          (portref LED_RX2)
+          )
+         )
+         (net N26 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1))
+          )
+         )
+         (net (rename GPIF_D_22_ "GPIF_D[22]") (joined
+          (portref IO (instanceref GPIF_D_22_IOBUF))
+          (portref (member GPIF_D 9))
+          )
+         )
+         (net (rename GPIF_D_17_ "GPIF_D[17]") (joined
+          (portref IO (instanceref GPIF_D_17_IOBUF))
+          (portref (member GPIF_D 14))
+          )
+         )
+         (net N34 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr5_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_5))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5__rt))
+          )
+         )
+         (net N40 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set))
+          )
+         )
+         (net N42 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv))
+          )
+         )
+         (net N38 (joined
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW0))
+          )
+         )
+         (net (rename GPIF_D_23_ "GPIF_D[23]") (joined
+          (portref IO (instanceref GPIF_D_23_IOBUF))
+          (portref (member GPIF_D 8))
+          )
+         )
+         (net (rename GPIF_D_18_ "GPIF_D[18]") (joined
+          (portref IO (instanceref GPIF_D_18_IOBUF))
+          (portref (member GPIF_D 13))
+          )
+         )
+         (net N50 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3))
+          )
+         )
+         (net N52 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1))
+          )
+         )
+         (net (rename GPIF_D_24_ "GPIF_D[24]") (joined
+          (portref IO (instanceref GPIF_D_24_IOBUF))
+          (portref (member GPIF_D 7))
+          )
+         )
+         (net (rename GPIF_D_19_ "GPIF_D[19]") (joined
+          (portref IO (instanceref GPIF_D_19_IOBUF))
+          (portref (member GPIF_D 12))
+          )
+         )
+         (net N54 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o))
+          )
+         )
+         (net N60 (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+          )
+         )
+         (net N56 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv))
+          )
+         )
+         (net N62 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1))
+          )
+         )
+         (net N58 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_4__rt "f0/Mcount_wr_addr_cy<4>_rt") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_4__rt))
+          (portref S (instanceref f0_Mcount_wr_addr_cy_4_))
+          (portref LI (instanceref f0_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net (rename GPIF_D_30_ "GPIF_D[30]") (joined
+          (portref IO (instanceref GPIF_D_30_IOBUF))
+          (portref (member GPIF_D 1))
+          )
+         )
+         (net (rename GPIF_D_25_ "GPIF_D[25]") (joined
+          (portref IO (instanceref GPIF_D_25_IOBUF))
+          (portref (member GPIF_D 6))
+          )
+         )
+         (net N64 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set))
+          )
+         )
+         (net N66 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv))
+          )
+         )
+         (net (rename f0_dont_write_past_me_9__FRB "f0/dont_write_past_me<9>_FRB") (joined
+          (portref I1 (instanceref f0_Mcompar_becoming_full_lut_3_))
+          (portref Q (instanceref f0_dont_write_past_me_9__FRB))
+          )
+         )
+         (net (rename GPIF_D_31_ "GPIF_D[31]") (joined
+          (portref IO (instanceref GPIF_D_31_IOBUF))
+          (portref (member GPIF_D 0))
+          )
+         )
+         (net (rename GPIF_D_26_ "GPIF_D[26]") (joined
+          (portref IO (instanceref GPIF_D_26_IOBUF))
+          (portref (member GPIF_D 5))
+          )
+         )
+         (net (rename f1_read_state_FSM_FFd1 "f1/read_state_FSM_FFd1") (joined
+          (portref Q (instanceref f1_read_state_FSM_FFd1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111))
+          (portref I1 (instanceref f1__n0161_inv1_lut))
+          (portref I1 (instanceref f1__n0161_inv1_lut1))
+          (portref I0 (instanceref f1_GND_14_o_read_OR_37_o1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1))
+          (portref I0 (instanceref f1_read_state_FSM_FFd1_In111))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst))
+          (portref I0 (instanceref f1_read_state_FSM_FFd2_In1))
+          (portref I3 (instanceref f1_full_reg_glue_set))
+          )
+         )
+         (net N80 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o))
+          )
+         )
+         (net (rename f1_read_state_FSM_FFd2 "f1/read_state_FSM_FFd2") (joined
+          (portref Q (instanceref f1_read_state_FSM_FFd2))
+          (portref I0 (instanceref f1__n0161_inv1_lut1))
+          (portref I2 (instanceref f1_GND_14_o_read_OR_37_o1))
+          (portref I3 (instanceref f1_read_state_FSM_FFd1_In111))
+          (portref I5 (instanceref f1_read_state_FSM_FFd2_In1))
+          )
+         )
+         (net N76 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3))
+          )
+         )
+         (net N82 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv))
+          )
+         )
+         (net N78 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1))
+          )
+         )
+         (net (rename GPIF_D_27_ "GPIF_D[27]") (joined
+          (portref IO (instanceref GPIF_D_27_IOBUF))
+          (portref (member GPIF_D 4))
+          )
+         )
+         (net N84 (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+          )
+         )
+         (net N90 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          )
+         )
+         (net N86 (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+          )
+         )
+         (net debug_clk_1_OBUF (joined
+          (portref Q (instanceref ODDR2_ifclk_dbg))
+          (portref I (instanceref debug_clk_1_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1_))
+          )
+         )
+         (net N88 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61))
+          )
+         )
+         (net (rename GPIF_D_28_ "GPIF_D[28]") (joined
+          (portref IO (instanceref GPIF_D_28_IOBUF))
+          (portref (member GPIF_D 3))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012111") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0121111))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217))
+          )
+         )
+         (net N96 (joined
+          (portref D (instanceref slave_fifo32_gpif_data_in_31))
+          (portref O (instanceref GPIF_D_31_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr3_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_3))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012112") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111))
+          )
+         )
+         (net N97 (joined
+          (portref D (instanceref slave_fifo32_gpif_data_in_30))
+          (portref O (instanceref GPIF_D_30_IOBUF))
+          )
+         )
+         (net locked (joined
+          (portref LOCKED (instanceref gen_clks_dcm_sp_inst))
+          (portref D (instanceref slave_fifo32_debug1_21))
+          (portref I0 (instanceref reset_global_locked_OR_1_o1))
+          (portref I1 (instanceref slave_fifo32__n0230_inv1))
+          (portref I0 (instanceref slave_fifo32__n0223_inv1))
+          (portref I5 (instanceref slave_fifo32__n0237_inv1))
+          (portref I0 (instanceref slave_fifo32__n0290_inv1))
+          (portref I0 (instanceref slave_fifo32__n0279_inv))
+          (portref I1 (instanceref slave_fifo32_state_FSM_FFd2_In1))
+          (portref I1 (instanceref slave_fifo32_wr_one_rstpot))
+          (portref I2 (instanceref slave_fifo32_slrd_rstpot))
+          (portref I3 (instanceref slave_fifo32_sloe_1_rstpot))
+          (portref I1 (instanceref slave_fifo32_state_FSM_FFd1_In3_F))
+          (portref I5 (instanceref slave_fifo32_state_FSM_FFd1_In3_G))
+          (portref I0 (instanceref slave_fifo32_state_FSM_FFd2_In3))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012113") (joined
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112))
+          )
+         )
+         (net N98 (joined
+          (portref D (instanceref slave_fifo32_gpif_data_in_29))
+          (portref O (instanceref GPIF_D_29_IOBUF))
+          )
+         )
+         (net (rename GPIF_D_29_ "GPIF_D[29]") (joined
+          (portref IO (instanceref GPIF_D_29_IOBUF))
+          (portref (member GPIF_D 2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012114") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114))
+          )
+         )
+         (net N99 (joined
+          (portref D (instanceref slave_fifo32_gpif_data_in_28))
+          (portref O (instanceref GPIF_D_28_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[10]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_10_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRAWRADDR 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_7_))
+          )
+         )
+         (net (rename f1_Result_9_2_FRB "f1/Result<9>2_FRB") (joined
+          (portref D (instanceref f1_wr_addr_9))
+          (portref Q (instanceref f1_Result_9_2_FRB))
+          (portref I0 (instanceref f1_Mcount_wr_addr_cy_9__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[11]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_11_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_11))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRAWRADDR 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[12]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_12_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_4_))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRAWRADDR 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename f0_Result_4_1_FRB "f0/Result<4>1_FRB") (joined
+          (portref D (instanceref f0_rd_addr_4))
+          (portref Q (instanceref f0_Result_4_1_FRB))
+          (portref I0 (instanceref f0_Mcount_rd_addr_cy_4__rt))
+          (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_4__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr4_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr10") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_10_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr11") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_11_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr12") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_12_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12))
+          )
+         )
+         (net pll_mosi (joined
+          (portref O (instanceref pll_mosi_OBUF))
+          (portref pll_mosi)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[1]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[2]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr8_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr8_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[3]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_0__inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state<0>_inv") (joined
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_0_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_0__inv1_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[4]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full92 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full92") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full921))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv4") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot))
+          )
+         )
+         (net (rename slave_fifo32_EP_WMARK1_1 "slave_fifo32/EP_WMARK1_1") (joined
+          (portref Q (instanceref slave_fifo32_EP_WMARK1_1))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0))
+          (portref I5 (instanceref slave_fifo32_slrd_rstpot))
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[5]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[6]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+          )
+         )
+         (net cat_mosi (joined
+          (portref O (instanceref cat_mosi_OBUF))
+          (portref cat_mosi)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[7]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          )
+         )
+         (net fx3_mosi_IBUF (joined
+          (portref I1 (instanceref cat_mosi1))
+          (portref O (instanceref fx3_mosi_IBUF))
+          )
+         )
+         (net (rename slave_fifo32_rd_one "slave_fifo32/rd_one") (joined
+          (portref D (instanceref slave_fifo32_rd_one_BRB1))
+          (portref O (instanceref slave_fifo32_rd_one_rstpot))
+          )
+         )
+         (net (rename slave_fifo32_sloe_rstpot "slave_fifo32/sloe_rstpot") (joined
+          (portref O (instanceref slave_fifo32_sloe_rstpot))
+          (portref D (instanceref slave_fifo32_sloe))
+          (portref D (instanceref slave_fifo32_sloe_33))
+          (portref D (instanceref slave_fifo32_sloe_32))
+          (portref D (instanceref slave_fifo32_sloe_31))
+          (portref D (instanceref slave_fifo32_sloe_30))
+          (portref D (instanceref slave_fifo32_sloe_29))
+          (portref D (instanceref slave_fifo32_sloe_28))
+          (portref D (instanceref slave_fifo32_sloe_27))
+          (portref D (instanceref slave_fifo32_sloe_26))
+          (portref D (instanceref slave_fifo32_sloe_25))
+          (portref D (instanceref slave_fifo32_sloe_24))
+          (portref D (instanceref slave_fifo32_sloe_23))
+          (portref D (instanceref slave_fifo32_sloe_22))
+          (portref D (instanceref slave_fifo32_sloe_21))
+          (portref D (instanceref slave_fifo32_sloe_20))
+          (portref D (instanceref slave_fifo32_sloe_19))
+          (portref D (instanceref slave_fifo32_sloe_18))
+          (portref D (instanceref slave_fifo32_sloe_17))
+          (portref D (instanceref slave_fifo32_sloe_16))
+          (portref D (instanceref slave_fifo32_sloe_15))
+          (portref D (instanceref slave_fifo32_sloe_14))
+          (portref D (instanceref slave_fifo32_sloe_13))
+          (portref D (instanceref slave_fifo32_sloe_12))
+          (portref D (instanceref slave_fifo32_sloe_11))
+          (portref D (instanceref slave_fifo32_sloe_10))
+          (portref D (instanceref slave_fifo32_sloe_9))
+          (portref D (instanceref slave_fifo32_sloe_8))
+          (portref D (instanceref slave_fifo32_sloe_7))
+          (portref D (instanceref slave_fifo32_sloe_6))
+          (portref D (instanceref slave_fifo32_sloe_5))
+          (portref D (instanceref slave_fifo32_sloe_4))
+          (portref D (instanceref slave_fifo32_sloe_3))
+          (portref D (instanceref slave_fifo32_sloe_2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr7_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_7))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<8>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__rt))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full_glue_set") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_3__rt "f1/Mcount_rd_addr_cy<3>_rt") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_3__rt))
+          (portref S (instanceref f1_Mcount_rd_addr_cy_3_))
+          (portref LI (instanceref f1_Mcount_rd_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr7_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr7_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__rt))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0))
+          )
+         )
+         (net (rename f0_Result_2_2_FRB "f0/Result<2>2_FRB") (joined
+          (portref D (instanceref f0_wr_addr_2))
+          (portref Q (instanceref f0_Result_2_2_FRB))
+          (portref I0 (instanceref f0_Mcount_wr_addr_cy_2__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<9>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/i_tvalid_o_tready_AND_73_o") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_4))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_5))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_6))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_7))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_8))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_9))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_10))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_11))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_12))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_13))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_14))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_15))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_16))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_17))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_18))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_19))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_20))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_22))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_23))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_24))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1))
+          )
+         )
+         (net (rename slave_fifo32_debug1_17_BRB0 "slave_fifo32/debug1_17_BRB0") (joined
+          (portref Q (instanceref slave_fifo32_debug1_17_BRB0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_o_tvalid1_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_chk_tready "slave_fifo32/fifo64_to_gpmc32_ctrl/chk_tready") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In12_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[0]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[1]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[2]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_0_ "f0/Mcount_rd_addr_cy[0]") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref f0_Mcount_rd_addr_cy_1_))
+          (portref CI (instanceref f0_Mcount_rd_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[3]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_1_ "f0/Mcount_rd_addr_cy[1]") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_1_))
+          (portref CI (instanceref f0_Mcount_rd_addr_cy_2_))
+          (portref CI (instanceref f0_Mcount_rd_addr_xor_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[4]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_2_ "f0/Mcount_rd_addr_cy[2]") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_2_))
+          (portref CI (instanceref f0_Mcount_rd_addr_cy_3_))
+          (portref CI (instanceref f0_Mcount_rd_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[5]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB3") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB4") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_3_ "f0/Mcount_rd_addr_cy[3]") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_3_))
+          (portref CI (instanceref f0_Mcount_rd_addr_cy_4_))
+          (portref CI (instanceref f0_Mcount_rd_addr_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[6]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_10_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[10]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata210))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_4_ "f0/Mcount_rd_addr_cy[4]") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_4_))
+          (portref CI (instanceref f0_Mcount_rd_addr_cy_5_))
+          (portref CI (instanceref f0_Mcount_rd_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[7]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_11_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[11]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata33))
+          )
+         )
+         (net (rename f1_Result_0_1_FRB "f1/Result<0>1_FRB") (joined
+          (portref D (instanceref f1_rd_addr_0))
+          (portref Q (instanceref f1_Result_0_1_FRB))
+          (portref I0 (instanceref f1_Msub_dont_write_past_me_cy_0__rt))
+          (portref I0 (instanceref f1_Mcount_rd_addr_lut_0__INV_0))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_5_ "f0/Mcount_rd_addr_cy[5]") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_5_))
+          (portref CI (instanceref f0_Mcount_rd_addr_cy_6_))
+          (portref CI (instanceref f0_Mcount_rd_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[8]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_12_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[12]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata41))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_6_ "f0/Mcount_rd_addr_cy[6]") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_6_))
+          (portref CI (instanceref f0_Mcount_rd_addr_cy_7_))
+          (portref CI (instanceref f0_Mcount_rd_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[9]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_13_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[13]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata51))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_7_ "f0/Mcount_rd_addr_cy[7]") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_7_))
+          (portref CI (instanceref f0_Mcount_rd_addr_cy_8_))
+          (portref CI (instanceref f0_Mcount_rd_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<5>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_14_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[14]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata61))
+          )
+         )
+         (instance codec_data_clk_inverter (viewref netlist (cellref INV (libraryref hdi_primitives))) (property tildeinv (boolean (TRUE))))
+         (net codec_data_clk (joined
+          (portref O (instanceref codec_data_clk_bufg))
+          (portref C0 (instanceref catgen_gen_pins_0__oddr2))
+          (portref C0 (instanceref catgen_gen_pins_1__oddr2))
+          (portref C0 (instanceref catgen_gen_pins_2__oddr2))
+          (portref C0 (instanceref catgen_gen_pins_3__oddr2))
+          (portref C0 (instanceref catgen_gen_pins_4__oddr2))
+          (portref C0 (instanceref catgen_gen_pins_5__oddr2))
+          (portref C0 (instanceref catgen_gen_pins_6__oddr2))
+          (portref C0 (instanceref catgen_gen_pins_7__oddr2))
+          (portref C0 (instanceref catgen_gen_pins_8__oddr2))
+          (portref C0 (instanceref catgen_gen_pins_9__oddr2))
+          (portref C0 (instanceref catgen_gen_pins_10__oddr2))
+          (portref C0 (instanceref catgen_gen_pins_11__oddr2))
+          (portref C0 (instanceref catgen_oddr2_frame))
+          (portref C0 (instanceref catgen_oddr2_clk))
+          (portref I (instanceref debug_clk_0_OBUF))
+          (portref I (instanceref codec_data_clk_inverter))
+          )
+         )
+         (net codec_data_clk_inv (joined
+          (portref O (instanceref codec_data_clk_inverter))
+          (portref C1 (instanceref catgen_oddr2_clk))
+          (portref C1 (instanceref catgen_gen_pins_0__oddr2))
+          (portref C1 (instanceref catgen_gen_pins_1__oddr2))
+          (portref C1 (instanceref catgen_gen_pins_2__oddr2))
+          (portref C1 (instanceref catgen_gen_pins_3__oddr2))
+          (portref C1 (instanceref catgen_gen_pins_4__oddr2))
+          (portref C1 (instanceref catgen_gen_pins_5__oddr2))
+          (portref C1 (instanceref catgen_gen_pins_6__oddr2))
+          (portref C1 (instanceref catgen_gen_pins_7__oddr2))
+          (portref C1 (instanceref catgen_gen_pins_8__oddr2))
+          (portref C1 (instanceref catgen_gen_pins_9__oddr2))
+          (portref C1 (instanceref catgen_gen_pins_10__oddr2))
+          (portref C1 (instanceref catgen_gen_pins_11__oddr2))
+          (portref C1 (instanceref catgen_oddr2_frame))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<8>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8__rt))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_8_ "f0/Mcount_rd_addr_cy[8]") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_8_))
+          (portref CI (instanceref f0_Mcount_rd_addr_cy_9_))
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+          )
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+          )
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+          )
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+          )
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+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1))
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+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F))
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+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv1_INV_0))
+          )
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+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_9_))
+          )
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+          )
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+          )
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+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_))
+          )
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+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_10_))
+          )
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+          )
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+          )
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+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_))
+          )
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+          )
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+          )
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+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[10]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_10_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_10_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_56_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[56]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata171))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_61_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[61]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata221))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[11]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_11_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_11_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[2]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_2_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_57_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[57]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata181))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_62_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[62]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata241))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[12]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_12_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_12_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[3]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_3_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0))
+          )
+         )
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+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata251))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_58_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[58]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata191))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[13]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_13_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_13_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[4]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_64_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[64]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_o_tlast1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_59_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[59]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata201))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[14]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_14_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_14_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[5]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<2>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[9]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_10_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[15]") (joined
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_15_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[6]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[7]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[8]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0))
+          )
+         )
+         (net tx_bandsel_a (joined
+          (portref O (instanceref tx_bandsel_a_OBUF))
+          (portref tx_bandsel_a)
+          )
+         )
+         (net tx_bandsel_b (joined
+          (portref O (instanceref tx_bandsel_b_OBUF))
+          (portref tx_bandsel_b)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[9]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4_))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_10__rt "f1/Mcount_rd_addr_cy<10>_rt") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_10__rt))
+          (portref S (instanceref f1_Mcount_rd_addr_cy_10_))
+          (portref LI (instanceref f1_Mcount_rd_addr_xor_10_))
+          )
+         )
+         (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[0]") (joined
+          (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          (portref CI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          )
+         )
+         (net GPIF_CTL0 (joined
+          (portref O (instanceref GPIF_CTL0_OBUF))
+          (portref GPIF_CTL0)
+          )
+         )
+         (net GPIF_CTL1 (joined
+          (portref O (instanceref GPIF_CTL1_OBUF))
+          (portref GPIF_CTL1)
+          )
+         )
+         (net GPIF_CTL2 (joined
+          (portref O (instanceref GPIF_CTL2_OBUF))
+          (portref GPIF_CTL2)
+          )
+         )
+         (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[1]") (joined
+          (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          (portref CI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          )
+         )
+         (net GPIF_CTL3 (joined
+          (portref O (instanceref GPIF_CTL3_OBUF))
+          (portref GPIF_CTL3)
+          )
+         )
+         (net GPIF_CTL4 (joined
+          (portref I (instanceref GPIF_CTL4_IBUF))
+          (portref GPIF_CTL4)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/clear_inv") (joined
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1))
+          )
+         )
+         (net GPIF_CTL5 (joined
+          (portref I (instanceref GPIF_CTL5_IBUF))
+          (portref GPIF_CTL5)
+          )
+         )
+         (net GPIF_CTL7 (joined
+          (portref O (instanceref GPIF_CTL7_OBUF))
+          (portref GPIF_CTL7)
+          )
+         )
+         (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[2]") (joined
+          (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          (portref CI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_0_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[0]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110))
+          (portref D (instanceref slave_fifo32_gpif_data_out_0))
+          )
+         )
+         (net GPIF_CTL9 (joined
+          (portref I (instanceref GPIF_CTL9_IBUF))
+          (portref GPIF_CTL9)
+          )
+         )
+         (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[3]") (joined
+          (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          (portref CI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_1_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[1]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121))
+          (portref D (instanceref slave_fifo32_gpif_data_out_1))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_2_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[2]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231))
+          (portref D (instanceref slave_fifo32_gpif_data_out_2))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_3_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[3]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261))
+          (portref D (instanceref slave_fifo32_gpif_data_out_3))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_4_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[4]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271))
+          (portref D (instanceref slave_fifo32_gpif_data_out_4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/GND_66_o_read_OR_144_o") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_5_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[5]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281))
+          (portref D (instanceref slave_fifo32_gpif_data_out_5))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_6_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[6]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291))
+          (portref D (instanceref slave_fifo32_gpif_data_out_6))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_7_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[7]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301))
+          (portref D (instanceref slave_fifo32_gpif_data_out_7))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[10]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_10_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_))
+          )
+         )
+         (net (rename n0035_10_ "n0035[10]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram6))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/_n0074_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[0]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRBRDADDR 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_8_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[8]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311))
+          (portref D (instanceref slave_fifo32_gpif_data_out_8))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[11]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_11_))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_))
+          )
+         )
+         (net (rename n0035_11_ "n0035[11]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram6))
+          )
+         )
+         (net pll_sclk (joined
+          (portref O (instanceref pll_sclk_OBUF))
+          (portref pll_sclk)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[1]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__rt))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member ADDRBRDADDR 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_9_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[9]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321))
+          (portref D (instanceref slave_fifo32_gpif_data_out_9))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[12]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_12_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_4_))
+          )
+         )
+         (net (rename n0035_12_ "n0035[12]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram7))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[2]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref (member ADDRBRDADDR 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0))
+          )
+         )
+         (net (rename n0035_13_ "n0035[13]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram7))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_6))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[3]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref (member ADDRBRDADDR 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0))
+          )
+         )
+         (net (rename n0035_14_ "n0035[14]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram8))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[4]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref (member ADDRBRDADDR 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0))
+          )
+         )
+         (net (rename n0035_20_ "n0035[20]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram11))
+          )
+         )
+         (net (rename n0035_15_ "n0035[15]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram8))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[5]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref (member ADDRBRDADDR 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0))
+          )
+         )
+         (net (rename n0035_21_ "n0035[21]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram11))
+          )
+         )
+         (net (rename n0035_16_ "n0035[16]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram9))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr1_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_1))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[10]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_11_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[6]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref (member ADDRBRDADDR 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0))
+          )
+         )
+         (net (rename n0035_22_ "n0035[22]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram12))
+          )
+         )
+         (net (rename n0035_17_ "n0035[17]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram9))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[7]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref (member ADDRBRDADDR 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0))
+          )
+         )
+         (net (rename n0035_23_ "n0035[23]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram12))
+          )
+         )
+         (net (rename n0035_18_ "n0035[18]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram10))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[8]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref (member ADDRBRDADDR 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0))
+          )
+         )
+         (net (rename n0035_19_ "n0035[19]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram10))
+          )
+         )
+         (net (rename n0035_24_ "n0035[24]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram13))
+          )
+         )
+         (net cat_sclk (joined
+          (portref O (instanceref cat_sclk_OBUF))
+          (portref cat_sclk)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[9]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref (member ADDRBRDADDR 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0))
+          )
+         )
+         (net (rename n0035_25_ "n0035[25]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram13))
+          )
+         )
+         (net (rename n0035_30_ "n0035[30]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram16))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[9]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_10_))
+          )
+         )
+         (net (rename n0035_26_ "n0035[26]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram14))
+          )
+         )
+         (net (rename n0035_31_ "n0035[31]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram16))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0146_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_10__rt "f1/Mcount_wr_addr_cy<10>_rt") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_10__rt))
+          (portref S (instanceref f1_Mcount_wr_addr_cy_10_))
+          (portref LI (instanceref f1_Mcount_wr_addr_xor_10_))
+          )
+         )
+         (net (rename n0035_27_ "n0035[27]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram14))
+          )
+         )
+         (net (rename n0035_32_ "n0035[32]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<0>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_0_))
+          )
+         )
+         (net (rename n0035_28_ "n0035[28]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram15))
+          )
+         )
+         (net (rename n0035_33_ "n0035[33]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram17))
+          )
+         )
+         (net (rename n0035_29_ "n0035[29]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram15))
+          )
+         )
+         (net (rename n0035_34_ "n0035[34]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram18))
+          )
+         )
+         (net (rename f0_Result_6_1_FRB "f0/Result<6>1_FRB") (joined
+          (portref D (instanceref f0_rd_addr_6))
+          (portref Q (instanceref f0_Result_6_1_FRB))
+          (portref I0 (instanceref f0_Mcount_rd_addr_cy_6__rt))
+          (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_6__INV_0))
+          )
+         )
+         (net (rename n0035_35_ "n0035[35]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram18))
+          )
+         )
+         (net (rename n0035_40_ "n0035[40]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram21))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_lut_0_ "f0/Mcount_wr_addr_lut[0]") (joined
+          (portref S (instanceref f0_Mcount_wr_addr_cy_0_))
+          (portref LI (instanceref f0_Mcount_wr_addr_xor_0_))
+          (portref O (instanceref f0_Mcount_wr_addr_lut_0__INV_0))
+          )
+         )
+         (net (rename n0035_36_ "n0035[36]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram19))
+          )
+         )
+         (net (rename n0035_41_ "n0035[41]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram21))
+          )
+         )
+         (net (rename n0035_37_ "n0035[37]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram19))
+          )
+         )
+         (net (rename n0035_42_ "n0035[42]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram22))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_tlast") (joined
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set))
+          (portref (member DIADI 15) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0))
+          )
+         )
+         (net ext_ref_enable (joined
+          (portref O (instanceref ext_ref_enable_OBUF))
+          (portref ext_ref_enable)
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_lut_0_ "f1/Mcount_rd_addr_lut[0]") (joined
+          (portref S (instanceref f1_Mcount_rd_addr_cy_0_))
+          (portref LI (instanceref f1_Mcount_rd_addr_xor_0_))
+          (portref O (instanceref f1_Mcount_rd_addr_lut_0__INV_0))
+          )
+         )
+         (net (rename n0035_38_ "n0035[38]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram20))
+          )
+         )
+         (net (rename n0035_43_ "n0035[43]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram22))
+          )
+         )
+         (net (rename n0035_44_ "n0035[44]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram23))
+          )
+         )
+         (net (rename n0035_39_ "n0035[39]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram20))
+          )
+         )
+         (net (rename n0035_50_ "n0035[50]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram26))
+          )
+         )
+         (net (rename n0035_45_ "n0035[45]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram23))
+          )
+         )
+         (net (rename f1_dont_write_past_me_10__FRB "f1/dont_write_past_me<10>_FRB") (joined
+          (portref I3 (instanceref f1_Mcompar_becoming_full_lut_3_))
+          (portref Q (instanceref f1_dont_write_past_me_10__FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror_bdd0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror_bdd0") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          )
+         )
+         (net (rename n0035_51_ "n0035[51]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram26))
+          )
+         )
+         (net (rename n0035_46_ "n0035[46]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram24))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror_bdd6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror_bdd6") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0))
+          )
+         )
+         (net (rename n0035_52_ "n0035[52]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram27))
+          )
+         )
+         (net (rename n0035_47_ "n0035[47]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram24))
+          )
+         )
+         (net (rename n0035_53_ "n0035[53]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram27))
+          )
+         )
+         (net (rename n0035_48_ "n0035[48]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram25))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr6_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_6))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0_ "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata261))
+          )
+         )
+         (net (rename n0035_54_ "n0035[54]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram28))
+          )
+         )
+         (net (rename n0035_49_ "n0035[49]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram25))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1_ "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata271))
+          )
+         )
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+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata301))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata311))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata321))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata331))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata341))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata351))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata361))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata371))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata381))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata391))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata401))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata411))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata421))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata431))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata441))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata451))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata461))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata471))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata481))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata491))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata501))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata511))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata521))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata531))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata541))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata551))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata561))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata571))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata581))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata591))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata601))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata611))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata621))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata631))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata641))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_glue_set))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tvalid11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_write1))
+          )
+         )
+         (net (rename ctrl_tdata_14_ "ctrl_tdata[14]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram8))
+          )
+         )
+         (net (rename GPIF_D_1_ "GPIF_D[1]") (joined
+          (portref IO (instanceref GPIF_D_1_IOBUF))
+          (portref (member GPIF_D 30))
+          )
+         )
+         (net (rename ctrl_tdata_20_ "ctrl_tdata[20]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram11))
+          )
+         )
+         (net (rename ctrl_tdata_15_ "ctrl_tdata[15]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram8))
+          )
+         )
+         (net (rename GPIF_D_2_ "GPIF_D[2]") (joined
+          (portref IO (instanceref GPIF_D_2_IOBUF))
+          (portref (member GPIF_D 29))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_chk_tready "slave_fifo32/fifo64_to_gpmc32_tx/chk_tready") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_read1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In12_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G))
+          )
+         )
+         (net (rename ctrl_tdata_21_ "ctrl_tdata[21]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram11))
+          )
+         )
+         (net (rename ctrl_tdata_16_ "ctrl_tdata[16]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram9))
+          )
+         )
+         (net (rename GPIF_D_3_ "GPIF_D[3]") (joined
+          (portref IO (instanceref GPIF_D_3_IOBUF))
+          (portref (member GPIF_D 28))
+          )
+         )
+         (net (rename ctrl_tdata_22_ "ctrl_tdata[22]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram12))
+          )
+         )
+         (net (rename ctrl_tdata_17_ "ctrl_tdata[17]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram9))
+          )
+         )
+         (net (rename GPIF_D_4_ "GPIF_D[4]") (joined
+          (portref IO (instanceref GPIF_D_4_IOBUF))
+          (portref (member GPIF_D 27))
+          )
+         )
+         (net (rename ctrl_tdata_23_ "ctrl_tdata[23]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram12))
+          )
+         )
+         (net (rename ctrl_tdata_18_ "ctrl_tdata[18]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram10))
+          )
+         )
+         (net (rename GPIF_D_5_ "GPIF_D[5]") (joined
+          (portref IO (instanceref GPIF_D_5_IOBUF))
+          (portref (member GPIF_D 26))
+          )
+         )
+         (net (rename ctrl_tdata_19_ "ctrl_tdata[19]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram10))
+          )
+         )
+         (net (rename ctrl_tdata_24_ "ctrl_tdata[24]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram13))
+          )
+         )
+         (instance gpif_clk_inverter (viewref netlist (cellref INV (libraryref hdi_primitives))) (property tildeinv (boolean (TRUE))))
+         (net gpif_clk (joined
+          (portref C (instanceref gpif_sync_reset_int))
+          (portref C (instanceref gpif_sync_reset_out))
+          (portref C0 (instanceref ODDR2_ifclk))
+          (portref C0 (instanceref ODDR2_ifclk_dbg))
+          (portref O (instanceref gen_clks_clkout2_buf))
+          (portref C (instanceref slave_fifo32_EP_WMARK))
+          (portref C (instanceref slave_fifo32_read_ready_go))
+          (portref C (instanceref slave_fifo32_write_ready_go))
+          (portref C (instanceref slave_fifo32_EP_READY))
+          (portref C (instanceref slave_fifo32_EP_READY1))
+          (portref C (instanceref slave_fifo32_EP_WMARK1))
+          (portref C (instanceref slave_fifo32_slrd1))
+          (portref C (instanceref slave_fifo32_slrd2))
+          (portref C (instanceref slave_fifo32_slrd3))
+          (portref C (instanceref slave_fifo32_slwr))
+          (portref C (instanceref slave_fifo32_pktend))
+          (portref C (instanceref slave_fifo32_gpif_data_in_0))
+          (portref C (instanceref slave_fifo32_gpif_data_in_1))
+          (portref C (instanceref slave_fifo32_gpif_data_in_2))
+          (portref C (instanceref slave_fifo32_gpif_data_in_3))
+          (portref C (instanceref slave_fifo32_gpif_data_in_4))
+          (portref C (instanceref slave_fifo32_gpif_data_in_5))
+          (portref C (instanceref slave_fifo32_gpif_data_in_6))
+          (portref C (instanceref slave_fifo32_gpif_data_in_7))
+          (portref C (instanceref slave_fifo32_gpif_data_in_8))
+          (portref C (instanceref slave_fifo32_gpif_data_in_9))
+          (portref C (instanceref slave_fifo32_gpif_data_in_10))
+          (portref C (instanceref slave_fifo32_gpif_data_in_11))
+          (portref C (instanceref slave_fifo32_gpif_data_in_12))
+          (portref C (instanceref slave_fifo32_gpif_data_in_13))
+          (portref C (instanceref slave_fifo32_gpif_data_in_14))
+          (portref C (instanceref slave_fifo32_gpif_data_in_15))
+          (portref C (instanceref slave_fifo32_gpif_data_in_16))
+          (portref C (instanceref slave_fifo32_gpif_data_in_17))
+          (portref C (instanceref slave_fifo32_gpif_data_in_18))
+          (portref C (instanceref slave_fifo32_gpif_data_in_19))
+          (portref C (instanceref slave_fifo32_gpif_data_in_20))
+          (portref C (instanceref slave_fifo32_gpif_data_in_21))
+          (portref C (instanceref slave_fifo32_gpif_data_in_22))
+          (portref C (instanceref slave_fifo32_gpif_data_in_23))
+          (portref C (instanceref slave_fifo32_gpif_data_in_24))
+          (portref C (instanceref slave_fifo32_gpif_data_in_25))
+          (portref C (instanceref slave_fifo32_gpif_data_in_26))
+          (portref C (instanceref slave_fifo32_gpif_data_in_27))
+          (portref C (instanceref slave_fifo32_gpif_data_in_28))
+          (portref C (instanceref slave_fifo32_gpif_data_in_29))
+          (portref C (instanceref slave_fifo32_gpif_data_in_30))
+          (portref C (instanceref slave_fifo32_gpif_data_in_31))
+          (portref C (instanceref slave_fifo32_debug1_0))
+          (portref C (instanceref slave_fifo32_debug1_1))
+          (portref C (instanceref slave_fifo32_debug1_2))
+          (portref C (instanceref slave_fifo32_debug1_3))
+          (portref C (instanceref slave_fifo32_debug1_4))
+          (portref C (instanceref slave_fifo32_debug1_5))
+          (portref C (instanceref slave_fifo32_debug1_6))
+          (portref C (instanceref slave_fifo32_debug1_7))
+          (portref C (instanceref slave_fifo32_debug1_8))
+          (portref C (instanceref slave_fifo32_debug1_9))
+          (portref C (instanceref slave_fifo32_debug1_10))
+          (portref C (instanceref slave_fifo32_debug1_11))
+          (portref C (instanceref slave_fifo32_debug1_12))
+          (portref C (instanceref slave_fifo32_debug1_13))
+          (portref C (instanceref slave_fifo32_debug1_14))
+          (portref C (instanceref slave_fifo32_debug1_15))
+          (portref C (instanceref slave_fifo32_debug1_18))
+          (portref C (instanceref slave_fifo32_debug1_19))
+          (portref C (instanceref slave_fifo32_debug1_21))
+          (portref C (instanceref slave_fifo32_debug1_22))
+          (portref C (instanceref slave_fifo32_debug1_23))
+          (portref C (instanceref slave_fifo32_debug1_26))
+          (portref C (instanceref slave_fifo32_debug1_27))
+          (portref C (instanceref slave_fifo32_debug1_28))
+          (portref C (instanceref slave_fifo32_debug1_29))
+          (portref C (instanceref slave_fifo32_debug1_31))
+          (portref C (instanceref slave_fifo32_debug2_0))
+          (portref C (instanceref slave_fifo32_debug2_1))
+          (portref C (instanceref slave_fifo32_debug2_2))
+          (portref C (instanceref slave_fifo32_debug2_3))
+          (portref C (instanceref slave_fifo32_debug2_4))
+          (portref C (instanceref slave_fifo32_debug2_5))
+          (portref C (instanceref slave_fifo32_debug2_6))
+          (portref C (instanceref slave_fifo32_debug2_7))
+          (portref C (instanceref slave_fifo32_debug2_8))
+          (portref C (instanceref slave_fifo32_debug2_9))
+          (portref C (instanceref slave_fifo32_debug2_10))
+          (portref C (instanceref slave_fifo32_debug2_11))
+          (portref C (instanceref slave_fifo32_debug2_12))
+          (portref C (instanceref slave_fifo32_debug2_13))
+          (portref C (instanceref slave_fifo32_debug2_14))
+          (portref C (instanceref slave_fifo32_debug2_15))
+          (portref C (instanceref slave_fifo32_debug2_16))
+          (portref C (instanceref slave_fifo32_debug2_17))
+          (portref C (instanceref slave_fifo32_debug2_18))
+          (portref C (instanceref slave_fifo32_debug2_19))
+          (portref C (instanceref slave_fifo32_debug2_21))
+          (portref C (instanceref slave_fifo32_debug2_22))
+          (portref C (instanceref slave_fifo32_debug2_23))
+          (portref C (instanceref slave_fifo32_debug2_26))
+          (portref C (instanceref slave_fifo32_debug2_27))
+          (portref C (instanceref slave_fifo32_debug2_28))
+          (portref C (instanceref slave_fifo32_debug2_29))
+          (portref C (instanceref slave_fifo32_debug2_31))
+          (portref C (instanceref slave_fifo32_state_FSM_FFd2))
+          (portref C (instanceref slave_fifo32_state_FSM_FFd1))
+          (portref C (instanceref slave_fifo32_fifoadr_0))
+          (portref C (instanceref slave_fifo32_fifoadr_1))
+          (portref C (instanceref slave_fifo32_idle_cycles_0))
+          (portref C (instanceref slave_fifo32_idle_cycles_1))
+          (portref C (instanceref slave_fifo32_idle_cycles_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_5))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_6))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_5))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_6))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_7))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_8))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_9))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_10))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_11))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_12))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_5))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_6))
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+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr7_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr8_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr2_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr4_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr5_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr7_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr2_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr3_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr4_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr7_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr8_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr6_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_14_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1))
+          (portref C (instanceref slave_fifo32_debug1_17_BRB0))
+          (portref C (instanceref slave_fifo32_debug1_16_BRB0))
+          (portref C (instanceref slave_fifo32_rd_one_BRB0))
+          (portref C (instanceref slave_fifo32_rd_one_BRB1))
+          (portref C (instanceref slave_fifo32_sloe))
+          (portref C (instanceref slave_fifo32_slrd2_1))
+          (portref C (instanceref slave_fifo32_EP_WMARK1_1))
+          (portref C (instanceref slave_fifo32_EP_READY1_1))
+          (portref C (instanceref slave_fifo32_gpif_data_out_31_1))
+          (portref C (instanceref slave_fifo32_slwr_1))
+          (portref C (instanceref slave_fifo32_sloe_34))
+          (portref C (instanceref slave_fifo32_slrd_1))
+          (portref C (instanceref slave_fifo32_pktend_1))
+          (portref C (instanceref slave_fifo32_fifoadr_1_1))
+          (portref C (instanceref slave_fifo32_fifoadr_0_1))
+          (portref C (instanceref slave_fifo32_gpif_data_out_31))
+          (portref C (instanceref slave_fifo32_sloe_33))
+          (portref C (instanceref slave_fifo32_gpif_data_out_30))
+          (portref C (instanceref slave_fifo32_sloe_32))
+          (portref C (instanceref slave_fifo32_gpif_data_out_29))
+          (portref C (instanceref slave_fifo32_sloe_31))
+          (portref C (instanceref slave_fifo32_gpif_data_out_28))
+          (portref C (instanceref slave_fifo32_sloe_30))
+          (portref C (instanceref slave_fifo32_gpif_data_out_27))
+          (portref C (instanceref slave_fifo32_sloe_29))
+          (portref C (instanceref slave_fifo32_gpif_data_out_26))
+          (portref C (instanceref slave_fifo32_sloe_28))
+          (portref C (instanceref slave_fifo32_gpif_data_out_25))
+          (portref C (instanceref slave_fifo32_sloe_27))
+          (portref C (instanceref slave_fifo32_gpif_data_out_24))
+          (portref C (instanceref slave_fifo32_sloe_26))
+          (portref C (instanceref slave_fifo32_gpif_data_out_23))
+          (portref C (instanceref slave_fifo32_sloe_25))
+          (portref C (instanceref slave_fifo32_gpif_data_out_22))
+          (portref C (instanceref slave_fifo32_sloe_24))
+          (portref C (instanceref slave_fifo32_gpif_data_out_21))
+          (portref C (instanceref slave_fifo32_sloe_23))
+          (portref C (instanceref slave_fifo32_gpif_data_out_20))
+          (portref C (instanceref slave_fifo32_sloe_22))
+          (portref C (instanceref slave_fifo32_gpif_data_out_19))
+          (portref C (instanceref slave_fifo32_sloe_21))
+          (portref C (instanceref slave_fifo32_gpif_data_out_18))
+          (portref C (instanceref slave_fifo32_sloe_20))
+          (portref C (instanceref slave_fifo32_gpif_data_out_17))
+          (portref C (instanceref slave_fifo32_sloe_19))
+          (portref C (instanceref slave_fifo32_gpif_data_out_16))
+          (portref C (instanceref slave_fifo32_sloe_18))
+          (portref C (instanceref slave_fifo32_gpif_data_out_15))
+          (portref C (instanceref slave_fifo32_sloe_17))
+          (portref C (instanceref slave_fifo32_gpif_data_out_14))
+          (portref C (instanceref slave_fifo32_sloe_16))
+          (portref C (instanceref slave_fifo32_gpif_data_out_13))
+          (portref C (instanceref slave_fifo32_sloe_15))
+          (portref C (instanceref slave_fifo32_gpif_data_out_12))
+          (portref C (instanceref slave_fifo32_sloe_14))
+          (portref C (instanceref slave_fifo32_gpif_data_out_11))
+          (portref C (instanceref slave_fifo32_sloe_13))
+          (portref C (instanceref slave_fifo32_gpif_data_out_10))
+          (portref C (instanceref slave_fifo32_sloe_12))
+          (portref C (instanceref slave_fifo32_gpif_data_out_9))
+          (portref C (instanceref slave_fifo32_sloe_11))
+          (portref C (instanceref slave_fifo32_gpif_data_out_8))
+          (portref C (instanceref slave_fifo32_sloe_10))
+          (portref C (instanceref slave_fifo32_gpif_data_out_7))
+          (portref C (instanceref slave_fifo32_sloe_9))
+          (portref C (instanceref slave_fifo32_gpif_data_out_6))
+          (portref C (instanceref slave_fifo32_sloe_8))
+          (portref C (instanceref slave_fifo32_gpif_data_out_5))
+          (portref C (instanceref slave_fifo32_sloe_7))
+          (portref C (instanceref slave_fifo32_gpif_data_out_4))
+          (portref C (instanceref slave_fifo32_sloe_6))
+          (portref C (instanceref slave_fifo32_gpif_data_out_3))
+          (portref C (instanceref slave_fifo32_sloe_5))
+          (portref C (instanceref slave_fifo32_gpif_data_out_2))
+          (portref C (instanceref slave_fifo32_sloe_4))
+          (portref C (instanceref slave_fifo32_gpif_data_out_1))
+          (portref C (instanceref slave_fifo32_sloe_3))
+          (portref C (instanceref slave_fifo32_gpif_data_out_0))
+          (portref C (instanceref slave_fifo32_sloe_2))
+          (portref CLKAWRCLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref CLKBRDCLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref wr_clk (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref wr_clk (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref rd_clk (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          (portref rd_clk (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          (portref I (instanceref gpif_clk_inverter))
+          )
+         )
+         (net gpif_clk_inv (joined
+          (portref O (instanceref gpif_clk_inverter))
+          (portref C1 (instanceref ODDR2_ifclk_dbg))
+          (portref C1 (instanceref ODDR2_ifclk))
+          )
+         )
+         (net (rename GPIF_D_6_ "GPIF_D[6]") (joined
+          (portref IO (instanceref GPIF_D_6_IOBUF))
+          (portref (member GPIF_D 25))
+          )
+         )
+         (net (rename ctrl_tdata_30_ "ctrl_tdata[30]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram16))
+          )
+         )
+         (net (rename ctrl_tdata_25_ "ctrl_tdata[25]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram13))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/i_tvalid_o_tready_AND_73_o") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_4))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_5))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_6))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_7))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_8))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_9))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_10))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_11))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_12))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_13))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_14))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_15))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_16))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_17))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_18))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_19))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_20))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_21))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_22))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_23))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_24))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_25))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_26))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_27))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_28))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_29))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_30))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_31))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1))
+          )
+         )
+         (net (rename GPIF_D_7_ "GPIF_D[7]") (joined
+          (portref IO (instanceref GPIF_D_7_IOBUF))
+          (portref (member GPIF_D 24))
+          )
+         )
+         (net (rename ctrl_tdata_31_ "ctrl_tdata[31]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram16))
+          )
+         )
+         (net (rename ctrl_tdata_26_ "ctrl_tdata[26]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram14))
+          )
+         )
+         (net (rename f1_dont_write_past_me_12__FRB "f1/dont_write_past_me<12>_FRB") (joined
+          (portref I1 (instanceref f1_Mcompar_becoming_full_lut_4_))
+          (portref Q (instanceref f1_dont_write_past_me_12__FRB))
+          )
+         )
+         (net (rename GPIF_D_8_ "GPIF_D[8]") (joined
+          (portref IO (instanceref GPIF_D_8_IOBUF))
+          (portref (member GPIF_D 23))
+          )
+         )
+         (net (rename f0_Result_4_2_FRB "f0/Result<4>2_FRB") (joined
+          (portref D (instanceref f0_wr_addr_4))
+          (portref Q (instanceref f0_Result_4_2_FRB))
+          (portref I0 (instanceref f0_Mcount_wr_addr_cy_4__rt))
+          )
+         )
+         (net reset_global_locked_OR_1_o (joined
+          (portref PRE (instanceref bus_sync_reset_int))
+          (portref PRE (instanceref bus_sync_reset_out))
+          (portref PRE (instanceref gpif_sync_reset_int))
+          (portref PRE (instanceref gpif_sync_reset_out))
+          (portref O (instanceref reset_global_locked_OR_1_o1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11))
+          (portref I3 (instanceref slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tvalid11))
+          )
+         )
+         (net (rename ctrl_tdata_32_ "ctrl_tdata[32]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram17))
+          )
+         )
+         (net (rename ctrl_tdata_27_ "ctrl_tdata[27]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram14))
+          )
+         )
+         (net (rename GPIF_D_9_ "GPIF_D[9]") (joined
+          (portref IO (instanceref GPIF_D_9_IOBUF))
+          (portref (member GPIF_D 22))
+          )
+         )
+         (net (rename ctrl_tdata_28_ "ctrl_tdata[28]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram15))
+          )
+         )
+         (net (rename ctrl_tdata_33_ "ctrl_tdata[33]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr5_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt))
+          )
+         )
+         (net (rename ctrl_tdata_29_ "ctrl_tdata[29]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram15))
+          )
+         )
+         (net (rename ctrl_tdata_34_ "ctrl_tdata[34]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram18))
+          )
+         )
+         (net (rename ctrl_tdata_35_ "ctrl_tdata[35]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram18))
+          )
+         )
+         (net (rename ctrl_tdata_40_ "ctrl_tdata[40]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram21))
+          )
+         )
+         (net (rename ctrl_tdata_36_ "ctrl_tdata[36]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram19))
+          )
+         )
+         (net (rename ctrl_tdata_41_ "ctrl_tdata[41]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram21))
+          )
+         )
+         (net (rename f1_Result_10_1_FRB "f1/Result<10>1_FRB") (joined
+          (portref D (instanceref f1_rd_addr_10))
+          (portref Q (instanceref f1_Result_10_1_FRB))
+          (portref I0 (instanceref f1_Mcount_rd_addr_cy_10__rt))
+          (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_10__INV_0))
+          )
+         )
+         (net (rename ctrl_tdata_37_ "ctrl_tdata[37]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram19))
+          )
+         )
+         (net (rename ctrl_tdata_42_ "ctrl_tdata[42]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram22))
+          )
+         )
+         (net (rename ctrl_tdata_38_ "ctrl_tdata[38]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram20))
+          )
+         )
+         (net (rename ctrl_tdata_43_ "ctrl_tdata[43]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram22))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11))
+          )
+         )
+         (net (rename ctrl_tdata_39_ "ctrl_tdata[39]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram20))
+          )
+         )
+         (net (rename ctrl_tdata_44_ "ctrl_tdata[44]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram23))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0_))
+          )
+         )
+         (net (rename ctrl_tdata_45_ "ctrl_tdata[45]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram23))
+          )
+         )
+         (net (rename ctrl_tdata_50_ "ctrl_tdata[50]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram26))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1))
+          )
+         )
+         (net (rename ctrl_tdata_46_ "ctrl_tdata[46]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram24))
+          )
+         )
+         (net (rename ctrl_tdata_51_ "ctrl_tdata[51]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram26))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2_))
+          )
+         )
+         (net (rename ctrl_tdata_47_ "ctrl_tdata[47]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram24))
+          )
+         )
+         (net (rename ctrl_tdata_52_ "ctrl_tdata[52]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram27))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_10_ "slave_fifo32/gpif_data_out[10]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_10))
+          (portref I (instanceref GPIF_D_10_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3_))
+          )
+         )
+         (net (rename ctrl_tdata_53_ "ctrl_tdata[53]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram27))
+          )
+         )
+         (net (rename ctrl_tdata_48_ "ctrl_tdata[48]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram25))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_11_ "slave_fifo32/gpif_data_out[11]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_11))
+          (portref I (instanceref GPIF_D_11_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4_))
+          )
+         )
+         (net (rename ctrl_tdata_54_ "ctrl_tdata[54]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram28))
+          )
+         )
+         (net (rename ctrl_tdata_49_ "ctrl_tdata[49]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram25))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/state<0>_inv") (joined
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_0_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv1_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_12_ "slave_fifo32/gpif_data_out[12]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_12))
+          (portref I (instanceref GPIF_D_12_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_i_tready))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1))
+          )
+         )
+         (net (rename ctrl_tdata_60_ "ctrl_tdata[60]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram31))
+          )
+         )
+         (net (rename ctrl_tdata_55_ "ctrl_tdata[55]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram28))
+          )
+         )
+         (net (rename f1_Result_2_1_FRB "f1/Result<2>1_FRB") (joined
+          (portref D (instanceref f1_rd_addr_2))
+          (portref Q (instanceref f1_Result_2_1_FRB))
+          (portref I0 (instanceref f1_Mcount_rd_addr_cy_2__rt))
+          (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_2__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_13_ "slave_fifo32/gpif_data_out[13]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_13))
+          (portref I (instanceref GPIF_D_13_IOBUF))
+          )
+         )
+         (net (rename ctrl_tdata_56_ "ctrl_tdata[56]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram29))
+          )
+         )
+         (net (rename ctrl_tdata_61_ "ctrl_tdata[61]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram31))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_14_ "slave_fifo32/gpif_data_out[14]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_14))
+          (portref I (instanceref GPIF_D_14_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_1_))
+          )
+         )
+         (net (rename ctrl_tdata_62_ "ctrl_tdata[62]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram32))
+          )
+         )
+         (net (rename ctrl_tdata_57_ "ctrl_tdata[57]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram29))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_20_ "slave_fifo32/gpif_data_out[20]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_20))
+          (portref I (instanceref GPIF_D_20_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_15_ "slave_fifo32/gpif_data_out[15]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_15))
+          (portref I (instanceref GPIF_D_15_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_2_))
+          )
+         )
+         (net (rename ctrl_tdata_63_ "ctrl_tdata[63]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram32))
+          )
+         )
+         (net (rename ctrl_tdata_58_ "ctrl_tdata[58]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref (member DIA 31) (instanceref f0_ram_Mram_ram30))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_16_ "slave_fifo32/gpif_data_out[16]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_16))
+          (portref I (instanceref GPIF_D_16_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_21_ "slave_fifo32/gpif_data_out[21]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_21))
+          (portref I (instanceref GPIF_D_21_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_3_))
+          )
+         )
+         (net (rename ctrl_tdata_59_ "ctrl_tdata[59]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref (member DIA 30) (instanceref f0_ram_Mram_ram30))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_22_ "slave_fifo32/gpif_data_out[22]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_22))
+          (portref I (instanceref GPIF_D_22_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_17_ "slave_fifo32/gpif_data_out[17]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_17))
+          (portref I (instanceref GPIF_D_17_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_23_ "slave_fifo32/gpif_data_out[23]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_23))
+          (portref I (instanceref GPIF_D_23_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_18_ "slave_fifo32/gpif_data_out[18]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_18))
+          (portref I (instanceref GPIF_D_18_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_24_ "slave_fifo32/gpif_data_out[24]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_24))
+          (portref I (instanceref GPIF_D_24_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_19_ "slave_fifo32/gpif_data_out[19]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_19))
+          (portref I (instanceref GPIF_D_19_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr8_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_8))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_30_ "slave_fifo32/gpif_data_out[30]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_30))
+          (portref I (instanceref GPIF_D_30_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_25_ "slave_fifo32/gpif_data_out[25]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_25))
+          (portref I (instanceref GPIF_D_25_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_i_tready "slave_fifo32/fifo64_to_gpmc32_ctrl/i_tready") (joined
+          (portref D (instanceref slave_fifo32_debug1_18))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_i_tready))
+          (portref I3 (instanceref slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_31_ "slave_fifo32/gpif_data_out[31]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_31))
+          (portref I (instanceref GPIF_D_31_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_26_ "slave_fifo32/gpif_data_out[26]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_26))
+          (portref I (instanceref GPIF_D_26_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>11") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_27_ "slave_fifo32/gpif_data_out[27]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_27))
+          (portref I (instanceref GPIF_D_27_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_4__rt "f1/Mcount_rd_addr_cy<4>_rt") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_4__rt))
+          (portref S (instanceref f1_Mcount_rd_addr_cy_4_))
+          (portref LI (instanceref f1_Mcount_rd_addr_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_28_ "slave_fifo32/gpif_data_out[28]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_28))
+          (portref I (instanceref GPIF_D_28_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[9]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_10_))
+          )
+         )
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+          (portref Q (instanceref slave_fifo32_gpif_data_out_29))
+          (portref I (instanceref GPIF_D_29_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr8_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt))
+          )
+         )
+         (net (rename f1_Mcompar_becoming_full_lut_0_ "f1/Mcompar_becoming_full_lut[0]") (joined
+          (portref O (instanceref f1_Mcompar_becoming_full_lut_0_))
+          (portref S (instanceref f1_Mcompar_becoming_full_cy_0_))
+          )
+         )
+         (net (rename f1_Mcompar_becoming_full_lut_1_ "f1/Mcompar_becoming_full_lut[1]") (joined
+          (portref O (instanceref f1_Mcompar_becoming_full_lut_1_))
+          (portref S (instanceref f1_Mcompar_becoming_full_cy_1_))
+          )
+         )
+         (net (rename f1_Mcompar_becoming_full_lut_2_ "f1/Mcompar_becoming_full_lut[2]") (joined
+          (portref O (instanceref f1_Mcompar_becoming_full_lut_2_))
+          (portref S (instanceref f1_Mcompar_becoming_full_cy_2_))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_0_ "slave_fifo32/data_rx_tdata[0]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename f1_Mcompar_becoming_full_lut_3_ "f1/Mcompar_becoming_full_lut[3]") (joined
+          (portref O (instanceref f1_Mcompar_becoming_full_lut_3_))
+          (portref S (instanceref f1_Mcompar_becoming_full_cy_3_))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_1_ "slave_fifo32/data_rx_tdata[1]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename f1_Mcompar_becoming_full_lut_4_ "f1/Mcompar_becoming_full_lut[4]") (joined
+          (portref O (instanceref f1_Mcompar_becoming_full_lut_4_))
+          (portref S (instanceref f1_Mcompar_becoming_full_cy_4_))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_2_ "slave_fifo32/data_rx_tdata[2]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_EP_WMARK "slave_fifo32/EP_WMARK") (joined
+          (portref Q (instanceref slave_fifo32_EP_WMARK))
+          (portref D (instanceref slave_fifo32_EP_WMARK1))
+          (portref D (instanceref slave_fifo32_EP_WMARK1_1))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_3_ "slave_fifo32/data_rx_tdata[3]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_4_ "slave_fifo32/data_rx_tdata[4]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4_))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_10_ "f0/Mcount_rd_addr_cy[10]") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_10_))
+          (portref CI (instanceref f0_Mcount_rd_addr_cy_11_))
+          (portref CI (instanceref f0_Mcount_rd_addr_xor_11_))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_5_ "slave_fifo32/data_rx_tdata[5]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_6_ "slave_fifo32/data_rx_tdata[6]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          )
+         )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifoadr_0_1 "slave_fifo32/fifoadr_0_1") (joined
+          (portref Q (instanceref slave_fifo32_fifoadr_0_1))
+          (portref D (instanceref slave_fifo32_debug1_26))
+          (portref I1 (instanceref slave_fifo32_Mcount_fifoadr_xor_1_11))
+          (portref I0 (instanceref slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT171))
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+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT211))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT41))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT51))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT61))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT71))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT81))
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT91))
+          (portref I2 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_write1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1))
+          (portref I0 (instanceref slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1))
+          (portref I2 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0))
+          (portref I2 (instanceref slave_fifo32_ctrl_tx_tvalid1))
+          (portref I2 (instanceref slave_fifo32_data_tx_tvalid1))
+          (portref I0 (instanceref slave_fifo32_Mcount_fifoadr_xor_0_11_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/write") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write1))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename f1_Result_0_2_FRB "f1/Result<0>2_FRB") (joined
+          (portref D (instanceref f1_wr_addr_0))
+          (portref Q (instanceref f1_Result_0_2_FRB))
+          (portref I0 (instanceref f1_Mcount_wr_addr_lut_0__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_7_ "slave_fifo32/data_rx_tdata[7]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          )
+         )
+         (net (rename slave_fifo32_sloe_1_rstpot "slave_fifo32/sloe_1_rstpot") (joined
+          (portref D (instanceref slave_fifo32_sloe_1))
+          (portref O (instanceref slave_fifo32_sloe_1_rstpot))
+          (portref D (instanceref slave_fifo32_sloe_34))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_8_ "slave_fifo32/data_rx_tdata[8]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_o_tready_int "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/o_tready_int") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo__n0146_inv1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt__n0074_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<6>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tdata_9_ "slave_fifo32/data_rx_tdata[9]") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          )
+         )
+         (net (rename slave_fifo32_fifoadr_1_1 "slave_fifo32/fifoadr_1_1") (joined
+          (portref Q (instanceref slave_fifo32_fifoadr_1_1))
+          (portref D (instanceref slave_fifo32_debug1_27))
+          (portref I0 (instanceref slave_fifo32_Mcount_fifoadr_xor_1_11))
+          (portref I1 (instanceref slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1))
+          (portref I2 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110))
+          (portref I2 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101))
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+          (portref I2 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT81))
+          (portref I2 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT91))
+          (portref I2 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_write1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1))
+          (portref I1 (instanceref slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1))
+          (portref I3 (instanceref slave_fifo32_ctrl_tx_tvalid1))
+          (portref I3 (instanceref slave_fifo32_data_tx_tvalid1))
+          (portref I0 (instanceref slave_fifo32_state_FSM_FFd1_In2))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[10]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_10))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata371))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[11]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata381))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[12]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_12))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata391))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[13]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_13))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata401))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_becoming_full_l1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/becoming_full_l1") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[14]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_14))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata411))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_1__rt "f1/Mcount_wr_addr_cy<1>_rt") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_1__rt))
+          (portref S (instanceref f1_Mcount_wr_addr_cy_1_))
+          (portref LI (instanceref f1_Mcount_wr_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/state_glue_set") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_glue_set))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[15]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_15))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata421))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_20_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[20]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_20))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata481))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_16_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[16]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_16))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata431))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[21]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata491))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2_1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr11_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr11_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_11))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr11_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11__rt))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_17_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[17]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_17))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata441))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_22_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[22]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_22))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata501))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_18_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[18]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_18))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata461))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_23_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[23]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_23))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata511))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_19_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[19]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_19))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata471))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_24_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[24]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_24))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata521))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_0_ "slave_fifo32/gpif_data_out[0]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_0))
+          (portref I (instanceref GPIF_D_0_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_write_AND_42_o_inv") (joined
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2))
+          )
+         )
+         (net (rename f1_rd_addr_0_ "f1/rd_addr[0]") (joined
+          (portref Q (instanceref f1_rd_addr_0))
+          (portref I0 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref (member ADDRBRDADDR 12) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[30]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata591))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[25]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata531))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_1_ "slave_fifo32/gpif_data_out[1]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_1))
+          (portref I (instanceref GPIF_D_1_IOBUF))
+          )
+         )
+         (net (rename f1_rd_addr_1_ "f1/rd_addr[1]") (joined
+          (portref Q (instanceref f1_rd_addr_1))
+          (portref I2 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref (member ADDRBRDADDR 11) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[31]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata601))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[26]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata541))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_2_ "slave_fifo32/gpif_data_out[2]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_2))
+          (portref I (instanceref GPIF_D_2_IOBUF))
+          )
+         )
+         (net (rename f1_rd_addr_2_ "f1/rd_addr[2]") (joined
+          (portref Q (instanceref f1_rd_addr_2))
+          (portref I4 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref (member ADDRBRDADDR 10) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[27]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata551))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_3_ "slave_fifo32/gpif_data_out[3]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_3))
+          (portref I (instanceref GPIF_D_3_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt))
+          )
+         )
+         (net (rename f1_rd_addr_3_ "f1/rd_addr[3]") (joined
+          (portref Q (instanceref f1_rd_addr_3))
+          (portref I0 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref (member ADDRBRDADDR 9) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[28]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata571))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tvalid "slave_fifo32/ctrl_rx_tvalid") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1))
+          (portref I2 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11))
+          (portref I5 (instanceref slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1))
+          (portref I4 (instanceref slave_fifo32_state_FSM_FFd1_In2))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_4_ "slave_fifo32/gpif_data_out[4]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_4))
+          (portref I (instanceref GPIF_D_4_IOBUF))
+          )
+         )
+         (net (rename f1_rd_addr_4_ "f1/rd_addr[4]") (joined
+          (portref Q (instanceref f1_rd_addr_4))
+          (portref I2 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref (member ADDRBRDADDR 8) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[29]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata581))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_5_ "slave_fifo32/gpif_data_out[5]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_5))
+          (portref I (instanceref GPIF_D_5_IOBUF))
+          )
+         )
+         (net (rename f1_rd_addr_5_ "f1/rd_addr[5]") (joined
+          (portref Q (instanceref f1_rd_addr_5))
+          (portref I4 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref (member ADDRBRDADDR 7) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_6_ "slave_fifo32/gpif_data_out[6]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_6))
+          (portref I (instanceref GPIF_D_6_IOBUF))
+          )
+         )
+         (net (rename f1_rd_addr_6_ "f1/rd_addr[6]") (joined
+          (portref Q (instanceref f1_rd_addr_6))
+          (portref I0 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref (member ADDRBRDADDR 6) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_7_ "slave_fifo32/gpif_data_out[7]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_7))
+          (portref I (instanceref GPIF_D_7_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set))
+          )
+         )
+         (net (rename f1_rd_addr_7_ "f1/rd_addr[7]") (joined
+          (portref Q (instanceref f1_rd_addr_7))
+          (portref I2 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref (member ADDRBRDADDR 5) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_8_ "slave_fifo32/gpif_data_out[8]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_8))
+          (portref I (instanceref GPIF_D_8_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_9_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_))
+          )
+         )
+         (net (rename f1_rd_addr_8_ "f1/rd_addr[8]") (joined
+          (portref Q (instanceref f1_rd_addr_8))
+          (portref I4 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref (member ADDRBRDADDR 4) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_9_ "slave_fifo32/gpif_data_out[9]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_9))
+          (portref I (instanceref GPIF_D_9_IOBUF))
+          )
+         )
+         (net (rename f1_rd_addr_9_ "f1/rd_addr[9]") (joined
+          (portref Q (instanceref f1_rd_addr_9))
+          (portref I0 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref (member ADDRBRDADDR 3) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0))
+          )
+         )
+         (net (rename f1_rd_addr_12__wr_addr_12__equal_11_o "f1/rd_addr[12]_wr_addr[12]_equal_11_o") (joined
+          (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_))
+          (portref CI (instanceref f1__n0161_inv1_cy))
+          (portref I2 (instanceref f1_read_state_FSM_FFd1_In111))
+          (portref I1 (instanceref f1_read_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<3>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[3]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0))
+          )
+         )
+         (net (rename f0_dont_write_past_me_11__FRB "f0/dont_write_past_me<11>_FRB") (joined
+          (portref I5 (instanceref f0_Mcompar_becoming_full_lut_3_))
+          (portref Q (instanceref f0_dont_write_past_me_11__FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[0]") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[4]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[5]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15))
+          )
+         )
+         (net (rename f0_Result_8_1_FRB "f0/Result<8>1_FRB") (joined
+          (portref D (instanceref f0_rd_addr_8))
+          (portref Q (instanceref f0_Result_8_1_FRB))
+          (portref I0 (instanceref f0_Mcount_rd_addr_cy_8__rt))
+          (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_8__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[6]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+          )
+         )
+         (net (rename tx_codec_d_0_ "tx_codec_d[0]") (joined
+          (portref O (instanceref tx_codec_d_0_OBUF))
+          (portref (member tx_codec_d 11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[3]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_tx_tvalid "slave_fifo32/ctrl_tx_tvalid") (joined
+          (portref D (instanceref slave_fifo32_debug1_19))
+          (portref O (instanceref slave_fifo32_ctrl_tx_tvalid1))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_11__rt "f1/Mcount_rd_addr_cy<11>_rt") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_11__rt))
+          (portref S (instanceref f1_Mcount_rd_addr_cy_11_))
+          (portref LI (instanceref f1_Mcount_rd_addr_xor_11_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_))
+          )
+         )
+         (net (rename tx_codec_d_1_ "tx_codec_d[1]") (joined
+          (portref O (instanceref tx_codec_d_1_OBUF))
+          (portref (member tx_codec_d 10))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[4]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_))
+          )
+         )
+         (net (rename tx_codec_d_2_ "tx_codec_d[2]") (joined
+          (portref O (instanceref tx_codec_d_2_OBUF))
+          (portref (member tx_codec_d 9))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[5]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_))
+          )
+         )
+         (net (rename tx_codec_d_3_ "tx_codec_d[3]") (joined
+          (portref O (instanceref tx_codec_d_3_OBUF))
+          (portref (member tx_codec_d 8))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01211 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01211") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[6]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01213") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01214") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01215") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_))
+          )
+         )
+         (net (rename tx_codec_d_4_ "tx_codec_d[4]") (joined
+          (portref O (instanceref tx_codec_d_4_OBUF))
+          (portref (member tx_codec_d 7))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01216") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01217") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219))
+          )
+         )
+         (net (rename slave_fifo32_sloe_10 "slave_fifo32/sloe_10") (joined
+          (portref Q (instanceref slave_fifo32_sloe_10))
+          (portref T (instanceref GPIF_D_8_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01218") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219))
+          )
+         )
+         (net (rename slave_fifo32_sloe_11 "slave_fifo32/sloe_11") (joined
+          (portref Q (instanceref slave_fifo32_sloe_11))
+          (portref T (instanceref GPIF_D_9_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_12 "slave_fifo32/sloe_12") (joined
+          (portref Q (instanceref slave_fifo32_sloe_12))
+          (portref T (instanceref GPIF_D_10_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_sloe_13 "slave_fifo32/sloe_13") (joined
+          (portref Q (instanceref slave_fifo32_sloe_13))
+          (portref T (instanceref GPIF_D_11_IOBUF))
+          )
+         )
+         (net (rename tx_codec_d_5_ "tx_codec_d[5]") (joined
+          (portref O (instanceref tx_codec_d_5_OBUF))
+          (portref (member tx_codec_d 6))
+          )
+         )
+         (net (rename slave_fifo32_sloe_14 "slave_fifo32/sloe_14") (joined
+          (portref Q (instanceref slave_fifo32_sloe_14))
+          (portref T (instanceref GPIF_D_12_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_20 "slave_fifo32/sloe_20") (joined
+          (portref Q (instanceref slave_fifo32_sloe_20))
+          (portref T (instanceref GPIF_D_18_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_15 "slave_fifo32/sloe_15") (joined
+          (portref Q (instanceref slave_fifo32_sloe_15))
+          (portref T (instanceref GPIF_D_13_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_21 "slave_fifo32/sloe_21") (joined
+          (portref Q (instanceref slave_fifo32_sloe_21))
+          (portref T (instanceref GPIF_D_19_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_16 "slave_fifo32/sloe_16") (joined
+          (portref Q (instanceref slave_fifo32_sloe_16))
+          (portref T (instanceref GPIF_D_14_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_22 "slave_fifo32/sloe_22") (joined
+          (portref Q (instanceref slave_fifo32_sloe_22))
+          (portref T (instanceref GPIF_D_20_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_17 "slave_fifo32/sloe_17") (joined
+          (portref Q (instanceref slave_fifo32_sloe_17))
+          (portref T (instanceref GPIF_D_15_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_sloe_18 "slave_fifo32/sloe_18") (joined
+          (portref Q (instanceref slave_fifo32_sloe_18))
+          (portref T (instanceref GPIF_D_16_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_23 "slave_fifo32/sloe_23") (joined
+          (portref Q (instanceref slave_fifo32_sloe_23))
+          (portref T (instanceref GPIF_D_21_IOBUF))
+          )
+         )
+         (net (rename tx_codec_d_6_ "tx_codec_d[6]") (joined
+          (portref O (instanceref tx_codec_d_6_OBUF))
+          (portref (member tx_codec_d 5))
+          )
+         )
+         (net (rename slave_fifo32_sloe_19 "slave_fifo32/sloe_19") (joined
+          (portref Q (instanceref slave_fifo32_sloe_19))
+          (portref T (instanceref GPIF_D_17_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_24 "slave_fifo32/sloe_24") (joined
+          (portref Q (instanceref slave_fifo32_sloe_24))
+          (portref T (instanceref GPIF_D_22_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_30 "slave_fifo32/sloe_30") (joined
+          (portref Q (instanceref slave_fifo32_sloe_30))
+          (portref T (instanceref GPIF_D_28_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_25 "slave_fifo32/sloe_25") (joined
+          (portref Q (instanceref slave_fifo32_sloe_25))
+          (portref T (instanceref GPIF_D_23_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_31 "slave_fifo32/sloe_31") (joined
+          (portref Q (instanceref slave_fifo32_sloe_31))
+          (portref T (instanceref GPIF_D_29_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_26 "slave_fifo32/sloe_26") (joined
+          (portref Q (instanceref slave_fifo32_sloe_26))
+          (portref T (instanceref GPIF_D_24_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_32 "slave_fifo32/sloe_32") (joined
+          (portref Q (instanceref slave_fifo32_sloe_32))
+          (portref T (instanceref GPIF_D_30_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_27 "slave_fifo32/sloe_27") (joined
+          (portref Q (instanceref slave_fifo32_sloe_27))
+          (portref T (instanceref GPIF_D_25_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_sloe_28 "slave_fifo32/sloe_28") (joined
+          (portref Q (instanceref slave_fifo32_sloe_28))
+          (portref T (instanceref GPIF_D_26_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_33 "slave_fifo32/sloe_33") (joined
+          (portref Q (instanceref slave_fifo32_sloe_33))
+          (portref T (instanceref GPIF_D_31_IOBUF))
+          )
+         )
+         (net (rename tx_codec_d_7_ "tx_codec_d[7]") (joined
+          (portref O (instanceref tx_codec_d_7_OBUF))
+          (portref (member tx_codec_d 4))
+          )
+         )
+         (net (rename slave_fifo32_sloe_29 "slave_fifo32/sloe_29") (joined
+          (portref Q (instanceref slave_fifo32_sloe_29))
+          (portref T (instanceref GPIF_D_27_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_sloe_34 "slave_fifo32/sloe_34") (joined
+          (portref Q (instanceref slave_fifo32_sloe_34))
+          (portref D (instanceref slave_fifo32_debug1_31))
+          (portref I0 (instanceref slave_fifo32_sloe_1_rstpot))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_))
+          )
+         )
+         (net (rename tx_codec_d_8_ "tx_codec_d[8]") (joined
+          (portref O (instanceref tx_codec_d_8_OBUF))
+          (portref (member tx_codec_d 3))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_))
+          )
+         )
+         (net (rename tx_codec_d_9_ "tx_codec_d[9]") (joined
+          (portref O (instanceref tx_codec_d_9_OBUF))
+          (portref (member tx_codec_d 2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[9]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_))
+          )
+         )
+         (net bus_clk (joined
+          (portref C (instanceref bus_sync_reset_int))
+          (portref C (instanceref bus_sync_reset_out))
+          (portref O (instanceref gen_clks_clkout3_buf))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_5))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_6))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_7))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_8))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_9))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_10))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_11))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_12))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_13))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_14))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_15))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_16))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_17))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_18))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_19))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_20))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_21))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_22))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_23))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_24))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_25))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_26))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_27))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_28))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_29))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_30))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_31))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_4))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_5))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_6))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_7))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_8))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_9))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_11))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_5))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_6))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_7))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_8))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_9))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_10))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_11))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_12))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_13))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_14))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_15))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_16))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_17))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_18))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_19))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_20))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_22))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_23))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_24))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9))
+          (portref C (instanceref f1_rd_addr_1))
+          (portref C (instanceref f1_rd_addr_2))
+          (portref C (instanceref f1_rd_addr_3))
+          (portref C (instanceref f1_rd_addr_4))
+          (portref C (instanceref f1_rd_addr_5))
+          (portref C (instanceref f1_rd_addr_6))
+          (portref C (instanceref f1_rd_addr_7))
+          (portref C (instanceref f1_rd_addr_8))
+          (portref C (instanceref f1_rd_addr_9))
+          (portref C (instanceref f1_rd_addr_10))
+          (portref C (instanceref f1_rd_addr_11))
+          (portref C (instanceref f1_rd_addr_12))
+          (portref C (instanceref f1_wr_addr_1))
+          (portref C (instanceref f1_wr_addr_2))
+          (portref C (instanceref f1_wr_addr_3))
+          (portref C (instanceref f1_wr_addr_4))
+          (portref C (instanceref f1_wr_addr_5))
+          (portref C (instanceref f1_wr_addr_6))
+          (portref C (instanceref f1_wr_addr_7))
+          (portref C (instanceref f1_wr_addr_8))
+          (portref C (instanceref f1_wr_addr_9))
+          (portref C (instanceref f1_wr_addr_10))
+          (portref C (instanceref f1_wr_addr_11))
+          (portref C (instanceref f1_wr_addr_12))
+          (portref C (instanceref f1_read_state_FSM_FFd2))
+          (portref C (instanceref f1_read_state_FSM_FFd1))
+          (portref C (instanceref f1_rd_addr_0))
+          (portref C (instanceref f1_wr_addr_0))
+          (portref C (instanceref f0_rd_addr_1))
+          (portref C (instanceref f0_rd_addr_2))
+          (portref C (instanceref f0_rd_addr_3))
+          (portref C (instanceref f0_rd_addr_4))
+          (portref C (instanceref f0_rd_addr_5))
+          (portref C (instanceref f0_rd_addr_6))
+          (portref C (instanceref f0_rd_addr_7))
+          (portref C (instanceref f0_rd_addr_8))
+          (portref C (instanceref f0_rd_addr_9))
+          (portref C (instanceref f0_rd_addr_10))
+          (portref C (instanceref f0_rd_addr_11))
+          (portref C (instanceref f0_rd_addr_12))
+          (portref C (instanceref f0_wr_addr_1))
+          (portref C (instanceref f0_wr_addr_2))
+          (portref C (instanceref f0_wr_addr_3))
+          (portref C (instanceref f0_wr_addr_4))
+          (portref C (instanceref f0_wr_addr_5))
+          (portref C (instanceref f0_wr_addr_6))
+          (portref C (instanceref f0_wr_addr_7))
+          (portref C (instanceref f0_wr_addr_8))
+          (portref C (instanceref f0_wr_addr_9))
+          (portref C (instanceref f0_wr_addr_10))
+          (portref C (instanceref f0_wr_addr_11))
+          (portref C (instanceref f0_wr_addr_12))
+          (portref C (instanceref f0_read_state_FSM_FFd2))
+          (portref C (instanceref f0_read_state_FSM_FFd1))
+          (portref C (instanceref f0_rd_addr_0))
+          (portref C (instanceref f0_wr_addr_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump))
+          (portref C (instanceref f1_full_reg))
+          (portref C (instanceref f0_full_reg))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg))
+          (portref C (instanceref f1_Result_0_2_FRB))
+          (portref C (instanceref f1_Result_1_2_FRB))
+          (portref C (instanceref f1_Result_2_2_FRB))
+          (portref C (instanceref f1_Result_3_2_FRB))
+          (portref C (instanceref f1_Result_4_2_FRB))
+          (portref C (instanceref f1_Result_5_2_FRB))
+          (portref C (instanceref f1_Result_6_2_FRB))
+          (portref C (instanceref f1_Result_7_2_FRB))
+          (portref C (instanceref f1_Result_8_2_FRB))
+          (portref C (instanceref f1_Result_9_2_FRB))
+          (portref C (instanceref f1_Result_10_2_FRB))
+          (portref C (instanceref f1_Result_11_2_FRB))
+          (portref C (instanceref f1_Result_12_2_FRB))
+          (portref C (instanceref f1_Result_0_1_FRB))
+          (portref C (instanceref f1_Result_1_1_FRB))
+          (portref C (instanceref f1_Result_2_1_FRB))
+          (portref C (instanceref f1_Result_3_1_FRB))
+          (portref C (instanceref f1_Result_4_1_FRB))
+          (portref C (instanceref f1_Result_5_1_FRB))
+          (portref C (instanceref f1_Result_6_1_FRB))
+          (portref C (instanceref f1_Result_7_1_FRB))
+          (portref C (instanceref f1_Result_8_1_FRB))
+          (portref C (instanceref f1_Result_9_1_FRB))
+          (portref C (instanceref f1_Result_10_1_FRB))
+          (portref C (instanceref f1_Result_11_1_FRB))
+          (portref C (instanceref f1_Result_12_1_FRB))
+          (portref C (instanceref f1_dont_write_past_me_0__FRB))
+          (portref C (instanceref f1_dont_write_past_me_1__FRB))
+          (portref C (instanceref f1_dont_write_past_me_2__FRB))
+          (portref C (instanceref f1_dont_write_past_me_3__FRB))
+          (portref C (instanceref f1_dont_write_past_me_4__FRB))
+          (portref C (instanceref f1_dont_write_past_me_5__FRB))
+          (portref C (instanceref f1_dont_write_past_me_6__FRB))
+          (portref C (instanceref f1_dont_write_past_me_7__FRB))
+          (portref C (instanceref f1_dont_write_past_me_8__FRB))
+          (portref C (instanceref f1_dont_write_past_me_9__FRB))
+          (portref C (instanceref f1_dont_write_past_me_10__FRB))
+          (portref C (instanceref f1_dont_write_past_me_11__FRB))
+          (portref C (instanceref f1_dont_write_past_me_12__FRB))
+          (portref C (instanceref f0_Result_0_2_FRB))
+          (portref C (instanceref f0_Result_1_2_FRB))
+          (portref C (instanceref f0_Result_2_2_FRB))
+          (portref C (instanceref f0_Result_3_2_FRB))
+          (portref C (instanceref f0_Result_4_2_FRB))
+          (portref C (instanceref f0_Result_5_2_FRB))
+          (portref C (instanceref f0_Result_6_2_FRB))
+          (portref C (instanceref f0_Result_7_2_FRB))
+          (portref C (instanceref f0_Result_8_2_FRB))
+          (portref C (instanceref f0_Result_9_2_FRB))
+          (portref C (instanceref f0_Result_10_2_FRB))
+          (portref C (instanceref f0_Result_11_2_FRB))
+          (portref C (instanceref f0_Result_12_2_FRB))
+          (portref C (instanceref f0_Result_0_1_FRB))
+          (portref C (instanceref f0_Result_1_1_FRB))
+          (portref C (instanceref f0_Result_2_1_FRB))
+          (portref C (instanceref f0_Result_3_1_FRB))
+          (portref C (instanceref f0_Result_4_1_FRB))
+          (portref C (instanceref f0_Result_5_1_FRB))
+          (portref C (instanceref f0_Result_6_1_FRB))
+          (portref C (instanceref f0_Result_7_1_FRB))
+          (portref C (instanceref f0_Result_8_1_FRB))
+          (portref C (instanceref f0_Result_9_1_FRB))
+          (portref C (instanceref f0_Result_10_1_FRB))
+          (portref C (instanceref f0_Result_11_1_FRB))
+          (portref C (instanceref f0_Result_12_1_FRB))
+          (portref C (instanceref f0_dont_write_past_me_0__FRB))
+          (portref C (instanceref f0_dont_write_past_me_1__FRB))
+          (portref C (instanceref f0_dont_write_past_me_2__FRB))
+          (portref C (instanceref f0_dont_write_past_me_3__FRB))
+          (portref C (instanceref f0_dont_write_past_me_4__FRB))
+          (portref C (instanceref f0_dont_write_past_me_5__FRB))
+          (portref C (instanceref f0_dont_write_past_me_6__FRB))
+          (portref C (instanceref f0_dont_write_past_me_7__FRB))
+          (portref C (instanceref f0_dont_write_past_me_8__FRB))
+          (portref C (instanceref f0_dont_write_past_me_9__FRB))
+          (portref C (instanceref f0_dont_write_past_me_10__FRB))
+          (portref C (instanceref f0_dont_write_past_me_11__FRB))
+          (portref C (instanceref f0_dont_write_past_me_12__FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4))
+          (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref CLKAWRCLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref CLKBRDCLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref CLKAWRCLK (instanceref f1_ram_Mram_ram33))
+          (portref CLKBRDCLK (instanceref f1_ram_Mram_ram33))
+          (portref CLKA (instanceref f1_ram_Mram_ram31))
+          (portref CLKB (instanceref f1_ram_Mram_ram31))
+          (portref CLKA (instanceref f1_ram_Mram_ram30))
+          (portref CLKB (instanceref f1_ram_Mram_ram30))
+          (portref CLKA (instanceref f1_ram_Mram_ram32))
+          (portref CLKB (instanceref f1_ram_Mram_ram32))
+          (portref CLKA (instanceref f1_ram_Mram_ram28))
+          (portref CLKB (instanceref f1_ram_Mram_ram28))
+          (portref CLKA (instanceref f1_ram_Mram_ram27))
+          (portref CLKB (instanceref f1_ram_Mram_ram27))
+          (portref CLKA (instanceref f1_ram_Mram_ram29))
+          (portref CLKB (instanceref f1_ram_Mram_ram29))
+          (portref CLKA (instanceref f1_ram_Mram_ram25))
+          (portref CLKB (instanceref f1_ram_Mram_ram25))
+          (portref CLKA (instanceref f1_ram_Mram_ram24))
+          (portref CLKB (instanceref f1_ram_Mram_ram24))
+          (portref CLKA (instanceref f1_ram_Mram_ram26))
+          (portref CLKB (instanceref f1_ram_Mram_ram26))
+          (portref CLKA (instanceref f1_ram_Mram_ram22))
+          (portref CLKB (instanceref f1_ram_Mram_ram22))
+          (portref CLKA (instanceref f1_ram_Mram_ram21))
+          (portref CLKB (instanceref f1_ram_Mram_ram21))
+          (portref CLKA (instanceref f1_ram_Mram_ram23))
+          (portref CLKB (instanceref f1_ram_Mram_ram23))
+          (portref CLKA (instanceref f1_ram_Mram_ram19))
+          (portref CLKB (instanceref f1_ram_Mram_ram19))
+          (portref CLKA (instanceref f1_ram_Mram_ram18))
+          (portref CLKB (instanceref f1_ram_Mram_ram18))
+          (portref CLKA (instanceref f1_ram_Mram_ram20))
+          (portref CLKB (instanceref f1_ram_Mram_ram20))
+          (portref CLKA (instanceref f1_ram_Mram_ram16))
+          (portref CLKB (instanceref f1_ram_Mram_ram16))
+          (portref CLKA (instanceref f1_ram_Mram_ram15))
+          (portref CLKB (instanceref f1_ram_Mram_ram15))
+          (portref CLKA (instanceref f1_ram_Mram_ram17))
+          (portref CLKB (instanceref f1_ram_Mram_ram17))
+          (portref CLKA (instanceref f1_ram_Mram_ram14))
+          (portref CLKB (instanceref f1_ram_Mram_ram14))
+          (portref CLKA (instanceref f1_ram_Mram_ram13))
+          (portref CLKB (instanceref f1_ram_Mram_ram13))
+          (portref CLKA (instanceref f1_ram_Mram_ram12))
+          (portref CLKB (instanceref f1_ram_Mram_ram12))
+          (portref CLKA (instanceref f1_ram_Mram_ram11))
+          (portref CLKB (instanceref f1_ram_Mram_ram11))
+          (portref CLKA (instanceref f1_ram_Mram_ram9))
+          (portref CLKB (instanceref f1_ram_Mram_ram9))
+          (portref CLKA (instanceref f1_ram_Mram_ram8))
+          (portref CLKB (instanceref f1_ram_Mram_ram8))
+          (portref CLKA (instanceref f1_ram_Mram_ram10))
+          (portref CLKB (instanceref f1_ram_Mram_ram10))
+          (portref CLKA (instanceref f1_ram_Mram_ram6))
+          (portref CLKB (instanceref f1_ram_Mram_ram6))
+          (portref CLKA (instanceref f1_ram_Mram_ram5))
+          (portref CLKB (instanceref f1_ram_Mram_ram5))
+          (portref CLKA (instanceref f1_ram_Mram_ram7))
+          (portref CLKB (instanceref f1_ram_Mram_ram7))
+          (portref CLKA (instanceref f1_ram_Mram_ram3))
+          (portref CLKB (instanceref f1_ram_Mram_ram3))
+          (portref CLKA (instanceref f1_ram_Mram_ram2))
+          (portref CLKB (instanceref f1_ram_Mram_ram2))
+          (portref CLKA (instanceref f1_ram_Mram_ram4))
+          (portref CLKB (instanceref f1_ram_Mram_ram4))
+          (portref CLKA (instanceref f1_ram_Mram_ram1))
+          (portref CLKB (instanceref f1_ram_Mram_ram1))
+          (portref CLKAWRCLK (instanceref f0_ram_Mram_ram33))
+          (portref CLKBRDCLK (instanceref f0_ram_Mram_ram33))
+          (portref CLKA (instanceref f0_ram_Mram_ram31))
+          (portref CLKB (instanceref f0_ram_Mram_ram31))
+          (portref CLKA (instanceref f0_ram_Mram_ram30))
+          (portref CLKB (instanceref f0_ram_Mram_ram30))
+          (portref CLKA (instanceref f0_ram_Mram_ram32))
+          (portref CLKB (instanceref f0_ram_Mram_ram32))
+          (portref CLKA (instanceref f0_ram_Mram_ram28))
+          (portref CLKB (instanceref f0_ram_Mram_ram28))
+          (portref CLKA (instanceref f0_ram_Mram_ram27))
+          (portref CLKB (instanceref f0_ram_Mram_ram27))
+          (portref CLKA (instanceref f0_ram_Mram_ram29))
+          (portref CLKB (instanceref f0_ram_Mram_ram29))
+          (portref CLKA (instanceref f0_ram_Mram_ram25))
+          (portref CLKB (instanceref f0_ram_Mram_ram25))
+          (portref CLKA (instanceref f0_ram_Mram_ram24))
+          (portref CLKB (instanceref f0_ram_Mram_ram24))
+          (portref CLKA (instanceref f0_ram_Mram_ram26))
+          (portref CLKB (instanceref f0_ram_Mram_ram26))
+          (portref CLKA (instanceref f0_ram_Mram_ram22))
+          (portref CLKB (instanceref f0_ram_Mram_ram22))
+          (portref CLKA (instanceref f0_ram_Mram_ram21))
+          (portref CLKB (instanceref f0_ram_Mram_ram21))
+          (portref CLKA (instanceref f0_ram_Mram_ram23))
+          (portref CLKB (instanceref f0_ram_Mram_ram23))
+          (portref CLKA (instanceref f0_ram_Mram_ram19))
+          (portref CLKB (instanceref f0_ram_Mram_ram19))
+          (portref CLKA (instanceref f0_ram_Mram_ram18))
+          (portref CLKB (instanceref f0_ram_Mram_ram18))
+          (portref CLKA (instanceref f0_ram_Mram_ram20))
+          (portref CLKB (instanceref f0_ram_Mram_ram20))
+          (portref CLKA (instanceref f0_ram_Mram_ram16))
+          (portref CLKB (instanceref f0_ram_Mram_ram16))
+          (portref CLKA (instanceref f0_ram_Mram_ram15))
+          (portref CLKB (instanceref f0_ram_Mram_ram15))
+          (portref CLKA (instanceref f0_ram_Mram_ram17))
+          (portref CLKB (instanceref f0_ram_Mram_ram17))
+          (portref CLKA (instanceref f0_ram_Mram_ram14))
+          (portref CLKB (instanceref f0_ram_Mram_ram14))
+          (portref CLKA (instanceref f0_ram_Mram_ram13))
+          (portref CLKB (instanceref f0_ram_Mram_ram13))
+          (portref CLKA (instanceref f0_ram_Mram_ram12))
+          (portref CLKB (instanceref f0_ram_Mram_ram12))
+          (portref CLKA (instanceref f0_ram_Mram_ram11))
+          (portref CLKB (instanceref f0_ram_Mram_ram11))
+          (portref CLKA (instanceref f0_ram_Mram_ram9))
+          (portref CLKB (instanceref f0_ram_Mram_ram9))
+          (portref CLKA (instanceref f0_ram_Mram_ram8))
+          (portref CLKB (instanceref f0_ram_Mram_ram8))
+          (portref CLKA (instanceref f0_ram_Mram_ram10))
+          (portref CLKB (instanceref f0_ram_Mram_ram10))
+          (portref CLKA (instanceref f0_ram_Mram_ram6))
+          (portref CLKB (instanceref f0_ram_Mram_ram6))
+          (portref CLKA (instanceref f0_ram_Mram_ram5))
+          (portref CLKB (instanceref f0_ram_Mram_ram5))
+          (portref CLKA (instanceref f0_ram_Mram_ram7))
+          (portref CLKB (instanceref f0_ram_Mram_ram7))
+          (portref CLKA (instanceref f0_ram_Mram_ram3))
+          (portref CLKB (instanceref f0_ram_Mram_ram3))
+          (portref CLKA (instanceref f0_ram_Mram_ram2))
+          (portref CLKB (instanceref f0_ram_Mram_ram2))
+          (portref CLKA (instanceref f0_ram_Mram_ram4))
+          (portref CLKB (instanceref f0_ram_Mram_ram4))
+          (portref CLKA (instanceref f0_ram_Mram_ram1))
+          (portref CLKB (instanceref f0_ram_Mram_ram1))
+          (portref rd_clk (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          (portref rd_clk (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          (portref wr_clk (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          (portref wr_clk (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename gen_clks_CLK_OUT1_40_int "gen_clks/CLK_OUT1_40_int") (joined
+          (portref O (instanceref gen_clks_clkout1_buf))
+          (portref CLKFB (instanceref gen_clks_dcm_sp_inst))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_10_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[10]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_10))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata210))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata371))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012121 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n012121") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216))
+          )
+         )
+         (net (rename n0036_10_ "n0036[10]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram6))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_11_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[11]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata310))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata381))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          )
+         )
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+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram6))
+          )
+         )
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+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_12))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata410))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata391))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          )
+         )
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+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram7))
+          )
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+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata510))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata401))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          )
+         )
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+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram7))
+          )
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+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1))
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+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11))
+          )
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+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_7))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt))
+          )
+         )
+         (net (rename n0036_14_ "n0036[14]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram8))
+          )
+         )
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+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5))
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+          (portref (member DIA 17) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G))
+          )
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+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_20))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata131))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata481))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          )
+         )
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+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata71))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata421))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          )
+         )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT53 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT53") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+          )
+         )
+         (net (rename n0036_15_ "n0036[15]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram8))
+          )
+         )
+         (net (rename n0036_20_ "n0036[20]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_21_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[21]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_21))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata141))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata491))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_16_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[16]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_16))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata81))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata431))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          )
+         )
+         (net (rename n0036_16_ "n0036[16]") (joined
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+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram9))
+          )
+         )
+         (net (rename n0036_21_ "n0036[21]") (joined
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+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr2_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_2))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr2_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_22_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[22]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_22))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata151))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata501))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_17_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[17]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_17))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata91))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata441))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          )
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+         (net (rename n0036_17_ "n0036[17]") (joined
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+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram9))
+          )
+         )
+         (net (rename n0036_22_ "n0036[22]") (joined
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+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram12))
+          )
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+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata161))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata511))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          )
+         )
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+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_18))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata101))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata461))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          )
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+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram10))
+          )
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+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram12))
+          )
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+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata521))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          )
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+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_19))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata111))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata471))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          )
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+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut))
+          )
+         )
+         (net (rename n0036_19_ "n0036[19]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram10))
+          )
+         )
+         (net (rename n0036_24_ "n0036[24]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram13))
+          )
+         )
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+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_30))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata241))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata591))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          )
+         )
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+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_25))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata181))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata531))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          )
+         )
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+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata110))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata261))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename n0036_25_ "n0036[25]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram13))
+          )
+         )
+         (net (rename n0036_30_ "n0036[30]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram16))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[10]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_10_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_10_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_26_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[26]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_26))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata191))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata541))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_31_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[31]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_31))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata251))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata601))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[1]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata121))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata271))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename n0036_26_ "n0036[26]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram14))
+          )
+         )
+         (net (rename n0036_31_ "n0036[31]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram16))
+          )
+         )
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+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_11_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_11_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_27_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[27]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_27))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata201))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata551))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_11__rt "f1/Mcount_wr_addr_cy<11>_rt") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_11__rt))
+          (portref S (instanceref f1_Mcount_wr_addr_cy_11_))
+          (portref LI (instanceref f1_Mcount_wr_addr_xor_11_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[2]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata231))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata281))
+          (portref (member DOB 29) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename n0036_27_ "n0036[27]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram14))
+          )
+         )
+         (net (rename n0036_32_ "n0036[32]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram17))
+          )
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+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_28_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[28]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_28))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata211))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata571))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<1>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[3]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_3))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata291))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata341))
+          (portref (member DOB 28) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename n0036_28_ "n0036[28]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram15))
+          )
+         )
+         (net (rename n0036_33_ "n0036[33]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[13]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[29]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_29))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata221))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata581))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[4]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_4))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata301))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata451))
+          (portref (member DOB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17))
+          )
+         )
+         (net (rename n0036_29_ "n0036[29]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram15))
+          )
+         )
+         (net (rename n0036_34_ "n0036[34]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram18))
+          )
+         )
+         (net (rename f0_Result_6_2_FRB "f0/Result<6>2_FRB") (joined
+          (portref D (instanceref f0_wr_addr_6))
+          (portref Q (instanceref f0_Result_6_2_FRB))
+          (portref I0 (instanceref f0_Mcount_wr_addr_cy_6__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[14]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_14_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_14_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[5]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_5))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata311))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata561))
+          (portref (member DOB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename f1__n0161_inv1_lut "f1/_n0161_inv1_lut") (joined
+          (portref O (instanceref f1__n0161_inv1_lut))
+          (portref S (instanceref f1__n0161_inv1_cy))
+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81))
+          )
+         )
+         (net (rename n0036_35_ "n0036[35]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram18))
+          )
+         )
+         (net (rename n0036_40_ "n0036[40]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram21))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[0]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata110))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[15]") (joined
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[6]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_6))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata321))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata611))
+          (portref (member DOB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91))
+          )
+         )
+         (net (rename n0036_36_ "n0036[36]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram19))
+          )
+         )
+         (net (rename n0036_41_ "n0036[41]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram21))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[1]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata121))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full101 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full101") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1011))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[7]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_7))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata331))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata621))
+          (portref (member DOB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full102 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full102") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1021))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101))
+          )
+         )
+         (net (rename n0036_37_ "n0036[37]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram19))
+          )
+         )
+         (net (rename n0036_42_ "n0036[42]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram22))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[2]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata231))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[8]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_8))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata351))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata631))
+          (portref (member DOB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111))
+          )
+         )
+         (net (rename n0036_38_ "n0036[38]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram20))
+          )
+         )
+         (net (rename n0036_43_ "n0036[43]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram22))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[3]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata341))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[9]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_9))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata361))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata641))
+          (portref (member DOB 22) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121))
+          )
+         )
+         (net (rename n0036_39_ "n0036[39]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram20))
+          )
+         )
+         (net (rename n0036_44_ "n0036[44]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram23))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[4]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata451))
+          )
+         )
+         (net LED_TXRX1_RX (joined
+          (portref O (instanceref LED_TXRX1_RX_OBUF))
+          (portref LED_TXRX1_RX)
+          )
+         )
+         (net (rename f1_Result_12_1_FRB "f1/Result<12>1_FRB") (joined
+          (portref D (instanceref f1_rd_addr_12))
+          (portref Q (instanceref f1_Result_12_1_FRB))
+          (portref I0 (instanceref f1_Mcount_rd_addr_xor_12__rt))
+          (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_12__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[10]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_))
+          )
+         )
+         (net (rename n0036_45_ "n0036[45]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram23))
+          )
+         )
+         (net (rename n0036_50_ "n0036[50]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram26))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[5]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata561))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[11]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_))
+          )
+         )
+         (net (rename n0036_46_ "n0036[46]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram24))
+          )
+         )
+         (net (rename n0036_51_ "n0036[51]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram26))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[6]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata611))
+          )
+         )
+         (net LED_TXRX1_TX (joined
+          (portref O (instanceref LED_TXRX1_TX_OBUF))
+          (portref LED_TXRX1_TX)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[12]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_))
+          )
+         )
+         (net (rename n0036_47_ "n0036[47]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram24))
+          )
+         )
+         (net (rename n0036_52_ "n0036[52]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram27))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[7]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata621))
+          )
+         )
+         (net cat_miso_IBUF (joined
+          (portref I1 (instanceref fx3_miso1))
+          (portref O (instanceref cat_miso_IBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[9]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[13]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14_))
+          )
+         )
+         (net (rename n0036_48_ "n0036[48]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram25))
+          )
+         )
+         (net (rename n0036_53_ "n0036[53]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram27))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0_ "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0))
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+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_0_11_INV_0))
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+          )
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+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_7))
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+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1))
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+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_))
+          )
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+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram25))
+          )
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+          )
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+          )
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+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_2))
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+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_SW0))
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+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_52_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[52]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata481))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_47_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[47]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata421))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_slrd "slave_fifo32/slrd") (joined
+          (portref I (instanceref GPIF_CTL3_OBUF))
+          (portref Q (instanceref slave_fifo32_slrd))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[7]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_53_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[53]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata491))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_48_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[48]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata431))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_0_rstpot") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_54_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[54]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata501))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_49_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[49]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata441))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_60_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[60]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata571))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_55_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[55]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata511))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_61_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[61]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata581))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_56_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[56]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata521))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_62_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[62]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata591))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_57_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[57]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata531))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_full "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/full") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2))
+          (portref full (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f1_Result_2_2_FRB "f1/Result<2>2_FRB") (joined
+          (portref D (instanceref f1_wr_addr_2))
+          (portref Q (instanceref f1_Result_2_2_FRB))
+          (portref I0 (instanceref f1_Mcount_wr_addr_cy_2__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_63_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[63]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata601))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_58_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[58]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata541))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_59_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[59]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata551))
+          )
+         )
+         (net (rename slave_fifo32_slwr "slave_fifo32/slwr") (joined
+          (portref Q (instanceref slave_fifo32_slwr))
+          (portref I (instanceref GPIF_CTL1_OBUF))
+          )
+         )
+         (net (rename f0__n0161_inv1_lut "f0/_n0161_inv1_lut") (joined
+          (portref O (instanceref f0__n0161_inv1_lut))
+          (portref S (instanceref f0__n0161_inv1_cy))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr9_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218_SW0_FRB") (joined
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012111") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012112") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012113") (joined
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012114") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_5__rt "f1/Mcount_rd_addr_cy<5>_rt") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_5__rt))
+          (portref S (instanceref f1_Mcount_rd_addr_cy_5_))
+          (portref LI (instanceref f1_Mcount_rd_addr_xor_5_))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_1__rt "f0/Mcount_rd_addr_cy<1>_rt") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_1__rt))
+          (portref S (instanceref f0_Mcount_rd_addr_cy_1_))
+          (portref LI (instanceref f0_Mcount_rd_addr_xor_1_))
+          )
+         )
+         (net (rename f0_read_state_FSM_FFd2_In "f0/read_state_FSM_FFd2-In") (joined
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+          (portref O (instanceref f0_read_state_FSM_FFd2_In1))
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0))
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0))
+          )
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+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219))
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+          )
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+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0))
+          )
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+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv2") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6))
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+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv5") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6))
+          )
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+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41))
+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_11_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT53 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT53") (joined
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          )
+         )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[11]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_12_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_10_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[10]") (joined
+          (portref (member DIA 21) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 61) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_11_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[11]") (joined
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+          (portref (member dout 60) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_12_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[12]") (joined
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+          (portref (member dout 59) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref (member dout 58) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_7_))
+          )
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+          (portref (member dout 57) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref (member dout 51) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref (member dout 56) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref (member dout 50) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref (member dout 55) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref LI (instanceref f1_Msub_dont_write_past_me_xor_2_))
+          (portref O (instanceref f1_Msub_dont_write_past_me_lut_2__INV_0))
+          )
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+          (portref (member dout 49) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref (member dout 54) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref O (instanceref f1_Msub_dont_write_past_me_lut_3__INV_0))
+          )
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+          (portref (member dout 48) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref (member dout 53) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref O (instanceref f1_Msub_dont_write_past_me_lut_4__INV_0))
+          )
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+          (portref (member dout 47) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref (member dout 52) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref LI (instanceref f1_Msub_dont_write_past_me_xor_5_))
+          (portref O (instanceref f1_Msub_dont_write_past_me_lut_5__INV_0))
+          )
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+          )
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+          (portref (member dout 46) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref S (instanceref f1_Mcount_wr_addr_cy_2_))
+          (portref LI (instanceref f1_Mcount_wr_addr_xor_2_))
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+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_32_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[32]") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          (portref (member DIA 17) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1))
+          (portref (member dout 39) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_lut_8_ "f1/Msub_dont_write_past_me_lut[8]") (joined
+          (portref S (instanceref f1_Msub_dont_write_past_me_cy_8_))
+          (portref LI (instanceref f1_Msub_dont_write_past_me_xor_8_))
+          (portref O (instanceref f1_Msub_dont_write_past_me_lut_8__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_28_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[28]") (joined
+          (portref (member DIA 21) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 43) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_lut_9_ "f1/Msub_dont_write_past_me_lut[9]") (joined
+          (portref S (instanceref f1_Msub_dont_write_past_me_cy_9_))
+          (portref LI (instanceref f1_Msub_dont_write_past_me_xor_9_))
+          (portref O (instanceref f1_Msub_dont_write_past_me_lut_9__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_29_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[29]") (joined
+          (portref (member DIA 20) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 42) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr12_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr12_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_12))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr12_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_12__rt))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full921))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_2))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr[3]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In1") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In3") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr[4]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_write_AND_42_o_inv "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_write_AND_42_o_inv") (joined
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_write_AND_42_o_inv2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_10_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr[5]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr[6]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_6))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_clear_inv "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/clear_inv") (joined
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0_))
+          (portref P (instanceref XST_VCC))
+          (portref CE (instanceref ODDR2_ifclk))
+          (portref D0 (instanceref ODDR2_ifclk))
+          (portref CE (instanceref ODDR2_ifclk_dbg))
+          (portref D0 (instanceref ODDR2_ifclk_dbg))
+          (portref CE (instanceref catgen_gen_pins_0__oddr2))
+          (portref CE (instanceref catgen_gen_pins_1__oddr2))
+          (portref CE (instanceref catgen_gen_pins_2__oddr2))
+          (portref CE (instanceref catgen_gen_pins_3__oddr2))
+          (portref CE (instanceref catgen_gen_pins_4__oddr2))
+          (portref CE (instanceref catgen_gen_pins_5__oddr2))
+          (portref CE (instanceref catgen_gen_pins_6__oddr2))
+          (portref CE (instanceref catgen_gen_pins_7__oddr2))
+          (portref CE (instanceref catgen_gen_pins_8__oddr2))
+          (portref CE (instanceref catgen_gen_pins_9__oddr2))
+          (portref CE (instanceref catgen_gen_pins_10__oddr2))
+          (portref CE (instanceref catgen_gen_pins_11__oddr2))
+          (portref CE (instanceref catgen_oddr2_frame))
+          (portref CE (instanceref catgen_oddr2_clk))
+          (portref D0 (instanceref catgen_oddr2_clk))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_10_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_11_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_12_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_13_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_14_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_5_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_6_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_7_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_8_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_9_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_10_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_11_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_14_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_cy_0_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_xor_0_))
+          (portref DI (instanceref f1_Msub_dont_write_past_me_cy_2_))
+          (portref DI (instanceref f1_Msub_dont_write_past_me_cy_3_))
+          (portref DI (instanceref f1_Msub_dont_write_past_me_cy_4_))
+          (portref DI (instanceref f1_Msub_dont_write_past_me_cy_5_))
+          (portref DI (instanceref f1_Msub_dont_write_past_me_cy_6_))
+          (portref DI (instanceref f1_Msub_dont_write_past_me_cy_7_))
+          (portref DI (instanceref f1_Msub_dont_write_past_me_cy_8_))
+          (portref DI (instanceref f1_Msub_dont_write_past_me_cy_9_))
+          (portref DI (instanceref f1_Msub_dont_write_past_me_cy_10_))
+          (portref DI (instanceref f1_Msub_dont_write_past_me_cy_11_))
+          (portref DI (instanceref f1_Mcount_wr_addr_cy_0_))
+          (portref DI (instanceref f1_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref f1_Mcompar_becoming_full_cy_0_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_cy_0_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_xor_0_))
+          (portref DI (instanceref f0_Msub_dont_write_past_me_cy_2_))
+          (portref DI (instanceref f0_Msub_dont_write_past_me_cy_3_))
+          (portref DI (instanceref f0_Msub_dont_write_past_me_cy_4_))
+          (portref DI (instanceref f0_Msub_dont_write_past_me_cy_5_))
+          (portref DI (instanceref f0_Msub_dont_write_past_me_cy_6_))
+          (portref DI (instanceref f0_Msub_dont_write_past_me_cy_7_))
+          (portref DI (instanceref f0_Msub_dont_write_past_me_cy_8_))
+          (portref DI (instanceref f0_Msub_dont_write_past_me_cy_9_))
+          (portref DI (instanceref f0_Msub_dont_write_past_me_cy_10_))
+          (portref DI (instanceref f0_Msub_dont_write_past_me_cy_11_))
+          (portref DI (instanceref f0_Mcount_wr_addr_cy_0_))
+          (portref DI (instanceref f0_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref f0_Mcompar_becoming_full_cy_0_))
+          (portref I (instanceref codec_enable_OBUF))
+          (portref I (instanceref codec_reset_OBUF))
+          (portref I (instanceref FX3_EXTINT_OBUF))
+          (portref I (instanceref LED_RX1_OBUF))
+          (portref I (instanceref LED_RX2_OBUF))
+          (portref I (instanceref LED_TXRX1_RX_OBUF))
+          (portref I (instanceref LED_TXRX1_TX_OBUF))
+          (portref I (instanceref LED_TXRX2_RX_OBUF))
+          (portref I (instanceref LED_TXRX2_TX_OBUF))
+          (portref I (instanceref SFDX1_RX_OBUF))
+          (portref I (instanceref SFDX1_TX_OBUF))
+          (portref I (instanceref SFDX2_RX_OBUF))
+          (portref I (instanceref SFDX2_TX_OBUF))
+          (portref I (instanceref SRX1_RX_OBUF))
+          (portref I (instanceref SRX1_TX_OBUF))
+          (portref I (instanceref SRX2_RX_OBUF))
+          (portref I (instanceref SRX2_TX_OBUF))
+          (portref I (instanceref tx_enable1_OBUF))
+          (portref I (instanceref tx_enable2_OBUF))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy1))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy))
+          (portref DI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_))
+          (portref DI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          (portref DI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          (portref DI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          (portref DI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          (portref DI (instanceref f1__n0161_inv1_cy1))
+          (portref DI (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_))
+          (portref DI (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          (portref DI (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          (portref DI (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          (portref DI (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          (portref DI (instanceref f0__n0161_inv1_cy1))
+          (portref (member DIBDI 15) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref ENAWREN (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 29) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 28) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 22) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 21) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 19) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 18) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 17) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 29) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 28) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 22) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 21) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 19) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 18) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 17) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 16) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIPB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIPB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 29) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 28) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 22) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 21) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 19) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 18) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 17) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 16) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 15) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 14) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 13) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIPB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
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+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
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+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
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+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
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+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
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+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
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+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
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+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
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+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
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+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref (member DIBDI 15) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref ENAWREN (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 29) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 28) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 22) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 21) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 19) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 18) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 17) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 16) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 15) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 14) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 13) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIPB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 29) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 28) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 22) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 21) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 19) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 18) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 17) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 16) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
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+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member DIB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
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+          (portref (member DIB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
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+          (portref (member DIB 18) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member DIB 17) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref ENA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member DIBDI 15) (instanceref f1_ram_Mram_ram33))
+          (portref ENAWREN (instanceref f1_ram_Mram_ram33))
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+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram27))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram27))
+          (portref ENA (instanceref f1_ram_Mram_ram27))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram29))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram29))
+          (portref ENA (instanceref f1_ram_Mram_ram29))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram25))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram25))
+          (portref ENA (instanceref f1_ram_Mram_ram25))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram24))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram24))
+          (portref ENA (instanceref f1_ram_Mram_ram24))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram26))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram26))
+          (portref ENA (instanceref f1_ram_Mram_ram26))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram22))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram22))
+          (portref ENA (instanceref f1_ram_Mram_ram22))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram21))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram21))
+          (portref ENA (instanceref f1_ram_Mram_ram21))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram23))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram23))
+          (portref ENA (instanceref f1_ram_Mram_ram23))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram19))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram19))
+          (portref ENA (instanceref f1_ram_Mram_ram19))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram18))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram18))
+          (portref ENA (instanceref f1_ram_Mram_ram18))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram20))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram20))
+          (portref ENA (instanceref f1_ram_Mram_ram20))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram16))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram16))
+          (portref ENA (instanceref f1_ram_Mram_ram16))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram15))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram15))
+          (portref ENA (instanceref f1_ram_Mram_ram15))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram17))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram17))
+          (portref ENA (instanceref f1_ram_Mram_ram17))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram14))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram14))
+          (portref ENA (instanceref f1_ram_Mram_ram14))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram13))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram13))
+          (portref ENA (instanceref f1_ram_Mram_ram13))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram12))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram12))
+          (portref ENA (instanceref f1_ram_Mram_ram12))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram11))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram11))
+          (portref ENA (instanceref f1_ram_Mram_ram11))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram9))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram9))
+          (portref ENA (instanceref f1_ram_Mram_ram9))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram8))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram8))
+          (portref ENA (instanceref f1_ram_Mram_ram8))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram10))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram10))
+          (portref ENA (instanceref f1_ram_Mram_ram10))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram6))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram6))
+          (portref ENA (instanceref f1_ram_Mram_ram6))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram5))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram5))
+          (portref ENA (instanceref f1_ram_Mram_ram5))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram7))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram7))
+          (portref ENA (instanceref f1_ram_Mram_ram7))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram3))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram3))
+          (portref ENA (instanceref f1_ram_Mram_ram3))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram2))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram2))
+          (portref ENA (instanceref f1_ram_Mram_ram2))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram4))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram4))
+          (portref ENA (instanceref f1_ram_Mram_ram4))
+          (portref (member DIB 31) (instanceref f1_ram_Mram_ram1))
+          (portref (member DIB 30) (instanceref f1_ram_Mram_ram1))
+          (portref ENA (instanceref f1_ram_Mram_ram1))
+          (portref (member DIBDI 15) (instanceref f0_ram_Mram_ram33))
+          (portref ENAWREN (instanceref f0_ram_Mram_ram33))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram31))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram31))
+          (portref ENA (instanceref f0_ram_Mram_ram31))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram30))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram30))
+          (portref ENA (instanceref f0_ram_Mram_ram30))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram32))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram32))
+          (portref ENA (instanceref f0_ram_Mram_ram32))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram28))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram28))
+          (portref ENA (instanceref f0_ram_Mram_ram28))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram27))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram27))
+          (portref ENA (instanceref f0_ram_Mram_ram27))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram29))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram29))
+          (portref ENA (instanceref f0_ram_Mram_ram29))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram25))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram25))
+          (portref ENA (instanceref f0_ram_Mram_ram25))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram24))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram24))
+          (portref ENA (instanceref f0_ram_Mram_ram24))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram26))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram26))
+          (portref ENA (instanceref f0_ram_Mram_ram26))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram22))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram22))
+          (portref ENA (instanceref f0_ram_Mram_ram22))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram21))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram21))
+          (portref ENA (instanceref f0_ram_Mram_ram21))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram23))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram23))
+          (portref ENA (instanceref f0_ram_Mram_ram23))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram19))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram19))
+          (portref ENA (instanceref f0_ram_Mram_ram19))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram18))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram18))
+          (portref ENA (instanceref f0_ram_Mram_ram18))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram20))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram20))
+          (portref ENA (instanceref f0_ram_Mram_ram20))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram16))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram16))
+          (portref ENA (instanceref f0_ram_Mram_ram16))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram15))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram15))
+          (portref ENA (instanceref f0_ram_Mram_ram15))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram17))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram17))
+          (portref ENA (instanceref f0_ram_Mram_ram17))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram14))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram14))
+          (portref ENA (instanceref f0_ram_Mram_ram14))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram13))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram13))
+          (portref ENA (instanceref f0_ram_Mram_ram13))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram12))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram12))
+          (portref ENA (instanceref f0_ram_Mram_ram12))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram11))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram11))
+          (portref ENA (instanceref f0_ram_Mram_ram11))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram9))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram9))
+          (portref ENA (instanceref f0_ram_Mram_ram9))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram8))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram8))
+          (portref ENA (instanceref f0_ram_Mram_ram8))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram10))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram10))
+          (portref ENA (instanceref f0_ram_Mram_ram10))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram6))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram6))
+          (portref ENA (instanceref f0_ram_Mram_ram6))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram5))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram5))
+          (portref ENA (instanceref f0_ram_Mram_ram5))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram7))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram7))
+          (portref ENA (instanceref f0_ram_Mram_ram7))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram3))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram3))
+          (portref ENA (instanceref f0_ram_Mram_ram3))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram2))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram2))
+          (portref ENA (instanceref f0_ram_Mram_ram2))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram4))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram4))
+          (portref ENA (instanceref f0_ram_Mram_ram4))
+          (portref (member DIB 31) (instanceref f0_ram_Mram_ram1))
+          (portref (member DIB 30) (instanceref f0_ram_Mram_ram1))
+          (portref ENA (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr[7]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_i_tvalid_int "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/i_tvalid_int") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_write1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt__n0074_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr[8]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata110))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata210))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata33))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata41))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata51))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata61))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata71))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata81))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata91))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata101))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata111))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata121))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata131))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata141))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata151))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata161))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata171))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata181))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata191))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata201))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata211))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata221))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata231))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata241))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata251))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata261))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata271))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata281))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata291))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata301))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata311))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata321))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_o_tlast1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_i_tready1))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121221 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0121221") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[10]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_10_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_10_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_10_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[11]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_11_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_11_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_11_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_0_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata110))
+          (portref (member din 71) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[12]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_12_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_12_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_1_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata121))
+          (portref (member din 70) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f0_Mcompar_becoming_full_lut_0_ "f0/Mcompar_becoming_full_lut[0]") (joined
+          (portref O (instanceref f0_Mcompar_becoming_full_lut_0_))
+          (portref S (instanceref f0_Mcompar_becoming_full_cy_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_2_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata231))
+          (portref (member din 69) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2-In") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1))
+          )
+         )
+         (net gps_ref_enable (joined
+          (portref O (instanceref gps_ref_enable_OBUF))
+          (portref gps_ref_enable)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<4>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net (rename f0_Mcompar_becoming_full_lut_1_ "f0/Mcompar_becoming_full_lut[1]") (joined
+          (portref O (instanceref f0_Mcompar_becoming_full_lut_1_))
+          (portref S (instanceref f0_Mcompar_becoming_full_cy_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_3_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata261))
+          (portref (member din 68) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f0_Mcompar_becoming_full_lut_2_ "f0/Mcompar_becoming_full_lut[2]") (joined
+          (portref O (instanceref f0_Mcompar_becoming_full_lut_2_))
+          (portref S (instanceref f0_Mcompar_becoming_full_cy_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_4_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata271))
+          (portref (member din 67) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net tx_codec_d_0_OBUF (joined
+          (portref Q (instanceref catgen_gen_pins_0__oddr2))
+          (portref I (instanceref tx_codec_d_0_OBUF))
+          )
+         )
+         (net (rename f0_Mcompar_becoming_full_lut_3_ "f0/Mcompar_becoming_full_lut[3]") (joined
+          (portref O (instanceref f0_Mcompar_becoming_full_lut_3_))
+          (portref S (instanceref f0_Mcompar_becoming_full_cy_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_5_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata281))
+          (portref (member din 66) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f0_Mcompar_becoming_full_lut_4_ "f0/Mcompar_becoming_full_lut[4]") (joined
+          (portref O (instanceref f0_Mcompar_becoming_full_lut_4_))
+          (portref S (instanceref f0_Mcompar_becoming_full_cy_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_6_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata291))
+          (portref (member din 65) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f1_full_reg_glue_set "f1/full_reg_glue_set") (joined
+          (portref D (instanceref f1_full_reg))
+          (portref O (instanceref f1_full_reg_glue_set))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_7_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata301))
+          (portref (member din 64) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f0_Result_8_2_FRB "f0/Result<8>2_FRB") (joined
+          (portref D (instanceref f0_wr_addr_8))
+          (portref Q (instanceref f0_Result_8_2_FRB))
+          (portref I0 (instanceref f0_Mcount_wr_addr_cy_8__rt))
+          )
+         )
+         (net tx_frame_p (joined
+          (portref O (instanceref tx_frame_p_OBUF))
+          (portref tx_frame_p)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_8_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata311))
+          (portref (member din 63) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In11") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In12") (joined
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1))
+          (portref rd_en (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_9_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[9]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata321))
+          (portref (member din 62) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In31") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In32") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB0") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_))
+          )
+         )
+         (net (rename f0_Result_10_1_FRB "f0/Result<10>1_FRB") (joined
+          (portref D (instanceref f0_rd_addr_10))
+          (portref Q (instanceref f0_Result_10_1_FRB))
+          (portref I0 (instanceref f0_Mcount_rd_addr_cy_10__rt))
+          (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_10__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<10>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_10_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[2]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_2_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_EP_READY1 "slave_fifo32/EP_READY1") (joined
+          (portref Q (instanceref slave_fifo32_EP_READY1))
+          (portref I (instanceref debug_24_OBUF))
+          )
+         )
+         (net (rename f1_read_state_FSM_FFd2_In "f1/read_state_FSM_FFd2-In") (joined
+          (portref D (instanceref f1_read_state_FSM_FFd2))
+          (portref O (instanceref f1_read_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[3]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_3_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[4]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_4_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[5]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_5_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[6]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_6_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0))
+          )
+         )
+         (net (rename f1_Result_6_1_FRB "f1/Result<6>1_FRB") (joined
+          (portref D (instanceref f1_rd_addr_6))
+          (portref Q (instanceref f1_Result_6_1_FRB))
+          (portref I0 (instanceref f1_Mcount_rd_addr_cy_6__rt))
+          (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_6__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[7]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_7_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[8]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_8_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr8_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_8))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[9]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0))
+          )
+         )
+         (net tx_codec_d_2_OBUF (joined
+          (portref Q (instanceref catgen_gen_pins_2__oddr2))
+          (portref I (instanceref tx_codec_d_2_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr3_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_3))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr3_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0154_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0154_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0154_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15_))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_0__inv1_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_0_11_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv31))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_write1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_write_AND_42_o_inv2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+          )
+         )
+         (net (rename f1_becoming_full "f1/becoming_full") (joined
+          (portref O (instanceref f1_Mcompar_becoming_full_cy_4_))
+          (portref I1 (instanceref f1_full_reg_glue_set))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0_ "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_36__srlc32e))
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+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e))
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+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref (member A 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_2_11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_1_11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_3_11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_4_11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_SW1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_0_11_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a[3]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e))
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+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e))
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+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e))
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+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e))
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+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e))
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+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e))
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+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e))
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+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref (member A 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_14_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1_ "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e))
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+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_20__srlc32e))
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+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_30__srlc32e))
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+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref (member A 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_2_11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_1_11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_3_11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_4_11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT821 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT821") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a[4]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4))
+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e))
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+          (portref (member A 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2_ "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2))
+          (portref (member A 2) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e))
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+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net (rename gpif_sync_reset_int "gpif_sync/reset_int") (joined
+          (portref Q (instanceref gpif_sync_reset_int))
+          (portref D (instanceref gpif_sync_reset_out))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0003_0_ "slave_fifo32/fifo64_to_gpmc32_rx/n0003[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata110))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr1_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_1))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr1_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__rt))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0003_1_ "slave_fifo32/fifo64_to_gpmc32_rx/n0003[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata121))
+          )
+         )
+         (net (rename f1_Result_4_2_FRB "f1/Result<4>2_FRB") (joined
+          (portref D (instanceref f1_wr_addr_4))
+          (portref Q (instanceref f1_Result_4_2_FRB))
+          (portref I0 (instanceref f1_Mcount_wr_addr_cy_4__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0003_2_ "slave_fifo32/fifo64_to_gpmc32_rx/n0003[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata231))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0003_3_ "slave_fifo32/fifo64_to_gpmc32_rx/n0003[3]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata261))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr6_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_6))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_31_rstpot "slave_fifo32/gpif_data_out_31_rstpot") (joined
+          (portref O (instanceref slave_fifo32_gpif_data_out_31_rstpot))
+          (portref D (instanceref slave_fifo32_gpif_data_out_31_1))
+          (portref D (instanceref slave_fifo32_gpif_data_out_31))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421_FRB") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0003_4_ "slave_fifo32/fifo64_to_gpmc32_rx/n0003[4]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata271))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0003_5_ "slave_fifo32/fifo64_to_gpmc32_rx/n0003[5]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata281))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0003_6_ "slave_fifo32/fifo64_to_gpmc32_rx/n0003[6]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata291))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0003_7_ "slave_fifo32/fifo64_to_gpmc32_rx/n0003[7]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata301))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0003_8_ "slave_fifo32/fifo64_to_gpmc32_rx/n0003[8]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata311))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0003_9_ "slave_fifo32/fifo64_to_gpmc32_rx/n0003[9]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata321))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__0_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][0]") (joined
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 71) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__1_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][1]") (joined
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 70) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+          )
+         )
+         (net (rename f0_wr_addr_10_ "f0/wr_addr[10]") (joined
+          (portref Q (instanceref f0_wr_addr_10))
+          (portref I3 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref I2 (instanceref f0_Mcompar_becoming_full_lut_3_))
+          (portref (member ADDRAWRADDR 2) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__2_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][2]") (joined
+          (portref (member DOB 29) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 69) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f0_wr_addr_11_ "f0/wr_addr[11]") (joined
+          (portref Q (instanceref f0_wr_addr_11))
+          (portref I5 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref I4 (instanceref f0_Mcompar_becoming_full_lut_3_))
+          (portref (member ADDRAWRADDR 1) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_slrd2_1 "slave_fifo32/slrd2_1") (joined
+          (portref Q (instanceref slave_fifo32_slrd2_1))
+          (portref D (instanceref slave_fifo32_slrd3))
+          (portref (member DIPA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIPA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__3_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][3]") (joined
+          (portref (member DOB 28) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 68) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f0_wr_addr_12_ "f0/wr_addr[12]") (joined
+          (portref Q (instanceref f0_wr_addr_12))
+          (portref I1 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_))
+          (portref I0 (instanceref f0_Mcompar_becoming_full_lut_4_))
+          (portref (member ADDRAWRADDR 0) (instanceref f0_ram_Mram_ram33))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram31))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram30))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram32))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram28))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram27))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram29))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram25))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram24))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram26))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram22))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram21))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram23))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram19))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram18))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram20))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram16))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram15))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram17))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram14))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram13))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram12))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram11))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram9))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram8))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram10))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram6))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram5))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram7))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram3))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram2))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram4))
+          (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__4_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][4]") (joined
+          (portref (member DOB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 67) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__5_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][5]") (joined
+          (portref (member DOB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 66) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr7_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__6_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][6]") (joined
+          (portref (member DOB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 65) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__7_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][7]") (joined
+          (portref (member DOB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 64) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__8_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][8]") (joined
+          (portref (member DOB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 63) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net tx_codec_d_6_OBUF (joined
+          (portref Q (instanceref catgen_gen_pins_6__oddr2))
+          (portref I (instanceref tx_codec_d_6_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__9_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][9]") (joined
+          (portref (member DOB 22) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 62) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_lut_10_ "f1/Msub_dont_write_past_me_lut[10]") (joined
+          (portref S (instanceref f1_Msub_dont_write_past_me_cy_10_))
+          (portref LI (instanceref f1_Msub_dont_write_past_me_xor_10_))
+          (portref O (instanceref f1_Msub_dont_write_past_me_lut_10__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int11") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int14") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_lut_11_ "f1/Msub_dont_write_past_me_lut[11]") (joined
+          (portref S (instanceref f1_Msub_dont_write_past_me_cy_11_))
+          (portref LI (instanceref f1_Msub_dont_write_past_me_xor_11_))
+          (portref O (instanceref f1_Msub_dont_write_past_me_lut_11__INV_0))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_lut_12_ "f1/Msub_dont_write_past_me_lut[12]") (joined
+          (portref LI (instanceref f1_Msub_dont_write_past_me_xor_12_))
+          (portref O (instanceref f1_Msub_dont_write_past_me_lut_12__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2_))
+          )
+         )
+         (net (rename tx_codec_d_10_ "tx_codec_d[10]") (joined
+          (portref O (instanceref tx_codec_d_10_OBUF))
+          (portref (member tx_codec_d 1))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_xor_12__rt "f0/Mcount_rd_addr_xor<12>_rt") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_xor_12__rt))
+          (portref LI (instanceref f0_Mcount_rd_addr_xor_12_))
+          )
+         )
+         (net (rename n0035_0_ "n0035[0]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_o_tready_int "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/o_tready_int") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1))
+          )
+         )
+         (net (rename tx_codec_d_11_ "tx_codec_d[11]") (joined
+          (portref O (instanceref tx_codec_d_11_OBUF))
+          (portref (member tx_codec_d 0))
+          )
+         )
+         (net (rename n0035_1_ "n0035[1]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst))
+          )
+         )
+         (net (rename n0035_2_ "n0035[2]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[0]") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0_))
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0))
+          (portref (member dout 71) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename n0035_3_ "n0035[3]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[1]") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1_))
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1))
+          (portref (member dout 70) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename n0035_4_ "n0035[4]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram3))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[2]") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2_))
+          (portref (member DIA 29) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 69) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename n0035_5_ "n0035[5]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram3))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[3]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3_))
+          (portref (member DIA 28) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 68) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename n0035_6_ "n0035[6]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o5") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[4]") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4_))
+          (portref (member DIA 27) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 67) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o7") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+          )
+         )
+         (net (rename n0035_7_ "n0035[7]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o8") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[5]") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5_))
+          (portref (member DIA 26) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F))
+          (portref (member dout 66) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net GPIF_CTL4_IBUF (joined
+          (portref D (instanceref slave_fifo32_EP_READY))
+          (portref O (instanceref GPIF_CTL4_IBUF))
+          )
+         )
+         (net (rename n0035_8_ "n0035[8]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref (member DOB 31) (instanceref f0_ram_Mram_ram5))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[6]") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6_))
+          (portref (member DIA 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F))
+          (portref (member dout 65) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename n0035_9_ "n0035[9]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref (member DOB 30) (instanceref f0_ram_Mram_ram5))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[7]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7_))
+          (portref (member DIA 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F))
+          (portref (member dout 64) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f0_becoming_full "f0/becoming_full") (joined
+          (portref O (instanceref f0_Mcompar_becoming_full_cy_4_))
+          (portref I1 (instanceref f0_full_reg_glue_set))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0144_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr2_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr4_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr5_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr7_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[8]") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8_))
+          (portref (member DIA 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61))
+          (portref (member dout 63) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[9]") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9_))
+          (portref (member DIA 22) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1))
+          (portref (member dout 62) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+          )
+         )
+         (net tx_codec_d_10_OBUF (joined
+          (portref Q (instanceref catgen_gen_pins_10__oddr2))
+          (portref I (instanceref tx_codec_d_10_OBUF))
+          )
+         )
+         (net (rename gpif_sync_reset_out "gpif_sync/reset_out") (joined
+          (portref Q (instanceref gpif_sync_reset_out))
+          (portref S (instanceref slave_fifo32_slwr))
+          (portref S (instanceref slave_fifo32_pktend))
+          (portref R (instanceref slave_fifo32_state_FSM_FFd2))
+          (portref R (instanceref slave_fifo32_state_FSM_FFd1))
+          (portref R (instanceref slave_fifo32_fifoadr_0))
+          (portref R (instanceref slave_fifo32_fifoadr_1))
+          (portref R (instanceref slave_fifo32_idle_cycles_0))
+          (portref R (instanceref slave_fifo32_idle_cycles_1))
+          (portref R (instanceref slave_fifo32_idle_cycles_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_5))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_6))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_7))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_8))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_9))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_10))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_11))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_12))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_5))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_6))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_7))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_8))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_9))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_10))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_11))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_12))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_5))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_6))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_7))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_8))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_5))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_6))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_7))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_8))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_9))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_0))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_2))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_3))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_4))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_5))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_6))
+          (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_7))
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+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_1_ "f0/Mcount_wr_addr_cy[1]") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_1_))
+          (portref CI (instanceref f0_Mcount_wr_addr_cy_2_))
+          (portref CI (instanceref f0_Mcount_wr_addr_xor_2_))
+          )
+         )
+         (net (rename f0_rd_addr_12__wr_addr_12__equal_11_o "f0/rd_addr[12]_wr_addr[12]_equal_11_o") (joined
+          (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_))
+          (portref CI (instanceref f0__n0161_inv1_cy))
+          (portref I2 (instanceref f0_read_state_FSM_FFd1_In111))
+          (portref I1 (instanceref f0_read_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_2_ "f0/Mcount_wr_addr_cy[2]") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_2_))
+          (portref CI (instanceref f0_Mcount_wr_addr_cy_3_))
+          (portref CI (instanceref f0_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_3_ "f0/Mcount_wr_addr_cy[3]") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_3_))
+          (portref CI (instanceref f0_Mcount_wr_addr_cy_4_))
+          (portref CI (instanceref f0_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_2__rt "f0/Mcount_rd_addr_cy<2>_rt") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_2__rt))
+          (portref S (instanceref f0_Mcount_rd_addr_cy_2_))
+          (portref LI (instanceref f0_Mcount_rd_addr_xor_2_))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_0_ "f1/Mcount_wr_addr_cy[0]") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_0_))
+          (portref CI (instanceref f1_Mcount_wr_addr_cy_1_))
+          (portref CI (instanceref f1_Mcount_wr_addr_xor_1_))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_4_ "f0/Mcount_wr_addr_cy[4]") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_4_))
+          (portref CI (instanceref f0_Mcount_wr_addr_cy_5_))
+          (portref CI (instanceref f0_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_1_ "f1/Mcount_wr_addr_cy[1]") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_1_))
+          (portref CI (instanceref f1_Mcount_wr_addr_cy_2_))
+          (portref CI (instanceref f1_Mcount_wr_addr_xor_2_))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_5_ "f0/Mcount_wr_addr_cy[5]") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_5_))
+          (portref CI (instanceref f0_Mcount_wr_addr_cy_6_))
+          (portref CI (instanceref f0_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_2_ "f1/Mcount_wr_addr_cy[2]") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_2_))
+          (portref CI (instanceref f1_Mcount_wr_addr_cy_3_))
+          (portref CI (instanceref f1_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_6_ "f0/Mcount_wr_addr_cy[6]") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_6_))
+          (portref CI (instanceref f0_Mcount_wr_addr_cy_7_))
+          (portref CI (instanceref f0_Mcount_wr_addr_xor_7_))
+          )
+         )
+         (net (rename n0036_0_ "n0036[0]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_3_ "f1/Mcount_wr_addr_cy[3]") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_3_))
+          (portref CI (instanceref f1_Mcount_wr_addr_cy_4_))
+          (portref CI (instanceref f1_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_cy_0_ "f1/Msub_dont_write_past_me_cy[0]") (joined
+          (portref O (instanceref f1_Msub_dont_write_past_me_cy_0_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_cy_1_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_xor_1_))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_7_ "f0/Mcount_wr_addr_cy[7]") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_7_))
+          (portref CI (instanceref f0_Mcount_wr_addr_cy_8_))
+          (portref CI (instanceref f0_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net (rename n0036_1_ "n0036[1]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_4_ "f1/Mcount_wr_addr_cy[4]") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_4_))
+          (portref CI (instanceref f1_Mcount_wr_addr_cy_5_))
+          (portref CI (instanceref f1_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_cy_1_ "f1/Msub_dont_write_past_me_cy[1]") (joined
+          (portref O (instanceref f1_Msub_dont_write_past_me_cy_1_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_cy_2_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_xor_2_))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_8_ "f0/Mcount_wr_addr_cy[8]") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_8_))
+          (portref CI (instanceref f0_Mcount_wr_addr_cy_9_))
+          (portref CI (instanceref f0_Mcount_wr_addr_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_0_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[0]") (joined
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 71) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename n0036_2_ "n0036[2]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram2))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_5_ "f1/Mcount_wr_addr_cy[5]") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_5_))
+          (portref CI (instanceref f1_Mcount_wr_addr_cy_6_))
+          (portref CI (instanceref f1_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_cy_2_ "f1/Msub_dont_write_past_me_cy[2]") (joined
+          (portref O (instanceref f1_Msub_dont_write_past_me_cy_2_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_cy_3_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6_))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_9_ "f0/Mcount_wr_addr_cy[9]") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_9_))
+          (portref CI (instanceref f0_Mcount_wr_addr_cy_10_))
+          (portref CI (instanceref f0_Mcount_wr_addr_xor_10_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_1_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[1]") (joined
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 70) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename n0036_3_ "n0036[3]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram2))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_6_ "f1/Mcount_wr_addr_cy[6]") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_6_))
+          (portref CI (instanceref f1_Mcount_wr_addr_cy_7_))
+          (portref CI (instanceref f1_Mcount_wr_addr_xor_7_))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_cy_3_ "f1/Msub_dont_write_past_me_cy[3]") (joined
+          (portref O (instanceref f1_Msub_dont_write_past_me_cy_3_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_cy_4_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_2_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[2]") (joined
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 69) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename n0036_4_ "n0036[4]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram3))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_7_ "f1/Mcount_wr_addr_cy[7]") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_7_))
+          (portref CI (instanceref f1_Mcount_wr_addr_cy_8_))
+          (portref CI (instanceref f1_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_cy_4_ "f1/Msub_dont_write_past_me_cy[4]") (joined
+          (portref O (instanceref f1_Msub_dont_write_past_me_cy_4_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_cy_5_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_xor_5_))
+          )
+         )
+         (net (rename gen_clks_clkfx "gen_clks/clkfx") (joined
+          (portref I (instanceref gen_clks_clkout3_buf))
+          (portref I (instanceref gen_clks_clkout2_buf))
+          (portref CLKFX (instanceref gen_clks_dcm_sp_inst))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_3_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[3]") (joined
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member dout 68) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv3") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214))
+          )
+         )
+         (net (rename n0036_5_ "n0036[5]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram3))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_8_ "f1/Mcount_wr_addr_cy[8]") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_8_))
+          (portref CI (instanceref f1_Mcount_wr_addr_cy_9_))
+          (portref CI (instanceref f1_Mcount_wr_addr_xor_9_))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_cy_5_ "f1/Msub_dont_write_past_me_cy[5]") (joined
+          (portref O (instanceref f1_Msub_dont_write_past_me_cy_5_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_cy_6_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_4_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[4]") (joined
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member dout 67) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename n0036_6_ "n0036[6]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram4))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_9_ "f1/Mcount_wr_addr_cy[9]") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_9_))
+          (portref CI (instanceref f1_Mcount_wr_addr_cy_10_))
+          (portref CI (instanceref f1_Mcount_wr_addr_xor_10_))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_cy_6_ "f1/Msub_dont_write_past_me_cy[6]") (joined
+          (portref O (instanceref f1_Msub_dont_write_past_me_cy_6_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_cy_7_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[10]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_10_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref (member ADDRBRDADDR 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_5_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[5]") (joined
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref (member dout 66) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename n0036_7_ "n0036[7]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram4))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_cy_7_ "f1/Msub_dont_write_past_me_cy[7]") (joined
+          (portref O (instanceref f1_Msub_dont_write_past_me_cy_7_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_cy_8_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[11]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_11_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref (member ADDRBRDADDR 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_6_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[6]") (joined
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member dout 65) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename n0036_8_ "n0036[8]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref (member DOB 31) (instanceref f1_ram_Mram_ram5))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_cy_8_ "f1/Msub_dont_write_past_me_cy[8]") (joined
+          (portref O (instanceref f1_Msub_dont_write_past_me_cy_8_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_cy_9_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_Result_0_ "slave_fifo32/Result[0]") (joined
+          (portref D (instanceref slave_fifo32_fifoadr_0))
+          (portref D (instanceref slave_fifo32_fifoadr_0_1))
+          (portref O (instanceref slave_fifo32_Mcount_fifoadr_xor_0_11_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[12]") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_12_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_))
+          (portref (member ADDRBRDADDR 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_7_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[7]") (joined
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref (member dout 64) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename n0036_9_ "n0036[9]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref (member DOB 30) (instanceref f1_ram_Mram_ram5))
+          )
+         )
+         (net (rename f1_Msub_dont_write_past_me_cy_9_ "f1/Msub_dont_write_past_me_cy[9]") (joined
+          (portref O (instanceref f1_Msub_dont_write_past_me_cy_9_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_cy_10_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_xor_10_))
+          )
+         )
+         (net (rename slave_fifo32_Result_1_ "slave_fifo32/Result[1]") (joined
+          (portref D (instanceref slave_fifo32_fifoadr_1))
+          (portref O (instanceref slave_fifo32_Mcount_fifoadr_xor_1_11))
+          (portref D (instanceref slave_fifo32_fifoadr_1_1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_8_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[8]") (joined
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member dout 63) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_9_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[9]") (joined
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref (member dout 62) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr10_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr10_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_10))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr10_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_1__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<1>_FRB") (joined
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_1__FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0_lut") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_3__rt "f1/Mcount_wr_addr_cy<3>_rt") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_3__rt))
+          (portref S (instanceref f1_Mcount_wr_addr_cy_3_))
+          (portref LI (instanceref f1_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[10]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_11_))
+          )
+         )
+         (net (rename f0_Result_12_1_FRB "f0/Result<12>1_FRB") (joined
+          (portref D (instanceref f0_rd_addr_12))
+          (portref Q (instanceref f0_Result_12_1_FRB))
+          (portref I0 (instanceref f0_Mcount_rd_addr_xor_12__rt))
+          (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_12__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[11]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_12_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In1") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_0))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__rt))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tlast "slave_fifo32/ctrl_rx_tlast") (joined
+          (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1))
+          (portref (member DOB 17) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref I1 (instanceref slave_fifo32_state_FSM_FFd1_In2))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1))
+          )
+         )
+         (net (rename f1_Result_8_1_FRB "f1/Result<8>1_FRB") (joined
+          (portref D (instanceref f1_rd_addr_8))
+          (portref Q (instanceref f1_Result_8_1_FRB))
+          (portref I0 (instanceref f1_Mcount_rd_addr_cy_8__rt))
+          (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_8__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_0_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata110))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[10]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_1_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata121))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[11]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_BRB1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_2_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata231))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<6>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[12]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_3__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<3>_FRB") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_3__FRB))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_10_ "slave_fifo32/gpif_data_in[10]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_10))
+          (portref D (instanceref slave_fifo32_debug1_10))
+          (portref (member DIA 21) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 21) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_3_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[3]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata261))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[13]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_11_ "slave_fifo32/gpif_data_in[11]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_11))
+          (portref D (instanceref slave_fifo32_debug1_11))
+          (portref (member DIA 20) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 20) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_4_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[4]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata271))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[14]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_14_BRB1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<5>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_12_ "slave_fifo32/gpif_data_in[12]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_12))
+          (portref D (instanceref slave_fifo32_debug1_12))
+          (portref (member DIA 19) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 19) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_5_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[5]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata281))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_15_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[15]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15_BRB1))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_13_ "slave_fifo32/gpif_data_in[13]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_13))
+          (portref D (instanceref slave_fifo32_debug1_13))
+          (portref (member DIA 18) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 18) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_6_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[6]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata291))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_14_ "slave_fifo32/gpif_data_in[14]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_14))
+          (portref D (instanceref slave_fifo32_debug1_14))
+          (portref (member DIA 17) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 17) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_7_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[7]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata301))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_20_ "slave_fifo32/gpif_data_in[20]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_20))
+          (portref (member DIA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_15_ "slave_fifo32/gpif_data_in[15]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_15))
+          (portref D (instanceref slave_fifo32_debug1_15))
+          (portref (member DIA 16) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 16) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_8_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[8]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata311))
+          )
+         )
+         (net (rename f0_Mcompar_becoming_full_cy_0_ "f0/Mcompar_becoming_full_cy[0]") (joined
+          (portref O (instanceref f0_Mcompar_becoming_full_cy_0_))
+          (portref CI (instanceref f0_Mcompar_becoming_full_cy_1_))
+          )
+         )
+         (net (rename slave_fifo32__n0237_inv "slave_fifo32/_n0237_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifoadr_0))
+          (portref CE (instanceref slave_fifo32_fifoadr_1))
+          (portref O (instanceref slave_fifo32__n0237_inv1))
+          (portref CE (instanceref slave_fifo32_fifoadr_1_1))
+          (portref CE (instanceref slave_fifo32_fifoadr_0_1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0121211 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121211") (joined
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_21_ "slave_fifo32/gpif_data_in[21]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_21))
+          (portref (member DIA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_16_ "slave_fifo32/gpif_data_in[16]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_16))
+          (portref (member DIA 15) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 15) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_9_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[9]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata321))
+          )
+         )
+         (net (rename f0_Mcompar_becoming_full_cy_1_ "f0/Mcompar_becoming_full_cy[1]") (joined
+          (portref O (instanceref f0_Mcompar_becoming_full_cy_1_))
+          (portref CI (instanceref f0_Mcompar_becoming_full_cy_2_))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_22_ "slave_fifo32/gpif_data_in[22]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_22))
+          (portref (member DIA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_17_ "slave_fifo32/gpif_data_in[17]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_17))
+          (portref (member DIA 14) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 14) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename f0_Mcompar_becoming_full_cy_2_ "f0/Mcompar_becoming_full_cy[2]") (joined
+          (portref O (instanceref f0_Mcompar_becoming_full_cy_2_))
+          (portref CI (instanceref f0_Mcompar_becoming_full_cy_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines321 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines321") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_1_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_18_ "slave_fifo32/gpif_data_in[18]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_18))
+          (portref (member DIA 13) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 13) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_23_ "slave_fifo32/gpif_data_in[23]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_23))
+          (portref (member DIA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines322 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines322") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_2_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2))
+          )
+         )
+         (net (rename f0_Mcompar_becoming_full_cy_3_ "f0/Mcompar_becoming_full_cy[3]") (joined
+          (portref O (instanceref f0_Mcompar_becoming_full_cy_3_))
+          (portref CI (instanceref f0_Mcompar_becoming_full_cy_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines323 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines323") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_3_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines324 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines324") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_4_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines325 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines325") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_5_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines326 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines326") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_6_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_19_ "slave_fifo32/gpif_data_in[19]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_19))
+          (portref (member DIA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_24_ "slave_fifo32/gpif_data_in[24]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_24))
+          (portref (member DIA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines327 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines327") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_7_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[10]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_11_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines328 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines328") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_8_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines329 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines329") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_9_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_25_ "slave_fifo32/gpif_data_in[25]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_25))
+          (portref (member DIA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_30_ "slave_fifo32/gpif_data_in[30]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_30))
+          (portref (member DIA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[11]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_12_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_12_))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_26_ "slave_fifo32/gpif_data_in[26]") (joined
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+          (portref (member DIA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
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+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr9_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_9))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[10]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full621_FRB") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[2]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[11]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[3]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[12]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_4))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[4]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51))
+          )
+         )
+         (net (rename f0_Result_1_1_FRB "f0/Result<1>1_FRB") (joined
+          (portref D (instanceref f0_rd_addr_1))
+          (portref Q (instanceref f0_Result_1_1_FRB))
+          (portref I0 (instanceref f0_Mcount_rd_addr_cy_1__rt))
+          (portref I0 (instanceref f0_Msub_dont_write_past_me_cy_1__rt))
+          )
+         )
+         (net FX3_EXTINT (joined
+          (portref O (instanceref FX3_EXTINT_OBUF))
+          (portref FX3_EXTINT)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01216))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[13]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111))
+          (portref I0 (instanceref f0__n0161_inv1_lut))
+          (portref I1 (instanceref f0_GND_14_o_read_OR_37_o1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_write1))
+          (portref I1 (instanceref f0_read_state_FSM_FFd1_In111))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst))
+          (portref I2 (instanceref f0_read_state_FSM_FFd2_In1))
+          (portref I2 (instanceref f0_full_reg_glue_set))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[5]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full921))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[14]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_10_ "slave_fifo32/ctrl_rx_tdata[10]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210))
+          (portref (member DOB 21) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[6]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_2))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[15]") (joined
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[0]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_11_ "slave_fifo32/ctrl_rx_tdata[11]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33))
+          (portref (member DOB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[7]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[3]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_3))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[1]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_12_ "slave_fifo32/ctrl_rx_tdata[12]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT41))
+          (portref (member DOB 19) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[4]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_4))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[2]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0154_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_11))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_13_ "slave_fifo32/ctrl_rx_tdata[13]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT51))
+          (portref (member DOB 18) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[5]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_5))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[3]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_14_ "slave_fifo32/ctrl_rx_tdata[14]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT61))
+          (portref (member DOB 17) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[6]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_6))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[4]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_20_ "slave_fifo32/ctrl_rx_tdata[20]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131))
+          (portref (member DOB 29) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_15_ "slave_fifo32/ctrl_rx_tdata[15]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT71))
+          (portref (member DOB 16) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[7]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_7))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[5]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_16_ "slave_fifo32/ctrl_rx_tdata[16]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT81))
+          (portref (member DOPB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_21_ "slave_fifo32/ctrl_rx_tdata[21]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141))
+          (portref (member DOB 28) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[8]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_8))
+          (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01214))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[6]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_17_ "slave_fifo32/ctrl_rx_tdata[17]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT91))
+          (portref (member DOPB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_22_ "slave_fifo32/ctrl_rx_tdata[22]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151))
+          (portref (member DOB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[7]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_18_ "slave_fifo32/ctrl_rx_tdata[18]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101))
+          (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_23_ "slave_fifo32/ctrl_rx_tdata[23]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161))
+          (portref (member DOB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In11))
+          )
+         )
+         (net (rename slave_fifo32_debug1_10_ "slave_fifo32/debug1[10]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_10))
+          (portref D (instanceref slave_fifo32_debug2_10))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[8]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_19_ "slave_fifo32/ctrl_rx_tdata[19]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111))
+          (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_24_ "slave_fifo32/ctrl_rx_tdata[24]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT171))
+          (portref (member DOB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_debug1_11_ "slave_fifo32/debug1[11]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_11))
+          (portref D (instanceref slave_fifo32_debug2_11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[9]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_25_ "slave_fifo32/ctrl_rx_tdata[25]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT181))
+          (portref (member DOB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_30_ "slave_fifo32/ctrl_rx_tdata[30]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241))
+          (portref (member DOB 19) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_debug1_12_ "slave_fifo32/debug1[12]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_12))
+          (portref D (instanceref slave_fifo32_debug2_12))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_dont_write_past_me_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/dont_write_past_me[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01214))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_26_ "slave_fifo32/ctrl_rx_tdata[26]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191))
+          (portref (member DOB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_31_ "slave_fifo32/ctrl_rx_tdata[31]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251))
+          (portref (member DOB 18) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tlast "slave_fifo32/fifo64_to_gpmc32_rx/i32_tlast") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_o_tlast1))
+          (portref (member din 39) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<11>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_11_))
+          )
+         )
+         (net (rename slave_fifo32_debug1_13_ "slave_fifo32/debug1[13]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_13))
+          (portref D (instanceref slave_fifo32_debug2_13))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_27_ "slave_fifo32/ctrl_rx_tdata[27]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201))
+          (portref (member DOB 22) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_debug1_14_ "slave_fifo32/debug1[14]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_14))
+          (portref D (instanceref slave_fifo32_debug2_14))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_7__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<7>_FRB") (joined
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_7__FRB))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_28_ "slave_fifo32/ctrl_rx_tdata[28]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT211))
+          (portref (member DOB 21) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_debug1_15_ "slave_fifo32/debug1[15]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_15))
+          (portref D (instanceref slave_fifo32_debug2_15))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tdata_29_ "slave_fifo32/ctrl_rx_tdata[29]") (joined
+          (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221))
+          (portref (member DOB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_debug1_21_ "slave_fifo32/debug1[21]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_21))
+          (portref D (instanceref slave_fifo32_debug2_21))
+          )
+         )
+         (net (rename slave_fifo32_debug1_16_ "slave_fifo32/debug1[16]") (joined
+          (portref D (instanceref slave_fifo32_debug2_16))
+          (portref O (instanceref f0_i_tready1_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_debug1_22_ "slave_fifo32/debug1[22]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_22))
+          (portref D (instanceref slave_fifo32_debug2_22))
+          )
+         )
+         (net (rename slave_fifo32_debug1_17_ "slave_fifo32/debug1[17]") (joined
+          (portref D (instanceref slave_fifo32_debug2_17))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_o_tvalid1_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_write1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt__n0074_inv1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1))
+          )
+         )
+         (net (rename slave_fifo32_debug1_23_ "slave_fifo32/debug1[23]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_23))
+          (portref D (instanceref slave_fifo32_debug2_23))
+          (portref I2 (instanceref slave_fifo32_rd_one_rstpot))
+          (portref I2 (instanceref slave_fifo32_state_FSM_FFd1_In3_G))
+          )
+         )
+         (net (rename slave_fifo32_debug1_18_ "slave_fifo32/debug1[18]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_18))
+          (portref D (instanceref slave_fifo32_debug2_18))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          )
+         )
+         (net (rename f0_write "f0/write") (joined
+          (portref CE (instanceref f0_wr_addr_1))
+          (portref CE (instanceref f0_wr_addr_2))
+          (portref CE (instanceref f0_wr_addr_3))
+          (portref CE (instanceref f0_wr_addr_4))
+          (portref CE (instanceref f0_wr_addr_5))
+          (portref CE (instanceref f0_wr_addr_6))
+          (portref CE (instanceref f0_wr_addr_7))
+          (portref CE (instanceref f0_wr_addr_8))
+          (portref CE (instanceref f0_wr_addr_9))
+          (portref CE (instanceref f0_wr_addr_10))
+          (portref CE (instanceref f0_wr_addr_11))
+          (portref CE (instanceref f0_wr_addr_12))
+          (portref CE (instanceref f0_wr_addr_0))
+          (portref O (instanceref f0_write11))
+          (portref CE (instanceref f0_Result_0_2_FRB))
+          (portref CE (instanceref f0_Result_1_2_FRB))
+          (portref CE (instanceref f0_Result_2_2_FRB))
+          (portref CE (instanceref f0_Result_3_2_FRB))
+          (portref CE (instanceref f0_Result_4_2_FRB))
+          (portref CE (instanceref f0_Result_5_2_FRB))
+          (portref CE (instanceref f0_Result_6_2_FRB))
+          (portref CE (instanceref f0_Result_7_2_FRB))
+          (portref CE (instanceref f0_Result_8_2_FRB))
+          (portref CE (instanceref f0_Result_9_2_FRB))
+          (portref CE (instanceref f0_Result_10_2_FRB))
+          (portref CE (instanceref f0_Result_11_2_FRB))
+          (portref CE (instanceref f0_Result_12_2_FRB))
+          (portref (member WEAWEL 1) (instanceref f0_ram_Mram_ram33))
+          (portref (member WEAWEL 0) (instanceref f0_ram_Mram_ram33))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram31))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram31))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram31))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram31))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram30))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram30))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram30))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram30))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram32))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram32))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram32))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram32))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram28))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram28))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram28))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram28))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram27))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram27))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram27))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram27))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram29))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram29))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram29))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram29))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram25))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram25))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram25))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram25))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram24))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram24))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram24))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram24))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram26))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram26))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram26))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram26))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram22))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram22))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram22))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram22))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram21))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram21))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram21))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram21))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram23))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram23))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram23))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram23))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram19))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram19))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram19))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram19))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram18))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram18))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram18))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram18))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram20))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram20))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram20))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram20))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram16))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram16))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram16))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram16))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram15))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram15))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram15))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram15))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram17))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram17))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram17))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram17))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram14))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram14))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram14))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram14))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram13))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram13))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram13))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram13))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram12))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram12))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram12))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram12))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram11))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram11))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram11))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram11))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram9))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram9))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram9))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram9))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram8))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram8))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram8))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram8))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram10))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram10))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram10))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram10))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram6))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram6))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram6))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram6))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram5))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram5))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram5))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram5))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram7))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram7))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram7))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram7))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram3))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram3))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram3))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram3))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram2))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram2))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram2))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram2))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram4))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram4))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram4))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram4))
+          (portref (member WEA 3) (instanceref f0_ram_Mram_ram1))
+          (portref (member WEA 2) (instanceref f0_ram_Mram_ram1))
+          (portref (member WEA 1) (instanceref f0_ram_Mram_ram1))
+          (portref (member WEA 0) (instanceref f0_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_debug1_19_ "slave_fifo32/debug1[19]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_19))
+          (portref D (instanceref slave_fifo32_debug2_19))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_8__rt "f0/Mcount_wr_addr_cy<8>_rt") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_8__rt))
+          (portref S (instanceref f0_Mcount_wr_addr_cy_8_))
+          (portref LI (instanceref f0_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr2_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_2))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr2_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2__rt))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          )
+         )
+         (net (rename slave_fifo32_debug1_31_ "slave_fifo32/debug1[31]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_31))
+          (portref D (instanceref slave_fifo32_debug2_31))
+          )
+         )
+         (net (rename slave_fifo32_debug1_26_ "slave_fifo32/debug1[26]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_26))
+          (portref D (instanceref slave_fifo32_debug2_26))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_))
+          )
+         )
+         (net (rename slave_fifo32_debug1_27_ "slave_fifo32/debug1[27]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_27))
+          (portref D (instanceref slave_fifo32_debug2_27))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_0_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[0]") (joined
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 71) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr7_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_7))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_debug1_28_ "slave_fifo32/debug1[28]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_28))
+          (portref D (instanceref slave_fifo32_debug2_28))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_1_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[1]") (joined
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 70) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_debug1_29_ "slave_fifo32/debug1[29]") (joined
+          (portref Q (instanceref slave_fifo32_debug1_29))
+          (portref D (instanceref slave_fifo32_debug2_29))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_2_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[2]") (joined
+          (portref (member DIA 29) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 69) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_3_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[3]") (joined
+          (portref (member DIA 28) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 68) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_4_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[4]") (joined
+          (portref (member DIA 27) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 67) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f1_dont_write_past_me_0__FRB "f1/dont_write_past_me<0>_FRB") (joined
+          (portref I1 (instanceref f1_Mcompar_becoming_full_lut_0_))
+          (portref Q (instanceref f1_dont_write_past_me_0__FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_5_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[5]") (joined
+          (portref (member DIA 26) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 66) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_6_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[6]") (joined
+          (portref (member DIA 25) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 65) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_xor_12__rt "f0/Mcount_wr_addr_xor<12>_rt") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_xor_12__rt))
+          (portref LI (instanceref f0_Mcount_wr_addr_xor_12_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_7_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[7]") (joined
+          (portref (member DIA 24) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 64) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_8_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[8]") (joined
+          (portref (member DIA 23) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 63) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_9_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[9]") (joined
+          (portref (member DIA 22) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref (member dout 62) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In3") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34))
+          )
+         )
+         (net (rename f1_full_reg "f1/full_reg") (joined
+          (portref I1 (instanceref f1_write11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0))
+          (portref Q (instanceref f1_full_reg))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+          (portref I4 (instanceref f1_read_state_FSM_FFd2_In1))
+          (portref I4 (instanceref f1_full_reg_glue_set))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_out_31_1 "slave_fifo32/gpif_data_out_31_1") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_out_31_1))
+          (portref I1 (instanceref slave_fifo32_gpif_data_out_31_rstpot))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_1))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_9__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<9>_FRB") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_9__FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr8_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_cy_10_ "f0/Msub_dont_write_past_me_cy[10]") (joined
+          (portref O (instanceref f0_Msub_dont_write_past_me_cy_10_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_cy_11_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_xor_11_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr1_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_10_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[10]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[11]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[12]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[13]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[14]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1))
+          )
+         )
+         (net (rename f0_dont_write_past_me_0__FRB "f0/dont_write_past_me<0>_FRB") (joined
+          (portref I1 (instanceref f0_Mcompar_becoming_full_lut_0_))
+          (portref Q (instanceref f0_dont_write_past_me_0__FRB))
+          )
+         )
+         (net (rename f1_dont_write_past_me_2__FRB "f1/dont_write_past_me<2>_FRB") (joined
+          (portref I5 (instanceref f1_Mcompar_becoming_full_lut_0_))
+          (portref Q (instanceref f1_dont_write_past_me_2__FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[15]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[10]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_11_))
+          )
+         )
+         (net (rename f0__n0161_inv "f0/_n0161_inv") (joined
+          (portref CE (instanceref f0_rd_addr_1))
+          (portref CE (instanceref f0_rd_addr_2))
+          (portref CE (instanceref f0_rd_addr_3))
+          (portref CE (instanceref f0_rd_addr_4))
+          (portref CE (instanceref f0_rd_addr_5))
+          (portref CE (instanceref f0_rd_addr_6))
+          (portref CE (instanceref f0_rd_addr_7))
+          (portref CE (instanceref f0_rd_addr_8))
+          (portref CE (instanceref f0_rd_addr_9))
+          (portref CE (instanceref f0_rd_addr_10))
+          (portref CE (instanceref f0_rd_addr_11))
+          (portref CE (instanceref f0_rd_addr_12))
+          (portref CE (instanceref f0_rd_addr_0))
+          (portref CE (instanceref f0_Result_0_1_FRB))
+          (portref CE (instanceref f0_Result_1_1_FRB))
+          (portref CE (instanceref f0_Result_2_1_FRB))
+          (portref CE (instanceref f0_Result_3_1_FRB))
+          (portref CE (instanceref f0_Result_4_1_FRB))
+          (portref CE (instanceref f0_Result_5_1_FRB))
+          (portref CE (instanceref f0_Result_6_1_FRB))
+          (portref CE (instanceref f0_Result_7_1_FRB))
+          (portref CE (instanceref f0_Result_8_1_FRB))
+          (portref CE (instanceref f0_Result_9_1_FRB))
+          (portref CE (instanceref f0_Result_10_1_FRB))
+          (portref CE (instanceref f0_Result_11_1_FRB))
+          (portref CE (instanceref f0_Result_12_1_FRB))
+          (portref CE (instanceref f0_dont_write_past_me_0__FRB))
+          (portref CE (instanceref f0_dont_write_past_me_1__FRB))
+          (portref CE (instanceref f0_dont_write_past_me_2__FRB))
+          (portref CE (instanceref f0_dont_write_past_me_3__FRB))
+          (portref CE (instanceref f0_dont_write_past_me_4__FRB))
+          (portref CE (instanceref f0_dont_write_past_me_5__FRB))
+          (portref CE (instanceref f0_dont_write_past_me_6__FRB))
+          (portref CE (instanceref f0_dont_write_past_me_7__FRB))
+          (portref CE (instanceref f0_dont_write_past_me_8__FRB))
+          (portref CE (instanceref f0_dont_write_past_me_9__FRB))
+          (portref CE (instanceref f0_dont_write_past_me_10__FRB))
+          (portref CE (instanceref f0_dont_write_past_me_11__FRB))
+          (portref CE (instanceref f0_dont_write_past_me_12__FRB))
+          (portref O (instanceref f0__n0161_inv1_cy1))
+          )
+         )
+         (net cat_ce (joined
+          (portref O (instanceref cat_ce_OBUF))
+          (portref cat_ce)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a1") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_0_11_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a2 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a2") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_1_11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a3 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a3") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_2_11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In11") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_xor_12__rt "f1/Mcount_rd_addr_xor<12>_rt") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_xor_12__rt))
+          (portref LI (instanceref f1_Mcount_rd_addr_xor_12_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a4 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a4") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_3_11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In12") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_read1))
+          (portref rd_en (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a5 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a5") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_4_11))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_7__rt "f1/Mcount_rd_addr_cy<7>_rt") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_7__rt))
+          (portref S (instanceref f1_Mcount_rd_addr_cy_7_))
+          (portref LI (instanceref f1_Mcount_rd_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In31") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In32") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB0") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_i_tvalid_int "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/i_tvalid_int") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_write1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net codec_fb_clk_p (joined
+          (portref O (instanceref codec_fb_clk_p_OBUF))
+          (portref codec_fb_clk_p)
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_3__rt "f0/Mcount_rd_addr_cy<3>_rt") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_3__rt))
+          (portref S (instanceref f0_Mcount_rd_addr_cy_3_))
+          (portref LI (instanceref f0_Mcount_rd_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7_))
+          )
+         )
+         (net (rename f0_dont_write_past_me_2__FRB "f0/dont_write_past_me<2>_FRB") (joined
+          (portref I5 (instanceref f0_Mcompar_becoming_full_lut_0_))
+          (portref Q (instanceref f0_dont_write_past_me_2__FRB))
+          )
+         )
+         (net (rename f1_dont_write_past_me_4__FRB "f1/dont_write_past_me<4>_FRB") (joined
+          (portref I3 (instanceref f1_Mcompar_becoming_full_lut_1_))
+          (portref Q (instanceref f1_dont_write_past_me_4__FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[9]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_10_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[10]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210))
+          (portref D (instanceref slave_fifo32_gpif_data_out_10))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_11_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[11]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33))
+          (portref D (instanceref slave_fifo32_gpif_data_out_11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o "slave_fifo32/fifo64_to_gpmc32_ctrl/GND_63_o_space[15]_LessThan_2_o") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_i_tready))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_12_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[12]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT41))
+          (portref D (instanceref slave_fifo32_gpif_data_out_12))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/GND_50_o_read_OR_57_o") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_13_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[13]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT51))
+          (portref D (instanceref slave_fifo32_gpif_data_out_13))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_14_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[14]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT61))
+          (portref D (instanceref slave_fifo32_gpif_data_out_14))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_15_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[15]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT71))
+          (portref D (instanceref slave_fifo32_gpif_data_out_15))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_20_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[20]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131))
+          (portref D (instanceref slave_fifo32_gpif_data_out_20))
+          )
+         )
+         (net (rename slave_fifo32_data_rx_tlast "slave_fifo32/data_rx_tlast") (joined
+          (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1))
+          (portref (member DOBDO 15) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref I2 (instanceref slave_fifo32_state_FSM_FFd1_In2))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt__n0074_inv1))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_16_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[16]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT81))
+          (portref D (instanceref slave_fifo32_gpif_data_out_16))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_21_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[21]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141))
+          (portref D (instanceref slave_fifo32_gpif_data_out_21))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_17_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[17]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT91))
+          (portref D (instanceref slave_fifo32_gpif_data_out_17))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_22_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[22]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151))
+          (portref D (instanceref slave_fifo32_gpif_data_out_22))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_18_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[18]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101))
+          (portref D (instanceref slave_fifo32_gpif_data_out_18))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_23_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[23]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161))
+          (portref D (instanceref slave_fifo32_gpif_data_out_23))
+          )
+         )
+         (net (rename slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o "slave_fifo32/ctrl_rx_tvalid_data_rx_tvalid_OR_56_o") (joined
+          (portref D (instanceref slave_fifo32_write_ready_go))
+          (portref O (instanceref slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_19_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[19]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111))
+          (portref D (instanceref slave_fifo32_gpif_data_out_19))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_24_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[24]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT171))
+          (portref D (instanceref slave_fifo32_gpif_data_out_24))
+          )
+         )
+         (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[0]") (joined
+          (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          (portref CI (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_25_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[25]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT181))
+          (portref D (instanceref slave_fifo32_gpif_data_out_25))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_30_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[30]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241))
+          (portref D (instanceref slave_fifo32_gpif_data_out_30))
+          )
+         )
+         (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[1]") (joined
+          (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          (portref CI (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          )
+         )
+         (net (rename slave_fifo32_pktend "slave_fifo32/pktend") (joined
+          (portref Q (instanceref slave_fifo32_pktend))
+          (portref I (instanceref GPIF_CTL7_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_26_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[26]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191))
+          (portref D (instanceref slave_fifo32_gpif_data_out_26))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_31_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[31]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251))
+          (portref I2 (instanceref slave_fifo32_gpif_data_out_31_rstpot))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr11_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr11_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_11))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr11_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__rt))
+          )
+         )
+         (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[2]") (joined
+          (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          (portref CI (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_27_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[27]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201))
+          (portref D (instanceref slave_fifo32_gpif_data_out_27))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_14_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_14_BRB1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_14_BRB1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_))
+          )
+         )
+         (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[3]") (joined
+          (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          (portref CI (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_28_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[28]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT211))
+          (portref D (instanceref slave_fifo32_gpif_data_out_28))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_29_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[29]") (joined
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221))
+          (portref D (instanceref slave_fifo32_gpif_data_out_29))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_cy_4__rt "f1/Mcount_wr_addr_cy<4>_rt") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_4__rt))
+          (portref S (instanceref f1_Mcount_wr_addr_cy_4_))
+          (portref LI (instanceref f1_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32__n0223_inv "slave_fifo32/_n0223_inv") (joined
+          (portref CE (instanceref slave_fifo32_pktend))
+          (portref CE (instanceref slave_fifo32_slwr))
+          (portref O (instanceref slave_fifo32__n0223_inv1))
+          (portref I0 (instanceref slave_fifo32_gpif_data_out_31_rstpot))
+          (portref CE (instanceref slave_fifo32_slwr_1))
+          (portref CE (instanceref slave_fifo32_pktend_1))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_30))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_29))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_28))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_27))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_26))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_25))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_24))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_23))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_22))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_21))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_20))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_19))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_18))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_17))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_16))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_15))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_14))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_13))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_12))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_11))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_10))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_9))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_8))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_7))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_6))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_5))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_4))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_3))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_2))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_1))
+          (portref CE (instanceref slave_fifo32_gpif_data_out_0))
+          )
+         )
+         (net IFCLK_OBUF (joined
+          (portref Q (instanceref ODDR2_ifclk))
+          (portref I (instanceref IFCLK_OBUF))
+          )
+         )
+         (net (rename f0_dont_write_past_me_4__FRB "f0/dont_write_past_me<4>_FRB") (joined
+          (portref I3 (instanceref f0_Mcompar_becoming_full_lut_1_))
+          (portref Q (instanceref f0_dont_write_past_me_4__FRB))
+          )
+         )
+         (net (rename f1_dont_write_past_me_6__FRB "f1/dont_write_past_me<6>_FRB") (joined
+          (portref I1 (instanceref f1_Mcompar_becoming_full_lut_2_))
+          (portref Q (instanceref f1_dont_write_past_me_6__FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT821 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT821") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          )
+         )
+         (net N100 (joined
+          (portref D (instanceref slave_fifo32_gpif_data_in_27))
+          (portref O (instanceref GPIF_D_27_IOBUF))
+          )
+         )
+         (net N101 (joined
+          (portref D (instanceref slave_fifo32_gpif_data_in_26))
+          (portref O (instanceref GPIF_D_26_IOBUF))
+          )
+         )
+         (net N102 (joined
+          (portref D (instanceref slave_fifo32_gpif_data_in_25))
+          (portref O (instanceref GPIF_D_25_IOBUF))
+          )
+         )
+         (net (rename slave_fifo32_EP_READY "slave_fifo32/EP_READY") (joined
+          (portref Q (instanceref slave_fifo32_EP_READY))
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+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3_))
+          )
+         )
+         (net N198 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr10_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_10_))
+          )
+         )
+         (net N303 (joined
+          (portref D (instanceref f0_Result_3_1_FRB))
+          (portref O (instanceref f0_Mcount_rd_addr_xor_3_))
+          )
+         )
+         (net N253 (joined
+          (portref D (instanceref f1_Result_9_2_FRB))
+          (portref O (instanceref f1_Mcount_wr_addr_xor_9_))
+          )
+         )
+         (net N248 (joined
+          (portref D (instanceref f1_Result_4_2_FRB))
+          (portref O (instanceref f1_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net N199 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr11_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_11_))
+          )
+         )
+         (net N304 (joined
+          (portref D (instanceref f0_Result_4_1_FRB))
+          (portref O (instanceref f0_Mcount_rd_addr_xor_4_))
+          )
+         )
+         (net N254 (joined
+          (portref D (instanceref f1_Result_10_2_FRB))
+          (portref O (instanceref f1_Mcount_wr_addr_xor_10_))
+          )
+         )
+         (net N249 (joined
+          (portref D (instanceref f1_Result_5_2_FRB))
+          (portref O (instanceref f1_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net N255 (joined
+          (portref D (instanceref f1_Result_11_2_FRB))
+          (portref O (instanceref f1_Mcount_wr_addr_xor_11_))
+          )
+         )
+         (net N310 (joined
+          (portref D (instanceref f0_Result_10_1_FRB))
+          (portref O (instanceref f0_Mcount_rd_addr_xor_10_))
+          )
+         )
+         (net N305 (joined
+          (portref D (instanceref f0_Result_5_1_FRB))
+          (portref O (instanceref f0_Mcount_rd_addr_xor_5_))
+          )
+         )
+         (net N260 (joined
+          (portref D (instanceref f1_Result_2_1_FRB))
+          (portref O (instanceref f1_Mcount_rd_addr_xor_2_))
+          )
+         )
+         (net N256 (joined
+          (portref O (instanceref f1_Mcount_wr_addr_cy_11_))
+          (portref CI (instanceref f1_Mcount_wr_addr_xor_12_))
+          )
+         )
+         (net N311 (joined
+          (portref D (instanceref f0_Result_11_1_FRB))
+          (portref O (instanceref f0_Mcount_rd_addr_xor_11_))
+          )
+         )
+         (net N306 (joined
+          (portref D (instanceref f0_Result_6_1_FRB))
+          (portref O (instanceref f0_Mcount_rd_addr_xor_6_))
+          )
+         )
+         (net N261 (joined
+          (portref D (instanceref f1_Result_3_1_FRB))
+          (portref O (instanceref f1_Mcount_rd_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4_))
+          )
+         )
+         (net N312 (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_11_))
+          (portref CI (instanceref f0_Mcount_rd_addr_xor_12_))
+          )
+         )
+         (net N307 (joined
+          (portref D (instanceref f0_Result_7_1_FRB))
+          (portref O (instanceref f0_Mcount_rd_addr_xor_7_))
+          )
+         )
+         (net N262 (joined
+          (portref D (instanceref f1_Result_4_1_FRB))
+          (portref O (instanceref f1_Mcount_rd_addr_xor_4_))
+          )
+         )
+         (net N257 (joined
+          (portref D (instanceref f1_Result_12_2_FRB))
+          (portref O (instanceref f1_Mcount_wr_addr_xor_12_))
+          )
+         )
+         (net (rename f0_Result_3_1_FRB "f0/Result<3>1_FRB") (joined
+          (portref D (instanceref f0_rd_addr_3))
+          (portref Q (instanceref f0_Result_3_1_FRB))
+          (portref I0 (instanceref f0_Mcount_rd_addr_cy_3__rt))
+          (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_3__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7_))
+          )
+         )
+         (net N313 (joined
+          (portref D (instanceref f0_Result_12_1_FRB))
+          (portref O (instanceref f0_Mcount_rd_addr_xor_12_))
+          )
+         )
+         (net N308 (joined
+          (portref D (instanceref f0_Result_8_1_FRB))
+          (portref O (instanceref f0_Mcount_rd_addr_xor_8_))
+          )
+         )
+         (net N263 (joined
+          (portref D (instanceref f1_Result_5_1_FRB))
+          (portref O (instanceref f1_Mcount_rd_addr_xor_5_))
+          )
+         )
+         (net N258 (joined
+          (portref D (instanceref f1_Result_0_1_FRB))
+          (portref O (instanceref f1_Mcount_rd_addr_xor_0_))
+          )
+         )
+         (net N259 (joined
+          (portref D (instanceref f1_Result_1_1_FRB))
+          (portref O (instanceref f1_Mcount_rd_addr_xor_1_))
+          )
+         )
+         (net N314 (joined
+          (portref D (instanceref f0_dont_write_past_me_0__FRB))
+          (portref O (instanceref f0_Msub_dont_write_past_me_xor_0_))
+          )
+         )
+         (net N309 (joined
+          (portref D (instanceref f0_Result_9_1_FRB))
+          (portref O (instanceref f0_Mcount_rd_addr_xor_9_))
+          )
+         )
+         (net N264 (joined
+          (portref D (instanceref f1_Result_6_1_FRB))
+          (portref O (instanceref f1_Mcount_rd_addr_xor_6_))
+          )
+         )
+         (net N265 (joined
+          (portref D (instanceref f1_Result_7_1_FRB))
+          (portref O (instanceref f1_Mcount_rd_addr_xor_7_))
+          )
+         )
+         (net N320 (joined
+          (portref D (instanceref f0_dont_write_past_me_6__FRB))
+          (portref O (instanceref f0_Msub_dont_write_past_me_xor_6_))
+          )
+         )
+         (net N315 (joined
+          (portref D (instanceref f0_dont_write_past_me_1__FRB))
+          (portref O (instanceref f0_Msub_dont_write_past_me_xor_1_))
+          )
+         )
+         (net N270 (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_11_))
+          (portref CI (instanceref f1_Mcount_rd_addr_xor_12_))
+          )
+         )
+         (net N266 (joined
+          (portref D (instanceref f1_Result_8_1_FRB))
+          (portref O (instanceref f1_Mcount_rd_addr_xor_8_))
+          )
+         )
+         (net N321 (joined
+          (portref D (instanceref f0_dont_write_past_me_7__FRB))
+          (portref O (instanceref f0_Msub_dont_write_past_me_xor_7_))
+          )
+         )
+         (net N316 (joined
+          (portref D (instanceref f0_dont_write_past_me_2__FRB))
+          (portref O (instanceref f0_Msub_dont_write_past_me_xor_2_))
+          )
+         )
+         (net N271 (joined
+          (portref D (instanceref f1_Result_12_1_FRB))
+          (portref O (instanceref f1_Mcount_rd_addr_xor_12_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5_))
+          )
+         )
+         (net N322 (joined
+          (portref D (instanceref f0_dont_write_past_me_8__FRB))
+          (portref O (instanceref f0_Msub_dont_write_past_me_xor_8_))
+          )
+         )
+         (net N317 (joined
+          (portref D (instanceref f0_dont_write_past_me_3__FRB))
+          (portref O (instanceref f0_Msub_dont_write_past_me_xor_3_))
+          )
+         )
+         (net N272 (joined
+          (portref D (instanceref f1_dont_write_past_me_0__FRB))
+          (portref O (instanceref f1_Msub_dont_write_past_me_xor_0_))
+          )
+         )
+         (net N267 (joined
+          (portref D (instanceref f1_Result_9_1_FRB))
+          (portref O (instanceref f1_Mcount_rd_addr_xor_9_))
+          )
+         )
+         (net N268 (joined
+          (portref D (instanceref f1_Result_10_1_FRB))
+          (portref O (instanceref f1_Mcount_rd_addr_xor_10_))
+          )
+         )
+         (net N323 (joined
+          (portref D (instanceref f0_dont_write_past_me_9__FRB))
+          (portref O (instanceref f0_Msub_dont_write_past_me_xor_9_))
+          )
+         )
+         (net N318 (joined
+          (portref D (instanceref f0_dont_write_past_me_4__FRB))
+          (portref O (instanceref f0_Msub_dont_write_past_me_xor_4_))
+          )
+         )
+         (net N273 (joined
+          (portref D (instanceref f1_dont_write_past_me_1__FRB))
+          (portref O (instanceref f1_Msub_dont_write_past_me_xor_1_))
+          )
+         )
+         (net N269 (joined
+          (portref D (instanceref f1_Result_11_1_FRB))
+          (portref O (instanceref f1_Mcount_rd_addr_xor_11_))
+          )
+         )
+         (net N324 (joined
+          (portref D (instanceref f0_dont_write_past_me_10__FRB))
+          (portref O (instanceref f0_Msub_dont_write_past_me_xor_10_))
+          )
+         )
+         (net N319 (joined
+          (portref D (instanceref f0_dont_write_past_me_5__FRB))
+          (portref O (instanceref f0_Msub_dont_write_past_me_xor_5_))
+          )
+         )
+         (net N274 (joined
+          (portref D (instanceref f1_dont_write_past_me_2__FRB))
+          (portref O (instanceref f1_Msub_dont_write_past_me_xor_2_))
+          )
+         )
+         (net N275 (joined
+          (portref D (instanceref f1_dont_write_past_me_3__FRB))
+          (portref O (instanceref f1_Msub_dont_write_past_me_xor_3_))
+          )
+         )
+         (net N325 (joined
+          (portref D (instanceref f0_dont_write_past_me_11__FRB))
+          (portref O (instanceref f0_Msub_dont_write_past_me_xor_11_))
+          )
+         )
+         (net N280 (joined
+          (portref D (instanceref f1_dont_write_past_me_8__FRB))
+          (portref O (instanceref f1_Msub_dont_write_past_me_xor_8_))
+          )
+         )
+         (net N276 (joined
+          (portref D (instanceref f1_dont_write_past_me_4__FRB))
+          (portref O (instanceref f1_Msub_dont_write_past_me_xor_4_))
+          )
+         )
+         (net N331 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          )
+         )
+         (net N326 (joined
+          (portref O (instanceref f0_Msub_dont_write_past_me_cy_11_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_xor_12_))
+          )
+         )
+         (net N281 (joined
+          (portref D (instanceref f1_dont_write_past_me_9__FRB))
+          (portref O (instanceref f1_Msub_dont_write_past_me_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6_))
+          )
+         )
+         (net N332 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          )
+         )
+         (net N327 (joined
+          (portref D (instanceref f0_dont_write_past_me_12__FRB))
+          (portref O (instanceref f0_Msub_dont_write_past_me_xor_12_))
+          )
+         )
+         (net N282 (joined
+          (portref D (instanceref f1_dont_write_past_me_10__FRB))
+          (portref O (instanceref f1_Msub_dont_write_past_me_xor_10_))
+          )
+         )
+         (net N277 (joined
+          (portref D (instanceref f1_dont_write_past_me_5__FRB))
+          (portref O (instanceref f1_Msub_dont_write_past_me_xor_5_))
+          )
+         )
+         (net N278 (joined
+          (portref D (instanceref f1_dont_write_past_me_6__FRB))
+          (portref O (instanceref f1_Msub_dont_write_past_me_xor_6_))
+          )
+         )
+         (net N328 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          )
+         )
+         (net N283 (joined
+          (portref D (instanceref f1_dont_write_past_me_11__FRB))
+          (portref O (instanceref f1_Msub_dont_write_past_me_xor_11_))
+          )
+         )
+         (net N279 (joined
+          (portref D (instanceref f1_dont_write_past_me_7__FRB))
+          (portref O (instanceref f1_Msub_dont_write_past_me_xor_7_))
+          )
+         )
+         (net N334 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          )
+         )
+         (net N329 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          )
+         )
+         (net N284 (joined
+          (portref O (instanceref f1_Msub_dont_write_past_me_cy_11_))
+          (portref CI (instanceref f1_Msub_dont_write_past_me_xor_12_))
+          )
+         )
+         (net N285 (joined
+          (portref D (instanceref f1_dont_write_past_me_12__FRB))
+          (portref O (instanceref f1_Msub_dont_write_past_me_xor_12_))
+          )
+         )
+         (net N335 (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1))
+          )
+         )
+         (net N290 (joined
+          (portref D (instanceref f0_Result_4_2_FRB))
+          (portref O (instanceref f0_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<6>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net N291 (joined
+          (portref D (instanceref f0_Result_5_2_FRB))
+          (portref O (instanceref f0_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net N286 (joined
+          (portref D (instanceref f0_Result_0_2_FRB))
+          (portref O (instanceref f0_Mcount_wr_addr_xor_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7_))
+          )
+         )
+         (net N337 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1))
+          )
+         )
+         (net N292 (joined
+          (portref D (instanceref f0_Result_6_2_FRB))
+          (portref O (instanceref f0_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net N287 (joined
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+          (portref O (instanceref f0_Mcount_wr_addr_xor_1_))
+          )
+         )
+         (net N288 (joined
+          (portref D (instanceref f0_Result_2_2_FRB))
+          (portref O (instanceref f0_Mcount_wr_addr_xor_2_))
+          )
+         )
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+          (portref D (instanceref f0_Result_7_2_FRB))
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+          (portref D (instanceref f0_Result_3_2_FRB))
+          (portref O (instanceref f0_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net N339 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1))
+          )
+         )
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+          )
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+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[7]") (joined
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+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_))
+          )
+         )
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+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+          )
+         )
+         (net N297 (joined
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+          )
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+          (portref O (instanceref f0_Mcount_wr_addr_cy_11_))
+          (portref CI (instanceref f0_Mcount_wr_addr_xor_12_))
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+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61))
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+          )
+         )
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+          (portref O (instanceref f0_Mcount_wr_addr_xor_12_))
+          )
+         )
+         (net N354 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61))
+          )
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+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11))
+          )
+         )
+         (net N356 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16))
+          )
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+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set))
+          )
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+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[8]") (joined
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+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_))
+          )
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+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+          )
+         )
+         (net N357 (joined
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+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16))
+          )
+         )
+         (net N363 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0))
+          )
+         )
+         (net N413 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0))
+          )
+         )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW1))
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+          )
+         )
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+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2))
+          )
+         )
+         (net N415 (joined
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+          )
+         )
+         (net N370 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0))
+          )
+         )
+         (net N421 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+          )
+         )
+         (net N417 (joined
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+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11))
+          )
+         )
+         (net N372 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set))
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+         )
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+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+          )
+         )
+         (net N423 (joined
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+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1))
+          )
+         )
+         (net N369 (joined
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+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0))
+          )
+         )
+         (net N419 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2))
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+          )
+         )
+         (net N374 (joined
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+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+          )
+         )
+         (net N375 (joined
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+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+          )
+         )
+         (net N425 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01217_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set))
+          )
+         )
+         (net (rename f0_dont_write_past_me_6__FRB "f0/dont_write_past_me<6>_FRB") (joined
+          (portref I1 (instanceref f0_Mcompar_becoming_full_lut_2_))
+          (portref Q (instanceref f0_dont_write_past_me_6__FRB))
+          )
+         )
+         (net N431 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          )
+         )
+         (net N381 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_))
+          )
+         )
+         (net (rename f1_dont_write_past_me_8__FRB "f1/dont_write_past_me<8>_FRB") (joined
+          (portref I5 (instanceref f1_Mcompar_becoming_full_lut_2_))
+          (portref Q (instanceref f1_dont_write_past_me_8__FRB))
+          )
+         )
+         (net N427 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set))
+          )
+         )
+         (net N382 (joined
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1))
+          )
+         )
+         (net N433 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216))
+          )
+         )
+         (net N384 (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01217_SW0))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0))
+          )
+         )
+         (net N434 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216))
+          )
+         )
+         (net N429 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0))
+          )
+         )
+         (net N390 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot))
+          )
+         )
+         (net N435 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_))
+          )
+         )
+         (net N441 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+          )
+         )
+         (net N391 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot))
+          )
+         )
+         (net N386 (joined
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0))
+          )
+         )
+         (net N437 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In12_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_8_))
+          )
+         )
+         (net N443 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          )
+         )
+         (net N388 (joined
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0))
+          )
+         )
+         (net N439 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In12_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13))
+          )
+         )
+         (net N445 (joined
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+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+          )
+         )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_))
+          )
+         )
+         (net N451 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511))
+          )
+         )
+         (net N396 (joined
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+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          )
+         )
+         (net N397 (joined
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+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          )
+         )
+         (net N447 (joined
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1))
+          )
+         )
+         (net N453 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/clear_inv") (joined
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[0]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_0))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17))
+          )
+         )
+         (net N460 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr3_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net N455 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_))
+          )
+         )
+         (net N461 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr4_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net N457 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_0_))
+          )
+         )
+         (net N462 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net N458 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_1_))
+          )
+         )
+         (net N463 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net N459 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr2_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_2_))
+          )
+         )
+         (net N464 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr7_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[1]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81))
+          )
+         )
+         (net N470 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net N465 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_))
+          )
+         )
+         (net N471 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net N466 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr8_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net N467 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_0_))
+          )
+         )
+         (net N472 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net N468 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_1_))
+          )
+         )
+         (net N473 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr6_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net N469 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_2_))
+          )
+         )
+         (net N474 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[2]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_2))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91))
+          )
+         )
+         (net N480 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411))
+          )
+         )
+         (net N475 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_))
+          )
+         )
+         (net N481 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0))
+          )
+         )
+         (net N476 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net tx_enable1 (joined
+          (portref O (instanceref tx_enable1_OBUF))
+          (portref tx_enable1)
+          )
+         )
+         (net N482 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0))
+          )
+         )
+         (net N477 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421))
+          )
+         )
+         (net cat_mosi_OBUF (joined
+          (portref O (instanceref cat_mosi1))
+          (portref I (instanceref cat_mosi_OBUF))
+          )
+         )
+         (net N483 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621))
+          )
+         )
+         (net N478 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411))
+          )
+         )
+         (net tx_enable2 (joined
+          (portref O (instanceref tx_enable2_OBUF))
+          (portref tx_enable2)
+          )
+         )
+         (net N479 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421))
+          )
+         )
+         (net N484 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[3]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101))
+          )
+         )
+         (net N485 (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_))
+          )
+         )
+         (net N543 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[4]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_4))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111))
+          )
+         )
+         (net N550 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0))
+          )
+         )
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+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_))
+          )
+         )
+         (net N551 (joined
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+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1))
+          )
+         )
+         (net N546 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2))
+          )
+         )
+         (net N547 (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F))
+          )
+         )
+         (net N552 (joined
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+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1))
+          )
+         )
+         (net N548 (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G))
+          )
+         )
+         (net N553 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1))
+          )
+         )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0))
+          )
+         )
+         (net N554 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[5]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_5))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_))
+          )
+         )
+         (net N561 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst))
+          )
+         )
+         (net N563 (joined
+          (portref O (instanceref slave_fifo32_slrd_rstpot_SW0))
+          (portref I1 (instanceref slave_fifo32_slrd_rstpot))
+          )
+         )
+         (net N559 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[6]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_6))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131))
+          )
+         )
+         (net N565 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[9]") (joined
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+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_))
+          )
+         )
+         (net N571 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+          )
+         )
+         (net N567 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215))
+          )
+         )
+         (net N573 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1))
+          )
+         )
+         (net N569 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[0]") (joined
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+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17))
+          )
+         )
+         (net N575 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_SW1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[7]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_7))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141))
+          )
+         )
+         (net N581 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1))
+          )
+         )
+         (net N577 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_SW1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set))
+          )
+         )
+         (net N583 (joined
+          (portref O (instanceref slave_fifo32_state_FSM_FFd1_In3_F))
+          (portref I0 (instanceref slave_fifo32_state_FSM_FFd1_In3))
+          )
+         )
+         (net N579 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1))
+          )
+         )
+         (net N584 (joined
+          (portref O (instanceref slave_fifo32_state_FSM_FFd1_In3_G))
+          (portref I1 (instanceref slave_fifo32_state_FSM_FFd1_In3))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81))
+          )
+         )
+         (net N590 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2))
+          )
+         )
+         (net N585 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[8]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_8))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set))
+          )
+         )
+         (net N586 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14))
+          )
+         )
+         (net N587 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1))
+          )
+         )
+         (net N588 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01217_SW0))
+          )
+         )
+         (net N589 (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12__wr_addr_12__equal_11_o "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[12]_wr_addr[12]_equal_11_o") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_5))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[9]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1))
+          )
+         )
+         (net (rename f0_Result_1_2_FRB "f0/Result<1>2_FRB") (joined
+          (portref D (instanceref f0_wr_addr_1))
+          (portref Q (instanceref f0_Result_1_2_FRB))
+          (portref I0 (instanceref f0_Mcount_wr_addr_cy_1__rt))
+          )
+         )
+         (net (rename f0_dont_write_past_me_8__FRB "f0/dont_write_past_me<8>_FRB") (joined
+          (portref I5 (instanceref f0_Mcompar_becoming_full_lut_2_))
+          (portref Q (instanceref f0_dont_write_past_me_8__FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_))
+          )
+         )
+         (net (rename f0__n0161_inv1_lut1 "f0/_n0161_inv1_lut1") (joined
+          (portref O (instanceref f0__n0161_inv1_lut1))
+          (portref S (instanceref f0__n0161_inv1_cy1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net pps_fpga_out_enable (joined
+          (portref O (instanceref pps_fpga_out_enable_OBUF))
+          (portref pps_fpga_out_enable)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_debug2_10_ "slave_fifo32/debug2[10]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_10))
+          (portref I (instanceref debug_10_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_debug2_11_ "slave_fifo32/debug2[11]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_11))
+          (portref I (instanceref debug_11_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_debug2_12_ "slave_fifo32/debug2[12]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_12))
+          (portref I (instanceref debug_12_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[9]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_debug2_13_ "slave_fifo32/debug2[13]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_13))
+          (portref I (instanceref debug_13_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_0))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt))
+          )
+         )
+         (net (rename slave_fifo32_debug2_14_ "slave_fifo32/debug2[14]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_14))
+          (portref I (instanceref debug_14_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_debug2_15_ "slave_fifo32/debug2[15]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_15))
+          (portref I (instanceref debug_15_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_debug2_16_ "slave_fifo32/debug2[16]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_16))
+          (portref I (instanceref debug_16_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_debug2_21_ "slave_fifo32/debug2[21]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_21))
+          (portref I (instanceref debug_21_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1021))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_debug2_17_ "slave_fifo32/debug2[17]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_17))
+          (portref I (instanceref debug_17_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_debug2_22_ "slave_fifo32/debug2[22]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_22))
+          (portref I (instanceref debug_22_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1011))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212211))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_SW0))
+          )
+         )
+         (net (rename slave_fifo32_debug2_18_ "slave_fifo32/debug2[18]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_18))
+          (portref I (instanceref debug_18_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_debug2_23_ "slave_fifo32/debug2[23]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_23))
+          (portref I (instanceref debug_23_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr[3]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_3))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212211))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0121211))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_i_tready "slave_fifo32/fifo64_to_gpmc32_tx/i_tready") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_i_tready))
+          (portref I2 (instanceref slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1))
+          )
+         )
+         (net (rename slave_fifo32_debug2_19_ "slave_fifo32/debug2[19]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_19))
+          (portref I (instanceref debug_19_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr[4]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_4))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o41))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1))
+          )
+         )
+         (net (rename f0_Mcount_wr_addr_cy_9__rt "f0/Mcount_wr_addr_cy<9>_rt") (joined
+          (portref O (instanceref f0_Mcount_wr_addr_cy_9__rt))
+          (portref S (instanceref f0_Mcount_wr_addr_cy_9_))
+          (portref LI (instanceref f0_Mcount_wr_addr_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr[5]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_5))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0121211))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212211))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr3_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_3))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr3_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__rt))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621))
+          )
+         )
+         (net (rename slave_fifo32_debug2_26_ "slave_fifo32/debug2[26]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_26))
+          (portref I (instanceref debug_26_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_debug2_31_ "slave_fifo32/debug2[31]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_31))
+          (portref I (instanceref debug_31_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr[6]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_6))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_write "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_1__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_2__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_3__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_4__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_5__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_6__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_7__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_8__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_11__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_12__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_13__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_14__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_15__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_20__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_21__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_22__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_23__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_24__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_28__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_29__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_30__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_31__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_32__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_33__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_38__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_39__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_40__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_41__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_42__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_43__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_44__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_46__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_47__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_48__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_51__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_52__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_53__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_59__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_write1))
+          )
+         )
+         (net (rename slave_fifo32_debug2_27_ "slave_fifo32/debug2[27]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_27))
+          (portref I (instanceref debug_27_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr[7]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_7))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_2))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__10_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][10]") (joined
+          (portref (member DOB 21) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 61) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr8_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_8))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_debug2_28_ "slave_fifo32/debug2[28]") (joined
+          (portref Q (instanceref slave_fifo32_debug2_28))
+          (portref I (instanceref debug_28_OBUF))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_8_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr[8]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_8))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
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+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__26_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][26]") (joined
+          (portref (member DOB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 45) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__31_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][31]") (joined
+          (portref (member DOB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 40) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr2_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_2))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__32_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][32]") (joined
+          (portref (member DOPB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 39) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__27_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][27]") (joined
+          (portref (member DOB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 44) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net codec_en_agc (joined
+          (portref O (instanceref codec_en_agc_OBUF))
+          (portref codec_en_agc)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__28_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][28]") (joined
+          (portref (member DOB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 43) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__29_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][29]") (joined
+          (portref (member DOB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member din 42) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121211 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121211") (joined
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+          )
+         )
+         (net codec_fb_clk_p_OBUF (joined
+          (portref Q (instanceref catgen_oddr2_clk))
+          (portref I (instanceref codec_fb_clk_p_OBUF))
+          )
+         )
+         (net (rename f1_wr_addr_10_ "f1/wr_addr[10]") (joined
+          (portref Q (instanceref f1_wr_addr_10))
+          (portref I3 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref I2 (instanceref f1_Mcompar_becoming_full_lut_3_))
+          (portref (member ADDRAWRADDR 2) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRA 2) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr2_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr2_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621))
+          )
+         )
+         (net (rename f1_wr_addr_11_ "f1/wr_addr[11]") (joined
+          (portref Q (instanceref f1_wr_addr_11))
+          (portref I5 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref I4 (instanceref f1_Mcompar_becoming_full_lut_3_))
+          (portref (member ADDRAWRADDR 1) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_0_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_))
+          )
+         )
+         (net (rename slave_fifo32_wr_one_rstpot "slave_fifo32/wr_one_rstpot") (joined
+          (portref D (instanceref slave_fifo32_wr_one))
+          (portref O (instanceref slave_fifo32_wr_one_rstpot))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/GND_56_o_read_OR_123_o") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o1))
+          (portref ENBRDEN (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1))
+          )
+         )
+         (net (rename f1_wr_addr_12_ "f1/wr_addr[12]") (joined
+          (portref Q (instanceref f1_wr_addr_12))
+          (portref I1 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_))
+          (portref I0 (instanceref f1_Mcompar_becoming_full_lut_4_))
+          (portref (member ADDRAWRADDR 0) (instanceref f1_ram_Mram_ram33))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram31))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram30))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram32))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram28))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram27))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram29))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram25))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram24))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram26))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram22))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram21))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram23))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram19))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram18))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram20))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram16))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram15))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram17))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram14))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram13))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram12))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram11))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram9))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram8))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram10))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram6))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram5))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram7))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram3))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram2))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram4))
+          (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_1_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set))
+          )
+         )
+         (net (rename slave_fifo32_state_FSM_FFd1_In "slave_fifo32/state_FSM_FFd1-In") (joined
+          (portref D (instanceref slave_fifo32_state_FSM_FFd1))
+          (portref O (instanceref slave_fifo32_state_FSM_FFd1_In4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_2_))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net (rename f1_Mcount_wr_addr_xor_12__rt "f1/Mcount_wr_addr_xor<12>_rt") (joined
+          (portref O (instanceref f1_Mcount_wr_addr_xor_12__rt))
+          (portref LI (instanceref f1_Mcount_wr_addr_xor_12_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_3_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215))
+          (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full921))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218))
+          (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_debug1_16_BRB0 "slave_fifo32/debug1_16_BRB0") (joined
+          (portref Q (instanceref slave_fifo32_debug1_16_BRB0))
+          (portref I0 (instanceref f0_i_tready1_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5_))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218))
+          (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tvalid "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tvalid") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tvalid11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[3]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111))
+          (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7_))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In11))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0144_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[4]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112))
+          (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8_))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[5]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112))
+          (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[9]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[6]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112))
+          (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[7]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111))
+          (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1))
+          (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+          )
+         )
+         (net SRX1_RX (joined
+          (portref O (instanceref SRX1_RX_OBUF))
+          (portref SRX1_RX)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_1_))
+          )
+         )
+         (net SRX1_TX (joined
+          (portref O (instanceref SRX1_TX_OBUF))
+          (portref SRX1_TX)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<0>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2_))
+          )
+         )
+         (net (rename f1_Mcount_rd_addr_cy_8__rt "f1/Mcount_rd_addr_cy<8>_rt") (joined
+          (portref O (instanceref f1_Mcount_rd_addr_cy_8__rt))
+          (portref S (instanceref f1_Mcount_rd_addr_cy_8_))
+          (portref LI (instanceref f1_Mcount_rd_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7_))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_lut_10_ "f0/Msub_dont_write_past_me_lut[10]") (joined
+          (portref S (instanceref f0_Msub_dont_write_past_me_cy_10_))
+          (portref LI (instanceref f0_Msub_dont_write_past_me_xor_10_))
+          (portref O (instanceref f0_Msub_dont_write_past_me_lut_10__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[0]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_lut_11_ "f0/Msub_dont_write_past_me_lut[11]") (joined
+          (portref S (instanceref f0_Msub_dont_write_past_me_cy_11_))
+          (portref LI (instanceref f0_Msub_dont_write_past_me_xor_11_))
+          (portref O (instanceref f0_Msub_dont_write_past_me_lut_11__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv1_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[1]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_lut_12_ "f0/Msub_dont_write_past_me_lut[12]") (joined
+          (portref LI (instanceref f0_Msub_dont_write_past_me_xor_12_))
+          (portref O (instanceref f0_Msub_dont_write_past_me_lut_12__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_full "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/full") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_write1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_i_tready1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set))
+          (portref full (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f0_Mcount_rd_addr_cy_4__rt "f0/Mcount_rd_addr_cy<4>_rt") (joined
+          (portref O (instanceref f0_Mcount_rd_addr_cy_4__rt))
+          (portref S (instanceref f0_Mcount_rd_addr_cy_4_))
+          (portref LI (instanceref f0_Mcount_rd_addr_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[2]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91))
+          )
+         )
+         (net (rename slave_fifo32_state_FSM_FFd2_In "slave_fifo32/state_FSM_FFd2-In") (joined
+          (portref D (instanceref slave_fifo32_state_FSM_FFd2))
+          (portref O (instanceref slave_fifo32_state_FSM_FFd2_In3))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[3]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[4]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[5]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state_glue_set") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set))
+          )
+         )
+         (net (rename f1_Mcompar_becoming_full_cy_0_ "f1/Mcompar_becoming_full_cy[0]") (joined
+          (portref O (instanceref f1_Mcompar_becoming_full_cy_0_))
+          (portref CI (instanceref f1_Mcompar_becoming_full_cy_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[6]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131))
+          )
+         )
+         (net (rename f1_Mcompar_becoming_full_cy_1_ "f1/Mcompar_becoming_full_cy[1]") (joined
+          (portref O (instanceref f1_Mcompar_becoming_full_cy_1_))
+          (portref CI (instanceref f1_Mcompar_becoming_full_cy_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[10]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_11_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[7]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_7))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_8_))
+          )
+         )
+         (net (rename f1_Mcompar_becoming_full_cy_2_ "f1/Mcompar_becoming_full_cy[2]") (joined
+          (portref O (instanceref f1_Mcompar_becoming_full_cy_2_))
+          (portref CI (instanceref f1_Mcompar_becoming_full_cy_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[8]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_8))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151))
+          )
+         )
+         (net (rename f1_Mcompar_becoming_full_cy_3_ "f1/Mcompar_becoming_full_cy[3]") (joined
+          (portref O (instanceref f1_Mcompar_becoming_full_cy_3_))
+          (portref CI (instanceref f1_Mcompar_becoming_full_cy_4_))
+          )
+         )
+         (net (rename f0_Result_5_1_FRB "f0/Result<5>1_FRB") (joined
+          (portref D (instanceref f0_rd_addr_5))
+          (portref Q (instanceref f0_Result_5_1_FRB))
+          (portref I0 (instanceref f0_Mcount_rd_addr_cy_5__rt))
+          (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_5__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_state_FSM_FFd1 "slave_fifo32/state_FSM_FFd1") (joined
+          (portref D (instanceref slave_fifo32_debug1_23))
+          (portref Q (instanceref slave_fifo32_state_FSM_FFd1))
+          (portref I0 (instanceref slave_fifo32__n0230_inv1))
+          (portref I2 (instanceref slave_fifo32__n0223_inv1))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT171))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT181))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT211))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT41))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT51))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT61))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT71))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT81))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT91))
+          (portref I3 (instanceref slave_fifo32__n0237_inv1))
+          (portref I1 (instanceref slave_fifo32__n0290_inv1))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1))
+          (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0))
+          (portref I1 (instanceref slave_fifo32__n0279_inv))
+          (portref I0 (instanceref slave_fifo32_state_FSM_FFd2_In2))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1))
+          (portref I4 (instanceref slave_fifo32_wr_one_rstpot))
+          (portref I3 (instanceref slave_fifo32_slrd_rstpot))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_write1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1))
+          (portref I4 (instanceref slave_fifo32_sloe_1_rstpot))
+          (portref S (instanceref slave_fifo32_state_FSM_FFd1_In3))
+          (portref I4 (instanceref slave_fifo32_ctrl_tx_tvalid1))
+          (portref I4 (instanceref slave_fifo32_data_tx_tvalid1))
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+          )
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+          (portref Q (instanceref slave_fifo32_state_FSM_FFd2))
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+          (portref I0 (instanceref slave_fifo32_Mcount_idle_cycles_xor_2_11))
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+          (portref I4 (instanceref slave_fifo32__n0237_inv1))
+          (portref I4 (instanceref slave_fifo32__n0290_inv1))
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+          (portref I4 (instanceref slave_fifo32_slrd_rstpot))
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+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1))
+          (portref I5 (instanceref slave_fifo32_sloe_1_rstpot))
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+          (portref I0 (instanceref slave_fifo32_state_FSM_FFd1_In3_G))
+          (portref I1 (instanceref slave_fifo32_ctrl_tx_tvalid1))
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+          )
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+          (portref codec_data_clk_p)
+          )
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+          )
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+          (portref SRX2_RX)
+          )
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+          )
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+          )
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+          (portref SRX2_TX)
+          )
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+          )
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+          )
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+          )
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+          )
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+          )
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+          )
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+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_))
+          )
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+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9_))
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+          )
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+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set))
+          )
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+          (portref (member din 71) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
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+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+          )
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+          )
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+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
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+          )
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+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212))
+          )
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+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G))
+          )
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+          )
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+          )
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+          )
+         )
+         (net (rename f0_Result_3_2_FRB "f0/Result<3>2_FRB") (joined
+          (portref D (instanceref f0_wr_addr_3))
+          (portref Q (instanceref f0_Result_3_2_FRB))
+          (portref I0 (instanceref f0_Mcount_wr_addr_cy_3__rt))
+          )
+         )
+         (net (rename debug_10_ "debug[10]") (joined
+          (portref O (instanceref debug_10_OBUF))
+          (portref (member debug 21))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[1]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_1_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1))
+          )
+         )
+         (net (rename debug_11_ "debug[11]") (joined
+          (portref O (instanceref debug_11_OBUF))
+          (portref (member debug 20))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[2]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_2_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_2_))
+          )
+         )
+         (net (rename debug_12_ "debug[12]") (joined
+          (portref O (instanceref debug_12_OBUF))
+          (portref (member debug 19))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/full_reg_glue_set") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[3]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_3_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<7>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_7_))
+          )
+         )
+         (net (rename debug_13_ "debug[13]") (joined
+          (portref O (instanceref debug_13_OBUF))
+          (portref (member debug 18))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr1_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[4]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_4_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_4_))
+          )
+         )
+         (net (rename debug_14_ "debug[14]") (joined
+          (portref O (instanceref debug_14_OBUF))
+          (portref (member debug 17))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[5]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_5_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_5_))
+          )
+         )
+         (net (rename debug_20_ "debug[20]") (joined
+          (portref O (instanceref debug_20_OBUF))
+          (portref (member debug 11))
+          )
+         )
+         (net (rename debug_15_ "debug[15]") (joined
+          (portref O (instanceref debug_15_OBUF))
+          (portref (member debug 16))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[6]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_6_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_6_))
+          )
+         )
+         (net (rename debug_21_ "debug[21]") (joined
+          (portref O (instanceref debug_21_OBUF))
+          (portref (member debug 10))
+          )
+         )
+         (net (rename debug_16_ "debug[16]") (joined
+          (portref O (instanceref debug_16_OBUF))
+          (portref (member debug 15))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[7]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_7_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_7_))
+          )
+         )
+         (net (rename debug_22_ "debug[22]") (joined
+          (portref O (instanceref debug_22_OBUF))
+          (portref (member debug 9))
+          )
+         )
+         (net (rename debug_17_ "debug[17]") (joined
+          (portref O (instanceref debug_17_OBUF))
+          (portref (member debug 14))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[8]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_8_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_8_))
+          )
+         )
+         (net (rename debug_23_ "debug[23]") (joined
+          (portref O (instanceref debug_23_OBUF))
+          (portref (member debug 8))
+          )
+         )
+         (net (rename debug_18_ "debug[18]") (joined
+          (portref O (instanceref debug_18_OBUF))
+          (portref (member debug 13))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<9>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[9]") (joined
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_9_))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_9_))
+          )
+         )
+         (net (rename debug_24_ "debug[24]") (joined
+          (portref O (instanceref debug_24_OBUF))
+          (portref (member debug 7))
+          )
+         )
+         (net (rename debug_19_ "debug[19]") (joined
+          (portref O (instanceref debug_19_OBUF))
+          (portref (member debug 12))
+          )
+         )
+         (net (rename debug_30_ "debug[30]") (joined
+          (portref O (instanceref debug_30_OBUF))
+          (portref (member debug 1))
+          )
+         )
+         (net (rename debug_25_ "debug[25]") (joined
+          (portref O (instanceref debug_25_OBUF))
+          (portref (member debug 6))
+          )
+         )
+         (net (rename slave_fifo32_state_1__wr_fifo_xfer_Mux_21_o "slave_fifo32/state[1]_wr_fifo_xfer_Mux_21_o") (joined
+          (portref D (instanceref slave_fifo32_slwr))
+          (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1))
+          (portref D (instanceref slave_fifo32_slwr_1))
+          )
+         )
+         (net (rename debug_31_ "debug[31]") (joined
+          (portref O (instanceref debug_31_OBUF))
+          (portref (member debug 0))
+          )
+         )
+         (net (rename debug_26_ "debug[26]") (joined
+          (portref O (instanceref debug_26_OBUF))
+          (portref (member debug 5))
+          )
+         )
+         (net (rename debug_27_ "debug[27]") (joined
+          (portref O (instanceref debug_27_OBUF))
+          (portref (member debug 4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr1") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr2") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr3") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr4") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4))
+          )
+         )
+         (net (rename debug_28_ "debug[28]") (joined
+          (portref O (instanceref debug_28_OBUF))
+          (portref (member debug 3))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr5") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr6") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv") (joined
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6))
+          (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr7") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7))
+          )
+         )
+         (net (rename f1_Result_1_1_FRB "f1/Result<1>1_FRB") (joined
+          (portref D (instanceref f1_rd_addr_1))
+          (portref Q (instanceref f1_Result_1_1_FRB))
+          (portref I0 (instanceref f1_Mcount_rd_addr_cy_1__rt))
+          (portref I0 (instanceref f1_Msub_dont_write_past_me_cy_1__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr8") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr9") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9))
+          )
+         )
+         (net (rename debug_29_ "debug[29]") (joined
+          (portref O (instanceref debug_29_OBUF))
+          (portref (member debug 2))
+          )
+         )
+         (net (rename debug_clk_0_ "debug_clk[0]") (joined
+          (portref O (instanceref debug_clk_0_OBUF))
+          (portref (member debug_clk 1))
+          )
+         )
+         (net (rename debug_clk_1_ "debug_clk[1]") (joined
+          (portref O (instanceref debug_clk_1_OBUF))
+          (portref (member debug_clk 0))
+          )
+         )
+         (net rx_bandsel_a (joined
+          (portref O (instanceref rx_bandsel_a_OBUF))
+          (portref rx_bandsel_a)
+          )
+         )
+         (net rx_bandsel_b (joined
+          (portref O (instanceref rx_bandsel_b_OBUF))
+          (portref rx_bandsel_b)
+          )
+         )
+         (net rx_bandsel_c (joined
+          (portref O (instanceref rx_bandsel_c_OBUF))
+          (portref rx_bandsel_c)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_dont_write_past_me_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/dont_write_past_me[9]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr1_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1__rt))
+          )
+         )
+         (net gps_out_enable (joined
+          (portref O (instanceref gps_out_enable_OBUF))
+          (portref gps_out_enable)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_6))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[0]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>11") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_1_11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_3_11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o") (joined
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[1]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[2]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[3]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[4]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net SFDX1_RX (joined
+          (portref O (instanceref SFDX1_RX_OBUF))
+          (portref SFDX1_RX)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full61 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full61") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full611))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[5]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full62 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full62") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full621))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_11))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[6]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_6_1))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_space_xor<3>11") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_4_11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_3_11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_1_11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_2_11))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv))
+          )
+         )
+         (net SFDX1_TX (joined
+          (portref O (instanceref SFDX1_TX_OBUF))
+          (portref SFDX1_TX)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW0))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set))
+          (portref I2 (instanceref slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tvalid11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo__n0146_inv1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt__n0074_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") (joined
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo__n0146_inv1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tvalid "slave_fifo32/fifo64_to_gpmc32_tx/o64_tvalid") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tvalid11))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[9]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_10_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy[10]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_10_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_11_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy[11]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_11_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12_))
+          )
+         )
+         (net (rename f1_dont_write_past_me_11__FRB "f1/dont_write_past_me<11>_FRB") (joined
+          (portref I5 (instanceref f1_Mcompar_becoming_full_lut_3_))
+          (portref Q (instanceref f1_dont_write_past_me_11__FRB))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy[12]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy[13]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_14_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_14_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_))
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy[14]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_14_))
+          (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15_))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_0_ "slave_fifo32/gpif_data_in[0]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_0))
+          (portref D (instanceref slave_fifo32_debug1_0))
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tvalid "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tvalid") (joined
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tvalid11))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write1))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_1_ "slave_fifo32/gpif_data_in[1]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_1))
+          (portref D (instanceref slave_fifo32_debug1_1))
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_2_ "slave_fifo32/gpif_data_in[2]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_2))
+          (portref D (instanceref slave_fifo32_debug1_2))
+          (portref (member DIA 29) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 29) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32__n0279_inv "slave_fifo32/_n0279_inv") (joined
+          (portref O (instanceref slave_fifo32__n0279_inv))
+          (portref D (instanceref slave_fifo32_rd_one_BRB0))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_3_ "slave_fifo32/gpif_data_in[3]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_3))
+          (portref D (instanceref slave_fifo32_debug1_3))
+          (portref (member DIA 28) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 28) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/GND_66_o_read_OR_144_o") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1))
+          (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr4_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_4))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr4_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__rt))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_4_ "slave_fifo32/gpif_data_in[4]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_4))
+          (portref D (instanceref slave_fifo32_debug1_4))
+          (portref (member DIA 27) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 27) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty") (joined
+          (portref I0 (instanceref f1_write11))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0))
+          (portref I3 (instanceref f1_read_state_FSM_FFd2_In1))
+          (portref I0 (instanceref f1_full_reg_glue_set))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_5_ "slave_fifo32/gpif_data_in[5]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_5))
+          (portref D (instanceref slave_fifo32_debug1_5))
+          (portref (member DIA 26) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 26) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr9_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_9))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__rt))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_6_ "slave_fifo32/gpif_data_in[6]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_6))
+          (portref D (instanceref slave_fifo32_debug1_6))
+          (portref (member DIA 25) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[0]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_7_ "slave_fifo32/gpif_data_in[7]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_7))
+          (portref D (instanceref slave_fifo32_debug1_7))
+          (portref (member DIA 24) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[1]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_8_ "slave_fifo32/gpif_data_in[8]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_8))
+          (portref D (instanceref slave_fifo32_debug1_8))
+          (portref (member DIA 23) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[2]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31))
+          )
+         )
+         (net (rename slave_fifo32_gpif_data_in_9_ "slave_fifo32/gpif_data_in[9]") (joined
+          (portref Q (instanceref slave_fifo32_gpif_data_in_9))
+          (portref D (instanceref slave_fifo32_debug1_9))
+          (portref (member DIA 22) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram))
+          (portref (member DIA 22) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[5]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[3]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[6]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[0]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[4]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[7]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[1]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[5]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6))
+          )
+         )
+         (net SFDX2_RX (joined
+          (portref O (instanceref SFDX2_RX_OBUF))
+          (portref SFDX2_RX)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[8]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[2]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[6]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_lut_2_ "f0/Msub_dont_write_past_me_lut[2]") (joined
+          (portref S (instanceref f0_Msub_dont_write_past_me_cy_2_))
+          (portref LI (instanceref f0_Msub_dont_write_past_me_xor_2_))
+          (portref O (instanceref f0_Msub_dont_write_past_me_lut_2__INV_0))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_cy_0_ "f0/Msub_dont_write_past_me_cy[0]") (joined
+          (portref O (instanceref f0_Msub_dont_write_past_me_cy_0_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_cy_1_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_xor_1_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[9]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[3]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[7]") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7))
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_lut_3_ "f0/Msub_dont_write_past_me_lut[3]") (joined
+          (portref S (instanceref f0_Msub_dont_write_past_me_cy_3_))
+          (portref LI (instanceref f0_Msub_dont_write_past_me_xor_3_))
+          (portref O (instanceref f0_Msub_dont_write_past_me_lut_3__INV_0))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_cy_1_ "f0/Msub_dont_write_past_me_cy[1]") (joined
+          (portref O (instanceref f0_Msub_dont_write_past_me_cy_1_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_cy_2_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_xor_2_))
+          )
+         )
+         (net SFDX2_TX (joined
+          (portref O (instanceref SFDX2_TX_OBUF))
+          (portref SFDX2_TX)
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[4]") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_full "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/full") (joined
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_i_tready1))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_write1))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set))
+          (portref full (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_lut_4_ "f0/Msub_dont_write_past_me_lut[4]") (joined
+          (portref S (instanceref f0_Msub_dont_write_past_me_cy_4_))
+          (portref LI (instanceref f0_Msub_dont_write_past_me_xor_4_))
+          (portref O (instanceref f0_Msub_dont_write_past_me_lut_4__INV_0))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_cy_2_ "f0/Msub_dont_write_past_me_cy[2]") (joined
+          (portref O (instanceref f0_Msub_dont_write_past_me_cy_2_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_cy_3_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_xor_3_))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_lut_5_ "f0/Msub_dont_write_past_me_lut[5]") (joined
+          (portref S (instanceref f0_Msub_dont_write_past_me_cy_5_))
+          (portref LI (instanceref f0_Msub_dont_write_past_me_xor_5_))
+          (portref O (instanceref f0_Msub_dont_write_past_me_lut_5__INV_0))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_cy_3_ "f0/Msub_dont_write_past_me_cy[3]") (joined
+          (portref O (instanceref f0_Msub_dont_write_past_me_cy_3_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_cy_4_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_xor_4_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o5") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41))
+          (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o7") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61))
+          (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212))
+          (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr3_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_3))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o8") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_lut_6_ "f0/Msub_dont_write_past_me_lut[6]") (joined
+          (portref S (instanceref f0_Msub_dont_write_past_me_cy_6_))
+          (portref LI (instanceref f0_Msub_dont_write_past_me_xor_6_))
+          (portref O (instanceref f0_Msub_dont_write_past_me_lut_6__INV_0))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_cy_4_ "f0/Msub_dont_write_past_me_cy[4]") (joined
+          (portref O (instanceref f0_Msub_dont_write_past_me_cy_4_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_cy_5_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_xor_5_))
+          )
+         )
+         (net (rename slave_fifo32_write_ready_go "slave_fifo32/write_ready_go") (joined
+          (portref Q (instanceref slave_fifo32_write_ready_go))
+          (portref I1 (instanceref slave_fifo32__n0258_inv_SW0))
+          (portref I0 (instanceref slave_fifo32__n0279_inv_SW0))
+          (portref I5 (instanceref slave_fifo32_state_FSM_FFd2_In2))
+          (portref I4 (instanceref slave_fifo32_state_FSM_FFd1_In3_F))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_lut_7_ "f0/Msub_dont_write_past_me_lut[7]") (joined
+          (portref S (instanceref f0_Msub_dont_write_past_me_cy_7_))
+          (portref LI (instanceref f0_Msub_dont_write_past_me_xor_7_))
+          (portref O (instanceref f0_Msub_dont_write_past_me_lut_7__INV_0))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_cy_5_ "f0/Msub_dont_write_past_me_cy[5]") (joined
+          (portref O (instanceref f0_Msub_dont_write_past_me_cy_5_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_cy_6_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_xor_6_))
+          )
+         )
+         (net (rename debug_0_ "debug[0]") (joined
+          (portref O (instanceref debug_0_OBUF))
+          (portref (member debug 31))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_lut_8_ "f0/Msub_dont_write_past_me_lut[8]") (joined
+          (portref S (instanceref f0_Msub_dont_write_past_me_cy_8_))
+          (portref LI (instanceref f0_Msub_dont_write_past_me_xor_8_))
+          (portref O (instanceref f0_Msub_dont_write_past_me_lut_8__INV_0))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_cy_6_ "f0/Msub_dont_write_past_me_cy[6]") (joined
+          (portref O (instanceref f0_Msub_dont_write_past_me_cy_6_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_cy_7_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_xor_7_))
+          )
+         )
+         (net (rename debug_1_ "debug[1]") (joined
+          (portref O (instanceref debug_1_OBUF))
+          (portref (member debug 30))
+          )
+         )
+         (net fx3_ce (joined
+          (portref I (instanceref fx3_ce_IBUF))
+          (portref fx3_ce)
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_lut_9_ "f0/Msub_dont_write_past_me_lut[9]") (joined
+          (portref S (instanceref f0_Msub_dont_write_past_me_cy_9_))
+          (portref LI (instanceref f0_Msub_dont_write_past_me_xor_9_))
+          (portref O (instanceref f0_Msub_dont_write_past_me_lut_9__INV_0))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_cy_7_ "f0/Msub_dont_write_past_me_cy[7]") (joined
+          (portref O (instanceref f0_Msub_dont_write_past_me_cy_7_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_cy_8_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_xor_8_))
+          )
+         )
+         (net (rename debug_2_ "debug[2]") (joined
+          (portref O (instanceref debug_2_OBUF))
+          (portref (member debug 29))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_cy_8_ "f0/Msub_dont_write_past_me_cy[8]") (joined
+          (portref O (instanceref f0_Msub_dont_write_past_me_cy_8_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_cy_9_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_xor_9_))
+          )
+         )
+         (net (rename debug_3_ "debug[3]") (joined
+          (portref O (instanceref debug_3_OBUF))
+          (portref (member debug 28))
+          )
+         )
+         (net (rename f0_Msub_dont_write_past_me_cy_9_ "f0/Msub_dont_write_past_me_cy[9]") (joined
+          (portref O (instanceref f0_Msub_dont_write_past_me_cy_9_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_cy_10_))
+          (portref CI (instanceref f0_Msub_dont_write_past_me_xor_10_))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr3_FRB") (joined
+          (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3))
+          (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB))
+          (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421))
+          (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411))
+          (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621))
+          )
+         )
+         (net (rename debug_4_ "debug[4]") (joined
+          (portref O (instanceref debug_4_OBUF))
+          (portref (member debug 27))
+          )
+         )
+         (net (rename debug_5_ "debug[5]") (joined
+          (portref O (instanceref debug_5_OBUF))
+          (portref (member debug 26))
+          )
+         )
+         (net (rename debug_6_ "debug[6]") (joined
+          (portref O (instanceref debug_6_OBUF))
+          (portref (member debug 25))
+          )
+         )
+         (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") (joined
+          (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt))
+          (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_))
+          (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_))
+          )
+         )
+         (net (rename debug_7_ "debug[7]") (joined
+          (portref O (instanceref debug_7_OBUF))
+          (portref (member debug 24))
+          )
+         )
+         (net (rename debug_8_ "debug[8]") (joined
+          (portref O (instanceref debug_8_OBUF))
+          (portref (member debug 23))
+          )
+         )
+         (net (rename debug_9_ "debug[9]") (joined
+          (portref O (instanceref debug_9_OBUF))
+          (portref (member debug 22))
+          )
+         )
+       )
+
+           (property TYPE (string "b200"))
+           (property BUS_INFO (string "32:INOUT:GPIF_D<31:0>"))
+           (property SHREG_MIN_SIZE (string "2"))
+           (property X_CORE_INFO (string "fifo_generator_v9_3, Xilinx CORE Generator 14.4"))
+           (property CORE_GENERATION_INFO (string "b200_clk_gen,clk_wiz_v3_6,{component_name=b200_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"))
+           (property SHREG_EXTRACT_NGC (string "YES"))
+           (property NLW_UNIQUE_ID (integer 0))
+           (property NLW_MACRO_TAG (integer 0))
+           (property NLW_MACRO_ALIAS (string "b200_b200"))
+     )
+   )
+  )
+(comment "Reference To The Cell Of Highest Level")
+
+  (design b200
+    (cellref b200 (libraryref b200_lib))
+    (property PART (string "xc6slx75fgg484-3"))
+  )
+)
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ncd b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ncd
new file mode 100644
index 000000000..2ef54e4b7
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ncd
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
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FcmDdBVkuw2QTgD+XvYK5HzTb4Rn/ReKX4KyTDCR5MEkhARiv5vYE9y0u1yo7zbizvE1w4y4qGYaVCKVlbzjMGQDzzuBB5Wn2tt72pHQsweHzRsZyjrp7CTTND2Mr6+y3QQhqhzOtRvBll6R9D8R6S5Bktmu3S12N9jd6/+bdTnkhIqzoAJwXkhvLDMqyavpfc6q+nTrF/4i8C9Sa9jtTM1UoFcVPeFeMe2KlCcR0FhYwLHQTOdwmBwOOpbWMXifhz3fT9cHPj8ipUQpUyqUKqVGqVOivfP2atKitNnuonRTcpQ8pTP3usVk06cULMZN2LAyaQZGZDt7iORVH30THmTl1dJfCVtfFabRGRit2OHRX9loo2Z6nufUIJiILsCrYCmpbpTHyDQ4l5utjU9hp8pid7fN1lOrPDZVSarif1QCVIb2gvmhKvpoH7GgVDCvXMsdjsXrxzHl+IRNFQfHMiaDNhTlAALlI64flQAV2fpUpZmK7d1FbhP5P83ieJ/iK57OZTjrM3nFM7l4EJuBJw/msps/kWAFqj1+s6ngRXCMdTRUgNc4LDoGQ1VAo8OD/gjfvGnokake13cwvMNscpV+mvVVjdIpql/DEYbP9iC1BvuwRUcNDxpeNFxguCkGk+SG+B0cinTAyquGGwxPGm40zIlR1XK8bcXUMUSXLbf3T24HLC9arrRcabnDebmuBWEKPc77W+gIskpmGw7PKmlPI/4uxqTwd7VLu78b9uhjRaksd75BnwoX/m8Jl87Xf6RsCb1RVZRQJJfxbsSUtYTAI5KjdFMSPtEhxilrwSVKFYwHobKotCAdttGR7nGuCk6ZQw7/y4hB2SlFelk55uEdvg1lBxTppc4ofX7j9zJzkRZXJlXHGrZvww2LMgalod57HrH90KkKwlKeU4xfYpVef/eNP/IkOxrWkSws/lGx3fVtqGEdqbFh00l5z68TcaF6kW0k530lRCmRxfmv7UEnLBMkw5/CT8MNJ5AJEroPwGhYGVZFWI7sU/4hp2Ta88E8k8w4nbFzlH6TybQVzmv2P0zbaFxa0GX3h2krp+9Tq+4p9eZl2h7Vp4gk3QSmbUOvT5HW7nT/MG0juLTa6zVJl51Gl5WvYFWYtuWHaRuNS2sOX+HLtHXGw7WR5fz+YdpGIcPulyvbyLTdZNqml2mbfpi2on1+4YX2Tabt0lxpNZi284dpK9pyfDSmbSHTdupfGm73ATLsoc1+mbYRVFpwZfeXaetAxEXcd/9h2qrn/eXpJjJt+yduMm0Dmbbhh3HalGnbfpi27q82BNs1TTJtmy3LrsSXaet/mLYO1WDaJjJtk52ynP2JItrjh2kr2qehrk2uXOC3nw/JMiOFSmt8VVD4jGnrrBqel0rPcU05ZdReP0xbZ9Vk2i4ybZedOpRxqllbP5CItjTUJSIvUu+H3SSlDFnbP8NBtVd+ubKI+0jadx6NHOH9MxRVe1/seyPuFLBQC5V2GNP2ZxqYdoV2uRyZts4Q8/v/9dNW2Q==###6664:XlxV32DM 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   14bd     614eNrFmEuO4zgQRC8zB+D/500foBfTR+B32UCtC3X3CWVIXrGAQbcMb4hny84MUhQzQ0U9fs+Vinp8/fRVFfv54fPCd7OX85J+fH19fc46iiqu2OJ7a8UPgz+Zxz9zKXzTAXMW7/Lj55yjmM/vov2PRPNKNOLAMOsmkV03JFqSyBc/FbLNaDBMZFlublKayJTuD1N+d8l8f8lSaFOX0BUqhhZLUJAclFu7mzDeJlSfQoPyE0MfJWjbMNS8E2rfJtSceyzoDrXGbPdY+/s91uyVyDhb1sKPN+vgbkjknolqKsGqsUs0b0jkr0TWhDIdnprN0pkbEsVrM9mELWRXLcEFzM2NsHs889s2U7qEumVK8EFj6KuEYHc3wcy3Cc2X0OAzhoGbGB2e0djjbrf0twmtl9A4QwnJg1KH2mz1Tqh5m9B2PQz5WMfcdueIUzc8DP2Z6Lhr1e6qr+03JLrKfKhelxXddkb+hkTzmaiFopWp20w31Pm2rkxN4yBpaXcGW/v3iTrrtEOOjOerKxxWPe4OK5uYzd6/Y0WIuYT0jBNpKJxII+x6Be9eK+RZ/sZxho+127am3rD07prx1JjsxD0OR/DN0tfXzthfR9cyWPqVoWatVaIK24qs33V09XCuWFQpY8CVqMN2s8bXrli8hOhkMCxdovHbzWpfKyRdQkxsGGA8ovXbgza/Vki+hNjUS3QqYNifWvqFQr5+/Pj38xcqnHr8whX9+MCjhQ8f2vCTWXOVLLAijnBSelIrLi7+cGGLpxjJC7wG2CqcTC4nS8aU81rkUFxNnpyKa6qRKzhrMmJ2dcZZZUYXhCHP9VjJrqRRDTni+8H4Ohc30HcLd7BnHD2hPp1/MBA3+sm2uGkiGeKmU2SIQ3UmQ9yyFGEgbsXzN5jwmhSEBsarwMQWrlONSQ7gc1FQ3L0OzAv35HXk5NFOej0Z02Eb6JXJMK7GM47zh1OlThfBg9pQx71ZXFDXC9bt/M3CLjpzoeB7O7i43h7+jIuF9su7Sm14HtAYMq+vxzPJefkOrpw7vJ8PlnHQDPvQGCcgZrTUHxAzZmoL0JnOtT0MbmrUGRAzG2pD9fL5nGNEzNypJyJmtVyf6Esf5mTorJU6I2I2nciI2RJ1Ruhsi/ciIWbX1JaOlxyR8VOQFx7kJO89yE3eT5D5mkI4K3mdQDbyVoHs5OUCOcg7BnIWV09uYu7JQzw+eYnVF65GzDXZiccmB7Ha5CSOm9zE45KHWF3hpsSSko04U7IXB0mOYiTJVQwfuYvvIy/xZ8Jdi00jW3FrZC+mjZzEJpGruCVyF9NEnuKdhIcWt0K2YlrIXrwLOYqFIVcxDeQu3oE8xUIITyVOgszeneylhScnabXJVTpu8pDOmLykQRY+nB8aWbJjP8sPUfpOcpb2k9ylTSRP6RYP1kpJ00i20sGRvTRy5Cj9HLlKc0Xu0mORl/RCwmdLRLbSGZGDtCnkJN0KuUrTQu7Su5CXdAvCOByPpoFspXcgBynk5CT1nFylrJOH1FjyklIrjMPxqLhklj9ykCpITlIMH6hO/wGBe+Vy
\ No newline at end of file
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.twx b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.twx
new file mode 100644
index 000000000..7adb4c324
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.twx
@@ -0,0 +1,341 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE twReport [
+<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
+					twDebug*, twFoot?, twClientInfo?)>
+<!ATTLIST twReport version CDATA "10,4">
+<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
+<!ELEMENT twExecVer (#PCDATA)>
+<!ELEMENT twCopyright (#PCDATA)>
+<!ELEMENT twCmdLine (#PCDATA)>
+<!ELEMENT twDesign (#PCDATA)>
+<!ELEMENT twPCF (#PCDATA)>
+<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
+<!ELEMENT twDevName (#PCDATA)>
+<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
+<!ELEMENT twSpeedGrade (#PCDATA)>
+<!ELEMENT twSpeedVer (#PCDATA)>
+<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
+<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
+<!ATTLIST twRptInfo twAdvRpt  (TRUE | FALSE) "FALSE">
+<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
+<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
+<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
+<!ELEMENT twItemLimit (#PCDATA)>
+<!ELEMENT twUnconst EMPTY>
+<!ELEMENT twUnconstLimit (#PCDATA)>
+<!ELEMENT twEnvVar EMPTY>
+<!ATTLIST twEnvVar name CDATA #REQUIRED>
+<!ATTLIST twEnvVar description CDATA #REQUIRED>
+<!ELEMENT twWarn (#PCDATA)>
+<!ELEMENT twInfo (#PCDATA)>
+<!ELEMENT twDebug (#PCDATA)>
+<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
+<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
+<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
+<!ELEMENT twProc (#PCDATA)>
+<!ELEMENT twTemp (#PCDATA)>
+<!ELEMENT twVolt (#PCDATA)>
+<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
+<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG |  twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
+<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
+<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)> 
+<!ELEMENT twCycles (twSigConn+)>
+<!ATTLIST twCycles twNum CDATA #REQUIRED>
+<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
+<!ELEMENT twSig (#PCDATA)>
+<!ELEMENT twDriver (#PCDATA)>
+<!ELEMENT twLoad (#PCDATA)> 
+<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* |  (twPathRpt*, twRacePathRpt?) |  twNetRpt* | twClkSkewLimit*))>
+<!ATTLIST twConst twConstType (NET | 
+							   NETDELAY | 
+							   NETSKEW | 
+							   PATH |
+							   DEFPERIOD |
+							   UNCONSTPATH |
+							   DEFPATH | 
+							   PATH2SETUP |
+							   UNCONSTPATH2SETUP | 
+							   PATHCLASS | 
+							   PATHDELAY | 
+							   PERIOD |
+							   FREQUENCY |
+							   PATHBLOCK |
+							   OFFSET |
+							   OFFSETIN |
+							   OFFSETINCLOCK | 
+							   UNCONSTOFFSETINCLOCK |
+							   OFFSETINDELAY |
+							   OFFSETINMOD |
+							   OFFSETOUT |
+							   OFFSETOUTCLOCK |
+							   UNCONSTOFFSETOUTCLOCK | 
+							   OFFSETOUTDELAY |
+							   OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED> 
+<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
+					   twEndPtCnt?,
+					   twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
+<!ELEMENT twConstName (#PCDATA)>
+<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
+<!ATTLIST twConstHead uID CDATA #IMPLIED>
+<!ELEMENT twItemCnt (#PCDATA)>
+<!ELEMENT twErrCnt (#PCDATA)>
+<!ELEMENT twErrCntEndPt (#PCDATA)>
+<!ELEMENT twErrCntSetup (#PCDATA)>
+<!ELEMENT twErrCntHold (#PCDATA)>
+<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
+<!ELEMENT twEndPtCnt (#PCDATA)>
+<!ELEMENT twPathErrCnt (#PCDATA)>
+<!ELEMENT twMinPer (#PCDATA) >
+<!ELEMENT twFootnote EMPTY>
+<!ATTLIST twFootnote number CDATA #REQUIRED>
+<!ELEMENT twMaxDel (#PCDATA)>
+<!ELEMENT twMaxFreq (#PCDATA)>
+<!ELEMENT twMinOff (#PCDATA)>
+<!ELEMENT twMaxOff (#PCDATA)>
+<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
+<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
+<!ELEMENT twTIGName (#PCDATA)>
+<!ELEMENT twInstantiated (#PCDATA)>
+<!ELEMENT twBlocked (#PCDATA)>
+<!ELEMENT twRacePathRpt (twRacePath+)>
+<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
+<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest,  (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
+<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
+						twSimpleMinPath CDATA #IMPLIED>
+<!ELEMENT twTotDel (#PCDATA)>
+<!ELEMENT twSrc (#PCDATA)>
+<!ATTLIST twSrc BELType CDATA #IMPLIED>
+<!ELEMENT twDest (#PCDATA)>
+<!ATTLIST twDest BELType CDATA #IMPLIED>
+<!ELEMENT twDel (#PCDATA)>
+<!ELEMENT twSUTime (#PCDATA)>
+<!ELEMENT twTotPathDel (#PCDATA)>
+<!ELEMENT twClkSkew (#PCDATA)>
+<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
+<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
+<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
+<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
+<!ELEMENT twSlack (#PCDATA)>
+<!ELEMENT twDelConst (#PCDATA)>
+<!ELEMENT tw2Phase EMPTY>
+<!ELEMENT twClkUncert (#PCDATA)>
+<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED  fInputJit CDATA #IMPLIED
+					  fDCMJit CDATA #IMPLIED
+					  fPhaseErr CDATA #IMPLIED
+					  sEqu CDATA #IMPLIED>
+<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
+<!ELEMENT twPathRptBanner (#PCDATA)>
+<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
+<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
+<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
+<!ELEMENT twOff (#PCDATA)>
+<!ELEMENT twGuaranteed EMPTY>
+<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
+<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
+<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
+<!ELEMENT twClkDel (#PCDATA)>
+<!ELEMENT twClkSrc (#PCDATA)>
+<!ELEMENT twClkDest (#PCDATA)>
+<!ELEMENT twGuarInSetup (#PCDATA)>
+<!ELEMENT twOffSrc (#PCDATA)>
+<!ELEMENT twOffDest (#PCDATA)>
+<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
+<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
+<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
+<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
+<!ELEMENT twDataDel (#PCDATA)>
+<!ELEMENT twDataSrc (#PCDATA)>
+<!ELEMENT twDataDest (#PCDATA)>
+<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
+<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
+<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
+<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
+<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
+<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
+<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
+<!ELEMENT twLogLvls (#PCDATA)>
+<!ELEMENT twSrcSite (#PCDATA)>
+<!ELEMENT twSrcClk (#PCDATA)>
+<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
+<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
+<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
+<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
+<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
+<!ELEMENT twDelInfo (#PCDATA)>
+<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
+<!ELEMENT twSite (#PCDATA)>
+<!ELEMENT twDelType (#PCDATA)>
+<!ELEMENT twFanCnt (#PCDATA)>
+<!ELEMENT twComp (#PCDATA)>
+<!ELEMENT twNet (#PCDATA)>
+<!ELEMENT twBEL (#PCDATA)>
+<!ELEMENT twLogDel (#PCDATA)>
+<!ELEMENT twRouteDel (#PCDATA)>
+<!ELEMENT twDestClk (#PCDATA)>
+<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
+<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
+<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
+<!ELEMENT twPctLog (#PCDATA)>
+<!ELEMENT twPctRoute (#PCDATA)>
+<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
+<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
+<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
+<!ELEMENT twTimeConst (#PCDATA)>
+<!ELEMENT twAbsSlack (#PCDATA)>
+<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
+<!ELEMENT twSkew (#PCDATA)>
+<!ELEMENT twDetNet (twNetDel*)>
+<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
+<!ELEMENT twNetDelInfo (#PCDATA)>
+<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
+<!ELEMENT twDetSkewNet (twNetSkew*)>
+<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
+<!ELEMENT twClkSkewLimit  EMPTY>
+<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED                      arrv1 CDATA #IMPLIED
+		         arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
+<!ELEMENT twConstRollupTable (twConstRollup*)>
+<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
+<!ELEMENT twConstRollup  EMPTY>
+<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED                      requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
+<!ATTLIST twConstRollup  actualRollup CDATA #IMPLIED                      errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED                      itemsRollup CDATA #IMPLIED>
+<!ELEMENT twConstList (twConstListItem)*>
+<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)> 
+<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
+<!ELEMENT twNotMet EMPTY>
+<!ELEMENT twReqVal (#PCDATA)>
+<!ELEMENT twActVal (#PCDATA)>
+<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
+<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
+<!ELEMENT twConstStats (twConstName)>
+<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
+<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
+<!ATTLIST twConstStats twActual CDATA #IMPLIED>
+<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
+<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
+<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
+<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
+<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
+<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
+<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
+<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED  slackIndex CDATA #IMPLIED>
+<!ELEMENT twConstData EMPTY>
+<!ATTLIST twConstData type CDATA #IMPLIED  units (MHz | ns) "ns" slack CDATA #IMPLIED
+					  best CDATA #IMPLIED requested CDATA #IMPLIED
+					  errors CDATA #IMPLIED
+					  score CDATA #IMPLIED>
+<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
+<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
+<!ELEMENT twTimeGrpName (#PCDATA)>
+<!ELEMENT twCompList (twCompName+)>
+<!ELEMENT twCompName (#PCDATA)>
+<!ELEMENT twSigList (twSigName+)>
+<!ELEMENT twSigName (#PCDATA)>
+<!ELEMENT twBELList (twBELName+)>
+<!ELEMENT twBELName (#PCDATA)>
+<!ELEMENT twBlockList (twBlockName+)>
+<!ELEMENT twBlockName (#PCDATA)>
+<!ELEMENT twMacList (twMacName+)>
+<!ELEMENT twMacName (#PCDATA)>
+<!ELEMENT twPinList (twPinName+)>
+<!ELEMENT twPinName (#PCDATA)>
+<!ELEMENT twUnmetConstCnt (#PCDATA)>
+<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
+<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
+<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
+<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
+<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
+<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
+<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
+<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
+<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
+<!ELEMENT twSU2ClkTime (#PCDATA)>
+<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ELEMENT twH2ClkTime (#PCDATA)>
+<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
+<!ELEMENT twClk2Pad (twDest, twTime)>
+<!ELEMENT twTime (#PCDATA)>
+<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
+<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
+<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
+<!ELEMENT twClk2Out EMPTY>
+<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
+<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
+<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
+<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
+<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
+<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
+<!ELEMENT twRiseRise (#PCDATA)>
+<!ELEMENT twFallRise (#PCDATA)>
+<!ELEMENT twRiseFall (#PCDATA)>
+<!ELEMENT twFallFall (#PCDATA)>
+<!ELEMENT twPad2PadList (twPad2Pad+)>
+<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
+<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
+<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
+<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
+<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
+<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
+<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
+<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
+<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
+<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
+<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
+<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
+<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
+<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
+<!ELEMENT twOffOutTblRow EMPTY>
+<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
+<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
+<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
+<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
+<!ELEMENT twNonDedClk (#PCDATA)>
+<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
+<!ELEMENT twScore (#PCDATA)>
+<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
+<!ELEMENT twPathCnt (#PCDATA)>
+<!ELEMENT twNetCnt (#PCDATA)>
+<!ELEMENT twConnCnt (#PCDATA)>
+<!ELEMENT twPct (#PCDATA)>
+<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
+<!ELEMENT twMaxCombDel (#PCDATA)>
+<!ELEMENT twMaxFromToDel (#PCDATA)>
+<!ELEMENT twMaxNetDel (#PCDATA)>
+<!ELEMENT twMaxNetSkew (#PCDATA)>
+<!ELEMENT twMaxInAfterClk (#PCDATA)>
+<!ELEMENT twMinInBeforeClk (#PCDATA)>
+<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
+<!ELEMENT twMinOutAfterClk (#PCDATA)>
+<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
+<!ELEMENT twTimestamp (#PCDATA)>
+<!ELEMENT twFootnoteExplanation EMPTY>
+<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
+<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
+<!ELEMENT twClientInfo (twClientName, twAttrList?)>
+<!ELEMENT twClientName (#PCDATA)>
+<!ELEMENT twAttrList (twAttrListItem)*>
+<!ELEMENT twAttrListItem (twName, twValue*)>
+<!ELEMENT twName (#PCDATA)>
+<!ELEMENT twValue (#PCDATA)>
+]>
+<twReport><twHead anchorID="1"><twExecVer>Release 14.1 Trace  (lin64)</twExecVer><twCopyright>Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.</twCopyright><twCmdLine>/opt/Xilinx/14.1/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -e 10 -s 3
+-n 3 -fastpaths -xml b200.twx b200.ncd -o b200.twr b200.pcf
+
+</twCmdLine><twDesign>b200.ncd</twDesign><twDesignPath>b200.ncd</twDesignPath><twPCF>b200.pcf</twPCF><twPcfPath>b200.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="fgg484"><twDevName>xc6slx75</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRODUCTION 1.21 2012-04-23</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twErr" twReportMinPaths="true"  dlyHyperLnks="t" ><twItemLimit>10</twItemLimit><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twErrRpt><twConst anchorID="5" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="" ScopeName="">TS_codec_main_clk = PERIOD TIMEGRP &quot;codec_main_clk&quot; 25 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>16.000</twMinPer></twConstHead><twPinLimitRpt anchorID="6"><twPinLimitBanner>Component Switching Limit Checks: TS_codec_main_clk = PERIOD TIMEGRP &quot;codec_main_clk&quot; 25 ns HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConst anchorID="7" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="" ScopeName="">TS_IFCLK = PERIOD TIMEGRP &quot;IFCLK&quot; 10 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt></twConstHead><twPinLimitRpt anchorID="8"><twPinLimitBanner>Component Switching Limit Checks: TS_IFCLK = PERIOD TIMEGRP &quot;IFCLK&quot; 10 ns HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConst anchorID="9" twConstType="PERIOD" ><twConstHead uID="3"><twConstName UCFConstName="" ScopeName="">TS_codec_data_clk_p = PERIOD TIMEGRP &quot;codec_data_clk_p&quot; 16.276 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.639</twMinPer></twConstHead><twPinLimitRpt anchorID="10"><twPinLimitBanner>Component Switching Limit Checks: TS_codec_data_clk_p = PERIOD TIMEGRP &quot;codec_data_clk_p&quot; 16.276 ns HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConst anchorID="11" twConstType="PERIOD" ><twConstHead uID="4"><twConstName UCFConstName="" ScopeName="">TS_gen_clks_clkfx = PERIOD TIMEGRP &quot;gen_clks_clkfx&quot; TS_codec_main_clk / 2.5         HIGH 50%;</twConstName><twItemCnt>48903</twItemCnt><twErrCntSetup>2</twErrCntSetup><twErrCntEndPt>2</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>9931</twEndPtCnt><twPathErrCnt>2</twPathErrCnt><twMinPer>12.189</twMinPer></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point slave_fifo32/EP_READY1 (OLOGIC_X4Y173.D1), 1 path
+</twPathRptBanner><twPathRpt anchorID="12"><twConstPath anchorID="13" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-2.189</twSlack><twSrc BELType="FF">slave_fifo32/EP_READY</twSrc><twDest BELType="FF">slave_fifo32/EP_READY1</twDest><twTotPathDel>12.263</twTotPathDel><twClkSkew dest = "1.637" src = "1.328">-0.309</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.400" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.235</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>slave_fifo32/EP_READY</twSrc><twDest BELType='FF'>slave_fifo32/EP_READY1</twDest><twLogLvls>0</twLogLvls><twSrcSite>ILOGIC_X17Y55.CLK0</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">gpif_clk</twSrcClk><twPathDel><twSite>ILOGIC_X17Y55.Q4</twSite><twDelType>Tickq</twDelType><twDelInfo twEdge="twRising">0.992</twDelInfo><twComp>slave_fifo32/EP_READY</twComp><twBEL>slave_fifo32/EP_READY</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X4Y173.D1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">10.468</twDelInfo><twComp>slave_fifo32/EP_READY</twComp></twPathDel><twPathDel><twSite>OLOGIC_X4Y173.CLK0</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.803</twDelInfo><twComp>slave_fifo32/EP_READY1</twComp><twBEL>slave_fifo32/EP_READY1</twBEL></twPathDel><twLogDel>1.795</twLogDel><twRouteDel>10.468</twRouteDel><twTotDel>12.263</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">gpif_clk</twDestClk><twPctLog>14.6</twPctLog><twPctRoute>85.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point slave_fifo32/EP_WMARK1 (OLOGIC_X2Y175.D1), 1 path
+</twPathRptBanner><twPathRpt anchorID="14"><twConstPath anchorID="15" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-1.341</twSlack><twSrc BELType="FF">slave_fifo32/EP_WMARK</twSrc><twDest BELType="FF">slave_fifo32/EP_WMARK1</twDest><twTotPathDel>11.029</twTotPathDel><twClkSkew dest = "1.642" src = "1.719">0.077</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.400" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.235</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>slave_fifo32/EP_WMARK</twSrc><twDest BELType='FF'>slave_fifo32/EP_WMARK1</twDest><twLogLvls>0</twLogLvls><twSrcSite>ILOGIC_X17Y78.CLK0</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">gpif_clk</twSrcClk><twPathDel><twSite>ILOGIC_X17Y78.Q4</twSite><twDelType>Tickq</twDelType><twDelInfo twEdge="twRising">0.992</twDelInfo><twComp>slave_fifo32/EP_WMARK</twComp><twBEL>slave_fifo32/EP_WMARK</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X2Y175.D1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">9.234</twDelInfo><twComp>slave_fifo32/EP_WMARK</twComp></twPathDel><twPathDel><twSite>OLOGIC_X2Y175.CLK0</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.803</twDelInfo><twComp>slave_fifo32/EP_WMARK1</twComp><twBEL>slave_fifo32/EP_WMARK1</twBEL></twPathDel><twLogDel>1.795</twLogDel><twRouteDel>9.234</twRouteDel><twTotDel>11.029</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">gpif_clk</twDestClk><twPctLog>16.3</twPctLog><twPctRoute>83.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="16"><twPinLimitBanner>Component Switching Limit Checks: TS_gen_clks_clkfx = PERIOD TIMEGRP &quot;gen_clks_clkfx&quot; TS_codec_main_clk / 2.5
+        HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConstRollupTable uID="1" anchorID="17"><twConstRollup name="TS_codec_main_clk" fullName="TS_codec_main_clk = PERIOD TIMEGRP &quot;codec_main_clk&quot; 25 ns HIGH 50%;" type="origin" depth="0" requirement="25.000" prefType="period" actual="16.000" actualRollup="30.473" errors="0" errorRollup="2" items="0" itemsRollup="48903"/><twConstRollup name="TS_gen_clks_clkfx" fullName="TS_gen_clks_clkfx = PERIOD TIMEGRP &quot;gen_clks_clkfx&quot; TS_codec_main_clk / 2.5         HIGH 50%;" type="child" depth="1" requirement="10.000" prefType="period" actual="12.189" actualRollup="N/A" errors="2" errorRollup="0" items="48903" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="18">1</twUnmetConstCnt><twDataSheet anchorID="19" twNameLen="16"><twClk2SUList anchorID="20" twDestWidth="16"><twDest>codec_main_clk_n</twDest><twClk2SU><twSrc>codec_main_clk_n</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU><twClk2SU><twSrc>codec_main_clk_p</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="21" twDestWidth="16"><twDest>codec_main_clk_p</twDest><twClk2SU><twSrc>codec_main_clk_n</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU><twClk2SU><twSrc>codec_main_clk_p</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twErrRpt></twBody><twSum anchorID="22"><twErrCnt>2</twErrCnt><twScore>3530</twScore><twSetupScore>3530</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>48903</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>12388</twConnCnt></twConstCov><twStats anchorID="23"><twMinPer>16.000</twMinPer><twMaxFreq>62.500</twMaxFreq></twStats></twSum><twFoot><twTimestamp>Tue Jan 29 17:12:06 2013 </twTimestamp></twFoot><twClientInfo anchorID="24"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
+
+Peak Memory Usage: 536 MB
+</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ucf b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ucf
new file mode 100644
index 000000000..6c9af6954
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ucf
@@ -0,0 +1,415 @@
+
+####################################################################################
+# Generated by PlanAhead 14.4 built on 'Tue Dec 18 05:17:28 MST 2012' by 'xbuild'
+####################################################################################
+
+
+####################################################################################
+# Constraints from file : 'b200.ucf'
+####################################################################################
+
+## SPI Nets
+
+NET "cat_ce" LOC = Y1;
+NET "cat_ce" IOSTANDARD = LVCMOS18;
+NET "cat_miso" LOC = V1;
+NET "cat_miso" IOSTANDARD = LVCMOS18;
+NET "cat_mosi" LOC = T4;
+NET "cat_mosi" IOSTANDARD = LVCMOS18;
+NET "cat_sclk" LOC = P7;
+NET "cat_sclk" IOSTANDARD = LVCMOS18;
+
+NET "fx3_ce" LOC = H20;
+NET "fx3_miso" LOC = G20;
+NET "fx3_mosi" LOC = AA20;
+NET "fx3_sclk" LOC = Y21;
+
+NET "pll_ce" LOC = W11;
+NET "pll_mosi" LOC = AB11;
+NET "pll_sclk" LOC = Y12;
+
+NET "FPGA_RXD0" LOC = AB8;
+NET "FPGA_TXD0" LOC = AB7;
+
+NET "SCL_FPGA" LOC = P21;
+NET "SDA_FPGA" LOC = W22;
+
+## Catalina Controls
+
+NET "codec_enable" LOC = J6;
+NET "codec_enable" IOSTANDARD = LVCMOS18;
+NET "codec_en_agc" LOC = P6;
+NET "codec_en_agc" IOSTANDARD = LVCMOS18;
+NET "codec_reset" LOC = Y2;
+NET "codec_reset" IOSTANDARD = LVCMOS18;
+NET "codec_sync" LOC = M3;
+NET "codec_sync" IOSTANDARD = LVCMOS18;
+NET "codec_txrx" LOC = M7;
+NET "codec_txrx" IOSTANDARD = LVCMOS18;
+
+NET "codec_ctrl_in[0]" LOC = E3;
+NET "codec_ctrl_in[0]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_in[1]" LOC = F2;
+NET "codec_ctrl_in[1]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_in[2]" LOC = F1;
+NET "codec_ctrl_in[2]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_in[3]" LOC = E1;
+NET "codec_ctrl_in[3]" IOSTANDARD = LVCMOS18;
+
+NET "codec_ctrl_out[0]" LOC = D1;
+NET "codec_ctrl_out[0]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out[1]" LOC = C1;
+NET "codec_ctrl_out[1]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out[2]" LOC = H3;
+NET "codec_ctrl_out[2]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out[3]" LOC = F3;
+NET "codec_ctrl_out[3]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out[4]" LOC = P1;
+NET "codec_ctrl_out[4]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out[5]" LOC = J1;
+NET "codec_ctrl_out[5]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out[6]" LOC = B1;
+NET "codec_ctrl_out[6]" IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out[7]" LOC = H2;
+NET "codec_ctrl_out[7]" IOSTANDARD = LVCMOS18;
+
+## Catalina Data RX
+
+NET "rx_codec_d[0]" LOC = T2;
+NET "rx_codec_d[0]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[0]" DRIVE = 4;
+NET "rx_codec_d[1]" LOC = R1;
+NET "rx_codec_d[1]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[1]" DRIVE = 4;
+NET "rx_codec_d[2]" LOC = V2;
+NET "rx_codec_d[2]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[2]" DRIVE = 4;
+NET "rx_codec_d[3]" LOC = N1;
+NET "rx_codec_d[3]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[3]" DRIVE = 4;
+NET "rx_codec_d[4]" LOC = V3;
+NET "rx_codec_d[4]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[4]" DRIVE = 4;
+NET "rx_codec_d[5]" LOC = T1;
+NET "rx_codec_d[5]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[5]" DRIVE = 4;
+NET "rx_codec_d[6]" LOC = W1;
+NET "rx_codec_d[6]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[6]" DRIVE = 4;
+NET "rx_codec_d[7]" LOC = U1;
+NET "rx_codec_d[7]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[7]" DRIVE = 4;
+NET "rx_codec_d[8]" LOC = W3;
+NET "rx_codec_d[8]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[8]" DRIVE = 4;
+NET "rx_codec_d[9]" LOC = U3;
+NET "rx_codec_d[9]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[9]" DRIVE = 4;
+NET "rx_codec_d[10]" LOC = P2;
+NET "rx_codec_d[10]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[10]" DRIVE = 4;
+NET "rx_codec_d[11]" LOC = R3;
+NET "rx_codec_d[11]" IOSTANDARD = LVCMOS18;
+NET "rx_codec_d[11]" DRIVE = 4;
+
+## Catalina Data TX
+
+NET "tx_codec_d[0]" LOC = M1;
+NET "tx_codec_d[0]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[0]" DRIVE = 4;
+NET "tx_codec_d[1]" LOC = K1;
+NET "tx_codec_d[1]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[1]" DRIVE = 4;
+NET "tx_codec_d[2]" LOC = L3;
+NET "tx_codec_d[2]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[2]" DRIVE = 4;
+NET "tx_codec_d[3]" LOC = K2;
+NET "tx_codec_d[3]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[3]" DRIVE = 4;
+NET "tx_codec_d[4]" LOC = M4;
+NET "tx_codec_d[4]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[4]" DRIVE = 4;
+NET "tx_codec_d[5]" LOC = J4;
+NET "tx_codec_d[5]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[5]" DRIVE = 4;
+NET "tx_codec_d[6]" LOC = L4;
+NET "tx_codec_d[6]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[6]" DRIVE = 4;
+NET "tx_codec_d[7]" LOC = H1;
+NET "tx_codec_d[7]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[7]" DRIVE = 4;
+NET "tx_codec_d[8]" LOC = M2;
+NET "tx_codec_d[8]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[8]" DRIVE = 4;
+NET "tx_codec_d[9]" LOC = G1;
+NET "tx_codec_d[9]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[9]" DRIVE = 4;
+NET "tx_codec_d[10]" LOC = N3;
+NET "tx_codec_d[10]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[10]" DRIVE = 4;
+NET "tx_codec_d[11]" LOC = G3;
+NET "tx_codec_d[11]" IOSTANDARD = LVCMOS18;
+NET "tx_codec_d[11]" DRIVE = 4;
+
+## Catalina Clocks
+
+NET "cat_clkout_fpga" LOC = J3;
+NET "cat_clkout_fpga" IOSTANDARD = LVCMOS18;
+NET "codec_data_clk_p" LOC = K3;
+NET "codec_data_clk_p" IOSTANDARD = LVCMOS18;
+NET "codec_fb_clk_p" LOC = P3;
+NET "codec_fb_clk_p" IOSTANDARD = LVCMOS18;
+#  | IOSTANDARD = LVCMOS18;
+NET "codec_main_clk_p" LOC = K5;
+#  | IOSTANDARD = LVCMOS18;
+NET "codec_main_clk_n" LOC = K4;
+
+NET "rx_frame_p" LOC = U4;
+NET "rx_frame_p" IOSTANDARD = LVCMOS18;
+NET "tx_frame_p" LOC = T3;
+NET "tx_frame_p" IOSTANDARD = LVCMOS18;
+
+## Debug Bus
+
+NET "debug[0]" LOC = C14;
+NET "debug[1]" LOC = F15;
+NET "debug[2]" LOC = A18;
+NET "debug[3]" LOC = A17;
+NET "debug[4]" LOC = E14;
+NET "debug[5]" LOC = G13;
+NET "debug[6]" LOC = D13;
+NET "debug[7]" LOC = F13;
+NET "debug[8]" LOC = D8;
+NET "debug[9]" LOC = A6;
+NET "debug[10]" LOC = D7;
+NET "debug[11]" LOC = A5;
+NET "debug[12]" LOC = B6;
+NET "debug[13]" LOC = A3;
+NET "debug[14]" LOC = A7;
+NET "debug[15]" LOC = A8;
+NET "debug[16]" LOC = B18;
+NET "debug[17]" LOC = C17;
+NET "debug[18]" LOC = H13;
+NET "debug[19]" LOC = D12;
+NET "debug[20]" LOC = H14;
+NET "debug[21]" LOC = C10;
+NET "debug[22]" LOC = D10;
+NET "debug[23]" LOC = C8;
+NET "debug[24]" LOC = D9;
+NET "debug[25]" LOC = C5;
+NET "debug[26]" LOC = A9;
+NET "debug[27]" LOC = B8;
+NET "debug[28]" LOC = A4;
+NET "debug[29]" LOC = C7;
+NET "debug[30]" LOC = C6;
+NET "debug[31]" LOC = D6;
+
+NET "debug_clk[0]" LOC = A12;
+NET "debug_clk[1]" LOC = C12;
+
+## GPIF
+
+NET "IFCLK" LOC = H21;
+NET "FX3_EXTINT" LOC = U20;
+
+NET "GPIF_CTL0" LOC = V20;
+NET "GPIF_CTL1" LOC = T22;
+NET "GPIF_CTL2" LOC = R22;
+NET "GPIF_CTL3" LOC = U22;
+NET "GPIF_CTL4" LOC = P19;
+NET "GPIF_CTL5" LOC = N22;
+NET "GPIF_CTL6" LOC = T21;
+NET "GPIF_CTL7" LOC = V21;
+NET "GPIF_CTL8" LOC = K18;
+NET "GPIF_CTL9" LOC = R20;
+##GPIF_CTL10 is "FPGA_CFG_DONE", defined later.
+NET "GPIF_CTL11" LOC = P22;
+NET "GPIF_CTL12" LOC = M20;
+
+NET "GPIF_D[0]" LOC = T17;
+NET "GPIF_D[1]" LOC = U14;
+NET "GPIF_D[2]" LOC = U13;
+NET "GPIF_D[3]" LOC = AA6;
+NET "GPIF_D[4]" LOC = AB6;
+NET "GPIF_D[5]" LOC = Y3;
+NET "GPIF_D[6]" LOC = AB3;
+NET "GPIF_D[7]" LOC = AA4;
+NET "GPIF_D[8]" LOC = AA2;
+NET "GPIF_D[9]" LOC = AB2;
+NET "GPIF_D[10]" LOC = AB19;
+NET "GPIF_D[11]" LOC = AA18;
+NET "GPIF_D[12]" LOC = AB18;
+NET "GPIF_D[13]" LOC = Y13;
+NET "GPIF_D[14]" LOC = AA12;
+NET "GPIF_D[15]" LOC = AB12;
+NET "GPIF_D[16]" LOC = N20;
+NET "GPIF_D[17]" LOC = L20;
+NET "GPIF_D[18]" LOC = N19;
+NET "GPIF_D[19]" LOC = M22;
+NET "GPIF_D[20]" LOC = L19;
+NET "GPIF_D[21]" LOC = M21;
+NET "GPIF_D[22]" LOC = M19;
+NET "GPIF_D[23]" LOC = K22;
+NET "GPIF_D[24]" LOC = J20;
+NET "GPIF_D[25]" LOC = L22;
+NET "GPIF_D[26]" LOC = K19;
+NET "GPIF_D[27]" LOC = H22;
+NET "GPIF_D[28]" LOC = J22;
+NET "GPIF_D[29]" LOC = K20;
+NET "GPIF_D[30]" LOC = G22;
+NET "GPIF_D[31]" LOC = F22;
+
+## GPS
+
+NET "gps_lock" LOC = Y17;
+NET "gps_out_enable" LOC = V22;
+NET "gps_ref_enable" LOC = AB13;
+NET "gps_rxd" LOC = AB14;
+NET "gps_txd" LOC = W12;
+NET "gps_txd_nmea" LOC = AA14;
+
+## LEDS
+
+NET "LED_RX1" LOC = C22;
+NET "LED_RX2" LOC = L15;
+NET "LED_TXRX1_TX" LOC = C20;
+NET "LED_TXRX2_RX" LOC = D21;
+NET "LED_TXRX1_RX" LOC = K16;
+NET "LED_TXRX2_TX" LOC = D22;
+
+## Misc Hardware Control
+
+NET "ext_ref_enable" LOC = Y15;
+NET "pll_lock" LOC = AB10;
+NET "AUX_PWR_ON" LOC = AA21;
+#NET "RFUSE"  LOC = "P15"  ;
+
+## PPS
+
+NET "pps_fpga_out_enable" LOC = AB15;
+NET "PPS_IN_EXT" LOC = AB16;
+NET "PPS_IN_INT" LOC = AB21;
+NET "pps_out" LOC = AB17;
+
+## RF Hardware Control
+
+NET "SFDX1_RX" LOC = W4;
+NET "SFDX1_TX" LOC = T18;
+NET "SFDX2_RX" LOC = F18;
+NET "SFDX2_TX" LOC = H17;
+NET "SRX1_RX" LOC = Y7;
+NET "SRX1_TX" LOC = AA8;
+NET "SRX2_RX" LOC = J17;
+NET "SRX2_TX" LOC = F19;
+NET "tx_bandsel_a" LOC = N16;
+NET "tx_bandsel_b" LOC = M16;
+NET "tx_enable1" LOC = Y4;
+NET "tx_enable2" LOC = R19;
+NET "rx_bandsel_a" LOC = T20;
+NET "rx_bandsel_b" LOC = U19;
+NET "rx_bandsel_c" LOC = P20;
+
+## FPGA Config Pins
+
+#NET "FPGA_CFG_INIT_B"  LOC = "T6"  ;
+#NET "FPGA_CFG_DONE"  LOC = "Y22"  ;
+#NET "FPGA_CFG_M0"  LOC = "AA22"  ;
+#NET "FPGA_CFG_M1"  LOC = "U15"  ;
+#NET "FPGA_CFG_PROG_B"  LOC = "AA1"  ;
+
+## Special Pins
+
+#NET "VFS"  LOC = "P16"  ;
+#NET "TMS"  LOC = "C18"  ;
+#NET "TDO"  LOC = "A19"  ;
+#NET "TDI"  LOC = "E18"  ;
+#NET "TCK"  LOC = "G15"  ;
+#NET "GND"  LOC = "N15"  ;
+
+####################################################################################
+# Constraints from file : 'timing.ucf'
+####################################################################################
+
+
+# codec_main_clk is 40 MHz main tcxo clock
+NET "codec_main_clk*" TNM_NET = "codec_main_clk";
+TIMESPEC TS_codec_main_clk = PERIOD "codec_main_clk" 25000 ps HIGH 50 %;
+
+
+# IFCLK is 100 MHz GPIF clock
+NET "IFCLK" TNM_NET = "IFCLK";
+TIMESPEC TS_IFCLK = PERIOD "IFCLK" 10000 ps HIGH 50 %;
+
+
+# codec_data_clk is the data clock from catalina, sample rate dependent
+# this clock equals sample rate in CMOS DDR 1R1T mode
+# this clock is double the sample rate in CMOS DDR 2R2T mode
+# Max clock rate is 61.44 MHz
+NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p";
+TIMESPEC TS_codec_data_clk_p = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %;
+
+
+#always use IOB for GPIF pins for awesome timing
+INST "GPIF_D_9_IOBUF" IOB =TRUE;
+INST "GPIF_D_8_IOBUF" IOB =TRUE;
+INST "GPIF_D_7_IOBUF" IOB =TRUE;
+INST "GPIF_D_6_IOBUF" IOB =TRUE;
+INST "GPIF_D_5_IOBUF" IOB =TRUE;
+INST "GPIF_D_4_IOBUF" IOB =TRUE;
+INST "GPIF_D_3_IOBUF" IOB =TRUE;
+INST "GPIF_D_31_IOBUF" IOB =TRUE;
+INST "GPIF_D_30_IOBUF" IOB =TRUE;
+INST "GPIF_D_2_IOBUF" IOB =TRUE;
+INST "GPIF_D_29_IOBUF" IOB =TRUE;
+INST "GPIF_D_28_IOBUF" IOB =TRUE;
+INST "GPIF_D_27_IOBUF" IOB =TRUE;
+INST "GPIF_D_26_IOBUF" IOB =TRUE;
+INST "GPIF_D_25_IOBUF" IOB =TRUE;
+INST "GPIF_D_24_IOBUF" IOB =TRUE;
+INST "GPIF_D_23_IOBUF" IOB =TRUE;
+INST "GPIF_D_22_IOBUF" IOB =TRUE;
+INST "GPIF_D_21_IOBUF" IOB =TRUE;
+INST "GPIF_D_20_IOBUF" IOB =TRUE;
+INST "GPIF_D_1_IOBUF" IOB =TRUE;
+INST "GPIF_CTL0_OBUF" IOB =TRUE;
+INST "GPIF_CTL11_OBUF" IOB =TRUE;
+INST "GPIF_CTL12_OBUF" IOB =TRUE;
+INST "GPIF_CTL1_OBUF" IOB =TRUE;
+INST "GPIF_CTL2_OBUF" IOB =TRUE;
+INST "GPIF_CTL3_OBUF" IOB =TRUE;
+INST "GPIF_CTL4_IBUF" IOB =TRUE;
+INST "GPIF_CTL5_IBUF" IOB =TRUE;
+INST "GPIF_CTL7_OBUF" IOB =TRUE;
+INST "GPIF_CTL9_IBUF" IOB =TRUE;
+INST "GPIF_D_0_IOBUF" IOB =TRUE;
+INST "GPIF_D_10_IOBUF" IOB =TRUE;
+INST "GPIF_D_11_IOBUF" IOB =TRUE;
+INST "GPIF_D_12_IOBUF" IOB =TRUE;
+INST "GPIF_D_13_IOBUF" IOB =TRUE;
+INST "GPIF_D_14_IOBUF" IOB =TRUE;
+INST "GPIF_D_15_IOBUF" IOB =TRUE;
+INST "GPIF_D_16_IOBUF" IOB =TRUE;
+INST "GPIF_D_17_IOBUF" IOB =TRUE;
+INST "GPIF_D_18_IOBUF" IOB =TRUE;
+INST "GPIF_D_19_IOBUF" IOB =TRUE;
+
+# TODO not working... constraints ignored
+
+#constrain FX3 IO
+INST "GPIF_D[*]" TNM = "gpif_net_out";
+INST "GPIF_D[*]" TNM = "gpif_net_in";
+INST "GPIF_CTL0" TNM = "gpif_net_out";
+INST "GPIF_CTL1" TNM = "gpif_net_out";
+INST "GPIF_CTL2" TNM = "gpif_net_out";
+INST "GPIF_CTL3" TNM = "gpif_net_out";
+INST "GPIF_CTL4" TNM = "gpif_net_in";
+INST "GPIF_CTL5" TNM = "gpif_net_in";
+INST "GPIF_CTL7" TNM = "gpif_net_out";
+INST "GPIF_CTL11" TNM = "gpif_net_out";
+INST "GPIF_CTL12" TNM = "gpif_net_out";
+
+#NET "gpif_clk" TNM_NET = "TNM_gpif_clk";
+#OFFSET = OUT 5 ns AFTER "gpif_clk";
+#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %;
+#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING;
+#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING;
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.xdl b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.xdl
new file mode 100644
index 000000000..f35ea02e6
Binary files /dev/null and b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.xdl differ
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/htr.txt b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/htr.txt
new file mode 100644
index 000000000..bf500d659
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/htr.txt
@@ -0,0 +1,13 @@
+#
+# PlanAhead(TM)
+# htr.txt: a PlanAhead-generated description of how-to-repeat the
+#          the basic steps of a run.  Note that runme.bat/sh needs
+#          to be invoked for PlanAhead to track run status.
+# Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
+#
+
+ngdbuild -intstyle ise -p xc6slx75fgg484-3 -dd _ngo -uc "b200.ucf" "b200.edf"
+map -intstyle pa -w "b200.ngd"
+par -intstyle pa "b200.ncd" -w "b200_routed.ncd"
+trce -intstyle ise -o "b200.twr" -v 30 -l 30 "b200_routed.ncd" "b200.pcf"
+xdl -secure -ncd2xdl -nopips "b200_routed.ncd" "b200_routed.xdl"
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/rundef.js b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/rundef.js
new file mode 100644
index 000000000..759e0d89d
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/rundef.js
@@ -0,0 +1,48 @@
+//
+// PlanAhead(TM)
+// rundef.js: a PlanAhead-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+  PathVal = "/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64;/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64;/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin;";
+} else {
+  PathVal = "/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64;/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64;/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "ngdbuild",
+         "-intstyle ise -p xc6slx75fgg484-3 -dd _ngo -uc \"b200.ucf\" \"b200.edf\"" );
+ISEStep( "map",
+         "-intstyle pa -w \"b200.ngd\"" );
+ISEStep( "par",
+         "-intstyle pa \"b200.ncd\" -w \"b200_routed.ncd\"" );
+ISEStep( "trce",
+         "-intstyle ise -o \"b200.twr\" -v 30 -l 30 \"b200_routed.ncd\" \"b200.pcf\"" );
+ISEStep( "xdl",
+         "-secure -ncd2xdl -nopips \"b200_routed.ncd\" \"b200_routed.xdl\"" );
+
+
+
+function EAInclude( EAInclFilename ) {
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+  var EAIFContents = EAInclFile.ReadAll();
+  EAInclFile.Close();
+  return EAIFContents;
+}
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.bat b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.bat
new file mode 100644
index 000000000..4eed28871
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.bat
@@ -0,0 +1,11 @@
+@echo off
+
+rem  PlanAhead (TM)
+rem  runme.bat: a PlanAhead-generated Script
+rem  Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.log b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.log
new file mode 100644
index 000000000..9fee0944e
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.log
@@ -0,0 +1,4 @@
+*** PLEASE NOTE: this run was imported on Tue Jan 29 17:25:57 2013
+    from ISE results generated outside of PlanAhead.
+    Original messages and reports have not been imported
+    but you can launch bitgen on this run if desired...
diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.sh b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.sh
new file mode 100755
index 000000000..f814cb32f
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+
+# 
+# PlanAhead(TM)
+# runme.sh: a PlanAhead-generated Runs Script for UNIX
+# Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
+# 
+
+if [ -z "$PATH" ]; then
+  PATH=/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64:/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin
+else
+  PATH=/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64:/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+  LD_LIBRARY_PATH=/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64
+else
+  LD_LIBRARY_PATH=/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD=`dirname "$0"`
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+     if [ $? -ne 0 ]
+     then
+         exit
+     fi
+}
+
+EAStep ngdbuild -intstyle ise -p xc6slx75fgg484-3 -dd _ngo -uc "b200.ucf" "b200.edf"
+EAStep map -intstyle pa -w "b200.ngd"
+EAStep par -intstyle pa "b200.ncd" -w "b200_routed.ncd"
+EAStep trce -intstyle ise -o "b200.twr" -v 30 -l 30 "b200_routed.ncd" "b200.pcf"
+EAStep xdl -secure -ncd2xdl -nopips "b200_routed.ncd" "b200_routed.xdl"
diff --git a/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/b200.ucf b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/b200.ucf
new file mode 100644
index 000000000..75ffef7f3
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/b200.ucf
@@ -0,0 +1,241 @@
+## SPI Nets
+
+NET "cat_ce"  LOC = "Y1"    | IOSTANDARD = LVCMOS18;
+NET "cat_miso"  LOC = "V1"  | IOSTANDARD = LVCMOS18;
+NET "cat_mosi"  LOC = "T4"  | IOSTANDARD = LVCMOS18;
+NET "cat_sclk"  LOC = "P7"  | IOSTANDARD = LVCMOS18;
+
+NET "fx3_ce"  LOC = "H20"  ;
+NET "fx3_miso"  LOC = "G20"  ;
+NET "fx3_mosi"  LOC = "AA20"  ;
+NET "fx3_sclk"  LOC = "Y21"  ;
+
+NET "pll_ce"  LOC = "W11"  ;
+NET "pll_mosi"  LOC = "AB11"  ;
+NET "pll_sclk"  LOC = "Y12"  ;
+
+NET "FPGA_RXD0"  LOC = "AB8"  ;
+NET "FPGA_TXD0"  LOC = "AB7"  ;
+
+NET "SCL_FPGA"  LOC = "P21"  ;
+NET "SDA_FPGA"  LOC = "W22"  ;
+
+## Catalina Controls
+
+NET "codec_enable"  LOC = "J6"  | IOSTANDARD = LVCMOS18;
+NET "codec_en_agc"  LOC = "P6"  | IOSTANDARD = LVCMOS18;
+NET "codec_reset"  LOC = "Y2"  | IOSTANDARD = LVCMOS18;
+NET "codec_sync"  LOC = "M3"  | IOSTANDARD = LVCMOS18;
+NET "codec_txrx"  LOC = "M7"  | IOSTANDARD = LVCMOS18;
+
+NET "codec_ctrl_in<0>"  LOC = "E3"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_in<1>"  LOC = "F2"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_in<2>"  LOC = "F1"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_in<3>"  LOC = "E1"  | IOSTANDARD = LVCMOS18;
+
+NET "codec_ctrl_out<0>"  LOC = "D1"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out<1>"  LOC = "C1"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out<2>"  LOC = "H3"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out<3>"  LOC = "F3"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out<4>"  LOC = "P1"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out<5>"  LOC = "J1"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out<6>"  LOC = "B1"  | IOSTANDARD = LVCMOS18;
+NET "codec_ctrl_out<7>"  LOC = "H2"  | IOSTANDARD = LVCMOS18;
+
+## Catalina Data RX
+
+NET "rx_codec_d<0>"  LOC = "T2"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "rx_codec_d<1>"  LOC = "R1"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "rx_codec_d<2>"  LOC = "V2"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "rx_codec_d<3>"  LOC = "N1"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "rx_codec_d<4>"  LOC = "V3"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "rx_codec_d<5>"  LOC = "T1"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "rx_codec_d<6>"  LOC = "W1"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "rx_codec_d<7>"  LOC = "U1"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "rx_codec_d<8>"  LOC = "W3"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "rx_codec_d<9>"  LOC = "U3"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "rx_codec_d<10>"  LOC = "P2"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "rx_codec_d<11>"  LOC = "R3"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+
+## Catalina Data TX
+
+NET "tx_codec_d<0>"  LOC = "M1"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "tx_codec_d<1>"  LOC = "K1"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "tx_codec_d<2>"  LOC = "L3"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "tx_codec_d<3>"  LOC = "K2"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "tx_codec_d<4>"  LOC = "M4"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "tx_codec_d<5>"  LOC = "J4"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "tx_codec_d<6>"  LOC = "L4"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "tx_codec_d<7>"  LOC = "H1"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "tx_codec_d<8>"  LOC = "M2"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "tx_codec_d<9>"  LOC = "G1"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "tx_codec_d<10>"  LOC = "N3"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+NET "tx_codec_d<11>"  LOC = "G3"  | IOSTANDARD = LVCMOS18 | DRIVE = 4;
+
+## Catalina Clocks
+
+NET "cat_clkout_fpga"  LOC = "J3"  | IOSTANDARD = LVCMOS18;
+NET "codec_data_clk_p"  LOC = "K3"  | IOSTANDARD = LVCMOS18;
+NET "codec_fb_clk_p"  LOC = "P3"  | IOSTANDARD = LVCMOS18;
+NET "codec_main_clk_p"  LOC = "K5" ;#  | IOSTANDARD = LVCMOS18;
+NET "codec_main_clk_n"  LOC = "K4" ;#  | IOSTANDARD = LVCMOS18;
+
+NET "rx_frame_p"  LOC = "U4"  | IOSTANDARD = LVCMOS18;
+NET "tx_frame_p"  LOC = "T3"  | IOSTANDARD = LVCMOS18;
+
+## Debug Bus
+
+NET "debug<0>"  LOC = "C14"  ;
+NET "debug<1>"  LOC = "F15"  ;
+NET "debug<2>"  LOC = "A18"  ;
+NET "debug<3>"  LOC = "A17"  ;
+NET "debug<4>"  LOC = "E14"  ;
+NET "debug<5>"  LOC = "G13"  ;
+NET "debug<6>"  LOC = "D13"  ;
+NET "debug<7>"  LOC = "F13"  ;
+NET "debug<8>"  LOC = "D8"  ;
+NET "debug<9>"  LOC = "A6"  ;
+NET "debug<10>"  LOC = "D7"  ;
+NET "debug<11>"  LOC = "A5"  ;
+NET "debug<12>"  LOC = "B6"  ;
+NET "debug<13>"  LOC = "A3"  ;
+NET "debug<14>"  LOC = "A7"  ;
+NET "debug<15>"  LOC = "A8"  ;
+NET "debug<16>"  LOC = "B18"  ;
+NET "debug<17>"  LOC = "C17"  ;
+NET "debug<18>"  LOC = "H13"  ;
+NET "debug<19>"  LOC = "D12"  ;
+NET "debug<20>"  LOC = "H14"  ;
+NET "debug<21>"  LOC = "C10"  ;
+NET "debug<22>"  LOC = "D10"  ;
+NET "debug<23>"  LOC = "C8"  ;
+NET "debug<24>"  LOC = "D9"  ;
+NET "debug<25>"  LOC = "C5"  ;
+NET "debug<26>"  LOC = "A9"  ;
+NET "debug<27>"  LOC = "B8"  ;
+NET "debug<28>"  LOC = "A4"  ;
+NET "debug<29>"  LOC = "C7"  ;
+NET "debug<30>"  LOC = "C6"  ;
+NET "debug<31>"  LOC = "D6"  ;
+
+NET "debug_clk<0>"  LOC = "A12"  ;
+NET "debug_clk<1>"  LOC = "C12"  ;
+
+## GPIF
+
+NET "IFCLK"  LOC = "H21"  ;
+NET "FX3_EXTINT"  LOC = "U20"  ;
+
+NET "GPIF_CTL0"  LOC = "V20"  ;
+NET "GPIF_CTL1"  LOC = "T22"  ;
+NET "GPIF_CTL2"  LOC = "R22"  ;
+NET "GPIF_CTL3"  LOC = "U22"  ;
+NET "GPIF_CTL4"  LOC = "P19"  ;
+NET "GPIF_CTL5"  LOC = "N22"  ;
+NET "GPIF_CTL6"  LOC = "T21"  ;
+NET "GPIF_CTL7"  LOC = "V21"  ;
+NET "GPIF_CTL8"  LOC = "K18"  ;
+NET "GPIF_CTL9"  LOC = "R20"  ;
+##GPIF_CTL10 is "FPGA_CFG_DONE", defined later.
+NET "GPIF_CTL11"  LOC = "P22"  ;
+NET "GPIF_CTL12"  LOC = "M20"  ;
+
+NET "GPIF_D<0>"  LOC = "T17"  ;
+NET "GPIF_D<1>"  LOC = "U14"  ;
+NET "GPIF_D<2>"  LOC = "U13"  ;
+NET "GPIF_D<3>"  LOC = "AA6"  ;
+NET "GPIF_D<4>"  LOC = "AB6"  ;
+NET "GPIF_D<5>"  LOC = "Y3"  ;
+NET "GPIF_D<6>"  LOC = "AB3"  ;
+NET "GPIF_D<7>"  LOC = "AA4"  ;
+NET "GPIF_D<8>"  LOC = "AA2"  ;
+NET "GPIF_D<9>"  LOC = "AB2"  ;
+NET "GPIF_D<10>"  LOC = "AB19"  ;
+NET "GPIF_D<11>"  LOC = "AA18"  ;
+NET "GPIF_D<12>"  LOC = "AB18"  ;
+NET "GPIF_D<13>"  LOC = "Y13"  ;
+NET "GPIF_D<14>"  LOC = "AA12"  ;
+NET "GPIF_D<15>"  LOC = "AB12"  ;
+NET "GPIF_D<16>"  LOC = "N20"  ;
+NET "GPIF_D<17>"  LOC = "L20"  ;
+NET "GPIF_D<18>"  LOC = "N19"  ;
+NET "GPIF_D<19>"  LOC = "M22"  ;
+NET "GPIF_D<20>"  LOC = "L19"  ;
+NET "GPIF_D<21>"  LOC = "M21"  ;
+NET "GPIF_D<22>"  LOC = "M19"  ;
+NET "GPIF_D<23>"  LOC = "K22"  ;
+NET "GPIF_D<24>"  LOC = "J20"  ;
+NET "GPIF_D<25>"  LOC = "L22"  ;
+NET "GPIF_D<26>"  LOC = "K19"  ;
+NET "GPIF_D<27>"  LOC = "H22"  ;
+NET "GPIF_D<28>"  LOC = "J22"  ;
+NET "GPIF_D<29>"  LOC = "K20"  ;
+NET "GPIF_D<30>"  LOC = "G22"  ;
+NET "GPIF_D<31>"  LOC = "F22"  ;
+
+## GPS
+
+NET "gps_lock"  LOC = "Y17"  ;
+NET "gps_out_enable"  LOC = "V22"  ;
+NET "gps_ref_enable"  LOC = "AB13"  ;
+NET "gps_rxd"  LOC = "AB14"  ;
+NET "gps_txd"  LOC = "W12"  ;
+NET "gps_txd_nmea"  LOC = "AA14"  ;
+
+## LEDS
+
+NET "LED_RX1"  LOC = "C22"  ;
+NET "LED_RX2"  LOC = "L15"  ;
+NET "LED_TXRX1_TX"  LOC = "C20"  ;
+NET "LED_TXRX2_RX"  LOC = "D21"  ;
+NET "LED_TXRX1_RX"  LOC = "K16"  ;
+NET "LED_TXRX2_TX"  LOC = "D22"  ;
+
+## Misc Hardware Control
+
+NET "ext_ref_enable"  LOC = "Y15"  ;
+NET "pll_lock"  LOC = "AB10"  ;
+NET "AUX_PWR_ON"  LOC = "AA21"  ;
+#NET "RFUSE"  LOC = "P15"  ;
+
+## PPS
+
+NET "pps_fpga_out_enable"  LOC = "AB15"  ;
+NET "PPS_IN_EXT"  LOC = "AB16"  ;
+NET "PPS_IN_INT"  LOC = "AB21"  ;
+NET "pps_out"  LOC = "AB17"  ;
+
+## RF Hardware Control
+
+NET "SFDX1_RX"  LOC = "W4"  ;
+NET "SFDX1_TX"  LOC = "T18"  ;
+NET "SFDX2_RX"  LOC = "F18"  ;
+NET "SFDX2_TX"  LOC = "H17"  ;
+NET "SRX1_RX"  LOC = "Y7"  ;
+NET "SRX1_TX"  LOC = "AA8"  ;
+NET "SRX2_RX"  LOC = "J17"  ;
+NET "SRX2_TX"  LOC = "F19"  ;
+NET "tx_bandsel_a"  LOC = "N16"  ;
+NET "tx_bandsel_b"  LOC = "M16"  ;
+NET "tx_enable1"  LOC = "Y4"  ;
+NET "tx_enable2"  LOC = "R19"  ;
+NET "rx_bandsel_a"  LOC = "T20"  ;
+NET "rx_bandsel_b"  LOC = "U19"  ;
+NET "rx_bandsel_c"  LOC = "P20"  ;
+
+## FPGA Config Pins
+
+#NET "FPGA_CFG_INIT_B"  LOC = "T6"  ;
+#NET "FPGA_CFG_DONE"  LOC = "Y22"  ;
+#NET "FPGA_CFG_M0"  LOC = "AA22"  ;
+#NET "FPGA_CFG_M1"  LOC = "U15"  ;
+#NET "FPGA_CFG_PROG_B"  LOC = "AA1"  ;
+
+## Special Pins
+
+#NET "VFS"  LOC = "P16"  ;
+#NET "TMS"  LOC = "C18"  ;
+#NET "TDO"  LOC = "A19"  ;
+#NET "TDI"  LOC = "E18"  ;
+#NET "TCK"  LOC = "G15"  ;
+#NET "GND"  LOC = "N15"  ;
diff --git a/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/timing.ucf b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/timing.ucf
new file mode 100644
index 000000000..82d68aceb
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/timing.ucf
@@ -0,0 +1,44 @@
+
+# codec_main_clk is 40 MHz main tcxo clock
+NET "codec_main_clk*" TNM_NET = "codec_main_clk";
+TIMESPEC "TS_codec_main_clk" = PERIOD "codec_main_clk" 25000 ps HIGH 50 %;
+
+
+# IFCLK is 100 MHz GPIF clock
+NET "IFCLK" TNM_NET = "IFCLK";
+TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 10000 ps HIGH 50 %;
+
+
+# codec_data_clk is the data clock from catalina, sample rate dependent
+# this clock equals sample rate in CMOS DDR 1R1T mode
+# this clock is double the sample rate in CMOS DDR 2R2T mode
+# Max clock rate is 61.44 MHz
+NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p";
+TIMESPEC "TS_codec_data_clk_p" = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %;
+
+
+#always use IOB for GPIF pins for awesome timing
+INST "GPIF_*" IOB = TRUE;
+
+# TODO not working... constraints ignored
+
+#constrain FX3 IO
+INST "GPIF_D<*>" TNM = gpif_net_out;
+INST "GPIF_D<*>" TNM = gpif_net_in;
+INST "GPIF_CTL0" TNM = gpif_net_out;
+INST "GPIF_CTL1" TNM = gpif_net_out;
+INST "GPIF_CTL2" TNM = gpif_net_out;
+INST "GPIF_CTL3" TNM = gpif_net_out;
+INST "GPIF_CTL4" TNM = gpif_net_in;
+INST "GPIF_CTL5" TNM = gpif_net_in;
+INST "GPIF_CTL6" TNM = gpif_net_in;
+INST "GPIF_CTL7" TNM = gpif_net_out;
+INST "GPIF_CTL8" TNM = gpif_net_in;
+INST "GPIF_CTL11" TNM = gpif_net_out;
+INST "GPIF_CTL12" TNM = gpif_net_out;
+
+#NET "gpif_clk" TNM_NET = "TNM_gpif_clk";
+#OFFSET = OUT 5 ns AFTER "gpif_clk";
+#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %;
+#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING;
+#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING;
diff --git a/fpga/usrp3/top/b200/planahead/planahead.srcs/sources_1/imports/coregen/fifo_4k_2clk.ngc b/fpga/usrp3/top/b200/planahead/planahead.srcs/sources_1/imports/coregen/fifo_4k_2clk.ngc
new file mode 100644
index 000000000..b379066c6
--- /dev/null
+++ b/fpga/usrp3/top/b200/planahead/planahead.srcs/sources_1/imports/coregen/fifo_4k_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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diff --git a/fpga/usrp3/top/b200/radio_b200.v b/fpga/usrp3/top/b200/radio_b200.v
new file mode 100644
index 000000000..ea01aee69
--- /dev/null
+++ b/fpga/usrp3/top/b200/radio_b200.v
@@ -0,0 +1,318 @@
+//
+// Copyright 2013 Ettus Research LLC
+//
+
+
+// radio top level module for b200
+//  Contains all clock-rate DSP components, all radio and hardware controls and settings
+
+module radio_b200
+  #(
+    parameter FIFO_SIZE = 13
+  )
+  (input radio_clk, input radio_rst,
+   input [31:0] rx, output [31:0] tx,
+   inout [31:0] fe_atr, input pps,
+
+   input bus_clk, input bus_rst,
+   input [63:0] tx_tdata, input tx_tlast, input tx_tvalid, output tx_tready,
+   output [63:0] rx_tdata, output rx_tlast, output rx_tvalid, input rx_tready,
+   input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output ctrl_tready,
+   output [63:0] resp_tdata, output resp_tlast, output resp_tvalid, input resp_tready,
+
+   output [31:0] debug
+   );
+
+   // ///////////////////////////////////////////////////////////////////////////////
+   // FIFO Interfacing to the bus clk domain
+   // in_tdata splits to tx_tdata and ctrl_tdata
+   // rx_tdata and resp_tdata get muxed to out_tdata
+   // Everything except rx flow control must cross in to radio_clk domain before further use
+   // _b signifies bus_clk domain, _r signifies radio_clk domain
+  
+   wire [63:0] 	 ctrl_tdata_r;
+   wire 	 ctrl_tready_r, ctrl_tvalid_r;
+   wire 	 ctrl_tlast_r;
+   
+   wire [63:0] 	 resp_tdata_r;
+   wire 	 resp_tready_r, resp_tvalid_r;
+   wire 	 resp_tlast_r;
+   
+   wire [63:0] 	 rx_tdata_r;
+   wire 	 rx_tready_r, rx_tvalid_r;
+   wire 	 rx_tlast_r;
+
+   wire [63:0] 	 rx_mux_tdata_r;
+   wire 	 rx_mux_tready_r, rx_mux_tvalid_r;
+   wire 	 rx_mux_tlast_r;
+
+   wire [63:0] 	 rx_err_tdata_r;
+   wire 	 rx_err_tready_r, rx_err_tvalid_r;
+   wire 	 rx_err_tlast_r;
+
+   wire [63:0] 	 tx_tdata_r;
+   wire 	 tx_tready_r, tx_tvalid_r;
+   wire 	 tx_tlast_r;
+
+   wire [63:0] 	 txresp_tdata, txresp_tdata_r;
+   wire 	 txresp_tready, txresp_tready_r, txresp_tvalid, txresp_tvalid_r;
+   wire 	 txresp_tlast, txresp_tlast_r;
+
+   wire [63:0] 	 rmux_tdata_r;
+   wire 	 rmux_tlast_r, rmux_tvalid_r, rmux_tready_r;
+   
+   axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/)) ctrl_fifo
+     (.reset(bus_rst),
+      .i_aclk(bus_clk), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .i_tdata({ctrl_tlast, ctrl_tdata}), 
+      .o_aclk(radio_clk), .o_tvalid(ctrl_tvalid_r), .o_tready(ctrl_tready_r), .o_tdata({ctrl_tlast_r, ctrl_tdata_r}));
+   
+   axi_fifo_2clk #(.WIDTH(65), .SIZE(FIFO_SIZE)) tx_fifo
+     (.reset(bus_rst),
+      .i_aclk(bus_clk), .i_tvalid(tx_tvalid), .i_tready(tx_tready), .i_tdata({tx_tlast, tx_tdata}), 
+      .o_aclk(radio_clk), .o_tvalid(tx_tvalid_r), .o_tready(tx_tready_r), .o_tdata({tx_tlast_r, tx_tdata_r}));
+   
+   axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/)) resp_fifo
+     (.reset(radio_rst),
+      .i_aclk(radio_clk), .i_tvalid(rmux_tvalid_r), .i_tready(rmux_tready_r), .i_tdata({rmux_tlast_r, rmux_tdata_r}), 
+      .o_aclk(bus_clk), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .o_tdata({resp_tlast, resp_tdata}));
+   
+   axi_fifo_2clk #(.WIDTH(65), .SIZE(FIFO_SIZE)) rx_fifo
+     (.reset(radio_rst),
+      .i_aclk(radio_clk), .i_tvalid(rx_mux_tvalid_r), .i_tready(rx_mux_tready_r), .i_tdata({rx_mux_tlast_r, rx_mux_tdata_r}),
+      .o_aclk(bus_clk), .o_tvalid(rx_tvalid), .o_tready(rx_tready), .o_tdata({rx_tlast, rx_tdata}));
+   
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Setting bus and controls
+   
+   localparam SR_SPI       = 8'd8;
+   localparam SR_ATR       = 8'd12;
+   localparam SR_TEST      = 8'd21;
+   localparam SR_CODEC_IDLE = 8'd22;
+   localparam SR_READBACK  = 8'd32;
+   localparam SR_TX_CTRL   = 8'd64;
+   localparam SR_RX_CTRL   = 8'd96;
+   localparam SR_RX_DSP    = 8'd144;
+   localparam SR_TX_DSP    = 8'd184;
+   localparam SR_TIME      = 8'd128;
+   localparam SR_RX_FMT    = 8'd136;
+   localparam SR_TX_FMT    = 8'd138;
+
+
+   wire 	set_stb;
+   wire [7:0] 	set_addr;
+   wire [31:0] 	set_data;
+   wire [31:0] 	test_readback;
+   wire 	run_rx, run_tx;
+
+   reg [63:0] 	rb_data;
+   wire [1:0] 	rb_addr;
+
+   wire [63:0] vita_time, vita_time_lastpps;
+   timekeeper #(.BASE(SR_TIME)) timekeeper
+     (.clk(radio_clk), .reset(radio_rst), .pps(pps),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .vita_time(vita_time), .vita_time_lastpps(vita_time_lastpps));
+
+   radio_ctrl_proc radio_ctrl_proc
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .ctrl_tdata(ctrl_tdata_r), .ctrl_tlast(ctrl_tlast_r), .ctrl_tvalid(ctrl_tvalid_r), .ctrl_tready(ctrl_tready_r),
+      .resp_tdata(resp_tdata_r), .resp_tlast(resp_tlast_r), .resp_tvalid(resp_tvalid_r), .resp_tready(resp_tready_r),
+      .vita_time(vita_time),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .ready(1'b1), .readback(rb_data),
+      .debug());
+
+   always @*
+     case(rb_addr)
+       2'd0 : rb_data <= { 32'b0, test_readback };
+       2'd1 : rb_data <= vita_time;
+       2'd2 : rb_data <= vita_time_lastpps;
+       2'd3 : rb_data <= {tx, rx};
+       default : rb_data <= 64'd0;
+     endcase // case (rb_addr)
+
+   setting_reg #(.my_addr(SR_TEST), .awidth(8), .width(32)) sr_test
+     (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(test_readback), .changed());
+
+   wire [31:0] tx_idle;
+   setting_reg #(.my_addr(SR_CODEC_IDLE), .awidth(8), .width(32)) sr_codec_idle
+     (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(tx_idle), .changed());
+
+   setting_reg #(.my_addr(SR_READBACK), .awidth(8), .width(2)) sr_rdback
+     (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
+      .out(rb_addr), .changed());
+
+   gpio_atr #(.BASE(SR_ATR), .WIDTH(32)) gpio_atr
+     (.clk(radio_clk),.reset(radio_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .rx(run_rx), .tx(run_tx),
+      .gpio(fe_atr), .gpio_readback() );
+
+   // /////////////////////////////////////////////////////////////////////////////////
+   //  TX Chain
+
+   wire [175:0] txsample_tdata;
+   wire 	txsample_tvalid, txsample_tready;
+   wire [31:0] 	sample_tx;
+   wire 	ack_or_error, packet_consumed;
+   wire [11:0] 	seqnum;
+   wire [63:0] 	error_code;
+   wire [31:0] 	sid;
+   wire [23:0] tx_fe_i, tx_fe_q;
+
+   assign tx[31:16] = (run_tx)? tx_fe_i[23:8] : tx_idle[31:16];
+   assign tx[15:0]  = (run_tx)? tx_fe_q[23:8] : tx_idle[15:0];
+
+   wire [63:0] tx_tdata_i; wire tx_tlast_i, tx_tvalid_i, tx_tready_i;
+
+   new_tx_deframer tx_deframer
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .i_tdata(tx_tdata_i), .i_tlast(tx_tlast_i), .i_tvalid(tx_tvalid_i), .i_tready(tx_tready_i),
+      .sample_tdata(txsample_tdata), .sample_tvalid(txsample_tvalid), .sample_tready(txsample_tready));
+
+   new_tx_control #(.BASE(SR_TX_CTRL)) tx_control
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .vita_time(vita_time),
+      .ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
+      .seqnum(seqnum), .error_code(error_code), .sid(sid),
+      .sample_tdata(txsample_tdata), .sample_tvalid(txsample_tvalid), .sample_tready(txsample_tready),
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+      .debug());
+
+   tx_responder #(.BASE(SR_TX_CTRL+2)) tx_responder
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
+      .seqnum(seqnum), .error_code(error_code), .sid(sid),
+      .vita_time(vita_time),
+      .o_tdata(txresp_tdata_r), .o_tlast(txresp_tlast_r), .o_tvalid(txresp_tvalid_r), .o_tready(txresp_tready_r));
+
+   duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0), .WIDTH(24)) duc_chain
+     (.clk(radio_clk), .rst(radio_rst), .clr(1'b0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+      .debug() );
+
+    chdr_xxxx_to_16sc_chain #(.BASE(SR_TX_FMT)) convert_xxxx_to_16sc
+     (.clk(radio_clk), .reset(radio_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .i_tdata(tx_tdata_r), .i_tlast(tx_tlast_r), .i_tvalid(tx_tvalid_r), .i_tready(tx_tready_r),
+      .o_tdata(tx_tdata_i), .o_tlast(tx_tlast_i), .o_tvalid(tx_tvalid_i), .o_tready(tx_tready_i));
+
+   // /////////////////////////////////////////////////////////////////////////////////
+   //  RX Chain
+
+   wire 	full, eob_rx;
+   wire 	strobe_rx;
+   wire [31:0] 	sample_rx;
+   wire [31:0] 	  rx_sid;
+   wire [11:0] 	  rx_seqnum;
+   wire [63:0] rx_tdata_i; wire rx_tlast_i, rx_tvalid_i, rx_tready_i;
+
+   new_rx_framer #(.BASE(SR_RX_CTRL+4)) new_rx_framer
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .vita_time(vita_time),
+      .strobe(strobe_rx), .sample(sample_rx), .run(run_rx), .eob(eob_rx), .full(full),
+      .sid(rx_sid), .seqnum(rx_seqnum),
+      .o_tdata(rx_tdata_i), .o_tlast(rx_tlast_i), .o_tvalid(rx_tvalid_i), .o_tready(rx_tready_i),
+      .debug());
+
+   new_rx_control #(.BASE(SR_RX_CTRL)) new_rx_control
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .vita_time(vita_time),
+      .strobe(strobe_rx), .run(run_rx), .eob(eob_rx), .full(full),
+      .sid(rx_sid), .seqnum(rx_seqnum),
+      .err_tdata(rx_err_tdata_r), .err_tlast(rx_err_tlast_r), .err_tvalid(rx_err_tvalid_r), .err_tready(rx_err_tready_r),
+      .debug());
+
+   ddc_chain #(.BASE(SR_RX_DSP), .DSPNO(0), .WIDTH(24)) ddc_chain
+     (.clk(radio_clk), .rst(radio_rst), .clr(1'b0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .rx_fe_i({rx[31:16],8'd0}),.rx_fe_q({rx[15:0],8'd0}),
+      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .debug() );
+
+   chdr_16sc_to_xxxx_chain #(.BASE(SR_RX_FMT)) convert_16sc_to_xxxx
+     (.clk(radio_clk), .reset(radio_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .i_tdata(rx_tdata_i), .i_tlast(rx_tlast_i), .i_tvalid(rx_tvalid_i), .i_tready(rx_tready_i),
+      .o_tdata(rx_tdata_r), .o_tlast(rx_tlast_r), .o_tvalid(rx_tvalid_r), .o_tready(rx_tready_r));
+
+   // /////////////////////////////////////////////////////////////////////////////////
+   //  RX Channel Muxing
+
+   axi_mux4 #(.PRIO(1), .WIDTH(64)) rx_mux
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .i0_tdata(rx_tdata_r), .i0_tlast(rx_tlast_r), .i0_tvalid(rx_tvalid_r), .i0_tready(rx_tready_r),
+      .i1_tdata(rx_err_tdata_r), .i1_tlast(rx_err_tlast_r), .i1_tvalid(rx_err_tvalid_r), .i1_tready(rx_err_tready_r),
+      .i2_tdata(), .i2_tlast(), .i2_tvalid(1'b0), .i2_tready(),
+      .i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(),
+      .o_tdata(rx_mux_tdata_r), .o_tlast(rx_mux_tlast_r), .o_tvalid(rx_mux_tvalid_r), .o_tready(rx_mux_tready_r));
+
+   // /////////////////////////////////////////////////////////////////////////////////
+   //  Response Channel Muxing
+
+   axi_mux4 #(.PRIO(0), .WIDTH(64)) response_mux
+     (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
+      .i0_tdata(txresp_tdata_r), .i0_tlast(txresp_tlast_r), .i0_tvalid(txresp_tvalid_r), .i0_tready(txresp_tready_r),
+      .i1_tdata(resp_tdata_r), .i1_tlast(resp_tlast_r), .i1_tvalid(resp_tvalid_r), .i1_tready(resp_tready_r),
+      .i2_tdata(), .i2_tlast(), .i2_tvalid(1'b0), .i2_tready(),
+      .i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(),
+      .o_tdata(rmux_tdata_r), .o_tlast(rmux_tlast_r), .o_tvalid(rmux_tvalid_r), .o_tready(rmux_tready_r));
+
+   wire [255:0] debug1;
+   
+   reg [255:0] debug2;
+
+   
+/* -----\/----- EXCLUDED -----\/-----
+ 	
+   always @(posedge radio_clk)
+     debug2 <= debug1;
+   
+   wire [35:0] CONTROL0,CONTROL1;
+ 
+   chipscope_ila_256 chipscope_ila_256(
+				     .CONTROL(CONTROL0), // INOUT BUS [35:0]
+				     .CLK(radio_clk), // IN
+				     .TRIG0(debug2) // IN BUS [31:0]
+				     );
+   
+   chipscope_ila_32  chipscope_ila_32(
+				   .CONTROL(CONTROL1), // INOUT BUS [35:0]
+				   .CLK(radio_clk), // IN
+				   .TRIG0(32'd0) // IN BUS [31:0]
+				   );
+   
+   chipscope_icon  chipscope_icon(
+				 .CONTROL0(CONTROL0), // INOUT BUS [35:0]
+				   .CONTROL1(CONTROL1) // INOUT BUS [35:0]
+				    );
+
+   assign debug1 = {
+		    debug_tx_framer, // [214:206]
+		    debug_tx_control, // [205:177]
+		    set_data,     // [176:145]
+		    set_addr,     // [144:137]
+		     set_stb,     // [136]
+		     run_tx,      // [135]
+		     run_rx,      // [134]
+		     tx_tlast,    // [133]
+		     tx_tready,   // [132]
+		     tx_tvalid,   // [131]
+		     ctrl_tlast,  // [130]
+		     ctrl_tready, // [129]
+		     ctrl_tvalid, // [128]
+		     tx_tdata,    // [127:64]
+		     ctrl_tdata   // [63:0]
+		     };
+ -----/\----- EXCLUDED -----/\----- */
+
+   
+endmodule // radio_b200
diff --git a/fpga/usrp3/top/b200/timing.ucf b/fpga/usrp3/top/b200/timing.ucf
new file mode 100644
index 000000000..e21d4cb1a
--- /dev/null
+++ b/fpga/usrp3/top/b200/timing.ucf
@@ -0,0 +1,40 @@
+
+# codec_main_clk is 40 MHz main tcxo clock
+NET "codec_main_clk*" TNM_NET = "codec_main_clk";
+TIMESPEC "TS_codec_main_clk" = PERIOD "codec_main_clk" 25000 ps HIGH 50 %;
+
+
+# IFCLK is 100 MHz GPIF clock
+NET "IFCLK" TNM_NET = "IFCLK";
+TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 10000 ps HIGH 50 %;
+
+
+# codec_data_clk is the data clock from catalina, sample rate dependent
+# this clock equals sample rate in CMOS DDR 1R1T mode
+# this clock is double the sample rate in CMOS DDR 2R2T mode
+# Max clock rate is 61.44 MHz
+NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p";
+TIMESPEC "TS_codec_data_clk_p" = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %;
+
+#always use IOB for GPIF pins for awesome timing
+INST "GPIF_*" IOB = TRUE;
+
+#low speed misc output group
+INST "SFDX*" TNM = ls_misc_out;
+INST "SRX*" TNM = ls_misc_out;
+INST "LED_*" TNM = ls_misc_out;
+INST "tx_enable*" TNM = ls_misc_out;
+INST "tx_bandsel_*" TNM = ls_misc_out;
+INST "rx_bandsel_*" TNM = ls_misc_out;
+INST "ref_sel" TNM = ls_misc_out;
+INST "*_ce" TNM = ls_misc_out;
+INST "*_miso" TNM = ls_misc_out;
+INST "*_mosi" TNM = ls_misc_out;
+INST "*_sclk" TNM = ls_misc_out;
+INST "gps_*" TNM = ls_misc_out;
+INST "FPGA_*D0" TNM = ls_misc_out;
+
+#constrain the misc IOs to the bus clock
+NET "bus_clk" TNM_NET = "bus_clk";
+TIMESPEC "TS_bus_clk" = PERIOD "bus_clk" 10 ns HIGH 50 %;
+TIMEGRP "ls_misc_out" OFFSET = OUT 15 ns AFTER "bus_clk" RISING;
diff --git a/fpga/usrp3/top/impactor.sh b/fpga/usrp3/top/impactor.sh
new file mode 100755
index 000000000..c6699424d
--- /dev/null
+++ b/fpga/usrp3/top/impactor.sh
@@ -0,0 +1,17 @@
+#!/bin/bash
+
+echo "loading $1 into FPGA..."
+
+CMD_PATH=/tmp/impact.cmd
+
+echo "generating ${CMD_PATH}..."
+
+echo "setmode -bscan" > ${CMD_PATH}
+echo "setcable -p auto" >> ${CMD_PATH}
+echo "addDevice -p 1 -file $1" >> ${CMD_PATH}
+echo "program -p 1" >> ${CMD_PATH}
+echo "quit" >> ${CMD_PATH}
+
+impact -batch ${CMD_PATH}
+
+echo "done!"
diff --git a/fpga/usrp3/top/python/bit_to_zynq_bin.py b/fpga/usrp3/top/python/bit_to_zynq_bin.py
new file mode 100755
index 000000000..0d32bf656
--- /dev/null
+++ b/fpga/usrp3/top/python/bit_to_zynq_bin.py
@@ -0,0 +1,62 @@
+#!/usr/bin/python
+import sys
+import os
+import struct
+
+def flip32(data):
+	sl = struct.Struct('<I')
+	sb = struct.Struct('>I')
+	b = buffer(data)
+	d = bytearray(len(data))
+	for offset in xrange(0, len(data), 4):
+		 sb.pack_into(d, offset, sl.unpack_from(b, offset)[0])
+	return d
+
+import argparse
+parser = argparse.ArgumentParser(description='Convert FPGA bit files to raw bin format suitable for flashing')
+parser.add_argument('-f', '--flip', dest='flip', action='store_true', default=False, help='Flip 32-bit endianess (needed for Zynq)')
+parser.add_argument("bitfile", help="Input bit file name")
+parser.add_argument("binfile", help="Output bin file name")
+args = parser.parse_args()
+
+short = struct.Struct('>H')
+ulong = struct.Struct('>I')
+
+bitfile = open(args.bitfile, 'rb')
+
+l = short.unpack(bitfile.read(2))[0]
+if l != 9:
+	raise Exception, "Missing <0009> header (0x%x), not a bit file" % l
+bitfile.read(l)
+l = short.unpack(bitfile.read(2))[0]
+d = bitfile.read(l)
+if d != 'a':
+	raise Exception, "Missing <a> header, not a bit file"
+
+l = short.unpack(bitfile.read(2))[0]
+d = bitfile.read(l)
+print "Design name:", d
+
+KEYNAMES = {'b': "Partname", 'c': "Date", 'd': "Time"}
+
+while 1:
+	k = bitfile.read(1)
+	if not k:
+		raise Exception, "unexpected EOF"
+	elif k == 'e':
+		l = ulong.unpack(bitfile.read(4))[0]
+		print "found binary data:", l
+		d = bitfile.read(l)
+		if args.flip:
+			d = flip32(d)
+		open(args.binfile, 'wb').write(d)
+		break
+	elif k in KEYNAMES:
+		l = short.unpack(bitfile.read(2))[0]
+		d = bitfile.read(l)
+		print KEYNAMES[k], d
+	else:
+		print "Unexpected key: ", k
+		l = short.unpack(bitfile.read(2))[0]
+		d = bitfile.read(l)
+
diff --git a/fpga/usrp3/top/python/check_inout.py b/fpga/usrp3/top/python/check_inout.py
new file mode 100755
index 000000000..d3b63dc34
--- /dev/null
+++ b/fpga/usrp3/top/python/check_inout.py
@@ -0,0 +1,51 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+
+# Description:
+# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf.
+# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes
+
+import sys
+import re
+
+if __name__=='__main__':
+  if len(sys.argv) == 2:
+    print "Usage: %s <top level Verilog file> <pin definition UCF>"
+    sys.exit(-1)
+
+  verilog_filename = sys.argv[1]
+  ucf_filename = sys.argv[2]
+
+  verilog_file = open(verilog_filename, 'r')
+  ucf_file = open(ucf_filename, 'r')
+
+  verilog_iolist = list()
+  ucf_iolist = list()
+
+  #read in all input, inout, and output declarations and compile a list
+  for line in verilog_file:
+    for match in re.findall(r"(?:input|inout|output) (?:reg )*(?:\[.*\] )*(\w+)", line.split("//")[0]):
+      verilog_iolist.append(match)
+
+  for line in ucf_file:
+      m = re.search(r"""NET "(\w+).*" """, line.split("#")[0])
+      if m is not None:
+        ucf_iolist.append(m.group(1))
+
+  #now find corresponding matches and error when you don't find one
+  #we search for .v defs without matching .ucf defs since the reverse isn't necessarily a problem
+  err = False
+
+  for item in verilog_iolist:
+    if item not in ucf_iolist:
+      print "Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item
+      err = True
+
+  if err:
+    sys.exit(-1)
+
+  print "No errors found."
+  sys.exit(0)
diff --git a/fpga/usrp3/top/python/check_timing.py b/fpga/usrp3/top/python/check_timing.py
new file mode 100644
index 000000000..4fec3e7d4
--- /dev/null
+++ b/fpga/usrp3/top/python/check_timing.py
@@ -0,0 +1,25 @@
+#!/usr/bin/env python
+#
+# Copyright 2011-2012 Ettus Research LLC
+#
+
+import sys
+import re
+
+def print_timing_constraint_summary(twr_file):
+    output = ""
+    keep = False
+    done = False
+    try: open(twr_file)
+    except IOError:
+        print "cannot open or find %s; no timing summary to print!"%twr_file
+        exit(-1)
+    for line in open(twr_file).readlines():
+        if 'Derived Constraint Report' in line: keep = True
+        if 'constraint' in line and 'met' in line: done = True
+        if not keep and done: keep = True
+        if keep: output += line
+        if done: break
+    print("\n\n"+output)
+
+if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:])
diff --git a/fpga/usrp3/top/python/make_lvbitx.py b/fpga/usrp3/top/python/make_lvbitx.py
new file mode 100644
index 000000000..b8ed99866
--- /dev/null
+++ b/fpga/usrp3/top/python/make_lvbitx.py
@@ -0,0 +1,57 @@
+#!/usr/bin/env python
+#
+# Copyright 2012 Ettus Research LLC
+#
+
+
+import xml.etree.ElementTree as et
+import base64
+from optparse import OptionParser
+
+
+def main():
+    parser = OptionParser()
+    parser.add_option("-l", "--lvbitxfile", dest="lvbitxfile",
+                  help="donor labview fpga bitfile", metavar="LVBITXFILE")
+
+    parser.add_option("-b", "--bitfile", dest="bitfile",
+                  help="xilinx generated bitfile", metavar="BITFILE")
+
+    parser.add_option("-o", "--output", dest="outfile",
+                  help="output labview fpga bitfile", metavar="OUTFILE")
+
+    parser.add_option("-s", "--signature", dest="signature",
+                  help="output labview fpga bitfile signature", metavar="SIGNATURE",
+                  default="ABCDEFG")
+
+
+    (options, args) = parser.parse_args()
+
+    tree = et.parse(options.lvbitxfile)
+    root = tree.getroot()
+    bs = root.find('Bitstream')
+    if bs is None: return
+
+    print('Found "%s" tag in "%s"...' % (bs.tag, options.lvbitxfile))
+
+    print('Writing old bitfile content to "%s"...' % (options.bitfile+'.bak'))
+    f_old = open(options.bitfile+'.bak', 'w')
+    f_old.write(base64.b64decode(bs.text))
+    f_old.close()
+
+
+    print('Reading new bitfile "%s"...' % options.bitfile)
+    f = open(options.bitfile, 'r')
+    newbs = base64.b64encode(f.read())
+    f.close()
+
+
+    bs.text = newbs
+    print('Saving new labview bitfile to  "%s"...' % options.outfile)
+    tree.write(options.outfile, xml_declaration=True, encoding='utf-8')
+
+if __name__ == '__main__':
+    try:
+        main()
+    except KeyboardInterrupt:
+        pass
diff --git a/fpga/usrp3/top/tcl/ise_helper.tcl b/fpga/usrp3/top/tcl/ise_helper.tcl
new file mode 100644
index 000000000..01e8226f1
--- /dev/null
+++ b/fpga/usrp3/top/tcl/ise_helper.tcl
@@ -0,0 +1,79 @@
+#
+# Copyright 2008 Ettus Research LLC
+# 
+
+proc set_props {process options} {
+	if ![string compare $options ""] {
+		return
+	}
+	set state 1
+	foreach opt $options {
+		if $state {
+			set key $opt
+			set state 0
+		} else {
+			puts ">>> Setting: $process\[$key\] = $opt" 
+			if ![string compare $process "Project"] {
+				project set $key $opt
+			} else {
+				project set $key $opt -process $process
+			}
+			set state 1	
+		}
+	}
+}
+
+if [file isfile $env(ISE_FILE)] {
+	puts ">>> Opening project: $env(ISE_FILE)"
+	project open $env(ISE_FILE)
+} else {	
+	puts ">>> Creating project: $env(ISE_FILE)"
+	project new $env(ISE_FILE)
+	
+	##################################################
+	# Set the project properties
+	##################################################
+	set_props "Project" $env(PROJECT_PROPERTIES)
+	
+	##################################################
+	# Add the sources
+	##################################################
+	foreach source $env(SOURCES) {
+		puts ">>> Adding source to project: $source"
+		xfile add $source
+	}
+	
+	##################################################
+	# Add the custom sources
+	##################################################
+	foreach source $env(CUSTOM_SRCS) {
+		puts ">>> Adding custom source to project: $source"
+		xfile add $source -include_global
+	}
+	
+	##################################################
+	# Set the top level module
+	##################################################
+	project set top $env(TOP_MODULE)
+	
+	##################################################
+	# Set the process properties
+	##################################################
+	set_props "Synthesize - XST" $env(SYNTHESIZE_PROPERTIES)
+	set_props "Translate" $env(TRANSLATE_PROPERTIES)
+	set_props "Map" $env(MAP_PROPERTIES)
+	set_props "Place & Route" $env(PLACE_ROUTE_PROPERTIES)
+	set_props "Generate Post-Place & Route Static Timing" $env(STATIC_TIMING_PROPERTIES)
+	set_props "Generate Programming File" $env(GEN_PROG_FILE_PROPERTIES)
+	set_props "Generate Post-Place & Route Simulation Model" $env(SIM_MODEL_PROPERTIES)
+}
+
+if [string compare [lindex $argv 0] ""] {
+	puts ">>> Running Process: [lindex $argv 0]"
+	process run [lindex $argv 0]
+}
+
+project close
+exit
+
+
diff --git a/fpga/usrp3/vita_chdr.txt b/fpga/usrp3/vita_chdr.txt
new file mode 100644
index 000000000..a194a88c6
--- /dev/null
+++ b/fpga/usrp3/vita_chdr.txt
@@ -0,0 +1,41 @@
+
+
+VRLP and VITA Fields
+====================
+
+All VRT (VITA 49.0) packets will be carried in a VRL (VITA 49.1) frame when outside the FPGA core.
+Every VRL frame will hold exactly one VRT packet.
+VRT packets must have stream ID
+VRT packets must NOT have integer seconds timestamps
+VRT packets must NOT have class ID
+VRT packets may have fractional seconds timestamps
+VRT packets may have trailer
+Only VITA IF Data and VITA Extension Context packets are allowed
+
+VITA Compressed Headers
+=======================
+
+Structure of a normal VRL-encapsulated VRT packet, in 64-bit wide format:
+
+VRLP { VRLP_text[31:0], frame_count[11:0], frame_size[19:0] }
+VRT0 { VRT_Header[31:0], Stream ID[31:0] }
+VRT1 { Fractional timestamp[63:0] } OPTIONAL
+...  Packet contents ...
+Optional Trailer
+"VEND"
+
+Since packet contents can have variable length, 64-bit alignment of trailer and VEND will vary
+
+Inside the FPGA switching fabric, the first line of "compressed vita packets" will be called the "CHDR".
+The "CHDR" compresses the contents of the VRLP header and VRT header and streamID, and has the following format:
+
+BIT      Meaning
+63       is_extension_context  (0 for data, 1 for control packets)
+62       reserved
+61       has_time (0 for no, 1 for time field on next line)
+60       EOB (end of burst indicator)
+59:48    12-bit sequence number (from VRLP frame count, bottom 4 bits should match VRT seq number)
+47:32    16-bit length in bytes (from VRT length in words32)
+31:0     stream ID
+
+Inside the fabric, the "VEND" from VRLP is dropped.
-- 
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