From 05137529261bf9eae2a8b72cdf67e86a8ff96927 Mon Sep 17 00:00:00 2001
From: Wade Fife <wade.fife@ettus.com>
Date: Tue, 16 Jun 2020 12:16:33 -0500
Subject: fpga: tools: Fix ModelSim return status

---
 fpga/usrp3/tools/scripts/launch_modelsim.sh | 8 ++++++--
 fpga/usrp3/tools/scripts/launch_vlint.sh    | 9 ++++++---
 2 files changed, 12 insertions(+), 5 deletions(-)

(limited to 'fpga')

diff --git a/fpga/usrp3/tools/scripts/launch_modelsim.sh b/fpga/usrp3/tools/scripts/launch_modelsim.sh
index a0aa3d74e..8fc7309a0 100755
--- a/fpga/usrp3/tools/scripts/launch_modelsim.sh
+++ b/fpga/usrp3/tools/scripts/launch_modelsim.sh
@@ -57,13 +57,17 @@ do
 done
 
 if [ $MSIM_MODE == "gui" ]; then
+    echo "* Launching ModelSim"
     vsim $MSIM_DEFAULT $MSIM_ARGS $MSIM_LIB_ARGS $MSIM_SIM_TOP 2>&1 | while IFS= read -r line; do
         print_color $line
     done
-    if [ ${PIPESTATUS[0]} -ne 0 ]; then exit ${PIPESTATUS[0]}; fi
+    exit_status=${PIPESTATUS[0]}
+    if [ ${exit_status} -ne 0 ]; then exit ${exit_status}; fi
 elif [ $MSIM_MODE == "batch" ]; then
+    echo "* Launching ModelSim"
     vsim -batch -do "run -all; quit -f" $MSIM_DEFAULT $MSIM_ARGS $MSIM_LIB_ARGS $MSIM_SIM_TOP 2>&1 | while IFS= read -r line; do
         print_color $line
     done
-    if [ ${PIPESTATUS[0]} -ne 0 ]; then exit ${PIPESTATUS[0]}; fi
+    exit_status=${PIPESTATUS[0]}
+    if [ ${exit_status} -ne 0 ]; then exit ${exit_status}; fi
 fi
diff --git a/fpga/usrp3/tools/scripts/launch_vlint.sh b/fpga/usrp3/tools/scripts/launch_vlint.sh
index 90df485df..a0169ce3e 100755
--- a/fpga/usrp3/tools/scripts/launch_vlint.sh
+++ b/fpga/usrp3/tools/scripts/launch_vlint.sh
@@ -126,21 +126,24 @@ if [[ -n "$SV_FILES" ]]; then
     vlog $SVLOG_ARGS -sv -f svlogarglist.txt 2>&1 | while IFS= read -r line; do
         print_color $line
     done
-    if [ ${PIPESTATUS[0]} -ne 0 ]; then exit ${PIPESTATUS[0]}; fi
+    exit_status=${PIPESTATUS[0]}
+    if [ ${exit_status} -ne 0 ]; then exit ${exit_status}; fi
 fi
 if [[ -n "$V_FILES" ]]; then
     echo "* Compiling Verilog"
     vlog $VLOG_ARGS -f vlogarglist.txt 2>&1 | while IFS= read -r line; do
         print_color $line
     done
-    if [ ${PIPESTATUS[0]} -ne 0 ]; then exit ${PIPESTATUS[0]}; fi
+    exit_status=${PIPESTATUS[0]}
+    if [ ${exit_status} -ne 0 ]; then exit ${exit_status}; fi
 fi
 if [[ -n "$VHD_FILES" ]]; then
     echo "* Compiling VHDL"
     vcom $VHDL_ARGS -f vcomarglist.txt 2>&1 | while IFS= read -r line; do
         print_color $line
     done
-    if [ ${PIPESTATUS[0]} -ne 0 ]; then exit ${PIPESTATUS[0]}; fi
+    exit_status=${PIPESTATUS[0]}
+    if [ ${exit_status} -ne 0 ]; then exit ${exit_status}; fi
 fi
 
 
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