From 9335939b9b3ab85cee5908ff3357f9e7819e3366 Mon Sep 17 00:00:00 2001 From: Javier Valenzuela Date: Mon, 12 Jul 2021 13:54:33 -0500 Subject: fpga: x400: Add GPIO control via ATR and DB state --- fpga/usrp3/top/x400/Makefile.x4xx.inc | 1 + fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm | 37 +- fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm | 3636 +++++++++++++++----- fpga/usrp3/top/x400/doc/x4xx_core_common_buses.svg | 3 + .../top/x400/regmap/core_regs_regmap_utils.vh | 2 +- fpga/usrp3/top/x400/regmap/dio_regmap_utils.vh | 63 +- .../usrp3/top/x400/regmap/gpio_atr_regmap_utils.vh | 97 + .../top/x400/regmap/radio_dio_regmap_utils.vh | 31 + .../x400/regmap/versioning_regs_regmap_utils.vh | 2 +- fpga/usrp3/top/x400/x4xx.v | 2 +- fpga/usrp3/top/x400/x4xx_core.v | 3 +- fpga/usrp3/top/x400/x4xx_core_common.v | 259 +- fpga/usrp3/top/x400/x4xx_dio.v | 433 ++- fpga/usrp3/top/x400/x4xx_gpio_atr.v | 376 ++ 14 files changed, 3839 insertions(+), 1106 deletions(-) create mode 100644 fpga/usrp3/top/x400/doc/x4xx_core_common_buses.svg create mode 100644 fpga/usrp3/top/x400/regmap/gpio_atr_regmap_utils.vh create mode 100644 fpga/usrp3/top/x400/regmap/radio_dio_regmap_utils.vh create mode 100644 fpga/usrp3/top/x400/x4xx_gpio_atr.v (limited to 'fpga/usrp3/top/x400') diff --git a/fpga/usrp3/top/x400/Makefile.x4xx.inc b/fpga/usrp3/top/x400/Makefile.x4xx.inc index d031d7e83..2c6de75ec 100644 --- a/fpga/usrp3/top/x400/Makefile.x4xx.inc +++ b/fpga/usrp3/top/x400/Makefile.x4xx.inc @@ -73,6 +73,7 @@ x4xx_core_common.v \ x4xx_global_regs.v \ x4xx_versioning_regs.v \ x4xx_dio.v \ +x4xx_gpio_atr.v \ rf/100m/rf_core_100m.v \ rf/200m/rf_core_200m.v \ rf/200m/rf_down_4to2.v \ diff --git a/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm b/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm index 69ee17738..c302c2f9c 100644 --- a/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm +++ b/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm @@ -281,7 +281,12 @@

DIO_MASTER_REGISTER

DIO_DIRECTION_REGISTER

DIO_INPUT_REGISTER

-

DIO_OUTPUT_REGISTER

+

DIO_OUTPUT_REGISTER

+

DIO_SOURCE_REGISTER

+

RADIO_SOURCE_REGISTER

+

INTERFACE_DIO_SELECT

+

DIO_OVERRIDE

+

SW_DIO_CONTROL

@@ -346,6 +351,23 @@

QSFP_PORT_1_3_INFO_REG

+

+ + + GPIO_ATR_REGMAP +

+

+ + + GPIO_ATR_REGS +

+
+

ATR_STATE

+

CLASSIC_ATR_CONFIG

+

ATR_OPTION_REGISTRER

+

GPIO_DIR

+

GPIO_DISABLED

+

GPIO_IN

+
+

+ JTAG_REGMAP @@ -547,6 +569,19 @@

DIO_WINDOW

+

+ + + RADIO_DIO_REGMAP +

+

+ + + DIO_SOURCES +

+
+

RADIO_GPIO_ATR_REGS

+

DIO_SOURCE_CONTROL

+
+

+ RECONFIG_REGMAP diff --git a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm index be0e58707..4e3b3c3a8 100644 --- a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm +++ b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm @@ -2383,6 +2383,10 @@ This enumeration is used to create the constants held in the basic registers. The registers contained here conform the mboard-regs node that MPM uses to manage general FPGA control/status calls, such as versioning, timekeeper, GPIO, etc. + + The following diagram shows how the communication bus interacts with the + modules in CORE_REGS. +

CORE_REGS

@@ -2629,7 +2633,7 @@ Window to access the timekeeper register map. - +
DIO
  offset=0x2000
  size=0x20 (32 bytes)
  size=0x40 (64 bytes)
@@ -3232,10 +3236,15 @@ Total Offset =

DIO_REGMAP

DIO_REGS

- Registers to control the GPIO buffer direction on the FPGA connected to the DIO board. - Further registers enable the PS to control and read the GPIO lines as master. - Make sure the GPIO lines between FPGA and GPIO board are not driven by two drivers. - Set the DIO registers in PS_CPLD_BASE_REGMAP appropriately. + Registers to control the GPIO buffer direction on the FPGA connected to + the DIO board. Further registers enable different sources to control and + read the GPIO lines as master. The following diagram shows how source + selection multiplexers are arranged, as well as an indicator for the + register that control them.
+ Front-Panel Programmable GPIOs
+ Make sure the GPIO lines between FPGA and GPIO board are not driven by + two drivers. Set the DIO registers in PS_CPLD_BASE_REGMAP appropriately.
@@ -3302,8 +3311,6 @@ Total Offset = - - @@ -3313,6 +3320,15 @@ Total Offset = + + Total Offset = -
+ + + + +
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
  0x001000
+ +		 @@ -3323,7 +3339,7 @@ Total Offset =
  0x00C000 +
  0x00D000
@@ -3337,14 +3353,17 @@ Total Offset =

Initial Value = 0x00000000

-

This register is defined in HDL source file x4xx_dio.v.

+

This register is defined in HDL source file x4xx_dio.v.
+It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

-Sets whether the DIO signal line is driven by this register interface or the user application.
- 0 = user application is master, 1 = PS is master +Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Sets whether the DIO signal line is driven by this register interface + or the user application.
+ 0 = user application is master, 1 = output of SW_DIO_CONTROL is master
@@ -3363,7 +3382,7 @@ Sets whether the DIO signal line is driven by this register interface or the use 27..16 -

DIO_MASTER_B   (initialvalue=0)

+

DIO_PORT_B   (initialvalue=0)

@@ -3381,7 +3400,7 @@ Sets whether the DIO signal line is driven by this register interface or the use 11..0 -

DIO_MASTER_A   (initialvalue=0)

+

DIO_PORT_A   (initialvalue=0)

@@ -3457,8 +3476,6 @@ Total Offset = - - @@ -3468,6 +3485,15 @@ Total Offset = + + Total Offset = -
+ + + + +
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
  0x001000
+ +		 @@ -3478,7 +3504,7 @@ Total Offset =
  0x00C004 +
  0x00D004
@@ -3492,14 +3518,17 @@ Total Offset =

Initial Value = 0x00000000

-

This register is defined in HDL source file x4xx_dio.v.

+

This register is defined in HDL source file x4xx_dio.v.
+It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

+Holds a single bit setting for DIO lines in both ports. One bit per pin.
Set the direction of FPGA buffer connected to DIO ports on the DIO board.
- Each bit represents one signal line. 0 = line is an input to the FPGA, 1 = line is an output driven by the FPGA. + Each bit represents one signal line. 0 = line is an input to the FPGA, + 1 = line is an output driven by the FPGA.
@@ -3518,7 +3547,7 @@ Set the direction of FPGA buffer connected to DIO ports on the DIO board.
27..16 -

DIO_DIRECTION_B   (initialvalue=0)

+

DIO_PORT_B   (initialvalue=0)

@@ -3536,7 +3565,7 @@ Set the direction of FPGA buffer connected to DIO ports on the DIO board.
11..0 -

DIO_DIRECTION_A   (initialvalue=0)

+

DIO_PORT_A   (initialvalue=0)

@@ -3612,8 +3641,6 @@ Total Offset = - - @@ -3623,6 +3650,15 @@ Total Offset = + + Total Offset = -
+ + + + +
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
  0x001000
+ +		 @@ -3633,7 +3669,7 @@ Total Offset =
  0x00C008 +
  0x00D008
@@ -3644,15 +3680,17 @@ Total Offset =

-

Initial Value not specified +

Initial Value = 0x00000000

-

This register is defined in HDL source file x4xx_dio.v.

+

This register is defined in HDL source file x4xx_dio.v.
+It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

+Holds a single bit setting for DIO lines in both ports. One bit per pin.
Status of each bit at the FPGA input.
@@ -3672,7 +3710,7 @@ Status of each bit at the FPGA input. 27..16 -

DIO_INPUT_B

+

DIO_PORT_B   (initialvalue=0)

@@ -3690,7 +3728,7 @@ Status of each bit at the FPGA input. 11..0 -

DIO_INPUT_A

+

DIO_PORT_A   (initialvalue=0)

@@ -3766,8 +3804,6 @@ Total Offset = - - @@ -3777,6 +3813,15 @@ Total Offset = + + Total Offset = -
+ + + + +
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
  0x001000
+ +		 @@ -3787,7 +3832,7 @@ Total Offset =
  0x00C00C +
  0x00D00C
@@ -3801,13 +3846,16 @@ Total Offset =

Initial Value = 0x00000000

-

This register is defined in HDL source file x4xx_dio.v.

+

This register is defined in HDL source file x4xx_dio.v.
+It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

-Controls the values on each DIO signal line in case the line master is set to PS in DIO_MASTER_REGISTER. +Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls the values on each DIO signal line in case the line master is + set to PS in DIO_MASTER_REGISTER.
@@ -3826,7 +3874,7 @@ Controls the values on each DIO signal line in case the line master is set to PS 27..16 -

DIO_OUTPUT_B   (initialvalue=0)

+

DIO_PORT_B   (initialvalue=0)

@@ -3844,7 +3892,7 @@ Controls the values on each DIO signal line in case the line master is set to PS 11..0 -

DIO_OUTPUT_A   (initialvalue=0)

+

DIO_PORT_A   (initialvalue=0)

@@ -3854,41 +3902,13 @@ Controls the values on each DIO signal line in case the line master is set to PS - - - - -
- -

DMA_REGMAP

-
-
-

XILINX_DMA_REGISTERS

-
-

Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11

-
    -
  • https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
    • -
-
- -
- -
- -

ETH_DMA_CTRL_REGMAP

- This is the map that the nixge driver uses in Ethernet DMA to - move data between the Processing System's architecture and the fabric. - This map is a combination of two main components: a Xilix AXI DMA engine - and some registers for MAC/PHY control. -

ETH_DMA_CTRL

-
- + -

Offset 0x0000: AXI_DMA_CTRL Window (R|W)

+

Offset 0x0010: DIO_SOURCE_REGISTER Register (R|W)

- (show extended info) -
+ (show extended info) +
@@ -3905,8 +3925,8 @@ Controls the values on each DIO signal line in case the line master is set to PS @@ -3914,9 +3934,17 @@ Controls the values on each DIO signal line in case the line master is set to PS + + @@ -3929,7 +3957,7 @@ Controls the values on each DIO signal line in case the line master is set to PS Total Offset = -
- - + +
AXI_HPM0_REGMAP|INT_ETH_DMA
  0x10000A4000
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
 - - - + + +
AXI_DMA_CTRL
  offset=0x0000
  size=0x4000 (16 Kbytes)
CORE_REGS_REGMAP|DIO
  0x002000
+ +		 + + + +
DIO_SOURCE_REGISTER
  offset=0x0010
  0x10000A4000 +
  0x10000A2010
@@ -3938,47 +3966,13 @@ Total Offset = -

- -

This window is defined in HDL source file common_regs.v.

- -
- -
- -Refer to Xilinx' AXI DMA v7.1 IP product guide for further - information on this register map: - https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf - -
- -
- -
- - -

Offset 0x4000: ETH_IO_CTRL Window (R|W)

- - (show extended info) -
- - - - - @@ -3986,13 +3980,14 @@ Refer to Xilinx' AXI DMA v7.1 IP product guide for further + +
- - - -
Port ARM_M_AXI_HPM0
- -		 - - + +
AXI_HPM0_REGMAP|INT_ETH_DMA
  0x10000A4000
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
 - - - + +
ETH_IO_CTRL
  offset=0x4000
  size=0x2000 (8 Kbytes)
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
  0x001000
 @@ -4001,7 +3996,7 @@ Refer to Xilinx' AXI DMA v7.1 IP product guide for further Total Offset = -
  0x10000A8000 +
  0x00D010
@@ -4012,35 +4007,73 @@ Total Offset =

-

This window is defined in HDL source file common_regs.v.

+

Initial Value = 0x00000000 +

+ +

This register is defined in HDL source file x4xx_dio.v.
+It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

-MAC/PHY control for the Ethernet interface. - -
+Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls whether the DIO lines reflect the state of DIO_MASTER_REGISTER + or the radio blocks. 0 = DIO_MASTER_REGISTER, + 1 = Radio block output(DIO_OVERRIDE)
-
+ + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..28 +

Reserved

+

+ +
27..16 +

DIO_PORT_B   (initialvalue=0)

+

+ +
15..12 +

Reserved

+

+ +
11..0 +

DIO_PORT_A   (initialvalue=0)

+

+ +
-
- -

GLOBAL_REGS_REGMAP

- -

GLOBAL_REGS

-
- + -

Offset 0x0000: COMPAT_NUM_REG Register (R)

+

Offset 0x0014: RADIO_SOURCE_REGISTER Register (R|W)

- (show extended info) -
+ (show extended info) +
@@ -4066,8 +4099,17 @@ MAC/PHY control for the Ethernet interface. + + @@ -4075,12 +4117,42 @@ MAC/PHY control for the Ethernet interface. + + + + + + + + + +
- - + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
CORE_REGS_REGMAP|DIO
  0x002000
+ +		 + + + +
RADIO_SOURCE_REGISTER
  offset=0x0014
 - - + + + +
COMPAT_NUM_REG
  offset=0x0000
+ + +Total Offset =
  0x10000A2014 + +
+ +
+ + + + +
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
+ +		 + + + +
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
  0x001000
 @@ -4089,7 +4161,7 @@ MAC/PHY control for the Ethernet interface. Total Offset = -
  0x10000A0000 +
  0x00D014
@@ -4100,16 +4172,21 @@ Total Offset =

-

Initial Value not specified +

Initial Value = 0x00000000

-

This register is defined in HDL source file x4xx_global_regs.v.

+

This register is defined in HDL source file x4xx_dio.v.
+It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

-Revision number +Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls which radio block to use the ATR state from to determine the + state of the DIO lines. + 0 = Radio#0 + 1 = Radio#1
@@ -4117,34 +4194,52 @@ Revision number BitsName - 31..16 + 31..28 -

COMPAT_MAJOR

+

Reserved

- - 15..0 + + 27..16 -

COMPAT_MINOR

+

DIO_PORT_B   (initialvalue=0)

- - -
- -
- + + 15..12 + +

Reserved

+

-

Offset 0x0004: DATESTAMP_REG Register (R)

+ + + + + 11..0 + +

DIO_PORT_A   (initialvalue=0)

+

+ + + + + - (show extended info) -
+
+ +
+ + +

Offset 0x0018: INTERFACE_DIO_SELECT Register (R|W)

+ + (show extended info) +
@@ -4170,8 +4265,17 @@ Revision number + + @@ -4179,12 +4283,42 @@ Revision number + + + + + + + + + +
- - + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
CORE_REGS_REGMAP|DIO
  0x002000
+ +		 + + + +
INTERFACE_DIO_SELECT
  offset=0x0018
 - - + + + +
DATESTAMP_REG
  offset=0x0004
+ + +Total Offset =
  0x10000A2018 + +
+ +
+ + + + +
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
+ +		 + + + +
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
  0x001000
 @@ -4193,7 +4327,7 @@ Revision number Total Offset = -
  0x10000A0004 +
  0x00D018
@@ -4204,16 +4338,20 @@ Total Offset =

-

Initial Value not specified +

Initial Value = 0x00000000

-

This register is defined in HDL source file x4xx_global_regs.v.

+

This register is defined in HDL source file x4xx_dio.v.
+It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

-Build datestamp (32-bit) +Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls which of the two available digital interfaces controls the DIO lines. + 0 = Digital interface from Radio#0, + 1 = Digital Interface from Radio#1.
@@ -4221,54 +4359,36 @@ Build datestamp (32-bit) BitsName - 31..27 - -

DAY

-

- - - - - - 26..23 + 31..28 -

MONTH

+

Reserved

- 22..17 - -

YEAR

-

This is the year number after 2000 (e.g. 2019 = d19).

- - - - - - 16..12 + 27..16 -

HOUR

+

DIO_PORT_B   (initialvalue=0)

- - 11..6 + + 15..12 -

MINUTES

+

Reserved

- 5..0 + 11..0 -

SECONDS

+

DIO_PORT_A   (initialvalue=0)

@@ -4279,12 +4399,12 @@ Build datestamp (32-bit)
- + -

Offset 0x0008: GIT_HASH_REG Register (R)

+

Offset 0x001C: DIO_OVERRIDE Register (R|W)

- (show extended info) -
+ (show extended info) +
@@ -4310,17 +4430,17 @@ Build datestamp (32-bit) - @@ -4333,7 +4453,7 @@ Build datestamp (32-bit) Total Offset = -
- - + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
CORE_REGS_REGMAP|DIO
  0x002000
 + - - + +
GIT_HASH_REG
  offset=0x0008
DIO_OVERRIDE
  offset=0x001C
  0x10000A0008 +
  0x10000A201C
@@ -4342,48 +4462,13 @@ Total Offset = -

- -

Initial Value not specified -

- -

This register is defined in HDL source file x4xx_global_regs.v.

- -
- -
- -Git hash of source commit. - -
- -
- -
- - -

Offset 0x000C: SCRATCH_REG Register (R|W)

- - (show extended info) -
- - - - - @@ -4391,20 +4476,13 @@ Git hash of source commit. - + -
- - - -
Port ARM_M_AXI_HPM0
- -		 - - + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
 - - + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
  0x001000
 - - - - -
SCRATCH_REG
  offset=0x000C
- -		 @@ -4414,7 +4492,7 @@ Git hash of source commit. Total Offset =
  0x10000A000C +
  0x00D01C
@@ -4425,28 +4503,75 @@ Total Offset =

-

Initial Value not specified +

Initial Value = 0x00000000

-

This register is defined in HDL source file x4xx_global_regs.v.

+

This register is defined in HDL source file x4xx_dio.v.
+It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

-Scratch register for testing. +Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls whether the radio input to the DIO_SOURCE_REGISTER mux + connects to the ATR control or a Digital interface block. The output + of the mux controlled by this bit goes to DIO_SOURCE_REGISTER. + 0 = Drive the ATR state(RADIO_SOURCE_REGISTER), 1 = Drive + Digital interface block(Output of INTERFACE_DIO_SELECT).
+ + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..28 +

Reserved

+

+ +
27..16 +

DIO_PORT_B   (initialvalue=0)

+

+ +
15..12 +

Reserved

+

+ +
11..0 +

DIO_PORT_A   (initialvalue=0)

+

+ +
+
- + -

Offset 0x0010: DEVICE_ID_REG Register (R|W)

+

Offset 0x0020: SW_DIO_CONTROL Register (R|W)

- (show extended info) -
+ (show extended info) +
@@ -4472,17 +4597,17 @@ Scratch register for testing. - @@ -4495,7 +4620,7 @@ Scratch register for testing. Total Offset = -
- - + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
CORE_REGS_REGMAP|DIO
  0x002000
 + - - + +
DEVICE_ID_REG
  offset=0x0010
SW_DIO_CONTROL
  offset=0x0020
  0x10000A0010 +
  0x10000A2020
@@ -4504,44 +4629,87 @@ Total Offset = -

+ -

Initial Value not specified -

+ -

This register is defined in HDL source file x4xx_global_regs.v.

+ + + +
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
-
+ -
+ -Register that contains the motherboard's device ID. + + + +
RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
  0x001000
-
+ - - - - - - + + + + + +
BitsName
31 -

PCIE_PRESENT_BIT

-

Set to 1 if PCI-Express core is present in FPGA design.

+		 + + + + + +
+ + +Total Offset =
  0x00D020 + +
+ +

+ +

Initial Value = 0x00000000 +

+ +

This register is defined in HDL source file x4xx_dio.v.
+It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

+ +
+ +
+ +Holds a single bit setting for DIO lines in both ports. One bit per pin.
+Controls which source is forwarded to the DIO_MASTER_REGISTER mux. + This configuration is applied independently for each DIO line. + 0 = MPM Ctrlport endpoint, 1 = PS Netlist DIO signal. + +
+ + + + + + + - + - + - - + + @@ -4562,13 +4730,41 @@ Register that contains the motherboard's device ID. + + + + +
+ +

DMA_REGMAP

+
+
+

XILINX_DMA_REGISTERS

+
+

Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11

+
    +
  • https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
    • +
+
+ +
+ +
+ +

ETH_DMA_CTRL_REGMAP

+ This is the map that the nixge driver uses in Ethernet DMA to + move data between the Processing System's architecture and the fabric. + This map is a combination of two main components: a Xilix AXI DMA engine + and some registers for MAC/PHY control. +

ETH_DMA_CTRL

+
- + -

Offset 0x0014: RFNOC_INFO_REG Register (R)

+

Offset 0x0000: AXI_DMA_CTRL Window (R|W)

- (show extended info) -
BitsName
31..28 +

Reserved

+

30..2427..16 -

Reserved

+

DIO_PORT_B   (initialvalue=0)
23..1615..12

Reserved

@@ -4549,10 +4717,10 @@ Register that contains the motherboard's device ID.
15..0
11..0 -

DEVICE_ID

+

DIO_PORT_A   (initialvalue=0)

@@ -4585,8 +4781,8 @@ Register that contains the motherboard's device ID. @@ -4594,8 +4790,9 @@ Register that contains the motherboard's device ID. @@ -4603,8 +4800,71 @@ Register that contains the motherboard's device ID. + + + +
- - + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
AXI_HPM0_REGMAP|INT_ETH_DMA
  0x10000A4000
 - - + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
AXI_DMA_CTRL
  offset=0x0000
  size=0x4000 (16 Kbytes)
 - - + + + +
RFNOC_INFO_REG
  offset=0x0014
+ + +Total Offset =
  0x10000A4000 + +
+ +

+ +

This window is defined in HDL source file common_regs.v.

+ +
+ +
+ +Refer to Xilinx' AXI DMA v7.1 IP product guide for further + information on this register map: + https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf + +
+ +
+ +
+ + +

Offset 0x4000: ETH_IO_CTRL Window (R|W)

+ + (show extended info) +
+ + + + + + + + + + @@ -4617,7 +4877,7 @@ Register that contains the motherboard's device ID. Total Offset = -
+ + + +
Port ARM_M_AXI_HPM0
+ +		 + + + + +
AXI_HPM0_REGMAP|INT_ETH_DMA
  0x10000A4000
+ +		 + + + + +
ETH_IO_CTRL
  offset=0x4000
  size=0x2000 (8 Kbytes)
  0x10000A0014 +
  0x10000A8000
@@ -4628,60 +4888,35 @@ Total Offset =

-

Initial Value not specified -

- -

This register is defined in HDL source file x4xx_global_regs.v.

+

This window is defined in HDL source file common_regs.v.

-Register that provides information on the RFNoC protocol. +MAC/PHY control for the Ethernet interface.
- - - - - - - - - - - - - - - - - - -
BitsName
31..16 -

CHDR_WIDTH

-

- -
15..8 -

RFNOC_PROTO_MAJOR

-

- -
7..0 -

RFNOC_PROTO_MINOR

-

- -
+
+ +
+
+ +

GLOBAL_REGS_REGMAP

+ +

GLOBAL_REGS

+
- + -

Offset 0x0018: CLOCK_CTRL_REG Register (R|W)

+

Offset 0x0000: COMPAT_NUM_REG Register (R)

- (show extended info) -
+ (show extended info) +
@@ -4716,8 +4951,8 @@ Register that provides information on the RFNoC protocol. @@ -4730,7 +4965,7 @@ Register that provides information on the RFNoC protocol. Total Offset = -
- - + +
CLOCK_CTRL_REG
  offset=0x0018
COMPAT_NUM_REG
  offset=0x0000
  0x10000A0018 +
  0x10000A0000
@@ -4741,7 +4976,7 @@ Total Offset =

-

Initial Value = 0x00000000 +

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

@@ -4750,7 +4985,7 @@ Total Offset =
-Control register for clocking resources. +Revision number
@@ -4758,234 +4993,34 @@ Control register for clocking resources. BitsName - 31..24 + 31..16 -

PPS_BRC_DELAY

-

Number of base reference clock cycles from appearance of the PPS - rising edge to the occurrence of the aligned edge of base reference - clock and PLL reference clock at the sample PLL output. This number - is the sum of the actual value based on PLL_SYNC_DELAY (also - accumulate the fixed amount of clock cycles) and if any the number of - cycles the SPLL requires from issuing of the SYNC signal to the - aligned edge (with LMK04832 = 0).
- The number written to this register has to be reduced by 1 due to - HDL implementation.

+

COMPAT_MAJOR

+

- 23..16 + 15..0 -

PLL_SYNC_DELAY

-

Due to the HDL implementation the rising edge of the SYNC signal for - the LMK04832 is generated 2 clock cycles after the PPS rising edge. - This delay can be further increased by setting this delay value - (e.g. PLL_SYNC_DELAY=3 will result in a total delay of 5 clock cycles).
- In case two X400 devices are connected using the PPS and reference clock the master delay value needs to be 3 clock cycles - higher than the slave delay value to align the LMK sync edges in time.

+

COMPAT_MINOR

+

- - 15..10 - -

Reserved

-

- - - - - - 9r - -

PLL_SYNC_DONE

-

Indicates the success of the PLL reset started by PLL_SYNC_TRIGGER. Reset on deassertion of PLL_SYNC_TRIGGER.

- - - - - - 8w - -

PLL_SYNC_TRIGGER

-

Assertion triggers the SYNC signal generation for LMK04832 after the next appearance of the PPS rising edge. - There is no self reset on this trigger. - Keep this trigger asserted until PLL_SYNC_DONE is asserted.

- - - - - - 7..6 - -

Reserved

-

- - - - - - 5..4 - -

TRIGGER_IO_SELECT   (initialvalue=TRIG_IO_INPUT)

-

IMPORTANT! SW must ensure any TRIG_IO consumers (downstream devices) ignore - and/or re-sync after enabling this port, since the output-enable is basically - asynchronous to the actual TRIG_IO driver.

- -

- The values for this bitfield are in the TRIG_IO_ENUM table. - (show here) -

-
- -
- - - - - - - - - - - - - - - - - - - - - - - - - - -
Value Name
0 -

TRIG_IO_INPUT

- -
1 -

TRIG_IO_PPS_OUTPUT

- -
- -

- This enumerated type is defined in HDL source file x4xx_global_regs.v. -

- -
- -
- - - - - - 3r - -

REFCLK_LOCKED

-

RESERVED. This bit is not implemented on X4xx and reads as 0.

- - - - - - 2 - -

REF_SELECT

-

RESERVED. This bit is not implemented on X4xx and reads as 0.

- - - - - - 1..0 - -

PPS_SELECT   (initialvalue=PPS_INT_25MHZ)

-

Select the source of the PPS signal. - For the internal generation the value depending on the base reference clock has to be chosen. - The external reference is taken from the PPS_IN pin and is independent of the base reference clock.

- -

- The values for this bitfield are in the PPS_ENUM table. - (show here) -

-
- -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Value Name
0 -

PPS_INT_25MHZ

- -
1 -

PPS_INT_10MHZ

- -
2 -

PPS_EXT

- -
- -

- This enumerated type is defined in HDL source file x4xx_global_regs.v. -

- -
- -
- - - -
- + -

Offset 0x001C: PPS_CTRL_REG Register (R|W)

+

Offset 0x0004: DATESTAMP_REG Register (R)

- (show extended info) -
+ (show extended info) +
@@ -5020,8 +5055,8 @@ Control register for clocking resources. @@ -5034,7 +5069,7 @@ Control register for clocking resources. Total Offset = -
- - + +
PPS_CTRL_REG
  offset=0x001C
DATESTAMP_REG
  offset=0x0004
  0x10000A001C +
  0x10000A0004
@@ -5054,7 +5089,7 @@ Total Offset =
-Control registers for PPS generation. +Build datestamp (32-bit)
@@ -5062,58 +5097,55 @@ Control registers for PPS generation. BitsName - 31 + 31..27 -

PPS_RC_ENABLED

-

Enables the PPS signal in radio clock domain. Please make sure that - the values of PPS_BRC_DELAY, PPS_PRC_DELAY and PRC_RC_DIVIDER are - set before enabling this bit. It is recommended to disable the PPS - for changes on the other values. Use a wait time of at least 1 second - before changing this value to ensure the values are stable for the - next PPS edge.

+

DAY

+

- 30 + 26..23 -

Reserved

+

MONTH

- 29..28 + 22..17 -

PRC_RC_DIVIDER

-

Clock multiplier used to generate radio clock from PLL reference clock. - The value written to the register has to be reduced by 2 due to - HDL implementation.

+

YEAR

+

This is the year number after 2000 (e.g. 2019 = d19).

- 27..26 + 16..12 -

Reserved

+

HOUR

- 25..0 + 11..6 -

PPS_PRC_DELAY

-

The number of PLL reference clock cycles from one aligned edge to the - desired aligned edge to issue the PPS in radio clock domain. This - delay is configurable to any aligned edge within a maximum delay of 1 - second (period of PPS).
- The value written to the register has to be reduced by 4 due to - HDL implementation.

+

MINUTES

+

+ + + + + + 5..0 + +

SECONDS

+

@@ -5123,12 +5155,1326 @@ Control registers for PPS generation.
- + + +

Offset 0x0008: GIT_HASH_REG Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + +
+ + + +
Port ARM_M_AXI_HPM0
+ +		 + + + + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
+ +		 + + + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
+ +		 + + + + +
GIT_HASH_REG
  offset=0x0008
+ +		 + + + + + +
+ + +Total Offset =
  0x10000A0008 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file x4xx_global_regs.v.

+ +
+ +
+ +Git hash of source commit. + +
+ +
+ +
+ + +

Offset 0x000C: SCRATCH_REG Register (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + +
+ + + +
Port ARM_M_AXI_HPM0
+ +		 + + + + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
+ +		 + + + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
+ +		 + + + + +
SCRATCH_REG
  offset=0x000C
+ +		 + + + + + +
+ + +Total Offset =
  0x10000A000C + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file x4xx_global_regs.v.

+ +
+ +
+ +Scratch register for testing. + +
+ +
+ +
+ + +

Offset 0x0010: DEVICE_ID_REG Register (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + +
+ + + +
Port ARM_M_AXI_HPM0
+ +		 + + + + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
+ +		 + + + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
+ +		 + + + + +
DEVICE_ID_REG
  offset=0x0010
+ +		 + + + + + +
+ + +Total Offset =
  0x10000A0010 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file x4xx_global_regs.v.

+ +
+ +
+ +Register that contains the motherboard's device ID. + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31 +

PCIE_PRESENT_BIT

+

Set to 1 if PCI-Express core is present in FPGA design.

+ +
30..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..0 +

DEVICE_ID

+

+ +
+ +
+ +
+ + +

Offset 0x0014: RFNOC_INFO_REG Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + +
+ + + +
Port ARM_M_AXI_HPM0
+ +		 + + + + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
+ +		 + + + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
+ +		 + + + + +
RFNOC_INFO_REG
  offset=0x0014
+ +		 + + + + + +
+ + +Total Offset =
  0x10000A0014 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file x4xx_global_regs.v.

+ +
+ +
+ +Register that provides information on the RFNoC protocol. + +
+ + + + + + + + + + + + + + + + + + + +
BitsName
31..16 +

CHDR_WIDTH

+

+ +
15..8 +

RFNOC_PROTO_MAJOR

+

+ +
7..0 +

RFNOC_PROTO_MINOR

+

+ +
+ +
+ +
+ + +

Offset 0x0018: CLOCK_CTRL_REG Register (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + +
+ + + +
Port ARM_M_AXI_HPM0
+ +		 + + + + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
+ +		 + + + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
+ +		 + + + + +
CLOCK_CTRL_REG
  offset=0x0018
+ +		 + + + + + +
+ + +Total Offset =
  0x10000A0018 + +
+ +

+ +

Initial Value = 0x00000000 +

+ +

This register is defined in HDL source file x4xx_global_regs.v.

+ +
+ +
+ +Control register for clocking resources. + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

PPS_BRC_DELAY

+

Number of base reference clock cycles from appearance of the PPS + rising edge to the occurrence of the aligned edge of base reference + clock and PLL reference clock at the sample PLL output. This number + is the sum of the actual value based on PLL_SYNC_DELAY (also + accumulate the fixed amount of clock cycles) and if any the number of + cycles the SPLL requires from issuing of the SYNC signal to the + aligned edge (with LMK04832 = 0).
+ The number written to this register has to be reduced by 1 due to + HDL implementation.

+ +
23..16 +

PLL_SYNC_DELAY

+

Due to the HDL implementation the rising edge of the SYNC signal for + the LMK04832 is generated 2 clock cycles after the PPS rising edge. + This delay can be further increased by setting this delay value + (e.g. PLL_SYNC_DELAY=3 will result in a total delay of 5 clock cycles).
+ In case two X400 devices are connected using the PPS and reference clock the master delay value needs to be 3 clock cycles + higher than the slave delay value to align the LMK sync edges in time.

+ +
15..10 +

Reserved

+

+ +
9r +

PLL_SYNC_DONE

+

Indicates the success of the PLL reset started by PLL_SYNC_TRIGGER. Reset on deassertion of PLL_SYNC_TRIGGER.

+ +
8w +

PLL_SYNC_TRIGGER

+

Assertion triggers the SYNC signal generation for LMK04832 after the next appearance of the PPS rising edge. + There is no self reset on this trigger. + Keep this trigger asserted until PLL_SYNC_DONE is asserted.

+ +
7..6 +

Reserved

+

+ +
5..4 +

TRIGGER_IO_SELECT   (initialvalue=TRIG_IO_INPUT)

+

IMPORTANT! SW must ensure any TRIG_IO consumers (downstream devices) ignore + and/or re-sync after enabling this port, since the output-enable is basically + asynchronous to the actual TRIG_IO driver.

+ +

+ The values for this bitfield are in the TRIG_IO_ENUM table. + (show here) +

+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Name
0 +

TRIG_IO_INPUT

+ +
1 +

TRIG_IO_PPS_OUTPUT

+ +
+ +

+ This enumerated type is defined in HDL source file x4xx_global_regs.v. +

+ +
+ +
+ +
3r +

REFCLK_LOCKED

+

RESERVED. This bit is not implemented on X4xx and reads as 0.

+ +
2 +

REF_SELECT

+

RESERVED. This bit is not implemented on X4xx and reads as 0.

+ +
1..0 +

PPS_SELECT   (initialvalue=PPS_INT_25MHZ)

+

Select the source of the PPS signal. + For the internal generation the value depending on the base reference clock has to be chosen. + The external reference is taken from the PPS_IN pin and is independent of the base reference clock.

+ +

+ The values for this bitfield are in the PPS_ENUM table. + (show here) +

+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Name
0 +

PPS_INT_25MHZ

+ +
1 +

PPS_INT_10MHZ

+ +
2 +

PPS_EXT

+ +
+ +

+ This enumerated type is defined in HDL source file x4xx_global_regs.v. +

+ +
+ +
+ +
+ +
+ +
+ + +

Offset 0x001C: PPS_CTRL_REG Register (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + +
+ + + +
Port ARM_M_AXI_HPM0
+ +		 + + + + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
+ +		 + + + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
+ +		 + + + + +
PPS_CTRL_REG
  offset=0x001C
+ +		 + + + + + +
+ + +Total Offset =
  0x10000A001C + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file x4xx_global_regs.v.

+ +
+ +
+ +Control registers for PPS generation. + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31 +

PPS_RC_ENABLED

+

Enables the PPS signal in radio clock domain. Please make sure that + the values of PPS_BRC_DELAY, PPS_PRC_DELAY and PRC_RC_DIVIDER are + set before enabling this bit. It is recommended to disable the PPS + for changes on the other values. Use a wait time of at least 1 second + before changing this value to ensure the values are stable for the + next PPS edge.

+ +
30 +

Reserved

+

+ +
29..28 +

PRC_RC_DIVIDER

+

Clock multiplier used to generate radio clock from PLL reference clock. + The value written to the register has to be reduced by 2 due to + HDL implementation.

+ +
27..26 +

Reserved

+

+ +
25..0 +

PPS_PRC_DELAY

+

The number of PLL reference clock cycles from one aligned edge to the + desired aligned edge to issue the PPS in radio clock domain. This + delay is configurable to any aligned edge within a maximum delay of 1 + second (period of PPS).
+ The value written to the register has to be reduced by 4 due to + HDL implementation.

+ +
+ +
+ +
+ + +

Offset 0x0020: CHDR_CLK_RATE_REG Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + +
+ + + +
Port ARM_M_AXI_HPM0
+ +		 + + + + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
+ +		 + + + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
+ +		 + + + + +
CHDR_CLK_RATE_REG
  offset=0x0020
+ +		 + + + + + +
+ + +Total Offset =
  0x10000A0020 + +
+ +

+ +

Initial Value = 0x0BEBC200 +

+ +

This register is defined in HDL source file x4xx_global_regs.v.

+ +
+ +
+ +Returns the RFNoC bus clock rate (CHDR). + +
+ + + + + + + + + +
BitsName
31..0 +

CHDR_CLK   (initialvalue=CHDR_CLK_VALUE)

+

+ +

+ The values for this bitfield are in the CHDR_CLK_ENUM table. + (show here) +

+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Name
Dec Hex
2000000000xBEBC200 +

CHDR_CLK_VALUE

+ +
+ +

+ This enumerated type is defined in HDL source file x4xx_global_regs.v. +

+ +
+ +
+ +
+ +
+ +
+ + +

Offset 0x0024: CHDR_CLK_COUNT_REG Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + +
+ + + +
Port ARM_M_AXI_HPM0
+ +		 + + + + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
+ +		 + + + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
+ +		 + + + + +
CHDR_CLK_COUNT_REG
  offset=0x0024
+ +		 + + + + + +
+ + +Total Offset =
  0x10000A0024 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file x4xx_global_regs.v.

+ +
+ +
+ +Returns the count value of a free-running counter driven by the RFNoC + CHDR bus clock. + +
+ +
+ +
+ + +

Offset 0x0038: GPS_CTRL_REG Register (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + +
+ + + +
Port ARM_M_AXI_HPM0
+ +		 + + + + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
+ +		 + + + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
+ +		 + + + + +
GPS_CTRL_REG
  offset=0x0038
+ +		 + + + + + +
+ + +Total Offset =
  0x10000A0038 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file x4xx_global_regs.v.

+ +
+ +
+ +RESERVED. This register is not implemented on X4xx. GPS is connected + to the PS via a UART. + +
+ +
+ +
+ + +

Offset 0x003C: GPS_STATUS_REG Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + +
+ + + +
Port ARM_M_AXI_HPM0
+ +		 + + + + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
+ +		 + + + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
+ +		 + + + + +
GPS_STATUS_REG
  offset=0x003C
+ +		 + + + + + +
+ + +Total Offset =
  0x10000A003C + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file x4xx_global_regs.v.

+ +
+ +
+ +RESERVED. This register is not implemented on X4xx. GPS is connected + to the PS via a UART. + +
+ +
+ +
+ + +

Offset 0x0040: DBOARD_CTRL_REG Register (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + +
+ + + +
Port ARM_M_AXI_HPM0
+ +		 + + + + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
+ +		 + + + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
+ +		 + + + + +
DBOARD_CTRL_REG
  offset=0x0040
+ +		 + + + + + +
+ + +Total Offset =
  0x10000A0040 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file x4xx_global_regs.v.

+ +
+ +
+ +RESERVED. This register is not implemented on X4xx. + +
+ +
+ +
+ -

Offset 0x0020: CHDR_CLK_RATE_REG Register (R)

+

Offset 0x0044: DBOARD_STATUS_REG Register (R)

- (show extended info) -
+ (show extended info) +
@@ -5163,8 +6509,8 @@ Control registers for PPS generation. @@ -5177,7 +6523,7 @@ Control registers for PPS generation. Total Offset = -
- - + +
CHDR_CLK_RATE_REG
  offset=0x0020
DBOARD_STATUS_REG
  offset=0x0044
  0x10000A0020 +
  0x10000A0044
@@ -5188,7 +6534,7 @@ Total Offset =

-

Initial Value = 0x0BEBC200 +

Initial Value not specified

This register is defined in HDL source file x4xx_global_regs.v.

@@ -5197,81 +6543,100 @@ Total Offset =
-Returns the RFNoC bus clock rate (CHDR). +RESERVED. This register is not implemented on X4xx.
- - - - - - - + +
BitsName
31..0 -

CHDR_CLK   (initialvalue=CHDR_CLK_VALUE)

-

- -

- The values for this bitfield are in the CHDR_CLK_ENUM table. - (show here) -

-
- -
- - - - + + +
+ -
- - - +

Offset 0x0048: NUM_TIMEKEEPERS_REG Register (R)

- + (show extended info) +
+ +
Value Name
+ + - + +
Dec - Hex
+ +
Port ARM_M_AXI_HPM0
+ +
-
+ + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
- 200000000 - - 0xBEBC200 - - -

CHDR_CLK_VALUE

- - + + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
-

- This enumerated type is defined in HDL source file x4xx_global_regs.v. -

- -
+ -
+ - - - + + + +
NUM_TIMEKEEPERS_REG
  offset=0x0048
+ + + + + + + + +
+ + +Total Offset =
  0x10000A0048 + +
+ + + + +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file x4xx_global_regs.v.

+ +
+ +
+ +Register that specifies the number of timekeepers in the core. + +
+
- + -

Offset 0x0024: CHDR_CLK_COUNT_REG Register (R)

+

Offset 0x004C: SERIAL_NUM_LOW_REG Register (R|W)

- (show extended info) -
+ (show extended info) +
@@ -5306,8 +6671,8 @@ Returns the RFNoC bus clock rate (CHDR). @@ -5320,7 +6685,7 @@ Returns the RFNoC bus clock rate (CHDR). Total Offset = -
- - + +
CHDR_CLK_COUNT_REG
  offset=0x0024
SERIAL_NUM_LOW_REG
  offset=0x004C
  0x10000A0024 +
  0x10000A004C
@@ -5340,20 +6705,19 @@ Total Offset =
-Returns the count value of a free-running counter driven by the RFNoC - CHDR bus clock. +Least significant bytes of 8 byte serial number
- + -

Offset 0x0038: GPS_CTRL_REG Register (R|W)

+

Offset 0x0050: SERIAL_NUM_HIGH_REG Register (R|W)

- (show extended info) -
+ (show extended info) +
@@ -5388,8 +6752,8 @@ Returns the count value of a free-running counter driven by the RFNoC @@ -5402,7 +6766,7 @@ Returns the count value of a free-running counter driven by the RFNoC Total Offset = -
- - + +
GPS_CTRL_REG
  offset=0x0038
SERIAL_NUM_HIGH_REG
  offset=0x0050
  0x10000A0038 +
  0x10000A0050
@@ -5422,20 +6786,19 @@ Total Offset =
-RESERVED. This register is not implemented on X4xx. GPS is connected - to the PS via a UART. +Most significant bytes of 8 byte serial number
- + -

Offset 0x003C: GPS_STATUS_REG Register (R)

+

Offset 0x0054: MFG_TEST_CTRL_REG Register (R|W)

- (show extended info) -
+ (show extended info) +
@@ -5470,8 +6833,8 @@ RESERVED. This register is not implemented on X4xx. GPS is connected @@ -5484,7 +6847,7 @@ RESERVED. This register is not implemented on X4xx. GPS is connected Total Offset = -
- - + +
GPS_STATUS_REG
  offset=0x003C
MFG_TEST_CTRL_REG
  offset=0x0054
  0x10000A003C +
  0x10000A0054
@@ -5504,20 +6867,80 @@ Total Offset =
-RESERVED. This register is not implemented on X4xx. GPS is connected - to the PS via a UART. +Control register for mfg_test functions.
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..8 +

Reserved

+

+ +
7..2 +

Reserved

+

+ +
1 +

MFG_TEST_EN_FABRIC_CLK

+

When enabled, routes data_clk to FPGA_REF_CLK output port. + When disabled, the FPGA_REF_CLK output is driven to 0.

+ +
0 +

MFG_TEST_EN_GTY_RCV_CLK

+

When enabled, routes data_clk to GTY_RCV_CLK output port. + When disabled, the GTY_RCV_CLK output is driven to 0.

+ +
+
- + -

Offset 0x0040: DBOARD_CTRL_REG Register (R|W)

+

Offset 0x0058: MFG_TEST_STATUS_REG Register (R|W)

- (show extended info) -
+ (show extended info) +
@@ -5552,8 +6975,8 @@ RESERVED. This register is not implemented on X4xx. GPS is connected @@ -5566,7 +6989,7 @@ RESERVED. This register is not implemented on X4xx. GPS is connected Total Offset = -
- - + +
DBOARD_CTRL_REG
  offset=0x0040
MFG_TEST_STATUS_REG
  offset=0x0058
  0x10000A0040 +
  0x10000A0058
@@ -5586,19 +7009,45 @@ Total Offset =
-RESERVED. This register is not implemented on X4xx. +Status register for mfg_test functions.
+ + + + + + + + + + + + + +
BitsName
31..26 +

Reserved

+

+ +
25..0 +

MFG_TEST_FPGA_AUX_REF_FREQ

+

Report the time between rising edges on the FPGA_REF_CLK + input port in 40 MHz Clock ticks. If the count extends + to 1.2 seconds without an edge, the value reported is set + to zero.

+ +
+
- + -

Offset 0x0044: DBOARD_STATUS_REG Register (R)

+

Offset 0x0060: QSFP_PORT_0_0_INFO_REG Register (R)

- (show extended info) -
+ (show extended info) +
@@ -5633,8 +7082,8 @@ RESERVED. This register is not implemented on X4xx. @@ -5647,7 +7096,7 @@ RESERVED. This register is not implemented on X4xx. Total Offset = -
- - + +
DBOARD_STATUS_REG
  offset=0x0044
QSFP_PORT_0_0_INFO_REG
  offset=0x0060
  0x10000A0044 +
  0x10000A0060
@@ -5667,19 +7116,19 @@ Total Offset =
-RESERVED. This register is not implemented on X4xx. +Returns information from the QSFP0 Lane0.
- + -

Offset 0x0048: NUM_TIMEKEEPERS_REG Register (R)

+

Offset 0x0064: QSFP_PORT_0_1_INFO_REG Register (R)

- (show extended info) -
+ (show extended info) +
@@ -5714,8 +7163,8 @@ RESERVED. This register is not implemented on X4xx. @@ -5728,7 +7177,7 @@ RESERVED. This register is not implemented on X4xx. Total Offset = -
- - + +
NUM_TIMEKEEPERS_REG
  offset=0x0048
QSFP_PORT_0_1_INFO_REG
  offset=0x0064
  0x10000A0048 +
  0x10000A0064
@@ -5748,19 +7197,19 @@ Total Offset =
-Register that specifies the number of timekeepers in the core. +Returns information from the QSFP0 Lane1.
- + -

Offset 0x004C: SERIAL_NUM_LOW_REG Register (R|W)

+

Offset 0x0068: QSFP_PORT_0_2_INFO_REG Register (R)

- (show extended info) -
+ (show extended info) +
@@ -5795,8 +7244,8 @@ Register that specifies the number of timekeepers in the core. @@ -5809,7 +7258,7 @@ Register that specifies the number of timekeepers in the core. Total Offset = -
- - + +
SERIAL_NUM_LOW_REG
  offset=0x004C
QSFP_PORT_0_2_INFO_REG
  offset=0x0068
  0x10000A004C +
  0x10000A0068
@@ -5829,19 +7278,19 @@ Total Offset =
-Least significant bytes of 8 byte serial number +Returns information from the QSFP0 Lane2.
- + -

Offset 0x0050: SERIAL_NUM_HIGH_REG Register (R|W)

+

Offset 0x006C: QSFP_PORT_0_3_INFO_REG Register (R)

- (show extended info) -
+ (show extended info) +
@@ -5876,8 +7325,8 @@ Least significant bytes of 8 byte serial number @@ -5890,7 +7339,7 @@ Least significant bytes of 8 byte serial number Total Offset = -
- - + +
SERIAL_NUM_HIGH_REG
  offset=0x0050
QSFP_PORT_0_3_INFO_REG
  offset=0x006C
  0x10000A0050 +
  0x10000A006C
@@ -5910,19 +7359,19 @@ Total Offset =
-Most significant bytes of 8 byte serial number +Returns information from the QSFP0 Lane3.
- + -

Offset 0x0054: MFG_TEST_CTRL_REG Register (R|W)

+

Offset 0x0070: QSFP_PORT_1_0_INFO_REG Register (R)

- (show extended info) -
+ (show extended info) +
@@ -5957,8 +7406,8 @@ Most significant bytes of 8 byte serial number @@ -5971,7 +7420,7 @@ Most significant bytes of 8 byte serial number Total Offset = -
- - + +
MFG_TEST_CTRL_REG
  offset=0x0054
QSFP_PORT_1_0_INFO_REG
  offset=0x0070
  0x10000A0054 +
  0x10000A0070
@@ -5991,80 +7440,19 @@ Total Offset =
-Control register for mfg_test functions. +Returns information from the QSFP1 Lane0.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BitsName
31..24 -

Reserved

-

- -
23..16 -

Reserved

-

- -
15..8 -

Reserved

-

- -
7..2 -

Reserved

-

- -
1 -

MFG_TEST_EN_FABRIC_CLK

-

When enabled, routes data_clk to FPGA_REF_CLK output port. - When disabled, the FPGA_REF_CLK output is driven to 0.

- -
0 -

MFG_TEST_EN_GTY_RCV_CLK

-

When enabled, routes data_clk to GTY_RCV_CLK output port. - When disabled, the GTY_RCV_CLK output is driven to 0.

- -
-
- + -

Offset 0x0058: MFG_TEST_STATUS_REG Register (R|W)

+

Offset 0x0074: QSFP_PORT_1_1_INFO_REG Register (R)

- (show extended info) -
+ (show extended info) +
@@ -6099,8 +7487,8 @@ Control register for mfg_test functions. @@ -6113,7 +7501,7 @@ Control register for mfg_test functions. Total Offset = -
- - + +
MFG_TEST_STATUS_REG
  offset=0x0058
QSFP_PORT_1_1_INFO_REG
  offset=0x0074
  0x10000A0058 +
  0x10000A0074
@@ -6133,45 +7521,19 @@ Total Offset =
-Status register for mfg_test functions. +Returns information from the QSFP1 Lane1.
- - - - - - - - - - - - - -
BitsName
31..26 -

Reserved

-

- -
25..0 -

MFG_TEST_FPGA_AUX_REF_FREQ

-

Report the time between rising edges on the FPGA_REF_CLK - input port in 40 MHz Clock ticks. If the count extends - to 1.2 seconds without an edge, the value reported is set - to zero.

- -
-
- + -

Offset 0x0060: QSFP_PORT_0_0_INFO_REG Register (R)

+

Offset 0x0078: QSFP_PORT_1_2_INFO_REG Register (R)

- (show extended info) -
+ (show extended info) +
@@ -6206,8 +7568,8 @@ Status register for mfg_test functions. @@ -6220,7 +7582,7 @@ Status register for mfg_test functions. Total Offset = -
- - + +
QSFP_PORT_0_0_INFO_REG
  offset=0x0060
QSFP_PORT_1_2_INFO_REG
  offset=0x0078
  0x10000A0060 +
  0x10000A0078
@@ -6240,19 +7602,19 @@ Total Offset =
-Returns information from the QSFP0 Lane0. +Returns information from the QSFP1 Lane2.
- + -

Offset 0x0064: QSFP_PORT_0_1_INFO_REG Register (R)

+

Offset 0x007C: QSFP_PORT_1_3_INFO_REG Register (R)

- (show extended info) -
+ (show extended info) +
@@ -6287,8 +7649,8 @@ Returns information from the QSFP0 Lane0. @@ -6301,7 +7663,7 @@ Returns information from the QSFP0 Lane0. Total Offset = -
- - + +
QSFP_PORT_0_1_INFO_REG
  offset=0x0064
QSFP_PORT_1_3_INFO_REG
  offset=0x007C
  0x10000A0064 +
  0x10000A007C
@@ -6321,37 +7683,39 @@ Total Offset =
-Returns information from the QSFP0 Lane1. +Returns information from the QSFP1 Lane3. + +
+
+ +
+ +

GPIO_ATR_REGMAP

+ +

GPIO_ATR_REGS

+ Describes the behavior of GPIO lines when controlled by the ATR state.
- + -

Offset 0x0068: QSFP_PORT_0_2_INFO_REG Register (R)

+

Offset 0x0000: ATR_STATE(15:0) Register Array (R|W)

- (show extended info) -
+ (show extended info) +
- - @@ -6359,7 +7723,7 @@ Returns information from the QSFP0 Lane1. @@ -6381,8 +7745,10 @@ Returns information from the QSFP0 Lane1. + -
- - - -
Port ARM_M_AXI_HPM0
- -		 - - + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
 - +
CORE_REGS_REGMAP|GLOBAL_REGS
RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
  0x000000
@@ -6368,8 +7732,8 @@ Returns information from the QSFP0 Lane1. 		- - + +
QSFP_PORT_0_2_INFO_REG
  offset=0x0068
ATR_STATE
  offset=0x0000 + i*4
+Cannot determine accessibility through this path
Total Offset =
  0x10000A0068 +
  0x00C000 + i*4
@@ -6393,46 +7759,92 @@ Total Offset =

-

Initial Value not specified +

Initial Values
+ + +
default=>0x00000000

-

This register is defined in HDL source file x4xx_global_regs.v.

+

This register is defined in HDL source file x4xx_gpio_atr.v.
+It uses RegType GPIO_ATR_STATE which is defined in HDL source file x4xx_gpio_atr.v.

-Returns information from the QSFP0 Lane2. +Holds a single bit setting for GPIO lines in both ports for a particular ATR sate
+Describes GPIO behavior for the different ATR states. When ATR_OPTION + is set to use the DB states, TX and RX states for RF0 and RF1 are + combined to create a single vector. This creates 16 different + combinations, each with its own register. When ATR_OPTION is set to + classic ATR, offsets 0x00-0x03 in this register group will be driven + in accordance with the state of RF0, and offsets 0x04-0x07 will be + driven in accordance with the state of RF1. + CLASSIC ATR MAPPING: Idle[RF0:0x00; RF1:0x04], RX[RF0:0x01; RF1:0x05], + TX[RF0:0x02; RF1:0x06], FDX[RF0:0x03; RF1:0x07]
+ + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..28 +

Reserved

+

+ +
27..16 +

GPIO_STATE_B   (initialvalue=0)

+

+ +
15..12 +

Reserved

+

+ +
11..0 +

GPIO_STATE_A   (initialvalue=0)

+

+ +
+
- + -

Offset 0x006C: QSFP_PORT_0_3_INFO_REG Register (R)

+

Offset 0x0040: CLASSIC_ATR_CONFIG Register (R|W)

- (show extended info) -
+ (show extended info) +
- - @@ -6440,7 +7852,7 @@ Returns information from the QSFP0 Lane2. @@ -6463,7 +7875,7 @@ Returns information from the QSFP0 Lane2. Total Offset = -
- - - -
Port ARM_M_AXI_HPM0
- -		 - - + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
 - +
CORE_REGS_REGMAP|GLOBAL_REGS
RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
  0x000000
@@ -6449,8 +7861,8 @@ Returns information from the QSFP0 Lane2. 		- - + +
QSFP_PORT_0_3_INFO_REG
  offset=0x006C
CLASSIC_ATR_CONFIG
  offset=0x0040
  0x10000A006C +
  0x00C040
@@ -6474,46 +7886,88 @@ Total Offset =

-

Initial Value not specified +

Initial Value = 0x00000000

-

This register is defined in HDL source file x4xx_global_regs.v.

+

This register is defined in HDL source file x4xx_gpio_atr.v.

-Returns information from the QSFP0 Lane3. +Controls the RF state mapping of each GPIO line when classic + ATR mode is active.
+ + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..28 +

Reserved

+

+ +
27..16 +

RF_SELECT_B   (initialvalue=0)

+

Set which RF channel's state to reflect in the pins of + HDMI connector B when ATR_OPTION is set to classic ATR. + Controlled in a per-pin basis. + 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03) + 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)

+ +
15..12 +

Reserved

+

+ +
11..0 +

RF_SELECT_A   (initialvalue=0)

+

Set which RF channel's state to reflect in the pins for + HDMI connector A when ATR_OPTION is set to classic ATR. + Controlled in a per-pin basis. + 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03) + 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)

+ +
+
- + -

Offset 0x0070: QSFP_PORT_1_0_INFO_REG Register (R)

+

Offset 0x0044: ATR_OPTION_REGISTRER Register (R|W)

- (show extended info) -
+ (show extended info) +
- - @@ -6521,7 +7975,7 @@ Returns information from the QSFP0 Lane3. @@ -6544,7 +7998,7 @@ Returns information from the QSFP0 Lane3. Total Offset = -
- - - -
Port ARM_M_AXI_HPM0
- -		 - - + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
 - +
CORE_REGS_REGMAP|GLOBAL_REGS
RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
  0x000000
@@ -6530,8 +7984,8 @@ Returns information from the QSFP0 Lane3. 		- - + +
QSFP_PORT_1_0_INFO_REG
  offset=0x0070
ATR_OPTION_REGISTRER
  offset=0x0044
  0x10000A0070 +
  0x00C044
@@ -6555,46 +8009,95 @@ Total Offset =

-

Initial Value not specified +

Initial Value = 0x00000000

-

This register is defined in HDL source file x4xx_global_regs.v.

+

This register is defined in HDL source file x4xx_gpio_atr.v.

-Returns information from the QSFP1 Lane0. +Controls whether GPIO lines use the TX and RX state of an RF channel + (Classic ATR) or the daughterboard state the selector for the + @.GPIO_ATR_STATE.
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..8 +

Reserved

+

+ +
7..1 +

Reserved

+

+ +
0 +

ATR_OPTION   (initialvalue=0)

+

Sets the scheme in which RF states in the radio will control GPIO + lines. 0 = DB state is used. RF states are combined and the + GPIO state is driven based on all 16 @.GPIO_ATR_STATE registers. + 1 = Each RF channel has its separate ATR state(Classic ATR). + Use register CLASSIC_ATR_CONFIG to indicate the RF channel + to which each GPIO line responds to.

+ +
+
- + -

Offset 0x0074: QSFP_PORT_1_1_INFO_REG Register (R)

+

Offset 0x0048: GPIO_DIR Register (R|W)

- (show extended info) -
+ (show extended info) +
- - @@ -6602,7 +8105,7 @@ Returns information from the QSFP1 Lane0. @@ -6625,7 +8128,7 @@ Returns information from the QSFP1 Lane0. Total Offset = -
- - - -
Port ARM_M_AXI_HPM0
- -		 - - + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
 - +
CORE_REGS_REGMAP|GLOBAL_REGS
RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
  0x000000
@@ -6611,8 +8114,8 @@ Returns information from the QSFP1 Lane0. 		- - + +
QSFP_PORT_1_1_INFO_REG
  offset=0x0074
GPIO_DIR
  offset=0x0048
  0x10000A0074 +
  0x00C048
@@ -6636,46 +8139,80 @@ Total Offset =

-

Initial Value not specified +

Initial Value = 0x00000000

-

This register is defined in HDL source file x4xx_global_regs.v.

+

This register is defined in HDL source file x4xx_gpio_atr.v.

-Returns information from the QSFP1 Lane1. +Controls the direction of each GPIO signal when controlled by the radio state. + 0 = GPIO pin set to input. 1 = GPIO pin set to output
+ + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..28 +

Reserved

+

+ +
27..16 +

GPIO_DIR_B   (initialvalue=0)

+

+ +
15..12 +

Reserved

+

+ +
11..0 +

GPIO_DIR_A   (initialvalue=0)

+

+ +
+
- + -

Offset 0x0078: QSFP_PORT_1_2_INFO_REG Register (R)

+

Offset 0x004C: GPIO_DISABLED Register (R|W)

- (show extended info) -
+ (show extended info) +
- - @@ -6683,7 +8220,7 @@ Returns information from the QSFP1 Lane1. @@ -6706,7 +8243,7 @@ Returns information from the QSFP1 Lane1. Total Offset = -
- - - -
Port ARM_M_AXI_HPM0
- -		 - - + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
 - +
CORE_REGS_REGMAP|GLOBAL_REGS
RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
  0x000000
@@ -6692,8 +8229,8 @@ Returns information from the QSFP1 Lane1. 		- - + +
QSFP_PORT_1_2_INFO_REG
  offset=0x0078
GPIO_DISABLED
  offset=0x004C
  0x10000A0078 +
  0x00C04C
@@ -6717,46 +8254,79 @@ Total Offset =

-

Initial Value not specified +

Initial Value = 0x00000000

-

This register is defined in HDL source file x4xx_global_regs.v.

+

This register is defined in HDL source file x4xx_gpio_atr.v.

-Returns information from the QSFP1 Lane2. +Disable ATR Control. DB state 0 will be reflected regardless of the ATR state.
+ + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..28 +

Reserved

+

+ +
27..16 +

GPIO_DISABLED_B   (initialvalue=0)

+

+ +
15..12 +

Reserved

+

+ +
11..0 +

GPIO_DISABLED_A   (initialvalue=0)

+

+ +
+
- + -

Offset 0x007C: QSFP_PORT_1_3_INFO_REG Register (R)

+

Offset 0x0050: GPIO_IN Register (R|W)

- (show extended info) -
+ (show extended info) +
- - @@ -6764,7 +8334,7 @@ Returns information from the QSFP1 Lane2. @@ -6787,7 +8357,7 @@ Returns information from the QSFP1 Lane2. Total Offset = -
- - - -
Port ARM_M_AXI_HPM0
- -		 - - + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
 - +
CORE_REGS_REGMAP|GLOBAL_REGS
RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
  0x000000
@@ -6773,8 +8343,8 @@ Returns information from the QSFP1 Lane2. 		- - + +
QSFP_PORT_1_3_INFO_REG
  offset=0x007C
GPIO_IN
  offset=0x0050
  0x10000A007C +
  0x00C050
@@ -6798,19 +8368,60 @@ Total Offset =

-

Initial Value not specified +

Initial Value = 0x00000000

-

This register is defined in HDL source file x4xx_global_regs.v.

+

This register is defined in HDL source file x4xx_gpio_atr.v.

-Returns information from the QSFP1 Lane3. +Reflects the logic state of each GPIO input.
+ + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..28 +

Reserved

+

+ +
27..16 +

GPIO_IN_B   (initialvalue=0)

+

+ +
15..12 +

Reserved

+

+ +
11..0 +

GPIO_IN_A   (initialvalue=0)

+

+ +
+
@@ -14459,6 +16070,9 @@ Total Offset = Each radio's CtrlPort peripheral interface is divided into the following memory spaces. Note that the CtrlPort peripheral interface starts at offset 0x80000 in the RFNoC Radio block's register space. + The following diagram displays the distribution of the CtrlPort + interface to the different modules it interacts with. + @@ -14540,7 +16154,7 @@ RFDC timing control interface.

Offset 0xC000: DIO_WINDOW Window (R|W)

-

  Target regmap = DIO_REGMAP

+

  Target regmap = RADIO_DIO_REGMAP

(show extended info)
@@ -14568,7 +16182,143 @@ RFDC timing control interface.
-DIO control interface +DIO control interface. Interacts with the DIO source selection + block, ATR-based DIO control and the DIO digital interface + +
+ +
+ +
+ +
+ +
+ +

RADIO_DIO_REGMAP

+ This map contains register windows for controlling the different sources + that drive the state of DIO lines. +

DIO_SOURCES

+ +
+ + +

Offset 0x0000: RADIO_GPIO_ATR_REGS Window (R|W)

+

  Target regmap = GPIO_ATR_REGMAP

+ (show extended info) +
+ + + + + + + + + + + + + +
+ + + + +
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
+ +		 + + + + + +
RADIO_GPIO_ATR_REGS
  offset=0x0000
  size=0x1000 (4 Kbytes)
+ +		 + + + + + +
+ + +Total Offset =
  0x00C000 + +
+ +

+ +

This window is defined in HDL source file x4xx_core_common.v.

+ +
+ +
+ +Contains controls for DIO behavior based on the ATR state of the accessed radio + +
+ +
+ +
+ + +

Offset 0x1000: DIO_SOURCE_CONTROL Window (R|W)

+

  Target regmap = DIO_REGMAP

+ (show extended info) +
+ + + + + + + + + + + + + +
+ + + + +
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
+ +		 + + + + + +
DIO_SOURCE_CONTROL
  offset=0x1000
  size=0x1000 (4 Kbytes)
+ +		 + + + + + +
+ + +Total Offset =
  0x00D000 + +
+ +

+ +

This window is defined in HDL source file x4xx_core_common.v.

+ +
+ +
+ +Window to access the DIO register map through the control port from the radio blocks.
@@ -21832,9 +23582,9 @@ FPGA version.
- 554176790 + 554243347 - 0x21081116 + 0x21091513

FPGA_VERSION_LAST_MODIFIED_TIME

diff --git a/fpga/usrp3/top/x400/doc/x4xx_core_common_buses.svg b/fpga/usrp3/top/x400/doc/x4xx_core_common_buses.svg new file mode 100644 index 000000000..6dafbfe4a --- /dev/null +++ b/fpga/usrp3/top/x400/doc/x4xx_core_common_buses.svg @@ -0,0 +1,3 @@ + + +
s_radio_ctrlport_*[1:0]
s_radio_ctrlport_*[1:0]
rfdc_timing_control
rfdc_timing_control
ctrlport_decoder_param
ctrlport_decoder_param
rf_ctrlport
rf_ctrlport
m_radio_ctrlport_*[1:0]
m_radio_ctrlport_*[1:0]
gpio_atr_ctrlport
gpio_atr_ctrlport
radio_dio
radio_dio
x4xx_gpio_atr_i
x4xx_gpio_atr_i
x4xx_gpio_spi_wrapper_i
x4xx_gpio_spi_wrapper_i
ctrlport_combiner
(ctrlport_combiner_dio)
ctrlport_combiner...
dio_ctrlport
dio_ctrlport
windowed_mpm_dio
windowed_mpm_dio
x4xx_dio
x4xx_dio
ctrlport_decoder_param
(ctrlport_decoder_dio_window)
ctrlport_decoder_param...
ctrlport_clk_cross
(ctrlport_clk_cross_dio)
ctrlport_clk_cross...
mpm_dio_*
mpm_dio_*
ctrlport_splitter
ctrlport_splitter
m_*
m_*
ctrlport_clk_cross
ctrlport_clk_cross
s_ctrlport
s_ctrlport
timekeeper_*
timekeeper_*
versioning_*
versioning_*
global_regs_*
global_regs_*
dio_*
dio_*
x4xx_global_regs
x4xx_global_regs
x4xx_versioning_regs
x4xx_versioning_regs
timekeeper
timekeeper
From AXI
From AXI
From Radio
From Radio
One Instance Per Daghterboard
One Instance Per Dag...
To Daughterboards
To Daughterboards
gpio_spi_ctrlport
gpio_spi_ctrlportViewer does not support full SVG 1.1 \ No newline at end of file diff --git a/fpga/usrp3/top/x400/regmap/core_regs_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/core_regs_regmap_utils.vh index cef263b6d..f3fdde060 100644 --- a/fpga/usrp3/top/x400/regmap/core_regs_regmap_utils.vh +++ b/fpga/usrp3/top/x400/regmap/core_regs_regmap_utils.vh @@ -38,4 +38,4 @@ // DIO Window (from x4xx_core_common.v) localparam DIO = 'h2000; // Window Offset - localparam DIO_SIZE = 'h20; // size in bytes + localparam DIO_SIZE = 'h40; // size in bytes diff --git a/fpga/usrp3/top/x400/regmap/dio_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/dio_regmap_utils.vh index 7598bb1ee..027a464f5 100644 --- a/fpga/usrp3/top/x400/regmap/dio_regmap_utils.vh +++ b/fpga/usrp3/top/x400/regmap/dio_regmap_utils.vh @@ -15,11 +15,26 @@ // DIO_DIRECTION_REGISTER : 0x4 (x4xx_dio.v) // DIO_INPUT_REGISTER : 0x8 (x4xx_dio.v) // DIO_OUTPUT_REGISTER : 0xC (x4xx_dio.v) + // DIO_SOURCE_REGISTER : 0x10 (x4xx_dio.v) + // RADIO_SOURCE_REGISTER : 0x14 (x4xx_dio.v) + // INTERFACE_DIO_SELECT : 0x18 (x4xx_dio.v) + // DIO_OVERRIDE : 0x1C (x4xx_dio.v) + // SW_DIO_CONTROL : 0x20 (x4xx_dio.v) //=============================================================================== // RegTypes //=============================================================================== + // DIO_CONTROL_REG Type (from x4xx_dio.v) + localparam DIO_CONTROL_REG_SIZE = 32; + localparam DIO_CONTROL_REG_MASK = 32'hFFF0FFF; + localparam DIO_PORT_A_SIZE = 12; //DIO_CONTROL_REG:DIO_PORT_A + localparam DIO_PORT_A_MSB = 11; //DIO_CONTROL_REG:DIO_PORT_A + localparam DIO_PORT_A = 0; //DIO_CONTROL_REG:DIO_PORT_A + localparam DIO_PORT_B_SIZE = 12; //DIO_CONTROL_REG:DIO_PORT_B + localparam DIO_PORT_B_MSB = 27; //DIO_CONTROL_REG:DIO_PORT_B + localparam DIO_PORT_B = 16; //DIO_CONTROL_REG:DIO_PORT_B + //=============================================================================== // Register Group DIO_REGS //=============================================================================== @@ -27,43 +42,35 @@ // DIO_MASTER_REGISTER Register (from x4xx_dio.v) localparam DIO_MASTER_REGISTER = 'h0; // Register Offset localparam DIO_MASTER_REGISTER_SIZE = 32; // register width in bits - localparam DIO_MASTER_REGISTER_MASK = 32'hFFF0FFF; - localparam DIO_MASTER_A_SIZE = 12; //DIO_MASTER_REGISTER:DIO_MASTER_A - localparam DIO_MASTER_A_MSB = 11; //DIO_MASTER_REGISTER:DIO_MASTER_A - localparam DIO_MASTER_A = 0; //DIO_MASTER_REGISTER:DIO_MASTER_A - localparam DIO_MASTER_B_SIZE = 12; //DIO_MASTER_REGISTER:DIO_MASTER_B - localparam DIO_MASTER_B_MSB = 27; //DIO_MASTER_REGISTER:DIO_MASTER_B - localparam DIO_MASTER_B = 16; //DIO_MASTER_REGISTER:DIO_MASTER_B // DIO_DIRECTION_REGISTER Register (from x4xx_dio.v) localparam DIO_DIRECTION_REGISTER = 'h4; // Register Offset localparam DIO_DIRECTION_REGISTER_SIZE = 32; // register width in bits - localparam DIO_DIRECTION_REGISTER_MASK = 32'hFFF0FFF; - localparam DIO_DIRECTION_A_SIZE = 12; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_A - localparam DIO_DIRECTION_A_MSB = 11; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_A - localparam DIO_DIRECTION_A = 0; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_A - localparam DIO_DIRECTION_B_SIZE = 12; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_B - localparam DIO_DIRECTION_B_MSB = 27; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_B - localparam DIO_DIRECTION_B = 16; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_B // DIO_INPUT_REGISTER Register (from x4xx_dio.v) localparam DIO_INPUT_REGISTER = 'h8; // Register Offset localparam DIO_INPUT_REGISTER_SIZE = 32; // register width in bits - localparam DIO_INPUT_REGISTER_MASK = 32'hFFF0FFF; - localparam DIO_INPUT_A_SIZE = 12; //DIO_INPUT_REGISTER:DIO_INPUT_A - localparam DIO_INPUT_A_MSB = 11; //DIO_INPUT_REGISTER:DIO_INPUT_A - localparam DIO_INPUT_A = 0; //DIO_INPUT_REGISTER:DIO_INPUT_A - localparam DIO_INPUT_B_SIZE = 12; //DIO_INPUT_REGISTER:DIO_INPUT_B - localparam DIO_INPUT_B_MSB = 27; //DIO_INPUT_REGISTER:DIO_INPUT_B - localparam DIO_INPUT_B = 16; //DIO_INPUT_REGISTER:DIO_INPUT_B // DIO_OUTPUT_REGISTER Register (from x4xx_dio.v) localparam DIO_OUTPUT_REGISTER = 'hC; // Register Offset localparam DIO_OUTPUT_REGISTER_SIZE = 32; // register width in bits - localparam DIO_OUTPUT_REGISTER_MASK = 32'hFFF0FFF; - localparam DIO_OUTPUT_A_SIZE = 12; //DIO_OUTPUT_REGISTER:DIO_OUTPUT_A - localparam DIO_OUTPUT_A_MSB = 11; //DIO_OUTPUT_REGISTER:DIO_OUTPUT_A - localparam DIO_OUTPUT_A = 0; //DIO_OUTPUT_REGISTER:DIO_OUTPUT_A - localparam DIO_OUTPUT_B_SIZE = 12; //DIO_OUTPUT_REGISTER:DIO_OUTPUT_B - localparam DIO_OUTPUT_B_MSB = 27; //DIO_OUTPUT_REGISTER:DIO_OUTPUT_B - localparam DIO_OUTPUT_B = 16; //DIO_OUTPUT_REGISTER:DIO_OUTPUT_B + + // DIO_SOURCE_REGISTER Register (from x4xx_dio.v) + localparam DIO_SOURCE_REGISTER = 'h10; // Register Offset + localparam DIO_SOURCE_REGISTER_SIZE = 32; // register width in bits + + // RADIO_SOURCE_REGISTER Register (from x4xx_dio.v) + localparam RADIO_SOURCE_REGISTER = 'h14; // Register Offset + localparam RADIO_SOURCE_REGISTER_SIZE = 32; // register width in bits + + // INTERFACE_DIO_SELECT Register (from x4xx_dio.v) + localparam INTERFACE_DIO_SELECT = 'h18; // Register Offset + localparam INTERFACE_DIO_SELECT_SIZE = 32; // register width in bits + + // DIO_OVERRIDE Register (from x4xx_dio.v) + localparam DIO_OVERRIDE = 'h1C; // Register Offset + localparam DIO_OVERRIDE_SIZE = 32; // register width in bits + + // SW_DIO_CONTROL Register (from x4xx_dio.v) + localparam SW_DIO_CONTROL = 'h20; // Register Offset + localparam SW_DIO_CONTROL_SIZE = 32; // register width in bits diff --git a/fpga/usrp3/top/x400/regmap/gpio_atr_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/gpio_atr_regmap_utils.vh new file mode 100644 index 000000000..5fcb50c9e --- /dev/null +++ b/fpga/usrp3/top/x400/regmap/gpio_atr_regmap_utils.vh @@ -0,0 +1,97 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: gpio_atr_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // ATR_STATE : 0x0 (x4xx_gpio_atr.v) + // CLASSIC_ATR_CONFIG : 0x40 (x4xx_gpio_atr.v) + // ATR_OPTION_REGISTRER : 0x44 (x4xx_gpio_atr.v) + // GPIO_DIR : 0x48 (x4xx_gpio_atr.v) + // GPIO_DISABLED : 0x4C (x4xx_gpio_atr.v) + // GPIO_IN : 0x50 (x4xx_gpio_atr.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + + // GPIO_ATR_STATE Type (from x4xx_gpio_atr.v) + localparam GPIO_ATR_STATE_SIZE = 32; + localparam GPIO_ATR_STATE_MASK = 32'hFFF0FFF; + localparam GPIO_STATE_A_SIZE = 12; //GPIO_ATR_STATE:GPIO_STATE_A + localparam GPIO_STATE_A_MSB = 11; //GPIO_ATR_STATE:GPIO_STATE_A + localparam GPIO_STATE_A = 0; //GPIO_ATR_STATE:GPIO_STATE_A + localparam GPIO_STATE_B_SIZE = 12; //GPIO_ATR_STATE:GPIO_STATE_B + localparam GPIO_STATE_B_MSB = 27; //GPIO_ATR_STATE:GPIO_STATE_B + localparam GPIO_STATE_B = 16; //GPIO_ATR_STATE:GPIO_STATE_B + +//=============================================================================== +// Register Group GPIO_ATR_REGS +//=============================================================================== + + // ATR_STATE Register (from x4xx_gpio_atr.v) + localparam ATR_STATE_COUNT = 16; // Number of elements in array + + // CLASSIC_ATR_CONFIG Register (from x4xx_gpio_atr.v) + localparam CLASSIC_ATR_CONFIG = 'h40; // Register Offset + localparam CLASSIC_ATR_CONFIG_SIZE = 32; // register width in bits + localparam CLASSIC_ATR_CONFIG_MASK = 32'hFFF0FFF; + localparam RF_SELECT_A_SIZE = 12; //CLASSIC_ATR_CONFIG:RF_SELECT_A + localparam RF_SELECT_A_MSB = 11; //CLASSIC_ATR_CONFIG:RF_SELECT_A + localparam RF_SELECT_A = 0; //CLASSIC_ATR_CONFIG:RF_SELECT_A + localparam RF_SELECT_B_SIZE = 12; //CLASSIC_ATR_CONFIG:RF_SELECT_B + localparam RF_SELECT_B_MSB = 27; //CLASSIC_ATR_CONFIG:RF_SELECT_B + localparam RF_SELECT_B = 16; //CLASSIC_ATR_CONFIG:RF_SELECT_B + + // ATR_OPTION_REGISTRER Register (from x4xx_gpio_atr.v) + localparam ATR_OPTION_REGISTRER = 'h44; // Register Offset + localparam ATR_OPTION_REGISTRER_SIZE = 32; // register width in bits + localparam ATR_OPTION_REGISTRER_MASK = 32'h1; + localparam ATR_OPTION_SIZE = 1; //ATR_OPTION_REGISTRER:ATR_OPTION + localparam ATR_OPTION_MSB = 0; //ATR_OPTION_REGISTRER:ATR_OPTION + localparam ATR_OPTION = 0; //ATR_OPTION_REGISTRER:ATR_OPTION + + // GPIO_DIR Register (from x4xx_gpio_atr.v) + localparam GPIO_DIR = 'h48; // Register Offset + localparam GPIO_DIR_SIZE = 32; // register width in bits + localparam GPIO_DIR_MASK = 32'hFFF0FFF; + localparam GPIO_DIR_A_SIZE = 12; //GPIO_DIR:GPIO_DIR_A + localparam GPIO_DIR_A_MSB = 11; //GPIO_DIR:GPIO_DIR_A + localparam GPIO_DIR_A = 0; //GPIO_DIR:GPIO_DIR_A + localparam GPIO_DIR_B_SIZE = 12; //GPIO_DIR:GPIO_DIR_B + localparam GPIO_DIR_B_MSB = 27; //GPIO_DIR:GPIO_DIR_B + localparam GPIO_DIR_B = 16; //GPIO_DIR:GPIO_DIR_B + + // GPIO_DISABLED Register (from x4xx_gpio_atr.v) + localparam GPIO_DISABLED = 'h4C; // Register Offset + localparam GPIO_DISABLED_SIZE = 32; // register width in bits + localparam GPIO_DISABLED_MASK = 32'hFFF0FFF; + localparam GPIO_DISABLED_A_SIZE = 12; //GPIO_DISABLED:GPIO_DISABLED_A + localparam GPIO_DISABLED_A_MSB = 11; //GPIO_DISABLED:GPIO_DISABLED_A + localparam GPIO_DISABLED_A = 0; //GPIO_DISABLED:GPIO_DISABLED_A + localparam GPIO_DISABLED_B_SIZE = 12; //GPIO_DISABLED:GPIO_DISABLED_B + localparam GPIO_DISABLED_B_MSB = 27; //GPIO_DISABLED:GPIO_DISABLED_B + localparam GPIO_DISABLED_B = 16; //GPIO_DISABLED:GPIO_DISABLED_B + + // GPIO_IN Register (from x4xx_gpio_atr.v) + localparam GPIO_IN = 'h50; // Register Offset + localparam GPIO_IN_SIZE = 32; // register width in bits + localparam GPIO_IN_MASK = 32'hFFF0FFF; + localparam GPIO_IN_A_SIZE = 12; //GPIO_IN:GPIO_IN_A + localparam GPIO_IN_A_MSB = 11; //GPIO_IN:GPIO_IN_A + localparam GPIO_IN_A = 0; //GPIO_IN:GPIO_IN_A + localparam GPIO_IN_B_SIZE = 12; //GPIO_IN:GPIO_IN_B + localparam GPIO_IN_B_MSB = 27; //GPIO_IN:GPIO_IN_B + localparam GPIO_IN_B = 16; //GPIO_IN:GPIO_IN_B + + // Return the offset of an element of register array ATR_STATE + function integer ATR_STATE (input integer i); + ATR_STATE = (i * 'h4) + 'h0; + endfunction diff --git a/fpga/usrp3/top/x400/regmap/radio_dio_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/radio_dio_regmap_utils.vh new file mode 100644 index 000000000..62de3d75e --- /dev/null +++ b/fpga/usrp3/top/x400/regmap/radio_dio_regmap_utils.vh @@ -0,0 +1,31 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: radio_dio_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // RADIO_GPIO_ATR_REGS : 0x0 (x4xx_core_common.v) + // DIO_SOURCE_CONTROL : 0x1000 (x4xx_core_common.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group DIO_SOURCES +//=============================================================================== + + // RADIO_GPIO_ATR_REGS Window (from x4xx_core_common.v) + localparam RADIO_GPIO_ATR_REGS = 'h0; // Window Offset + localparam RADIO_GPIO_ATR_REGS_SIZE = 'h1000; // size in bytes + + // DIO_SOURCE_CONTROL Window (from x4xx_core_common.v) + localparam DIO_SOURCE_CONTROL = 'h1000; // Window Offset + localparam DIO_SOURCE_CONTROL_SIZE = 'h1000; // size in bytes diff --git a/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh index 6f34f9e25..dee16263a 100644 --- a/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh +++ b/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh @@ -85,7 +85,7 @@ localparam FPGA_CURRENT_VERSION_MINOR = 'h4; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR localparam FPGA_CURRENT_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR - localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h21081116; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME + localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h21091513; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME // Enumerated type RF_CORE_100M_VERSION localparam RF_CORE_100M_VERSION_SIZE = 7; diff --git a/fpga/usrp3/top/x400/x4xx.v b/fpga/usrp3/top/x400/x4xx.v index 69b4ea2de..4cc97b974 100644 --- a/fpga/usrp3/top/x400/x4xx.v +++ b/fpga/usrp3/top/x400/x4xx.v @@ -2225,7 +2225,7 @@ endmodule // // // -// +// // // // diff --git a/fpga/usrp3/top/x400/x4xx_core.v b/fpga/usrp3/top/x400/x4xx_core.v index c02596e27..4e944e335 100644 --- a/fpga/usrp3/top/x400/x4xx_core.v +++ b/fpga/usrp3/top/x400/x4xx_core.v @@ -241,7 +241,6 @@ module x4xx_core #( wire [ 2*NUM_DBOARDS-1:0] ctrlport_radio_resp_status; wire [ 32*NUM_DBOARDS-1:0] ctrlport_radio_resp_data; - x4xx_core_common #( .CHDR_CLK_RATE (CHDR_CLK_RATE), .CHDR_W (CHDR_W), @@ -318,6 +317,8 @@ module x4xx_core #( .nco_reset_done (nco_reset_done), .adc_reset_pulse (adc_reset_pulse), .dac_reset_pulse (dac_reset_pulse), + .tx_running (tx_running), + .rx_running (rx_running), .qsfp_port_0_0_info (qsfp_port_0_0_info), .qsfp_port_0_1_info (qsfp_port_0_1_info), .qsfp_port_0_2_info (qsfp_port_0_2_info), diff --git a/fpga/usrp3/top/x400/x4xx_core_common.v b/fpga/usrp3/top/x400/x4xx_core_common.v index 9920299c3..3dac18ad5 100644 --- a/fpga/usrp3/top/x400/x4xx_core_common.v +++ b/fpga/usrp3/top/x400/x4xx_core_common.v @@ -10,6 +10,11 @@ // This module contains the common core infrastructure for RFNoC, such as the // motherboard registers and timekeeper, as well as distribution of the // CtrlPort buses from each radio block. +// This module contains blocks that respond to the AXI ctrlport interface, +// the ctrlport interfaces in the radios, or a mix of both. A visual +// representation of how the AXI Ctrlport interface and the +// Ctrlport of each radio interact with the different blocks in this module +// can be found in ./doc/x4xx_core_common_buses.svg // // Parameters: // @@ -93,6 +98,14 @@ module x4xx_core_common #( input wire [11:0] gpio_out_fabric_a, input wire [11:0] gpio_out_fabric_b, + // PS GPIO Control + input wire [11:0] ps_gpio_out_a, + output wire [11:0] ps_gpio_in_a, + input wire [11:0] ps_gpio_ddr_a, + input wire [11:0] ps_gpio_out_b, + output wire [11:0] ps_gpio_in_b, + input wire [11:0] ps_gpio_ddr_b, + // CtrlPort Slave (from RFNoC Radio Blocks; Domain: radio_clk) input wire [ 1*NUM_DBOARDS-1:0] s_radio_ctrlport_req_wr, input wire [ 1*NUM_DBOARDS-1:0] s_radio_ctrlport_req_rd, @@ -123,6 +136,10 @@ module x4xx_core_common #( output wire adc_reset_pulse, output wire dac_reset_pulse, + // Radio state for ATR control + input wire [NUM_DBOARDS*2-1:0] tx_running, + input wire [NUM_DBOARDS*2-1:0] rx_running, + // Misc (Domain: rfnoc_ctrl_clk) input wire [31:0] qsfp_port_0_0_info, input wire [31:0] qsfp_port_0_1_info, @@ -146,6 +163,7 @@ module x4xx_core_common #( `include "regmap/radio_ctrlport_regmap_utils.vh" `include "../../lib/rfnoc/core/ctrlport.vh" `include "regmap/core_regs_regmap_utils.vh" + `include "regmap/radio_dio_regmap_utils.vh" //--------------------------------------------------------------------------- // AXI4-Lite to ctrlport @@ -342,37 +360,69 @@ module x4xx_core_common #( wire [ 2*NUM_DBOARDS-1:0] rf_ctrlport_resp_status; wire [ 32*NUM_DBOARDS-1:0] rf_ctrlport_resp_data; - wire [ 1*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_wr; - wire [ 1*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_rd; - wire [ 20*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_addr; - wire [ 32*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_data; - wire [ 4*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_byte_en; - wire [ 1*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_has_time; - wire [ 64*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_time; - wire [ 1*NUM_DBOARDS-1:0] dio_radio_ctrlport_resp_ack; - wire [ 2*NUM_DBOARDS-1:0] dio_radio_ctrlport_resp_status; - wire [ 32*NUM_DBOARDS-1:0] dio_radio_ctrlport_resp_data; + wire [ 1*NUM_DBOARDS-1:0] radio_dio_req_wr; + wire [ 1*NUM_DBOARDS-1:0] radio_dio_req_rd; + wire [ 20*NUM_DBOARDS-1:0] radio_dio_req_addr; + wire [ 32*NUM_DBOARDS-1:0] radio_dio_req_data; + wire [ 4*NUM_DBOARDS-1:0] radio_dio_req_byte_en; + wire [ 1*NUM_DBOARDS-1:0] radio_dio_req_has_time; + wire [ 64*NUM_DBOARDS-1:0] radio_dio_req_time; + wire [ 1*NUM_DBOARDS-1:0] radio_dio_resp_ack; + wire [ 2*NUM_DBOARDS-1:0] radio_dio_resp_status; + wire [ 32*NUM_DBOARDS-1:0] radio_dio_resp_data; + + wire [NUM_DBOARDS*32-1:0] atr_gpio_out; + wire [NUM_DBOARDS*32-1:0] atr_gpio_ddr; genvar db; generate for (db = 0; db < NUM_DBOARDS; db = db+1) begin : gen_radio_ctrlport //----------------------------------------------------------------------- - // CtrlPort Splitter + // Radio Block CtrlPort Splitter //----------------------------------------------------------------------- // This section takes the CtrlPort master from each radio block and splits it // into a CtrlPort bus for the associated daughter(m_radio_ctrlport_*), the - // RFDC timing control (rf_ctrlport_*) and DIO control(dio_radio_ctrlport_*). + // RFDC timing control (rf_ctrlport_*), the ATR GPIO control for the DB state + // the current radio(db) and DIO main control block(x4xx_dio). + // Refer to diagram in the RADIO_CTRLPORT_REGMAP Register map for a + // visual representation on how these interfaces are distributed. + + // Register space offset calculation + localparam [19:0] DIO_SOURCE_CONTROL_OFFSET = DIO_WINDOW + DIO_SOURCE_CONTROL; + localparam [19:0] RADIO_GPIO_ATR_OFFSET = DIO_WINDOW + RADIO_GPIO_ATR_REGS; - localparam [31:0] DIO_WINDOW_SIZE_W = $clog2(DIO_WINDOW_SIZE); + // Register space size calculation localparam [31:0] RFDC_TIMING_WINDOW_SIZE_W = $clog2(RFDC_TIMING_WINDOW_SIZE); localparam [31:0] DB_WINDOW_SIZE_W = $clog2(DB_WINDOW_SIZE); + localparam [31:0] DIO_SOURCE_CONTROL_SIZE_W = $clog2(DIO_SOURCE_CONTROL_SIZE); + localparam [31:0] RADIO_GPIO_ATR_SIZE_W = $clog2(RADIO_GPIO_ATR_REGS_SIZE); + + wire gpio_atr_ctrlport_req_wr; + wire gpio_atr_ctrlport_req_rd; + wire [19:0] gpio_atr_ctrlport_req_addr; + wire [31:0] gpio_atr_ctrlport_req_data; + wire [ 3:0] gpio_atr_ctrlport_req_byte_en; + wire gpio_atr_ctrlport_req_has_time; + wire [63:0] gpio_atr_ctrlport_req_time; + wire gpio_atr_ctrlport_resp_ack; + wire [ 1:0] gpio_atr_ctrlport_resp_status; + wire [31:0] gpio_atr_ctrlport_resp_data; + ctrlport_decoder_param #( - .NUM_SLAVES (3), - .PORT_BASE ({ DIO_WINDOW[19:0], RFDC_TIMING_WINDOW[19:0], DB_WINDOW[19:0] }), - .PORT_ADDR_W ({ DIO_WINDOW_SIZE_W, RFDC_TIMING_WINDOW_SIZE_W, DB_WINDOW_SIZE_W }) + .NUM_SLAVES (4), + .PORT_BASE ({ DIO_SOURCE_CONTROL_OFFSET, + RADIO_GPIO_ATR_OFFSET, + RFDC_TIMING_WINDOW[19:0], + DB_WINDOW[19:0] + }), + .PORT_ADDR_W ({ DIO_SOURCE_CONTROL_SIZE_W, + RADIO_GPIO_ATR_SIZE_W, + RFDC_TIMING_WINDOW_SIZE_W, + DB_WINDOW_SIZE_W + }) ) ctrlport_decoder_param_i ( .ctrlport_clk (radio_clk), .ctrlport_rst (radio_rst), @@ -386,16 +436,40 @@ module x4xx_core_common #( .s_ctrlport_resp_ack (s_radio_ctrlport_resp_ack [ 1*db+: 1]), .s_ctrlport_resp_status (s_radio_ctrlport_resp_status [ 2*db+: 2]), .s_ctrlport_resp_data (s_radio_ctrlport_resp_data [32*db+:32]), - .m_ctrlport_req_wr ({ dio_radio_ctrlport_req_wr [ 1*db+: 1], rf_ctrlport_req_wr [ 1*db+: 1], m_radio_ctrlport_req_wr [ 1*db+: 1] }), - .m_ctrlport_req_rd ({ dio_radio_ctrlport_req_rd [ 1*db+: 1], rf_ctrlport_req_rd [ 1*db+: 1], m_radio_ctrlport_req_rd [ 1*db+: 1] }), - .m_ctrlport_req_addr ({ dio_radio_ctrlport_req_addr [20*db+:20], rf_ctrlport_req_addr [20*db+:20], m_radio_ctrlport_req_addr [20*db+:20] }), - .m_ctrlport_req_data ({ dio_radio_ctrlport_req_data [32*db+:32], rf_ctrlport_req_data [32*db+:32], m_radio_ctrlport_req_data [32*db+:32] }), - .m_ctrlport_req_byte_en ({ dio_radio_ctrlport_req_byte_en [ 4*db+: 4], rf_ctrlport_req_byte_en [ 4*db+: 4], m_radio_ctrlport_req_byte_en [ 4*db+: 4] }), - .m_ctrlport_req_has_time ({ dio_radio_ctrlport_req_has_time [ 1*db+: 1], rf_ctrlport_req_has_time [ 1*db+: 1], m_radio_ctrlport_req_has_time [ 1*db+: 1] }), - .m_ctrlport_req_time ({ dio_radio_ctrlport_req_time [64*db+:64], rf_ctrlport_req_time [64*db+:64], m_radio_ctrlport_req_time [64*db+:64] }), - .m_ctrlport_resp_ack ({ dio_radio_ctrlport_resp_ack [ 1*db+: 1], rf_ctrlport_resp_ack [ 1*db+: 1], m_radio_ctrlport_resp_ack [ 1*db+: 1] }), - .m_ctrlport_resp_status ({ dio_radio_ctrlport_resp_status [ 2*db+: 2], rf_ctrlport_resp_status [ 2*db+: 2], m_radio_ctrlport_resp_status [ 2*db+: 2] }), - .m_ctrlport_resp_data ({ dio_radio_ctrlport_resp_data [32*db+:32], rf_ctrlport_resp_data [32*db+:32], m_radio_ctrlport_resp_data [32*db+:32] }) + .m_ctrlport_req_wr ({ radio_dio_req_wr [ 1*db+: 1], gpio_atr_ctrlport_req_wr, rf_ctrlport_req_wr [ 1*db+: 1], m_radio_ctrlport_req_wr [ 1*db+: 1] }), + .m_ctrlport_req_rd ({ radio_dio_req_rd [ 1*db+: 1], gpio_atr_ctrlport_req_rd, rf_ctrlport_req_rd [ 1*db+: 1], m_radio_ctrlport_req_rd [ 1*db+: 1] }), + .m_ctrlport_req_addr ({ radio_dio_req_addr [20*db+:20], gpio_atr_ctrlport_req_addr, rf_ctrlport_req_addr [20*db+:20], m_radio_ctrlport_req_addr [20*db+:20] }), + .m_ctrlport_req_data ({ radio_dio_req_data [32*db+:32], gpio_atr_ctrlport_req_data, rf_ctrlport_req_data [32*db+:32], m_radio_ctrlport_req_data [32*db+:32] }), + .m_ctrlport_req_byte_en ({ radio_dio_req_byte_en [ 4*db+: 4], gpio_atr_ctrlport_req_byte_en, rf_ctrlport_req_byte_en [ 4*db+: 4], m_radio_ctrlport_req_byte_en [ 4*db+: 4] }), + .m_ctrlport_req_has_time ({ radio_dio_req_has_time [ 1*db+: 1], gpio_atr_ctrlport_req_has_time, rf_ctrlport_req_has_time [ 1*db+: 1], m_radio_ctrlport_req_has_time [ 1*db+: 1] }), + .m_ctrlport_req_time ({ radio_dio_req_time [64*db+:64], gpio_atr_ctrlport_req_time, rf_ctrlport_req_time [64*db+:64], m_radio_ctrlport_req_time [64*db+:64] }), + .m_ctrlport_resp_ack ({ radio_dio_resp_ack [ 1*db+: 1], gpio_atr_ctrlport_resp_ack, rf_ctrlport_resp_ack [ 1*db+: 1], m_radio_ctrlport_resp_ack [ 1*db+: 1] }), + .m_ctrlport_resp_status ({ radio_dio_resp_status [ 2*db+: 2], gpio_atr_ctrlport_resp_status, rf_ctrlport_resp_status [ 2*db+: 2], m_radio_ctrlport_resp_status [ 2*db+: 2] }), + .m_ctrlport_resp_data ({ radio_dio_resp_data [32*db+:32], gpio_atr_ctrlport_resp_data, rf_ctrlport_resp_data [32*db+:32], m_radio_ctrlport_resp_data [32*db+:32] }) + ); + + // Compute ATR state for this radio + wire [ 3:0] db_state; + + assign db_state = { tx_running[2*db + 1], rx_running[2*db + 1], + tx_running[2*db + 0], rx_running[2*db + 0]}; + + x4xx_gpio_atr #( + .REG_SIZE (RADIO_GPIO_ATR_REGS_SIZE) + ) x4xx_gpio_atr_i ( + .ctrlport_clk (radio_clk), + .ctrlport_rst (radio_rst), + .s_ctrlport_req_wr (gpio_atr_ctrlport_req_wr), + .s_ctrlport_req_rd (gpio_atr_ctrlport_req_rd), + .s_ctrlport_req_addr (gpio_atr_ctrlport_req_addr), + .s_ctrlport_req_data (gpio_atr_ctrlport_req_data), + .s_ctrlport_resp_ack (gpio_atr_ctrlport_resp_ack), + .s_ctrlport_resp_status (gpio_atr_ctrlport_resp_status), + .s_ctrlport_resp_data (gpio_atr_ctrlport_resp_data), + .db_state (db_state), + .gpio_in ({4'b0, gpio_in_b, 4'b0, gpio_in_a}), + .gpio_out (atr_gpio_out[db*32+: 32]), + .gpio_ddr (atr_gpio_ddr[db*32+: 32]) ); end @@ -513,16 +587,16 @@ module x4xx_core_common #( wire [ 1:0] windowed_mpm_dio_resp_status; wire [31:0] windowed_mpm_dio_resp_data; - ctrlport_window #( - .BASE_ADDRESS (DIO), - .WINDOW_SIZE (DIO_SIZE) - ) ctrlport_window_dio ( + ctrlport_decoder_param #( + .NUM_SLAVES (1), + .PORT_BASE ({DIO[19:0]}), + .PORT_ADDR_W ({$clog2(DIO_SIZE)}) + ) ctrlport_decoder_dio_window ( + .ctrlport_clk (radio_clk), + .ctrlport_rst (radio_rst), .s_ctrlport_req_wr (mpm_dio_req_wr), .s_ctrlport_req_rd (mpm_dio_req_rd), .s_ctrlport_req_addr (mpm_dio_req_addr), - .s_ctrlport_req_portid (10'b0), - .s_ctrlport_req_rem_epid (16'b0), - .s_ctrlport_req_rem_portid (10'b0), .s_ctrlport_req_data (mpm_dio_req_data), .s_ctrlport_req_byte_en (4'hF), .s_ctrlport_req_has_time (1'b0), @@ -530,23 +604,20 @@ module x4xx_core_common #( .s_ctrlport_resp_ack (mpm_dio_resp_ack), .s_ctrlport_resp_status (mpm_dio_resp_status), .s_ctrlport_resp_data (mpm_dio_resp_data), - .m_ctrlport_req_wr (windowed_mpm_dio_req_wr), - .m_ctrlport_req_rd (windowed_mpm_dio_req_rd), - .m_ctrlport_req_addr (windowed_mpm_dio_req_addr), - .m_ctrlport_req_portid (), - .m_ctrlport_req_rem_epid (), - .m_ctrlport_req_rem_portid (), - .m_ctrlport_req_data (windowed_mpm_dio_req_data), + .m_ctrlport_req_wr ({windowed_mpm_dio_req_wr}), + .m_ctrlport_req_rd ({windowed_mpm_dio_req_rd}), + .m_ctrlport_req_addr ({windowed_mpm_dio_req_addr}), + .m_ctrlport_req_data ({windowed_mpm_dio_req_data}), .m_ctrlport_req_byte_en (), .m_ctrlport_req_has_time (), .m_ctrlport_req_time (), - .m_ctrlport_resp_ack (windowed_mpm_dio_resp_ack), - .m_ctrlport_resp_status (windowed_mpm_dio_resp_status), - .m_ctrlport_resp_data (windowed_mpm_dio_resp_data) + .m_ctrlport_resp_ack ({windowed_mpm_dio_resp_ack}), + .m_ctrlport_resp_status ({windowed_mpm_dio_resp_status}), + .m_ctrlport_resp_data ({windowed_mpm_dio_resp_data}) ); - // Combined ctrlport signals + // Combined dio ctrlport signals wire dio_ctrlport_req_wr; wire dio_ctrlport_req_rd; wire [19:0] dio_ctrlport_req_addr; @@ -564,19 +635,19 @@ module x4xx_core_common #( ) ctrlport_combiner_dio ( .ctrlport_clk (radio_clk), .ctrlport_rst (radio_rst), - .s_ctrlport_req_wr ({dio_radio_ctrlport_req_wr, windowed_mpm_dio_req_wr}), - .s_ctrlport_req_rd ({dio_radio_ctrlport_req_rd, windowed_mpm_dio_req_rd}), - .s_ctrlport_req_addr ({dio_radio_ctrlport_req_addr, windowed_mpm_dio_req_addr}), + .s_ctrlport_req_wr ({radio_dio_req_wr, windowed_mpm_dio_req_wr}), + .s_ctrlport_req_rd ({radio_dio_req_rd, windowed_mpm_dio_req_rd}), + .s_ctrlport_req_addr ({radio_dio_req_addr, windowed_mpm_dio_req_addr}), .s_ctrlport_req_portid ({(NUM_DBOARDS+1){10'b0}}), .s_ctrlport_req_rem_epid ({(NUM_DBOARDS+1){16'b0}}), .s_ctrlport_req_rem_portid ({(NUM_DBOARDS+1){10'b0}}), - .s_ctrlport_req_data ({dio_radio_ctrlport_req_data, windowed_mpm_dio_req_data}), + .s_ctrlport_req_data ({radio_dio_req_data, windowed_mpm_dio_req_data}), .s_ctrlport_req_byte_en ({(NUM_DBOARDS+1){4'hF}}), .s_ctrlport_req_has_time ({(NUM_DBOARDS+1){1'b0}}), .s_ctrlport_req_time ({(NUM_DBOARDS+1){64'b0}}), - .s_ctrlport_resp_ack ({dio_radio_ctrlport_resp_ack, windowed_mpm_dio_resp_ack}), - .s_ctrlport_resp_status ({dio_radio_ctrlport_resp_status, windowed_mpm_dio_resp_status}), - .s_ctrlport_resp_data ({dio_radio_ctrlport_resp_data, windowed_mpm_dio_resp_data}), + .s_ctrlport_resp_ack ({radio_dio_resp_ack, windowed_mpm_dio_resp_ack}), + .s_ctrlport_resp_status ({radio_dio_resp_status, windowed_mpm_dio_resp_status}), + .s_ctrlport_resp_data ({radio_dio_resp_data, windowed_mpm_dio_resp_data}), .m_ctrlport_req_wr (dio_ctrlport_req_wr), .m_ctrlport_req_rd (dio_ctrlport_req_rd), .m_ctrlport_req_addr (dio_ctrlport_req_addr), @@ -593,30 +664,41 @@ module x4xx_core_common #( ); x4xx_dio #( - .REG_BASE (DIO), - .REG_SIZE (DIO_SIZE) + .REG_SIZE (DIO_SIZE), + .NUM_DBOARDS (NUM_DBOARDS) ) x4xx_dio_i ( - .ctrlport_clk (radio_clk), - .ctrlport_rst (radio_rst), - .s_ctrlport_req_wr (dio_ctrlport_req_wr), - .s_ctrlport_req_rd (dio_ctrlport_req_rd), - .s_ctrlport_req_addr (dio_ctrlport_req_addr), - .s_ctrlport_req_data (dio_ctrlport_req_data), - .s_ctrlport_resp_ack (dio_ctrlport_resp_ack), - .s_ctrlport_resp_status (dio_ctrlport_resp_status), - .s_ctrlport_resp_data (dio_ctrlport_resp_data), - .gpio_in_a (gpio_in_a), - .gpio_in_b (gpio_in_b), - .gpio_out_a (gpio_out_a), - .gpio_out_b (gpio_out_b), - .gpio_en_a (gpio_en_a), - .gpio_en_b (gpio_en_b), - .gpio_in_fabric_a (gpio_in_fabric_a), - .gpio_in_fabric_b (gpio_in_fabric_b), - .gpio_out_fabric_a (gpio_out_fabric_a), - .gpio_out_fabric_b (gpio_out_fabric_b) + .ctrlport_clk (radio_clk), + .ctrlport_rst (radio_rst), + .s_ctrlport_req_wr (dio_ctrlport_req_wr), + .s_ctrlport_req_rd (dio_ctrlport_req_rd), + .s_ctrlport_req_addr (dio_ctrlport_req_addr), + .s_ctrlport_req_data (dio_ctrlport_req_data), + .s_ctrlport_resp_ack (dio_ctrlport_resp_ack), + .s_ctrlport_resp_status (dio_ctrlport_resp_status), + .s_ctrlport_resp_data (dio_ctrlport_resp_data), + .gpio_in_a (gpio_in_a), + .gpio_in_b (gpio_in_b), + .gpio_out_a (gpio_out_a), + .gpio_out_b (gpio_out_b), + .gpio_en_a (gpio_en_a), + .gpio_en_b (gpio_en_b), + .atr_gpio_out (atr_gpio_out), + .atr_gpio_ddr (atr_gpio_ddr), + .ps_gpio_out ({4'b0, ps_gpio_out_b, 4'b0, ps_gpio_out_a}), + .ps_gpio_ddr ({4'b0, ps_gpio_ddr_b, 4'b0, ps_gpio_ddr_a}), + .digital_ifc_gpio_out_radio0 (32'b0), + .digital_ifc_gpio_ddr_radio0 (32'b0), + .digital_ifc_gpio_out_radio1 (32'b0), + .digital_ifc_gpio_ddr_radio1 (32'b0), + .user_app_in_a (gpio_in_fabric_a), + .user_app_in_b (gpio_in_fabric_b), + .user_app_out_a (gpio_out_fabric_a), + .user_app_out_b (gpio_out_fabric_b) ); + assign ps_gpio_in_a = gpio_in_fabric_a; + assign ps_gpio_in_b = gpio_in_fabric_b; + endmodule @@ -629,7 +711,11 @@ endmodule // // Each radio's CtrlPort peripheral interface is divided into the // following memory spaces. Note that the CtrlPort peripheral interface -// starts at offset 0x80000 in the RFNoC Radio block's register space. +// starts at offset 0x80000 in the RFNoC Radio block's register space. +// The following diagram displays the distribution of the CtrlPort +// interface to the different modules it interacts with. +// // // Daughterboard GPIO interface. Register access within this space // is directed to the associated daughterboard CPLD. @@ -637,8 +723,9 @@ endmodule // // RFDC timing control interface. // -// -// DIO control interface +// +// DIO control interface. Interacts with the DIO source selection +// block, ATR-based DIO control and the DIO digital interface // // // @@ -651,6 +738,10 @@ endmodule // The registers contained here conform the mboard-regs node that MPM uses // to manage general FPGA control/status calls, such as versioning, // timekeeper, GPIO, etc. +// +// The following diagram shows how the communication bus interacts with the +// modules in CORE_REGS. +// // // @@ -662,9 +753,25 @@ endmodule // // Window to access the timekeeper register map. // -// +// // Window to access the DIO register map. // // // + +// +// +// This map contains register windows for controlling the different sources +// that drive the state of DIO lines. +// +// +// +// Contains controls for DIO behavior based on the ATR state of the accessed radio +// +// +// Window to access the DIO register map through the control port from the radio blocks. +// +// +// + //XmlParse xml_off diff --git a/fpga/usrp3/top/x400/x4xx_dio.v b/fpga/usrp3/top/x400/x4xx_dio.v index 871a239ee..b67ecfa4c 100644 --- a/fpga/usrp3/top/x400/x4xx_dio.v +++ b/fpga/usrp3/top/x400/x4xx_dio.v @@ -9,10 +9,23 @@ // // This module contains the motherboard registers for the DIO // auxiliary board and the logic to drive these GPIO signals. +// Arbitration between different sources to control the state +// of the GPIO lines includes support for the following sources: +// - s_ctrlport_* (combination of CtrlPort from PS AXI and radio blocks) +// - PS dio control from Processing System's GPIOs +// - ATR state (up to two DBs) +// - User Application +// - radio-controlled digital bus interface +// For a visual representation of how the different sources are +// arbitrated, as well as representation on what each source control +// register refers to, please refer to the "Front-Panel Programmable +// GPIOs" section of the USRP Manual. // // Parameters: // -// REG_BASE : Base address to use for registers. +// REG_BASE : Base address to use for registers. +// REG_SIZE : Register space size. +// NUM_DBOARDS : Number of daughterboards to support. // `default_nettype none @@ -20,7 +33,8 @@ module x4xx_dio #( parameter REG_BASE = 0, - parameter REG_SIZE = 'h20 + parameter REG_SIZE = 'h30, + parameter NUM_DBOARDS = 2 ) ( // Slave ctrlport interface input wire ctrlport_clk, @@ -43,11 +57,31 @@ module x4xx_dio #( output wire [11:0] gpio_out_a, output wire [11:0] gpio_out_b, - // GPIO to application (async) - output wire [11:0] gpio_in_fabric_a, - output wire [11:0] gpio_in_fabric_b, - input wire [11:0] gpio_out_fabric_a, - input wire [11:0] gpio_out_fabric_b + // ATR GPIO Control (ctrlport_clk) + input wire [NUM_DBOARDS*32-1:0] atr_gpio_out, + input wire [NUM_DBOARDS*32-1:0] atr_gpio_ddr, + + // PS GPIO Control from Block Design (async) + input wire [31:0] ps_gpio_out, + input wire [31:0] ps_gpio_ddr, + + // Digital Interface Control (ctrlport_clk) + input wire [31:0] digital_ifc_gpio_out_radio0, + input wire [31:0] digital_ifc_gpio_ddr_radio0, + input wire [31:0] digital_ifc_gpio_out_radio1, + input wire [31:0] digital_ifc_gpio_ddr_radio1, + + // GPIO to user application (async) + // User application relies on the local direction register + // for GPIO direction control. For this reason, we skip + // a mux to select between the user application and the + // local register direction control in the mux chain, and + // propagate their shared direction(from the local register) + // to the remainder of the mux chain. + output wire [11:0] user_app_in_a, + output wire [11:0] user_app_in_b, + input wire [11:0] user_app_out_a, + input wire [11:0] user_app_out_b ); `include "../../lib/rfnoc/core/ctrlport.vh" @@ -70,6 +104,16 @@ module x4xx_dio #( reg [DIO_WIDTH-1:0] dio_master_b = {DIO_WIDTH {1'b0}}; reg [DIO_WIDTH-1:0] dio_output_a = {DIO_WIDTH {1'b0}}; reg [DIO_WIDTH-1:0] dio_output_b = {DIO_WIDTH {1'b0}}; + reg [DIO_WIDTH-1:0] dio_source_a = {DIO_WIDTH {1'b0}}; + reg [DIO_WIDTH-1:0] dio_source_b = {DIO_WIDTH {1'b0}}; + reg [DIO_WIDTH-1:0] dio_radio_a = {DIO_WIDTH {1'b0}}; + reg [DIO_WIDTH-1:0] dio_radio_b = {DIO_WIDTH {1'b0}}; + reg [DIO_WIDTH-1:0] dio_interface_a = {DIO_WIDTH {1'b0}}; + reg [DIO_WIDTH-1:0] dio_interface_b = {DIO_WIDTH {1'b0}}; + reg [DIO_WIDTH-1:0] dio_override_a = {DIO_WIDTH {1'b0}}; + reg [DIO_WIDTH-1:0] dio_override_b = {DIO_WIDTH {1'b0}}; + reg [DIO_WIDTH-1:0] dio_sw_ctrl_a = {DIO_WIDTH {1'b0}}; + reg [DIO_WIDTH-1:0] dio_sw_ctrl_b = {DIO_WIDTH {1'b0}}; wire [DIO_WIDTH-1:0] dio_input_a; wire [DIO_WIDTH-1:0] dio_input_b; @@ -93,6 +137,16 @@ module x4xx_dio #( dio_master_b <= {DIO_WIDTH {1'b0}}; dio_output_a <= {DIO_WIDTH {1'b0}}; dio_output_b <= {DIO_WIDTH {1'b0}}; + dio_source_a <= {DIO_WIDTH {1'b0}}; + dio_source_b <= {DIO_WIDTH {1'b0}}; + dio_radio_a <= {DIO_WIDTH {1'b0}}; + dio_radio_b <= {DIO_WIDTH {1'b0}}; + dio_interface_a <= {DIO_WIDTH {1'b0}}; + dio_interface_b <= {DIO_WIDTH {1'b0}}; + dio_override_a <= {DIO_WIDTH {1'b0}}; + dio_override_b <= {DIO_WIDTH {1'b0}}; + dio_sw_ctrl_a <= {DIO_WIDTH {1'b0}}; + dio_sw_ctrl_b <= {DIO_WIDTH {1'b0}}; end else begin // Write registers @@ -104,18 +158,43 @@ module x4xx_dio #( case (s_ctrlport_req_addr) REG_BASE + DIO_MASTER_REGISTER: begin - dio_master_a <= s_ctrlport_req_data[DIO_MASTER_A_MSB:DIO_MASTER_A]; - dio_master_b <= s_ctrlport_req_data[DIO_MASTER_B_MSB:DIO_MASTER_B]; + dio_master_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A]; + dio_master_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B]; end REG_BASE + DIO_DIRECTION_REGISTER: begin - dio_direction_a <= s_ctrlport_req_data[DIO_DIRECTION_A_MSB:DIO_DIRECTION_A]; - dio_direction_b <= s_ctrlport_req_data[DIO_DIRECTION_B_MSB:DIO_DIRECTION_B]; + dio_direction_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A]; + dio_direction_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B]; end REG_BASE + DIO_OUTPUT_REGISTER: begin - dio_output_a <= s_ctrlport_req_data[DIO_OUTPUT_A_MSB:DIO_OUTPUT_A]; - dio_output_b <= s_ctrlport_req_data[DIO_OUTPUT_B_MSB:DIO_OUTPUT_B]; + dio_output_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A]; + dio_output_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B]; + end + + REG_BASE + DIO_SOURCE_REGISTER: begin + dio_source_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A]; + dio_source_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B]; + end + + REG_BASE + RADIO_SOURCE_REGISTER: begin + dio_radio_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A]; + dio_radio_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B]; + end + + REG_BASE + INTERFACE_DIO_SELECT: begin + dio_interface_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A]; + dio_interface_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B]; + end + + REG_BASE + DIO_OVERRIDE: begin + dio_override_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A]; + dio_override_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B]; + end + + REG_BASE + SW_DIO_CONTROL: begin + dio_sw_ctrl_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A]; + dio_sw_ctrl_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B]; end // No register implementation for provided address @@ -131,6 +210,7 @@ module x4xx_dio #( end endcase + // Read registers end else if (s_ctrlport_req_rd) begin // Acknowledge by default @@ -140,23 +220,48 @@ module x4xx_dio #( case (s_ctrlport_req_addr) REG_BASE + DIO_MASTER_REGISTER: begin - s_ctrlport_resp_data[DIO_MASTER_A_MSB:DIO_MASTER_A] <= dio_master_a; - s_ctrlport_resp_data[DIO_MASTER_B_MSB:DIO_MASTER_B] <= dio_master_b; + s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_master_a; + s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_master_b; end REG_BASE + DIO_DIRECTION_REGISTER: begin - s_ctrlport_resp_data[DIO_DIRECTION_A_MSB:DIO_DIRECTION_A] <= dio_direction_a; - s_ctrlport_resp_data[DIO_DIRECTION_B_MSB:DIO_DIRECTION_B] <= dio_direction_b; + s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_direction_a; + s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_direction_b; end REG_BASE + DIO_OUTPUT_REGISTER: begin - s_ctrlport_resp_data[DIO_OUTPUT_A_MSB:DIO_OUTPUT_A] <= dio_output_a; - s_ctrlport_resp_data[DIO_OUTPUT_B_MSB:DIO_OUTPUT_B] <= dio_output_b; + s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_output_a; + s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_output_b; end REG_BASE + DIO_INPUT_REGISTER: begin - s_ctrlport_resp_data[DIO_INPUT_A_MSB:DIO_INPUT_A] <= dio_input_a; - s_ctrlport_resp_data[DIO_INPUT_B_MSB:DIO_INPUT_B] <= dio_input_b; + s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_input_a; + s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_input_b; + end + + REG_BASE + DIO_SOURCE_REGISTER: begin + s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_source_a; + s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_source_b; + end + + REG_BASE + RADIO_SOURCE_REGISTER: begin + s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_radio_a; + s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_radio_b; + end + + REG_BASE + INTERFACE_DIO_SELECT: begin + s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_interface_a; + s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_interface_b; + end + + REG_BASE + DIO_OVERRIDE: begin + s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_override_a; + s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_override_b; + end + + REG_BASE + SW_DIO_CONTROL: begin + s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_sw_ctrl_a; + s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_sw_ctrl_b; end // No register implementation for provided address @@ -198,31 +303,205 @@ module x4xx_dio #( ); // Forward raw input to user application - assign gpio_in_fabric_a = gpio_in_a; - assign gpio_in_fabric_b = gpio_in_b; + assign user_app_in_a = gpio_in_a; + assign user_app_in_b = gpio_in_b; - // Direction control - assign gpio_en_a = dio_direction_a; - assign gpio_en_b = dio_direction_b; + wire [DIO_WIDTH-1:0] gpio_out_sw_a; + wire [DIO_WIDTH-1:0] gpio_out_sw_b; // Output assignment depending on master generate genvar i; for (i = 0; i < DIO_WIDTH; i = i + 1) begin: dio_output_gen - glitch_free_mux glitch_free_mux_dio_a ( + + reg atr_gpio_src_out_a_reg = 1'b0; + reg atr_gpio_src_out_b_reg = 1'b0; + reg atr_gpio_src_ddr_a_reg = 1'b0; + reg atr_gpio_src_ddr_b_reg = 1'b0; + + // 1) Select which radio drives the output + always @ (posedge ctrlport_clk) begin + if (ctrlport_rst) begin + atr_gpio_src_out_a_reg <= 1'b0; + atr_gpio_src_out_b_reg <= 1'b0; + end else begin + atr_gpio_src_out_a_reg <= atr_gpio_out[dio_radio_a[i]*32 + DIO_PORT_A + i]; + atr_gpio_src_out_b_reg <= atr_gpio_out[dio_radio_b[i]*32 + DIO_PORT_B + i]; + end + end + + // 2) Select which radio drives the direction + always @ (posedge ctrlport_clk) begin + if (ctrlport_rst) begin + atr_gpio_src_ddr_a_reg <= 1'b0; + atr_gpio_src_ddr_b_reg <= 1'b0; + end else begin + atr_gpio_src_ddr_a_reg <= atr_gpio_ddr[dio_radio_a[i]*32 + DIO_PORT_A + i]; + atr_gpio_src_ddr_b_reg <= atr_gpio_ddr[dio_radio_b[i]*32 + DIO_PORT_B + i]; + end + end + + // Select between the Digital Interface in each radio(INTERFACE_DIO_SELECT) + wire dio_interface_mux_out_a; + wire dio_interface_mux_out_b; + wire dio_interface_mux_ddr_a; + wire dio_interface_mux_ddr_b; + + glitch_free_mux glitch_free_interface_out_mux_dio_a ( + .select (dio_interface_a[i]), + .signal0 (digital_ifc_gpio_out_radio0[DIO_PORT_A + i]), + .signal1 (digital_ifc_gpio_out_radio1[DIO_PORT_A + i]), + .muxed_signal (dio_interface_mux_out_a) + ); + + glitch_free_mux glitch_free_interface_out_mux_dio_b ( + .select (dio_interface_b[i]), + .signal0 (digital_ifc_gpio_out_radio0[DIO_PORT_B + i]), + .signal1 (digital_ifc_gpio_out_radio1[DIO_PORT_B + i]), + .muxed_signal (dio_interface_mux_out_b) + ); + + glitch_free_mux glitch_free_interface_ddr_mux_dio_a ( + .select (dio_interface_a[i]), + .signal0 (digital_ifc_gpio_ddr_radio0[DIO_PORT_A + i]), + .signal1 (digital_ifc_gpio_ddr_radio1[DIO_PORT_A + i]), + .muxed_signal (dio_interface_mux_ddr_a) + ); + + glitch_free_mux glitch_free_interface_ddr_mux_dio_b ( + .select (dio_interface_b[i]), + .signal0 (digital_ifc_gpio_ddr_radio0[DIO_PORT_B + i]), + .signal1 (digital_ifc_gpio_ddr_radio1[DIO_PORT_B + i]), + .muxed_signal (dio_interface_mux_ddr_b) + ); + + + // Select between ATR or Digital control(DIO_OVERRIDE) + wire dio_override_mux_out_a; + wire dio_override_mux_out_b; + wire dio_override_mux_ddr_a; + wire dio_override_mux_ddr_b; + + glitch_free_mux glitch_free_override_out_mux_dio_a ( + .select (dio_override_a[i]), + .signal0 (atr_gpio_src_out_a_reg), + .signal1 (dio_interface_mux_out_a), + .muxed_signal (dio_override_mux_out_a) + ); + + glitch_free_mux glitch_free_override_out_mux_dio_b ( + .select (dio_override_b[i]), + .signal0 (atr_gpio_src_out_b_reg), + .signal1 (dio_interface_mux_out_b), + .muxed_signal (dio_override_mux_out_b) + ); + + glitch_free_mux glitch_free_override_ddr_mux_dio_a ( + .select (dio_override_a[i]), + .signal0 (atr_gpio_src_ddr_a_reg), + .signal1 (dio_interface_mux_ddr_a), + .muxed_signal (dio_override_mux_ddr_a) + ); + + glitch_free_mux glitch_free_override_ddr_mux_dio_b ( + .select (dio_override_b[i]), + .signal0 (atr_gpio_src_ddr_b_reg), + .signal1 (dio_interface_mux_ddr_b), + .muxed_signal (dio_override_mux_ddr_b) + ); + + + // SW source select + // SW_DIO_CONTROL, select between PS and local register + + wire dio_sw_control_mux_out_a; + wire dio_sw_control_mux_out_b; + wire dio_sw_control_mux_ddr_a; + wire dio_sw_control_mux_ddr_b; + + glitch_free_mux glitch_free_sw_control_out_mux_dio_a ( + .select (dio_sw_ctrl_a[i]), + .signal0 (dio_output_a[i]), + .signal1 (ps_gpio_out[DIO_PORT_A + i]), + .muxed_signal (dio_sw_control_mux_out_a) + ); + + glitch_free_mux glitch_free_sw_control_out_mux_dio_b ( + .select (dio_sw_ctrl_b[i]), + .signal0 (dio_output_b[i]), + .signal1 (ps_gpio_out[DIO_PORT_B + i]), + .muxed_signal (dio_sw_control_mux_out_b) + ); + + glitch_free_mux glitch_free_sw_control_ddr_mux_dio_a ( + .select (dio_sw_ctrl_a[i]), + .signal0 (dio_direction_a[i]), + .signal1 (ps_gpio_ddr[DIO_PORT_A + i]), + .muxed_signal (dio_sw_control_mux_ddr_a) + ); + + glitch_free_mux glitch_free_sw_control_ddr_mux_dio_b ( + .select (dio_sw_ctrl_b[i]), + .signal0 (dio_direction_b[i]), + .signal1 (ps_gpio_ddr[DIO_PORT_B + i]), + .muxed_signal (dio_sw_control_mux_ddr_b) + ); + + + // DIO_MASTER_REGISTER Mux, select between SW_DIO_CONTROL + // and user application + // User application relies on the local direction register + // for GPIO direction control. For this reason, we skip + // a mux to select between the user application and the + // local register direction control in the mux chain, and + // propagate their shared direction(from the local register) + // to the remainder of the mux chain. + glitch_free_mux glitch_free_master_mux_dio_a ( .select (dio_master_a[i]), - .signal0 (gpio_out_fabric_a[i]), - .signal1 (dio_output_a[i]), - .muxed_signal (gpio_out_a[i]) + .signal0 (user_app_out_a[i]), + .signal1 (dio_sw_control_mux_out_a), + .muxed_signal (gpio_out_sw_a[i]) ); - glitch_free_mux glitch_free_mux_dio_b ( + glitch_free_mux glitch_free_master_mux_dio_b ( .select (dio_master_b[i]), - .signal0 (gpio_out_fabric_b[i]), - .signal1 (dio_output_b[i]), + .signal0 (user_app_out_b[i]), + .signal1 (dio_sw_control_mux_out_b), + .muxed_signal (gpio_out_sw_b[i]) + ); + + // DIO_SOURCE_REGISTER mux, select between (DIO_MASTER_REGISTER output) and + // radio controlled source (DIO_OVERRIDE output). + glitch_free_mux glitch_free_source_out_mux_dio_a ( + .select (dio_source_a[i]), + .signal0 (gpio_out_sw_a[i]), + .signal1 (dio_override_mux_out_a), + .muxed_signal (gpio_out_a[i]) + ); + + glitch_free_mux glitch_free_source_out_mux_dio_b ( + .select (dio_source_b[i]), + .signal0 (gpio_out_sw_b[i]), + .signal1 (dio_override_mux_out_b), .muxed_signal (gpio_out_b[i]) ); + + // Direction control + glitch_free_mux glitch_free_dir_mux_dio_a ( + .select (dio_source_a[i]), + .signal0 (dio_sw_control_mux_ddr_a), + .signal1 (dio_override_mux_ddr_a), + .muxed_signal (gpio_en_a[i]) + ); + + glitch_free_mux glitch_free_dir_mux_dio_b ( + .select (dio_source_b[i]), + .signal0 (dio_sw_control_mux_ddr_b), + .signal1 (dio_override_mux_ddr_b), + .muxed_signal (gpio_en_b[i]) + ); end + endgenerate endmodule @@ -232,44 +511,90 @@ endmodule //XmlParse xml_on -// +// // // -// Registers to control the GPIO buffer direction on the FPGA connected to the DIO board. -// Further registers enable the PS to control and read the GPIO lines as master. -// Make sure the GPIO lines between FPGA and GPIO board are not driven by two drivers. -// Set the DIO registers in @.PS_CPLD_BASE_REGMAP appropriately. +// Registers to control the GPIO buffer direction on the FPGA connected to +// the DIO board. Further registers enable different sources to control and +// read the GPIO lines as master. The following diagram shows how source +// selection multiplexers are arranged, as well as an indicator for the +// register that control them.
+// Front-Panel Programmable GPIOs
+// Make sure the GPIO lines between FPGA and GPIO board are not driven by +// two drivers. Set the DIO registers in @.PS_CPLD_BASE_REGMAP appropriately. // // -// +// +// +// Holds a single bit setting for DIO lines in both ports. One bit per pin. +// +// +// +// +// +// // -// Sets whether the DIO signal line is driven by this register interface or the user application.{br/} -// 0 = user application is master, 1 = PS is master +// Sets whether the DIO signal line is driven by this register interface +// or the user application.{br/} +// 0 = user application is master, 1 = output of @.SW_DIO_CONTROL is master // -// -// // -// +// // // Set the direction of FPGA buffer connected to DIO ports on the DIO board.{br/} -// Each bit represents one signal line. 0 = line is an input to the FPGA, 1 = line is an output driven by the FPGA. +// Each bit represents one signal line. 0 = line is an input to the FPGA, +// 1 = line is an output driven by the FPGA. // -// -// // -// +// // // Status of each bit at the FPGA input. // -// -// // -// +// +// +// Controls the values on each DIO signal line in case the line master is +// set to PS in @.DIO_MASTER_REGISTER. +// +// +// +// +// Controls whether the DIO lines reflect the state of @.DIO_MASTER_REGISTER +// or the radio blocks. 0 = @.DIO_MASTER_REGISTER, +// 1 = Radio block output(@.DIO_OVERRIDE) +// +// +// +// +// Controls which radio block to use the ATR state from to determine the +// state of the DIO lines. +// 0 = Radio#0 +// 1 = Radio#1 +// +// +// +// +// Controls which of the two available digital interfaces controls the DIO lines. +// 0 = Digital interface from Radio#0, +// 1 = Digital Interface from Radio#1. +// +// +// +// +// Controls whether the radio input to the @.DIO_SOURCE_REGISTER mux +// connects to the ATR control or a Digital interface block. The output +// of the mux controlled by this bit goes to @.DIO_SOURCE_REGISTER. +// 0 = Drive the ATR state(@.RADIO_SOURCE_REGISTER), 1 = Drive +// Digital interface block(Output of @.INTERFACE_DIO_SELECT). +// +// +// // -// Controls the values on each DIO signal line in case the line master is set to PS in @.DIO_MASTER_REGISTER. +// Controls which source is forwarded to the @.DIO_MASTER_REGISTER mux. +// This configuration is applied independently for each DIO line. +// 0 = MPM Ctrlport endpoint, 1 = PS Netlist DIO signal. // -// -// // // // diff --git a/fpga/usrp3/top/x400/x4xx_gpio_atr.v b/fpga/usrp3/top/x400/x4xx_gpio_atr.v new file mode 100644 index 000000000..98ba881f3 --- /dev/null +++ b/fpga/usrp3/top/x400/x4xx_gpio_atr.v @@ -0,0 +1,376 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: x4xx_gpio_atr +// +// Description: +// +// This module controls the behavior of a GPIO bus of arbitrary width +// based on the current ATR state. The radio state is determined by +// combining the TX and RX states of each rf channel in the radio in +// the following order: {tx_rf1, rx_rf1, tx_rf0, rx_rf0} +// +// Parameters: +// +// REG_BASE : Base address to use for registers. +// REG_SIZE : Register space size. +// WIDTH : Number of GPIO lines controlled by this block. +// +module x4xx_gpio_atr #( + parameter REG_BASE = 0, + parameter REG_SIZE = 'h20, + parameter WIDTH = 32 +) ( + // Slave ctrlport interface + input wire ctrlport_clk, + input wire ctrlport_rst, + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + output reg s_ctrlport_resp_ack = 1'b0, + output reg [ 1:0] s_ctrlport_resp_status = 2'b00, + output reg [31:0] s_ctrlport_resp_data = {32 {1'bX}}, + // Run state signals that indicate tx and rx operation + input wire [3:0] db_state, + // GPIO control signals + input wire [WIDTH-1:0] gpio_in, //GPIO input state + output reg [WIDTH-1:0] gpio_out = {WIDTH {1'b0}}, //GPIO output state + output reg [WIDTH-1:0] gpio_ddr = {WIDTH {1'b0}} //GPIO direction (0=input, 1=output) +); + + `include "../../lib/rfnoc/core/ctrlport.vh" + `include "regmap/gpio_atr_regmap_utils.vh" + + reg [WIDTH-1:0] in_atr_state [15:0]; + + initial begin + in_atr_state[0] = {WIDTH {1'b0}}; + in_atr_state[1] = {WIDTH {1'b0}}; + in_atr_state[2] = {WIDTH {1'b0}}; + in_atr_state[3] = {WIDTH {1'b0}}; + in_atr_state[4] = {WIDTH {1'b0}}; + in_atr_state[5] = {WIDTH {1'b0}}; + in_atr_state[6] = {WIDTH {1'b0}}; + in_atr_state[7] = {WIDTH {1'b0}}; + in_atr_state[8] = {WIDTH {1'b0}}; + in_atr_state[9] = {WIDTH {1'b0}}; + in_atr_state[10] = {WIDTH {1'b0}}; + in_atr_state[11] = {WIDTH {1'b0}}; + in_atr_state[12] = {WIDTH {1'b0}}; + in_atr_state[13] = {WIDTH {1'b0}}; + in_atr_state[14] = {WIDTH {1'b0}}; + in_atr_state[15] = {WIDTH {1'b0}}; + end + + reg [WIDTH-1:0] ddr_reg, atr_disable, gpio_sw_rb = {WIDTH {1'b0}}; + reg [WIDTH-1:0] ogpio, igpio = {WIDTH {1'b0}}; + reg [WIDTH-1:0] classic_atr_select = {WIDTH {1'b0}}; + + // DB state/Classic ATR selector + reg atr_mode = 1'b0; + + genvar state; + //--------------------------------------------------------------------------- + // Control interface handling + //--------------------------------------------------------------------------- + + // Check that address is within this module's range. + wire address_in_range = (s_ctrlport_req_addr >= REG_BASE) && (s_ctrlport_req_addr < REG_BASE + REG_SIZE); + + // Check that address is targeting an ATR state. + wire address_is_atr = (s_ctrlport_req_addr >= REG_BASE + ATR_STATE(0)) && (s_ctrlport_req_addr <= REG_BASE + ATR_STATE(15)); + // Decode the ATR state being addressed. + wire [3:0]atr_address = s_ctrlport_req_addr[5:2]; + + always @ (posedge ctrlport_clk) begin + if (ctrlport_rst) begin + s_ctrlport_resp_ack <= 1'b0; + s_ctrlport_resp_data <= {32 {1'bX}}; + s_ctrlport_resp_status <= 2'b00; + + ddr_reg <= {WIDTH {1'b0}}; + atr_disable <= {WIDTH {1'b0}}; + classic_atr_select <= {WIDTH {1'b0}}; + atr_mode <= 1'b0; + + in_atr_state[0] <= {WIDTH {1'b0}}; + in_atr_state[1] <= {WIDTH {1'b0}}; + in_atr_state[2] <= {WIDTH {1'b0}}; + in_atr_state[3] <= {WIDTH {1'b0}}; + in_atr_state[4] <= {WIDTH {1'b0}}; + in_atr_state[5] <= {WIDTH {1'b0}}; + in_atr_state[6] <= {WIDTH {1'b0}}; + in_atr_state[7] <= {WIDTH {1'b0}}; + in_atr_state[8] <= {WIDTH {1'b0}}; + in_atr_state[9] <= {WIDTH {1'b0}}; + in_atr_state[10] <= {WIDTH {1'b0}}; + in_atr_state[11] <= {WIDTH {1'b0}}; + in_atr_state[12] <= {WIDTH {1'b0}}; + in_atr_state[13] <= {WIDTH {1'b0}}; + in_atr_state[14] <= {WIDTH {1'b0}}; + in_atr_state[15] <= {WIDTH {1'b0}}; + + end else begin + // Write registers + if (s_ctrlport_req_wr) begin + // Acknowledge by default + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}}; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + // Address ATR state writes + if(address_is_atr) begin + in_atr_state[atr_address][GPIO_STATE_A_MSB:GPIO_STATE_A] <= s_ctrlport_req_data[GPIO_STATE_A_MSB:GPIO_STATE_A]; + in_atr_state[atr_address][GPIO_STATE_B_MSB:GPIO_STATE_B] <= s_ctrlport_req_data[GPIO_STATE_B_MSB:GPIO_STATE_B]; + end else begin + + // Address writes to the rest of the register space + case (s_ctrlport_req_addr) + + REG_BASE + ATR_OPTION_REGISTRER: begin + atr_mode <= s_ctrlport_req_data[ATR_OPTION]; + end + + REG_BASE + CLASSIC_ATR_CONFIG: begin + classic_atr_select[RF_SELECT_A_MSB:RF_SELECT_A] <= s_ctrlport_req_data[RF_SELECT_A_MSB:RF_SELECT_A]; + classic_atr_select[RF_SELECT_B_MSB:RF_SELECT_B] <= s_ctrlport_req_data[RF_SELECT_B_MSB:RF_SELECT_B]; + end + + REG_BASE + GPIO_DIR: begin + ddr_reg[GPIO_DIR_A_MSB:GPIO_DIR_A] <= s_ctrlport_req_data[GPIO_DIR_A_MSB:GPIO_DIR_A]; + ddr_reg[GPIO_DIR_B_MSB:GPIO_DIR_B] <= s_ctrlport_req_data[GPIO_DIR_B_MSB:GPIO_DIR_B]; + end + + REG_BASE + GPIO_DISABLED: begin + atr_disable[GPIO_DISABLED_A_MSB:GPIO_DISABLED_A] <= s_ctrlport_req_data[GPIO_DISABLED_A_MSB:GPIO_DISABLED_A]; + atr_disable[GPIO_DISABLED_B_MSB:GPIO_DISABLED_B] <= s_ctrlport_req_data[GPIO_DISABLED_B_MSB:GPIO_DISABLED_B]; + end + + // No register implementation for provided address + default: begin + // Acknowledge and provide error status if address is in range + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // No response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + end + + // Read registers + end else if (s_ctrlport_req_rd) begin + // Acknowledge by default + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}}; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + // Address ATR state reads + if(address_is_atr) begin + s_ctrlport_resp_data[GPIO_STATE_A_MSB:GPIO_STATE_A] <= in_atr_state[atr_address][GPIO_STATE_A_MSB:GPIO_STATE_A]; + s_ctrlport_resp_data[GPIO_STATE_B_MSB:GPIO_STATE_B] <= in_atr_state[atr_address][GPIO_STATE_B_MSB:GPIO_STATE_B]; + end else begin + + // Address reads to the rest of the register space + case (s_ctrlport_req_addr) + + REG_BASE + ATR_OPTION_REGISTRER: begin + s_ctrlport_resp_data[ATR_OPTION] <= atr_mode; + end + + REG_BASE + CLASSIC_ATR_CONFIG: begin + s_ctrlport_resp_data[RF_SELECT_A_MSB:RF_SELECT_A] <= classic_atr_select[RF_SELECT_A_MSB:RF_SELECT_A]; + s_ctrlport_resp_data[RF_SELECT_B_MSB:RF_SELECT_B] <= classic_atr_select[RF_SELECT_B_MSB:RF_SELECT_B]; + end + + REG_BASE + GPIO_DIR: begin + s_ctrlport_resp_data[GPIO_DIR_A_MSB:GPIO_DIR_A] <= ddr_reg[GPIO_DIR_A_MSB:GPIO_DIR_A]; + s_ctrlport_resp_data[GPIO_DIR_B_MSB:GPIO_DIR_B] <= ddr_reg[GPIO_DIR_B_MSB:GPIO_DIR_B]; + end + + REG_BASE + GPIO_DISABLED: begin + s_ctrlport_resp_data[GPIO_DISABLED_A_MSB:GPIO_DISABLED_A] <= atr_disable[GPIO_DISABLED_A_MSB:GPIO_DISABLED_A]; + s_ctrlport_resp_data[GPIO_DISABLED_B_MSB:GPIO_DISABLED_B] <= atr_disable[GPIO_DISABLED_B_MSB:GPIO_DISABLED_B]; + end + + REG_BASE + GPIO_IN: begin + s_ctrlport_resp_data[GPIO_IN_A_MSB:GPIO_IN_A] <= gpio_sw_rb[GPIO_IN_A_MSB:GPIO_IN_A]; + s_ctrlport_resp_data[GPIO_IN_B_MSB:GPIO_IN_B] <= gpio_sw_rb[GPIO_IN_B_MSB:GPIO_IN_B]; + end + + // No register implementation for provided address + default: begin + // Acknowledge and provide error status if address is in range + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // No response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + end + + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + end + + genvar i; + + //Pipeline for easier timing closure + reg [ 3:0] db_state_d = 4'b0; + reg atr_mode_d = 1'b0; + reg [WIDTH-1:0] classic_atr_select_d = {WIDTH {1'b0}}; + always @(posedge ctrlport_clk) begin + db_state_d <= db_state; + atr_mode_d <= atr_mode; + classic_atr_select_d <= classic_atr_select; + end + + generate + for (i=0; i +// +// +// Describes the behavior of GPIO lines when controlled by the ATR state. +// +// +// +// Holds a single bit setting for GPIO lines in both ports for a particular ATR sate +// +// +// +// +// +// +// Describes GPIO behavior for the different ATR states. When @.ATR_OPTION +// is set to use the DB states, TX and RX states for RF0 and RF1 are +// combined to create a single vector. This creates 16 different +// combinations, each with its own register. When @.ATR_OPTION is set to +// classic ATR, offsets 0x00-0x03 in this register group will be driven +// in accordance with the state of RF0, and offsets 0x04-0x07 will be +// driven in accordance with the state of RF1. +// CLASSIC ATR MAPPING: Idle[RF0:0x00; RF1:0x04], RX[RF0:0x01; RF1:0x05], +// TX[RF0:0x02; RF1:0x06], FDX[RF0:0x03; RF1:0x07] +// +// +// +// +// Controls whether GPIO lines use the TX and RX state of an RF channel +// (Classic ATR) or the daughterboard state the selector for the +// @.GPIO_ATR_STATE. +// +// +// +// Sets the scheme in which RF states in the radio will control GPIO +// lines. 0 = DB state is used. RF states are combined and the +// GPIO state is driven based on all 16 @.GPIO_ATR_STATE registers. +// 1 = Each RF channel has its separate ATR state(Classic ATR). +// Use register @.CLASSIC_ATR_CONFIG to indicate the RF channel +// to which each GPIO line responds to. +// +// +// +// +// +// Controls the RF state mapping of each GPIO line when classic +// ATR mode is active. +// +// +// +// Set which RF channel's state to reflect in the pins for +// HDMI connector A when @.ATR_OPTION is set to classic ATR. +// Controlled in a per-pin basis. +// 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03) +// 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07) +// +// +// +// +// Set which RF channel's state to reflect in the pins of +// HDMI connector B when @.ATR_OPTION is set to classic ATR. +// Controlled in a per-pin basis. +// 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03) +// 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07) +// +// +// +// +// +// Controls the direction of each GPIO signal when controlled by the radio state. +// 0 = GPIO pin set to input. 1 = GPIO pin set to output +// +// +// +// +// +// +// Disable ATR Control. DB state 0 will be reflected regardless of the ATR state. +// +// +// +// +// +// +// Reflects the logic state of each GPIO input. +// +// +// +// +// +// +//XmlParse xml_off -- cgit v1.2.3