From 303ddf1238ef1d38fb8b25f7e97b2319475299c1 Mon Sep 17 00:00:00 2001 From: Javier Valenzuela Date: Tue, 14 Jun 2022 10:12:05 -0500 Subject: fpga: x400: zbx: Add support for XO3 CPLD variant. The main changes included are: - Variant-dependent pin-out instantiation. - Update clocking scheme in top level file to include XO3 PLL - Add ability to shift outgoing data for the GPIO communication interface with the X410 FPGA. - Include project files required to build the XO3 variant of the ZBX CPLD. - Add build flow for Lattice Diamond designs. - Add ability to build XO3 variant of ZBX CPLD. --- fpga/usrp3/top/x400/cpld/reconfig_engine.v | 9 +- .../top/x400/dboards/ctrlport_byte_deserializer.v | 91 ++- fpga/usrp3/top/x400/dboards/zbx/cpld/.gitignore | 8 + fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile | 51 +- .../x400/dboards/zbx/cpld/Makefile.zbx_cpld.inc | 5 + .../x400/dboards/zbx/cpld/doc/ZBX_CPLD_left.htm | 3 +- .../x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm | 154 +++- .../top/x400/dboards/zbx/cpld/lattice/build.tcl | 22 + .../x400/dboards/zbx/cpld/lattice/ip/pll/pll.ipx | 8 + .../x400/dboards/zbx/cpld/lattice/ip/pll/pll.lpc | 87 +++ .../top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.v | 100 +++ .../dboards/zbx/cpld/lattice/ip/pll/pll_tmpl.v | 7 + .../x400/dboards/zbx/cpld/lattice/zbx_top_cpld.ldf | 95 +++ .../x400/dboards/zbx/cpld/lattice/zbx_top_cpld.lpf | 803 +++++++++++++++++++++ .../x400/dboards/zbx/cpld/lattice/zbx_top_cpld.sty | 205 ++++++ .../zbx/cpld/register_endpoints/basic_regs.v | 29 +- .../zbx/cpld/register_endpoints/dsa_control.v | 22 +- .../zbx/cpld/register_endpoints/led_control.v | 11 +- .../zbx/cpld/register_endpoints/switch_control.v | 14 +- .../zbx/cpld/regmap/basic_regs_regmap_utils.vh | 15 +- .../usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.v | 133 +++- 21 files changed, 1788 insertions(+), 84 deletions(-) create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/build.tcl create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.ipx create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.lpc create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.v create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll_tmpl.v create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.ldf create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.lpf create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.sty (limited to 'fpga/usrp3/top/x400') diff --git a/fpga/usrp3/top/x400/cpld/reconfig_engine.v b/fpga/usrp3/top/x400/cpld/reconfig_engine.v index fc6a4837e..6674cc693 100644 --- a/fpga/usrp3/top/x400/cpld/reconfig_engine.v +++ b/fpga/usrp3/top/x400/cpld/reconfig_engine.v @@ -73,7 +73,7 @@ module reconfig_engine #( `include "regmap/reconfig_regmap_utils.vh" `include "../../../lib/rfnoc/core/ctrlport.vh" - // Check MAX10 variant target (10M04 or 10M08) + // Check MAX10 variant target (10M04, 10M08 or XO3) `ifdef VARIANT_10M04 localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT = FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04; localparam FLASH_PRIMARY_IMAGE_START_ADDR = FLASH_PRIMARY_IMAGE_START_ADDR_10M04; @@ -86,6 +86,13 @@ module reconfig_engine #( localparam FLASH_PRIMARY_IMAGE_END_ADDR = FLASH_PRIMARY_IMAGE_END_ADDR_10M08; localparam CFM0_WP_OFFSET_MSB = 27; // From Max 10 Flash Memory User Guide. localparam CFM0_WP_OFFSET_LSB = 25; // From Max 10 Flash Memory User Guide. + // The reconfiguration engine via flash is not supported in the XO3 variant. + `elsif VARIANT_XO3 + localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT = 0; + localparam FLASH_PRIMARY_IMAGE_START_ADDR = 0; + localparam FLASH_PRIMARY_IMAGE_END_ADDR = 0; + localparam CFM0_WP_OFFSET_MSB = 0; + localparam CFM0_WP_OFFSET_LSB = 0; `else ERROR_MAX10_variant_must_be_defined(); localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT = FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04; diff --git a/fpga/usrp3/top/x400/dboards/ctrlport_byte_deserializer.v b/fpga/usrp3/top/x400/dboards/ctrlport_byte_deserializer.v index b8fde0025..9e7e89c77 100644 --- a/fpga/usrp3/top/x400/dboards/ctrlport_byte_deserializer.v +++ b/fpga/usrp3/top/x400/dboards/ctrlport_byte_deserializer.v @@ -8,12 +8,18 @@ // Description: // Slave interface of CtrlPort interface serialized as byte stream. // See description in ctrlport_byte_serializer module for more details. +// Input and output data may be driven/registered using clocks with +// different phases (but same frequency), this allows the capability +// to facilitate meeting timing on this interface. // `default_nettype none module ctrlport_byte_deserializer ( + // clock domain used to register input data input wire ctrlport_clk, + // clock domain used to drive output data + input wire ctrlport_clk_adjusted, input wire ctrlport_rst, // Request @@ -58,17 +64,19 @@ module ctrlport_byte_deserializer ( localparam SENDING = 2'd3; // internal registers - reg [ 1:0] state = INIT_RX; - reg [NUM_BYTES_RX_WRITE*8-1:0] request_cache = {NUM_BYTES_RX_WRITE*8 {1'b0}}; - reg [ NUM_BYTES_TX_READ*8-1:0] response_cache = {NUM_BYTES_TX_READ*8 {1'b0}}; - reg [ 2:0] byte_counter = 3'b0; - reg transfer_complete = 1'b0; - reg write_transfer = 1'b0; + reg [ 1:0] state = INIT_RX; + reg [NUM_BYTES_RX_WRITE*8-1:0] request_cache = {NUM_BYTES_RX_WRITE*8 {1'b0}}; + reg [ NUM_BYTES_TX_READ*8-1:0] response_cache = {NUM_BYTES_TX_READ*8 {1'b0}}; + reg [ 2:0] request_byte_counter = 3'b0; + reg [ 2:0] response_byte_counter = 3'b0; + reg transfer_complete = 1'b0; + reg write_transfer = 1'b0; // input registers to relax input timing reg [7:0] bytestream_data_in_reg = 8'b0; reg bytestream_valid_in_reg = 1'b0; reg bytestream_direction_reg = 1'b0; + always @ (posedge ctrlport_clk) begin bytestream_data_in_reg <= bytestream_data_in; bytestream_valid_in_reg <= bytestream_valid_in; @@ -79,22 +87,19 @@ module ctrlport_byte_deserializer ( always @ (posedge ctrlport_clk) begin if (ctrlport_rst) begin state <= INIT_RX; - byte_counter <= 3'b0; + request_byte_counter <= 3'b0; transfer_complete <= 1'b0; - bytestream_output_enable <= 1'b0; + response_byte_counter <= 3'b0; end else begin // default assignments transfer_complete <= 1'b0; - // direction defined by master - bytestream_output_enable <= bytestream_direction; - bytestream_valid_out <= 1'b0; case (state) // additional cycle for switching to make sure valid signal is driven // from master when being in RECEIVE state INIT_RX: begin - byte_counter <= 3'b0; + request_byte_counter <= 3'b0; if (bytestream_direction_reg == 0) begin state <= RECEIVE; end @@ -103,17 +108,17 @@ module ctrlport_byte_deserializer ( // wait for reception of request from master RECEIVE: begin if (bytestream_valid_in_reg) begin - byte_counter <= byte_counter + 1'b1; + request_byte_counter <= request_byte_counter + 1'b1; request_cache <= {request_cache[NUM_BYTES_RX_WRITE*8-9:0], bytestream_data_in_reg}; // capture write or read - if (byte_counter == 0) begin + if (request_byte_counter == 0) begin write_transfer <= bytestream_data_in_reg[7]; end // wait until request completes - if ((write_transfer && byte_counter == NUM_BYTES_RX_WRITE-1) || - (~write_transfer && byte_counter == NUM_BYTES_RX_READ-1)) begin + if ((write_transfer && request_byte_counter == NUM_BYTES_RX_WRITE-1) || + (~write_transfer && request_byte_counter == NUM_BYTES_RX_READ-1)) begin transfer_complete <= 1'b1; state <= WAIT_RESPONSE; end @@ -127,15 +132,10 @@ module ctrlport_byte_deserializer ( end WAIT_RESPONSE: begin - byte_counter <= 3'b0; + request_byte_counter <= 3'b0; + response_byte_counter <= 3'b0; if (m_ctrlport_resp_ack) begin state <= SENDING; - - if (write_transfer) begin - response_cache <= {5'b0, 1'b1, m_ctrlport_resp_status, 32'b0}; - end else begin - response_cache <= {m_ctrlport_resp_data, 5'b0, 1'b1, m_ctrlport_resp_status}; - end end //abort by host @@ -145,14 +145,11 @@ module ctrlport_byte_deserializer ( end SENDING: begin - bytestream_valid_out <= 1'b1; - bytestream_data_out <= response_cache[NUM_BYTES_TX_READ*8-8+:8]; - response_cache <= {response_cache[NUM_BYTES_TX_READ*8-9:0], 8'b0}; - byte_counter <= byte_counter + 1'b1; + response_byte_counter <= response_byte_counter + 1'b1; // wait until request completes - if ((write_transfer && byte_counter == NUM_BYTES_TX_WRITE-1) || - (~write_transfer && byte_counter == NUM_BYTES_TX_READ-1)) begin + if ((write_transfer && response_byte_counter == NUM_BYTES_TX_WRITE-1) || + (~write_transfer && response_byte_counter == NUM_BYTES_TX_READ-1)) begin state <= INIT_RX; end @@ -169,6 +166,42 @@ module ctrlport_byte_deserializer ( end end + // Output data control + always @ (posedge ctrlport_clk_adjusted) begin + if (ctrlport_rst) begin + bytestream_valid_out <= 1'b0; + bytestream_output_enable <= 1'b0; + end else begin + + bytestream_valid_out <= 1'b0; + // direction defined by master + bytestream_output_enable <= bytestream_direction; + + case (state) + WAIT_RESPONSE: begin + + if (write_transfer) begin + response_cache <= {5'b0, 1'b1, m_ctrlport_resp_status, 32'b0}; + end else begin + response_cache <= {m_ctrlport_resp_data, 5'b0, 1'b1, m_ctrlport_resp_status}; + end + end + + SENDING: begin + + bytestream_valid_out <= 1'b1; + bytestream_data_out <= response_cache[NUM_BYTES_TX_READ*8-8+:8]; + response_cache <= {response_cache[NUM_BYTES_TX_READ*8-9:0], 8'b0}; + + end + + default: begin + // NOP + end + endcase + end + end + //---------------------------------------------------------- // assign request to ctrlport //---------------------------------------------------------- diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/.gitignore b/fpga/usrp3/top/x400/dboards/zbx/cpld/.gitignore index 9fd51d1a5..ce2981889 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/.gitignore +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/.gitignore @@ -5,3 +5,11 @@ doc/*.xml incremental_db/ output_files/ *.sopcinfo +# Ignore Diamond generated files. +lattice/impl1/ +lattice/zbx_*.dir/ +lattice/*_log.txt +lattice/*.xml +lattice/*.html +lattice/*.ini +lattice/*.recovery diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile b/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile index 2ab32fb11..5b13bdce3 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile @@ -12,16 +12,20 @@ ## make ## ##Output: -## build//usrp_zbx_cpld.pof: Bitstream to use with JTAG programmer -## build//usrp_zbx_cpld.svf: Bitstream to use with PS JTAG engine (background programming) -## build//usrp_zbx_cpld.rpd: Bitstream to use via reconfig engine -## build//usrp_zbx_cpld_isp_off.svf: Bitstream to use with JTAG test points (initial programming) +## build//usrp_zbx_cpld_10m04.pof: Bitstream to use with JTAG programmer +## build//usrp_zbx_cpld_10m04.svf: Bitstream to use with PS JTAG engine (background programming) +## build//usrp_zbx_cpld_10m04.rpd: Bitstream to use via reconfig engine +## build//usrp_zbx_cpld_10m04_isp_off.svf: Bitstream to use with JTAG test points (initial programming) +## build//usrp_zbx_cpld_xo3lf.jed: Bitstream to use with JTAG programmer +## build//usrp_zbx_cpld_xo3lf.svf: Bitstream to use with PS JTAG engine (background programming) # Definitions 10M04_ID = "10M04SAU324I7G" +XO3LF_ID = "LCMXO3LF-9400C" # Target specific variables ZBX_CPLD_10M04: DEFS = VARIANT_`echo $(10M04_ID) | cut -c1-5`=1 +ZBX_CPLD_XO3LF: IMPL = "impl1" # Using one of the files as a dependency (all files are generated at the same time) INIT_FILES := register_endpoints/memory_init_files/rx0_path_defaults.hex @@ -40,35 +44,56 @@ quartus_build = make -f Makefile.zbx_cpld.inc $(TARGET) NAME=$@ ARCH="MAX10" PAR # quartus_ip($1=Device, $2=Definitions) quartus_ip = make -f Makefile.zbx_cpld.inc quar_ip NAME=$@ ARCH="MAX10" PART_ID="$1" $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" -# post_build($1=Artifact Name) +# post_quar_build($1=Artifact Name) ifeq ($(TARGET),bin) - post_build = @\ + post_quar_build = @\ mkdir -p build/; \ echo "Exporting bitstream files..."; \ - cp build-$@/output_files/$(TOP).pof build/$(1).pof; \ - cp build-$@/output_files/$(TOP)_isp_off.svf build/$(1)_isp_off.svf; \ - cp build-$@/output_files/$(TOP)_isp_on.svf build/$(1).svf; \ - cp build-$@/output_files/$(TOP)_converted_cfm0_auto.rpd build/$(1).rpd; \ + cp build-$@/output_files/$(TOP).pof build/$(1)_10m04.pof; \ + cp build-$@/output_files/$(TOP)_isp_off.svf build/$(1)_10m04_isp_off.svf; \ + cp build-$@/output_files/$(TOP)_isp_on.svf build/$(1)_10m04.svf; \ + cp build-$@/output_files/$(TOP)_converted_cfm0_auto.rpd build/$(1)_10m04.rpd; \ echo -ne "\n\n---- Make: MB CPLD ready!\n"; \ echo -ne " Use build/$(1).pof via JTAG programmer or\n"; \ echo -ne " build/$(1).svf (ISP on) via PS JTAG-engine (background programming) or\n"; \ echo -ne " build/$(1).rpd via reconfig engine or\n"; \ echo -ne " build/$(1)_isp_off.svf via JTAG test points (initial programming)\n"; else - post_build = @echo "Skipping bitfile export." + post_quar_build = @echo "Skipping bitfile export." +endif + +# diamond_build($1=Device, $2=Implementation) +diamond_build = make -f Makefile.zbx_cpld.inc dmd_build NAME=$@ PART_ID="$1" IMPL=$2 TOP_MODULE=$(TOP) + +# post_dmd_build($1=Artifact Name, $2=Implementation Name) +ifeq ($(TARGET),bin) + post_dmd_build = @\ + mkdir -p build/; \ + echo "Exporting bitstream files..."; \ + cp build-$@/$(2)/$(TOP)_$(2).svf build/$(1)_xo3lf.svf; \ + echo -ne "\n\n---- Make: MB CPLD ready!\n"; \ + echo -ne " Use build/$(1)_xo3lf.svf via PS JTAG-engine \n"; +else + post_dmd_build = @echo "Skipping bitfile export." endif ## ##Supported Targets ##----------------- -all: ZBX_CPLD_10M04 ##(Default target) +all: ZBX_CPLD_10M04 ZBX_CPLD_XO3LF ##(Build all targets by default) ##ZBX_CPLD_10M04: ZBX CPLD targeted to 10M04SAU169I7G. ZBX_CPLD_10M04: $(INIT_FILES) $(call pre_build) $(call quartus_build,$(10M04_ID),$(DEFS)) - $(call post_build,"usrp_zbx_cpld") + $(call post_quar_build,"usrp_zbx_cpld") + +##ZBX_CPLD_XO3LF: ZBX CPLD targeted to LCMXO3LF-9400C. +ZBX_CPLD_XO3LF: $(INIT_FILES) + $(call pre_build) + $(call diamond_build,$(XO3LF_ID),$(IMPL)) + $(call post_dmd_build,"usrp_zbx_cpld",$(IMPL)) ZBX_CPLD_IP: ##Build IPs only, needed for simulation. @# Building only ZBX_CPLD_10M04 IP diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile.zbx_cpld.inc b/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile.zbx_cpld.inc index 7b47f61cd..6a5f1cb95 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile.zbx_cpld.inc +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile.zbx_cpld.inc @@ -20,6 +20,7 @@ PROJECT_DIR = $(abspath .) BASE_DIR = $(abspath ../../../../) IP_DIR = $(abspath ./ip) include $(BASE_DIR)/../tools/make/quartus_design_builder.mak +include $(BASE_DIR)/../tools/make/diamond_design_builder.mak # Include IP directory include $(IP_DIR)/Makefile.inc @@ -66,3 +67,7 @@ bin: .prereqs quar_ip: .prereqs ip @echo "IP Build DONE ..." + +dmd_build : .diamond_prereqs + $(call BUILD_DIAMOND_DESIGN,$(TOP_MODULE),$(PART_ID),$(PROJECT_DIR),$(BUILD_DIR),$(IMPL)) + diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_left.htm b/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_left.htm index be5ae68a8..565188740 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_left.htm +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_left.htm @@ -175,7 +175,8 @@

SLAVE_REVISION

SLAVE_OLDEST_REVISION

SLAVE_SCRATCH

-

GIT_HASH_REGISTER

+

GIT_HASH_REGISTER

+

SLAVE_VARIANT

diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm b/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm index fe82ee614..1310b5720 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm @@ -1471,6 +1471,32 @@ This enum is used to create the constants held in the basic registers in both ve + + + 5063000 + + 0x004D4158 + + +

VARIANT_ID_MAX10

+ + + + + + + + 5787443 + + 0x00584F33 + + +

VARIANT_ID_XO3

+ + + + + 537986577 @@ -1486,9 +1512,9 @@ This enum is used to create the constants held in the basic registers in both ve - 554767892 + 570627601 - 0x21111614 + 0x22031611

CPLD_REVISION

@@ -2143,6 +2169,130 @@ Git hash of commit used to build this image.
+ + +
+ + +

Offset 0x0014: SLAVE_VARIANT Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
Port GPIO
+ +		 + + + + +
GPIO_REGMAP|BASE_WINDOW_GPIO
  0x000000
+ +		 + + + + +
SLAVE_VARIANT
  offset=0x0014
+ +		 + + + + + +
+ + +Total Offset =
  0x000014 + +
+ +
+ + + +
Port SPI
+ +		 + + + + +
SPI_REGMAP|BASE_WINDOW_SPI
  0x000000
+ +		 + + + + + +
+ + +Total Offset =
  0x000014 + +
+ +

+ +

Initial Value = 0x00000000 +

+ +

This register is defined in HDL source file basic_regs.v.

+ +
+ +
+ +Contains information pertaining the variant of the programmable. + +
+ + + + + + + + + +
BitsName
31..0 +

VARIANT_REG   (initialvalue=0)

+

Returns the variant of the programmable based on the part vendor. + MAX10 variants return 0x583033(ASCII for MAX), while the XO3 variant + returns 0x584F33(ASCII for XO3)

+ +
+
diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/build.tcl b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/build.tcl new file mode 100644 index 000000000..b4b4d25d8 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/build.tcl @@ -0,0 +1,22 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# +# This file contains the sequence of steps required to +# build and generate outputs for the ZBX CPLD, XO3 variant. +# It is intended to be use as a parameter for +# pnmainc (Diamond TCL console). +# pnmainc.exe build.tcl > + +prj_project open "zbx_top_cpld.ldf" +prj_run Synthesis -impl impl1 +prj_run Translate -impl impl1 +prj_run Map -impl impl1 +prj_run PAR -impl impl1 +prj_run PAR -impl impl1 -task PARTrace +prj_run Export -impl impl1 -task Bitgen +prj_run Export -impl impl1 -task Jedecgen +prj_run Export -impl impl1 -task Jedec4Xo3l +prj_project close diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.ipx b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.ipx new file mode 100644 index 000000000..e1a58563e --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.lpc b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.lpc new file mode 100644 index 000000000..34390f519 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.lpc @@ -0,0 +1,87 @@ +[Device] +Family=machxo3lf +PartType=LCMXO3LF-9400C +PartName=LCMXO3LF-9400C-6BG256I +SpeedGrade=6 +Package=CABGA256 +OperatingCondition=IND +Status=S + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.8 +ModuleName=pll +SourceFormat=Verilog HDL +ParameterFileVersion=1.0 +Date=03/03/2022 +Time=14:15:48 + +[Parameters] +Verilog=1 +VHDL=0 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +mode=Frequency +CLKI=64 +CLKI_DIV=1 +BW=6.139 +VCO=512.000 +fb_mode=CLKOP +CLKFB_DIV=1 +FRACN_ENABLE=0 +FRACN_DIV=0 +DynamicPhase=STATIC +ClkEnable=1 +Standby=0 +Enable_sel=0 +PLLRst=0 +PLLMRst=0 +ClkOS2Rst=0 +ClkOS3Rst=0 +LockSig=1 +LockStk=0 +WBProt=0 +OPBypass=0 +OPUseDiv=0 +CLKOP_DIV=8 +FREQ_PIN_CLKOP=64 +OP_Tol=0.0 +CLKOP_AFREQ=64.000000 +CLKOP_PHASEADJ=0 +CLKOP_TRIM_POL=Rising +CLKOP_TRIM_DELAY=0 +EnCLKOS=1 +OSBypass=0 +OSUseDiv=0 +CLKOS_DIV=8 +FREQ_PIN_CLKOS=64 +OS_Tol=0.0 +CLKOS_AFREQ=64.000000 +CLKOS_PHASEADJ=225 +CLKOS_TRIM_POL=Rising +CLKOS_TRIM_DELAY=0 +EnCLKOS2=0 +OS2Bypass=0 +OS2UseDiv=0 +CLKOS2_DIV=1 +FREQ_PIN_CLKOS2=64 +OS2_Tol=0.0 +CLKOS2_AFREQ=64.000000 +CLKOS2_PHASEADJ=225 +EnCLKOS3=0 +OS3Bypass=0 +OS3UseDiv=0 +CLKOS3_DIV=1 +FREQ_PIN_CLKOS3=100 +OS3_Tol=0.0 +CLKOS3_AFREQ= +CLKOS3_PHASEADJ=0 + +[Command] +cmd_line= -w -n pll -lang verilog -synth synplify -arch xo3c00f -type pll -fin 64 -fclkop 64 -fclkop_tol 0.0 -fclkos 64 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 225 -trims_r -phase_cntl STATIC -enable_ports -fb_mode 1 -lock diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.v new file mode 100644 index 000000000..24f3fab22 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.v @@ -0,0 +1,100 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.0.240.2 */ +/* Module Version: 5.7 */ +/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang verilog -synth synplify -arch xo3c00f -type pll -fin 64 -fclkop 64 -fclkop_tol 0.0 -fclkos 64 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 225 -trims_r -phase_cntl STATIC -enable_ports -fb_mode 1 -lock */ +/* Thu Mar 03 14:15:48 2022 */ + + +`timescale 1 ns / 1 ps +module pll (CLKI, ENCLKOP, ENCLKOS, CLKOP, CLKOS, LOCK)/* synthesis NGD_DRC_MASK=1 */; + input wire CLKI; + input wire ENCLKOP; + input wire ENCLKOS; + output wire CLKOP; + output wire CLKOS; + output wire LOCK; + + wire CLKOS_t; + wire CLKOP_t; + wire scuba_vlo; + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.DDRST_ENA = "DISABLED" ; + defparam PLLInst_0.DCRST_ENA = "DISABLED" ; + defparam PLLInst_0.MRST_ENA = "DISABLED" ; + defparam PLLInst_0.PLLRST_ENA = "DISABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.PLL_USE_WB = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 0 ; + defparam PLLInst_0.CLKOS_FPHASE = 0 ; + defparam PLLInst_0.CLKOS_CPHASE = 12 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 7 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "RISING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "RISING" ; + defparam PLLInst_0.FRACN_DIV = 0 ; + defparam PLLInst_0.FRACN_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXD2 = "DIVD" ; + defparam PLLInst_0.PREDIVIDER_MUXD1 = 0 ; + defparam PLLInst_0.VCO_BYPASS_D0 = "DISABLED" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC2 = "DIVC" ; + defparam PLLInst_0.PREDIVIDER_MUXC1 = 0 ; + defparam PLLInst_0.VCO_BYPASS_C0 = "DISABLED" ; + defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB2 = "DIVB" ; + defparam PLLInst_0.PREDIVIDER_MUXB1 = 0 ; + defparam PLLInst_0.VCO_BYPASS_B0 = "DISABLED" ; + defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA2 = "DIVA" ; + defparam PLLInst_0.PREDIVIDER_MUXA1 = 0 ; + defparam PLLInst_0.VCO_BYPASS_A0 = "DISABLED" ; + defparam PLLInst_0.CLKOP_ENABLE = "DISABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 1 ; + defparam PLLInst_0.CLKOS_DIV = 8 ; + defparam PLLInst_0.CLKOP_DIV = 8 ; + defparam PLLInst_0.CLKFB_DIV = 1 ; + defparam PLLInst_0.CLKI_DIV = 1 ; + defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ; + EHXPLLJ PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .LOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(scuba_vlo), .RESETM(scuba_vlo), .RESETC(scuba_vlo), .RESETD(scuba_vlo), + .ENCLKOP(ENCLKOP), .ENCLKOS(ENCLKOS), .ENCLKOS2(scuba_vlo), .ENCLKOS3(scuba_vlo), + .PLLCLK(scuba_vlo), .PLLRST(scuba_vlo), .PLLSTB(scuba_vlo), .PLLWE(scuba_vlo), + .PLLADDR4(scuba_vlo), .PLLADDR3(scuba_vlo), .PLLADDR2(scuba_vlo), + .PLLADDR1(scuba_vlo), .PLLADDR0(scuba_vlo), .PLLDATI7(scuba_vlo), + .PLLDATI6(scuba_vlo), .PLLDATI5(scuba_vlo), .PLLDATI4(scuba_vlo), + .PLLDATI3(scuba_vlo), .PLLDATI2(scuba_vlo), .PLLDATI1(scuba_vlo), + .PLLDATI0(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(), + .CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(), .CLKINTFB(), .DPHSRC(), + .PLLACK(), .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(), + .PLLDATO2(), .PLLDATO1(), .PLLDATO0()) + /* synthesis FREQUENCY_PIN_CLKOS="64.000000" */ + /* synthesis FREQUENCY_PIN_CLKOP="64.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="64.000000" */ + /* synthesis ICP_CURRENT="9" */ + /* synthesis LPF_RESISTOR="72" */; + + assign CLKOS = CLKOS_t; + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 64.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 64.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 64.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 9 + // exemplar attribute PLLInst_0 LPF_RESISTOR 72 + // exemplar end + +endmodule diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll_tmpl.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll_tmpl.v new file mode 100644 index 000000000..6828b621b --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/ip/pll/pll_tmpl.v @@ -0,0 +1,7 @@ +/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.0.240.2 */ +/* Module Version: 5.7 */ +/* Thu Mar 03 14:15:48 2022 */ + +/* parameterized module instance */ +pll __ (.CLKI( ), .ENCLKOP( ), .ENCLKOS( ), .CLKOP( ), .CLKOS( ), + .LOCK( )); diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.ldf b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.ldf new file mode 100644 index 000000000..d1848e71e --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.ldf @@ -0,0 +1,95 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.lpf b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.lpf new file mode 100644 index 000000000..e41c58541 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.lpf @@ -0,0 +1,803 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# This file follows the Lattice Preference File style to describe +# timing constraints for a Lattice Diamond Synplify build flow. +# +##### GENERAL TIMING DISCLAIMER ######## + +# Multiple constraints within this file use constant numbers to describe their +# respective input and output delays. The values presented were generated by +# evaluating constraints described for the MAX10 variant of this CPLD. +# Additional considerations were used when a constraint could not be written +# in the same way for both variants(such as in additional delays present in +# the datapath or data being generated on falling edges). In such cases, +# additional comments describing the origin of the value used are provided. +# The original constraints used to compute the values used in this file are +# located at: +# ../quartus/zbx_top_cpld.qsf + +###################################################################################### +# Timing +###################################################################################### +# base clocks +@define $prc_clock_period 15.625 ; +@define $ctrl_sclk_period $prc_clock_period * 3.0 ; + +PERIOD PORT "CPLD_REFCLK" $prc_clock_period ; +PERIOD PORT "MB_CTRL_SCK" $ctrl_sclk_period ; +FREQUENCY NET "clk_int_osc" 66.500000 MHz ; + +############# MB GPIO ################## + +# OUTPUT PATH +# -------------------------------------------------------------------------------------- +# P&R fails when using delay values from original design. To make it easier for +# timing to be met, this interface uses an adjusted version of the clock, shifted +# by 225 degrees. Unfortunately, the use of a shifted clock result in the analysis +# of this input path to be incorrect +# The following diagram represents the timing for the GPIO communication interface +# considering data generated on a shifted clock. +# +# *Launch Edge(according to Diamond) +# | +# | * Latch edge(according to Diamond) +# | | +# | | * Actual Latch Edge. +# | | | +# ref_clk __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\ +# Max Output Delay _____________XXXXXXXX__________________________________________ +# Min Output Delay ________XXX____________________________________________________ +# shifted clk ----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\____ +# | +# | +# * Data gets generated by shifted clock +# A potential solution for this would be to use multi-cycle path constraints to +# shift the analysis to the actual latch edge. This is not supported in Diamond, +# as output delay constraints are incompatible with multi-cycle constraints. +# +# After contacting Lattice, it was determined that the best solution was to compensate +# the delay that would be inserted by a multi-cycle constraint in the output delay +# constraint(effectively analyzing the timing from the detected to the actual +# latch edge). +# An advantage of this implementation is the ability to consider the worst-case clock +# frequency for the different scenarios analyzed. + +# Maximum path delay = 8.5 ns +# Minimum path delay = -2 ns +# To shift timing analysis to the correct edges, the timing windows is shifted by +# one clock cycle, which is performed by subtracting a prc_clock period from +# the original path delays. +@define $gpio_max_output_delay 8.5 - $prc_clock_period ; +@define $gpio_min_output_delay -2.0 - $prc_clock_period ; + +# This analysis results in the following constraint. +CLOCK_TO_OUT PORT "MB_FPGA_GPIO*" OUTPUT_DELAY $gpio_max_output_delay ns + MIN $gpio_min_output_delay ns + CLKPORT "CPLD_REFCLK" ; + +# INPUT PATH +# -------------------------------------------------------------------------------------- +# This path uses prc_clk with no phase alterations. +# The input path for GPIO lanes is driven in the falling edge of the clock, and some correction +# is performed for this adjustment. +# +# *Launch Edge(according to Diamond) +# | +# | * Actual Launch Edge +# | | +# | | * Actual Latch Edge. +# | | | +# ref_clk __/-----------\___________/-----------\___________/-----------\___________/------ +# Max Delay ______________XXXXX______________________________________________________________ +# Min Delay ______________XXX________________________________________________________________ + + +# Maximum path delay = 4.561 +# Minimum path delay = 4.045 +# To adjust the analysis to the correct launch edge, we increase the input delays by +# half a prc_clock period. The CLK_OFFSET option is not used as it only changes +# the analysis on the receiving flop. +@define $gpio_max_input_delay $prc_clock_period / 2.0 + 4.561 ; +@define $gpio_min_input_delay $prc_clock_period / 2.0 + 4.045 ; +# Invert value for hold constraint +@define $gpio_min_input_hold -1.0 * $gpio_min_input_delay ; + +# The adjusted values are used in the input constraint. +INPUT_SETUP PORT "MB_FPGA_GPIO*" INPUT_DELAY $gpio_max_input_delay ns + HOLD $gpio_min_input_hold ns + CLKPORT "CPLD_REFCLK" ; + +############# LO SYNC ################## +INPUT_SETUP PORT MB_SYNTH_SYNC INPUT_DELAY 6.747 HOLD -5.860 ns CLKPORT "CPLD_REFCLK" ; + +DEFINE PORT GROUP "LO_SYNC" + "RX0_LO*_SYNC" + "RX1_LO*_SYNC" + "TX0_LO*_SYNC" + "TX1_LO*_SYNC" ; + +CLOCK_TO_OUT GROUP LO_SYNC OUTPUT_DELAY 2.445 MIN 2.145 ns CLKPORT "CPLD_REFCLK" ; + +##################################################################### +# Timing exceptions +##################################################################### +## synchronizers +BLOCK PATH FROM PORT "CTRL_REG_ARST" TO CELL "*synchronizer_false_path*value_0*" ; + +##################################################################### +# Asynchronous IO +##################################################################### +# For general I/O that don't have tight timing constraints, we can constrain +# these paths by creating a generic flip-flop that will interface to the +# device. +# For asynchronous outputs +@define $generic_ext_flop_tsu 1 ; +@define $generic_ext_flop_th 0 ; + +# # For asynchronous inputs +@define $generic_ext_flop_max_tco 1 ; +@define $generic_ext_flop_min_tco 1 ; + +# REF CLK +#-------------------------------------------------------------------- +DEFINE PORT GROUP "ASYNC_REFCLK_OUTPUTS" + "CH*_*X*_LED" + "RX*_DSA*_*[*]" + "TX*_DSA*[*]" + "*X*_SW*" ; + +CLOCK_TO_OUT GROUP ASYNC_REFCLK_OUTPUTS OUTPUT_DELAY $generic_ext_flop_tsu ns + MIN $generic_ext_flop_th ns + CLKPORT "CPLD_REFCLK" ; + + +DEFINE PORT GROUP "ASYNC_REFCLK_INPUTS" + "CTRL_REG_ARST" ; + +INPUT_SETUP GROUP ASYNC_REFCLK_INPUTS INPUT_DELAY $generic_ext_flop_max_tco ns + HOLD $generic_ext_flop_min_tco ns + CLKPORT "CPLD_REFCLK" ; + +# INT OSC +#-------------------------------------------------------------------- +DEFINE PORT GROUP "ASYNC_INTOSC_OUTPUTS" + "P*_ENABLE*" ; + +CLOCK_TO_OUT GROUP ASYNC_INTOSC_OUTPUTS OUTPUT_DELAY $generic_ext_flop_tsu ns + MIN $generic_ext_flop_th ns + CLKNET "clk_int_osc" ; +DEFINE PORT GROUP "ASYNC_INTOSC_INPUTS" + "P7V_PG_*" ; + +INPUT_SETUP GROUP ASYNC_INTOSC_INPUTS INPUT_DELAY $generic_ext_flop_max_tco ns + HOLD $generic_ext_flop_min_tco ns + CLKNET "clk_int_osc" ; + + +##################################################################### +# MB CPLD <-> DB CPLD CTRL SPI interface +##################################################################### +# The timing constants of the MB CPLD are defined in +# fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc + +@define $ctrl_spi_input_max_delay -2.014 ; +@define $ctrl_spi_input_min_delay -4.500 ; + +DEFINE PORT GROUP "CTRL_SLAVE_INPUTS" + "MB_CTRL_MOSI" + "MB_CTRL_CS" ; + +INPUT_SETUP GROUP CTRL_SLAVE_INPUTS INPUT_DELAY $ctrl_spi_input_max_delay ns + HOLD $ctrl_spi_input_min_delay ns + CLKPORT "MB_CTRL_SCK" + SS ; + +@define $ctrl_spi_output_max_delay 17.254 ; +@define $ctrl_spi_output_min_delay -0.500 ; + +DEFINE PORT GROUP "CTRL_SLAVE_OUTPUTS" + "MB_CTRL_MISO" ; + +CLOCK_TO_OUT GROUP CTRL_SLAVE_OUTPUTS OUTPUT_DELAY $ctrl_spi_output_max_delay ns + MIN $ctrl_spi_output_min_delay ns + CLKPORT "MB_CTRL_SCK" ; + + +# Additionally, Lattice detects an unconstrained path from MB_CTRL_CS +# to clk_int_osc. Since MB_CTRL_CS is asynchronous to that clock net, +# we use the same constraint strategy as for other asynchronous +# inputs. +INPUT_SETUP PORT "MB_CTRL_CS" INPUT_DELAY $generic_ext_flop_max_tco ns + HOLD $generic_ext_flop_min_tco ns + CLKNET "clk_int_osc" ; + +##################################################################### +# LO SPI interface +##################################################################### + +PERIOD PORT "TX0_LO1_SCK" $prc_clock_period ; +PERIOD PORT "RX0_LO1_SCK" $prc_clock_period ; +PERIOD PORT "TX0_LO2_SCK" $prc_clock_period ; +PERIOD PORT "RX0_LO2_SCK" $prc_clock_period ; +PERIOD PORT "TX1_LO1_SCK" $prc_clock_period ; +PERIOD PORT "RX1_LO1_SCK" $prc_clock_period ; +PERIOD PORT "TX1_LO2_SCK" $prc_clock_period ; +PERIOD PORT "RX1_LO2_SCK" $prc_clock_period ; + +DEFINE PORT GROUP "LO_SPI_CLKS" + "*X*_LO*_SCK" ; +DEFINE PORT GROUP "LO_SPI_TX0_LO1_OUTPUT_PORTS" + "RX_TX_LO_SDI" + "TX0_LO1_CSB" ; +DEFINE PORT GROUP "LO_SPI_TX0_LO2_OUTPUT_PORTS" + "RX_TX_LO_SDI" + "TX0_LO2_CSB" ; +DEFINE PORT GROUP "LO_SPI_TX1_LO1_OUTPUT_PORTS" + "RX_TX_LO_SDI" + "TX1_LO1_CSB" ; +DEFINE PORT GROUP "LO_SPI_TX1_LO2_OUTPUT_PORTS" + "RX_TX_LO_SDI" + "TX1_LO2_CSB" ; +DEFINE PORT GROUP "LO_SPI_RX0_LO1_OUTPUT_PORTS" + "RX_TX_LO_SDI" + "RX0_LO1_CSB" ; +DEFINE PORT GROUP "LO_SPI_RX0_LO2_OUTPUT_PORTS" + "RX_TX_LO_SDI" + "RX0_LO2_CSB" ; +DEFINE PORT GROUP "LO_SPI_RX1_LO1_OUTPUT_PORTS" + "RX_TX_LO_SDI" + "RX1_LO1_CSB" ; +DEFINE PORT GROUP "LO_SPI_RX1_LO2_OUTPUT_PORTS" + "RX_TX_LO_SDI" + "RX1_LO2_CSB" ; +DEFINE PORT GROUP "LO_SPI_INPUT_PORTS" + "*X*_LO*_MUXOUT" ; + +# -- Multi-cycle path for SPI CS and SDI -- +# ---------------------------------------- +# edge # 1 2 3 4 5 +# clk50 __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-- +# sclk __/-----------------------\_______________________/-------------- +# | launch edge (due to negedge reg) +# | | | +# 0 1 2 -- Edge used for setup analysis +# +# | | | +# 3 2 1 +# | | +# | \____ Edge used for hold +# | +# \____ Actual hold edge +# + + +# Maximum path delay = 13 ns + +# To shift timing analysis to the correct edges, the timing windows is shifted by +# one clock cycle, which is performed by subtracting a prc_clock period from +# the original path delays. +@define $lo_spi_output_max_delay 13.0 - $prc_clock_period ; + +# Minimum path delay = -13 ns +# This constraint can be left unmodified, this will result in a more conservative constraint +# (using edge #2 instead of edge #1 for timing analysis). The main reason for this +# over-constraining is that edge#1 requires making the minimum delay a positive number, +# higher than the maximum delay. The current state of this constraint still +# guarantees that data is held stable during the hold period. +@define $lo_spi_output_min_delay -13.000 ; + +CLOCK_TO_OUT GROUP LO_SPI_TX0_LO1_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns + MIN $lo_spi_output_min_delay ns + CLKPORT "CPLD_REFCLK" + CLKOUT PORT "TX0_LO1_SCK" ; + +CLOCK_TO_OUT GROUP LO_SPI_TX0_LO2_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns + MIN $lo_spi_output_min_delay ns + CLKPORT "CPLD_REFCLK" + CLKOUT PORT "TX0_LO2_SCK" ; + +CLOCK_TO_OUT GROUP LO_SPI_TX1_LO1_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns + MIN $lo_spi_output_min_delay ns + CLKPORT "CPLD_REFCLK" + CLKOUT PORT "TX1_LO1_SCK" ; + +CLOCK_TO_OUT GROUP LO_SPI_TX1_LO2_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns + MIN $lo_spi_output_min_delay ns + CLKPORT "CPLD_REFCLK" + CLKOUT PORT "TX1_LO2_SCK" ; + +CLOCK_TO_OUT GROUP LO_SPI_RX0_LO1_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns + MIN $lo_spi_output_min_delay ns + CLKPORT "CPLD_REFCLK" + CLKOUT PORT "RX0_LO1_SCK" ; + +CLOCK_TO_OUT GROUP LO_SPI_RX0_LO2_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns + MIN $lo_spi_output_min_delay ns + CLKPORT "CPLD_REFCLK" + CLKOUT PORT "RX0_LO2_SCK" ; + +CLOCK_TO_OUT GROUP LO_SPI_RX1_LO1_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns + MIN $lo_spi_output_min_delay ns + CLKPORT "CPLD_REFCLK" + CLKOUT PORT "RX1_LO1_SCK" ; + +CLOCK_TO_OUT GROUP LO_SPI_RX1_LO2_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns + MIN $lo_spi_output_min_delay ns + CLKPORT "CPLD_REFCLK" + CLKOUT PORT "RX1_LO2_SCK" ; + +# -- Multi-cycle path for SPI MUXOUT -- +# ---------------------------------------- +# edge # 1 2 3 4 5 6 7 8 +# clk50 __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-- +# sclk __/-----------------------\_______________________/-----------------------\_______________________/-- +# muxout MSB | MSB-1 +# launch edge | +# | | | +# 0 1 2 +# \_ Edge used for setup analysis +# | | | +# 3 2 1 +# | +# \____ Edge used for hold = 3 +# + +# Maximum path delay = 16 ns +# Setup analysis can be shifted from edge #4 to edge #5 by +# subtracting a clock period from the maximum delay. +@define $lo_spi_input_max_delay 16.000 - $prc_clock_period ; + +# For hold analysis, we conservatively set the minimum delay of the +# MUXOUT path to 0. +@define $lo_spi_input_min_delay 0.000 ; + +INPUT_SETUP GROUP LO_SPI_INPUT_PORTS INPUT_DELAY $lo_spi_input_max_delay ns + HOLD $lo_spi_input_min_delay ns + CLKPORT "CPLD_REFCLK"; + +# Add very loose timing requirements for clocks +CLOCK_TO_OUT GROUP LO_SPI_CLKS OUTPUT_DELAY $generic_ext_flop_tsu ns + MIN $generic_ext_flop_th ns + CLKPORT "CPLD_REFCLK" ; + +##################################################################### +# Clock Shift paths +##################################################################### +# pll_ref_clk_adjusted flip-flops will show hold violations from pll_ref_clk signals +# as Diamond fails to recognize the proper edges to use for the timing analysis. +# A multi-cycle constraint is used to analyze against the previous ref_clk cycle. +# +# *Launch Edge(with adjustments) +# | +# | * Launch edge(according to Diamond) +# | | +# | | +# ref_clk __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\ +# shifted clk ----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\____ +# | +# | +# Capture edge + +MULTICYCLE FROM CLKNET "pll_ref_clk" TO CLKNET "pll_ref_clk_adjusted" 0 X; + + +###################################################################################### +# Pin Location Information +###################################################################################### +LOCATE COMP "TX0_SW3_B" SITE "B1" ; +LOCATE COMP "MB_FPGA_GPIO[1]" SITE "D3" ; +LOCATE COMP "MB_CTRL_CS" SITE "D1" ; +LOCATE COMP "MB_CTRL_MOSI" SITE "E2" ; +LOCATE COMP "MB_FPGA_GPIO[12]" SITE "E3" ; +LOCATE COMP "MB_FPGA_GPIO[9]" SITE "C1" ; +LOCATE COMP "MB_FPGA_GPIO[10]" SITE "D2" ; +LOCATE COMP "MB_CTRL_SCK" SITE "E1" ; +LOCATE COMP "MB_FPGA_GPIO[13]" SITE "F2" ; +LOCATE COMP "MB_FPGA_GPIO[2]" SITE "F4" ; +LOCATE COMP "MB_FPGA_GPIO[0]" SITE "G6" ; +LOCATE COMP "MB_FPGA_GPIO[5]" SITE "F3" ; +LOCATE COMP "MB_FPGA_GPIO[6]" SITE "F1" ; +LOCATE COMP "MB_FPGA_GPIO[4]" SITE "G5" ; +LOCATE COMP "MB_CTRL_MISO" SITE "G4" ; +LOCATE COMP "MB_FPGA_GPIO[8]" SITE "G2" ; +LOCATE COMP "MB_FPGA_GPIO[7]" SITE "G3" ; +LOCATE COMP "MB_FPGA_GPIO[11]" SITE "F5" ; +LOCATE COMP "MB_FPGA_GPIO[3]" SITE "H6" ; +LOCATE COMP "TX1_SW3_A" SITE "G1" ; +LOCATE COMP "TX0_SW6_A" SITE "H2" ; +LOCATE COMP "TX0_SW4_B" SITE "H4" ; +LOCATE COMP "TX1_SW3_B" SITE "H3" ; +LOCATE COMP "TX0_SW6_B" SITE "J6" ; +LOCATE COMP "TX1_SW6_B" SITE "H1" ; +LOCATE COMP "MB_SYNTH_SYNC" SITE "J1" ; +LOCATE COMP "TX1_SW6_A" SITE "J3" ; +LOCATE COMP "TX0_SW4_A" SITE "J2" ; +LOCATE COMP "TX0_SW3_A" SITE "H5" ; +LOCATE COMP "TX1_SW4_B" SITE "K1" ; +LOCATE COMP "TX1_SW4_A" SITE "J4" ; +LOCATE COMP "TX0_SW5_B" SITE "K3" ; +LOCATE COMP "CTRL_REG_ARST" SITE "K2" ; +LOCATE COMP "TX0_SW5_A" SITE "J5" ; +LOCATE COMP "RX1_SW11_V3" SITE "L1" ; +LOCATE COMP "RX0_DSA1_n[3]" SITE "L3" ; +LOCATE COMP "RX0_SW11_V3" SITE "K4" ; +LOCATE COMP "RX0_DSA1_n[1]" SITE "L5" ; +LOCATE COMP "RX0_DSA1_n[2]" SITE "L2" ; +LOCATE COMP "TX1_SW5_B" SITE "M1" ; +LOCATE COMP "CH1_TX_LED" SITE "K5" ; +LOCATE COMP "TX1_DSA2[2]" SITE "L4" ; +LOCATE COMP "RX1_DSA2_n[4]" SITE "N2" ; +LOCATE COMP "RX1_DSA3_B_n[4]" SITE "P1" ; +LOCATE COMP "RX0_SW5_A" SITE "M3" ; +LOCATE COMP "TX1_SW5_A" SITE "N1" ; +LOCATE COMP "RX0_DSA1_n[4]" SITE "M2" ; +LOCATE COMP "RX1_DSA2_n[3]" SITE "N3" ; +LOCATE COMP "RX0_DSA3_B_n[1]" SITE "R1" ; +LOCATE COMP "RX0_DSA2_n[1]" SITE "P2" ; +LOCATE COMP "RX0_DSA2_n[3]" SITE "P4" ; +LOCATE COMP "RX0_DSA3_B_n[3]" SITE "T4" ; +LOCATE COMP "RX1_DSA3_B_n[3]" SITE "T2" ; +LOCATE COMP "RX0_DSA3_B_n[2]" SITE "R3" ; +LOCATE COMP "RX0_DSA2_n[4]" SITE "R5" ; +LOCATE COMP "RX1_DSA1_n[3]" SITE "P5" ; +LOCATE COMP "RX1_DSA3_B_n[2]" SITE "T3" ; +LOCATE COMP "RX1_DSA3_B_n[1]" SITE "R4" ; +LOCATE COMP "RX0_DSA3_B_n[4]" SITE "T5" ; +LOCATE COMP "TX0_SW10_A" SITE "R6" ; +LOCATE COMP "RX1_DSA2_n[1]" SITE "P6" ; +LOCATE COMP "TX0_SW10_B" SITE "T6" ; +LOCATE COMP "RX1_DSA1_n[2]" SITE "N6" ; +LOCATE COMP "RX1_SW4_A" SITE "L7" ; +LOCATE COMP "RX0_SW1_A" SITE "R7" ; +LOCATE COMP "RX0_SW2_A" SITE "P7" ; +LOCATE COMP "RX1_SW5_B" SITE "M7" ; +LOCATE COMP "RX0_DSA2_n[2]" SITE "N7" ; +LOCATE COMP "RX0_SW5_B" SITE "M6" ; +LOCATE COMP "CH1_RX_LED" SITE "L8" ; +LOCATE COMP "RX0_SW1_B" SITE "T7" ; +LOCATE COMP "RX1_SW6_A" SITE "R8" ; +LOCATE COMP "RX1_SW2_A" SITE "P8" ; +LOCATE COMP "RX1_SW6_B" SITE "T8" ; +LOCATE COMP "RX1_DSA1_n[1]" SITE "N8" ; +LOCATE COMP "TX1_DSA2[5]" SITE "L9" ; +LOCATE COMP "RX1_DSA2_n[2]" SITE "M8" ; +LOCATE COMP "RX0_SW11_V1" SITE "N9" ; +LOCATE COMP "RX0_SW6_B" SITE "T9" ; +LOCATE COMP "RX1_SW11_V2" SITE "P9" ; +LOCATE COMP "RX1_SW3_V1" SITE "R9" ; +LOCATE COMP "RX0_SW6_A" SITE "T10" ; +LOCATE COMP "RX1_DSA1_n[4]" SITE "M9" ; +LOCATE COMP "RX1_SW5_A" SITE "L10" ; +LOCATE COMP "RX0_SW10_V1" SITE "P10" ; +LOCATE COMP "RX0_SW3_V3" SITE "R10" ; +LOCATE COMP "RX1_SW10_V1" SITE "N10" ; +LOCATE COMP "RX0_DSA3_A_n[1]" SITE "M11" ; +LOCATE COMP "TX0_SW11_B" SITE "T11" ; +LOCATE COMP "RX1_LO2_MUXOUT" SITE "P11" ; +LOCATE COMP "CH0_RX2_LED" SITE "M10" ; +LOCATE COMP "CH0_TX_LED" SITE "N11" ; +LOCATE COMP "RX0_LO1_MUXOUT" SITE "R13" ; +LOCATE COMP "RX1_SW3_V2" SITE "T14" ; +LOCATE COMP "CH0_RX_LED" SITE "R11" ; +LOCATE COMP "TX0_SW11_A" SITE "T12" ; +LOCATE COMP "RX0_LO2_MUXOUT" SITE "P12" ; +LOCATE COMP "RX0_SW3_V1" SITE "T13" ; +LOCATE COMP "RX1_SW11_V1" SITE "T15" ; +LOCATE COMP "RX1_SW3_V3" SITE "R14" ; +LOCATE COMP "RX0_SW11_V2" SITE "R16" ; +LOCATE COMP "RX0_DSA3_A_n[2]" SITE "P15" ; +LOCATE COMP "RX0_SW9_V1" SITE "N14" ; +LOCATE COMP "P7V_PG_A" SITE "N16" ; +LOCATE COMP "P7V_ENABLE_B" SITE "P16" ; +LOCATE COMP "P7V_ENABLE_A" SITE "M15" ; +LOCATE COMP "P3D3VA_ENABLE" SITE "N15" ; +LOCATE COMP "RX1_LO1_MUXOUT" SITE "M14" ; +LOCATE COMP "RX1_SW9_V1" SITE "L13" ; +LOCATE COMP "P7V_PG_B" SITE "M16" ; +LOCATE COMP "RX0_SW4_A" SITE "K11" ; +LOCATE COMP "RX0_DSA3_A_n[4]" SITE "L15" ; +LOCATE COMP "RX1_DSA3_A_n[1]" SITE "K12" ; +LOCATE COMP "RX0_DSA3_A_n[3]" SITE "L14" ; +LOCATE COMP "RX1_DSA3_A_n[2]" SITE "K13" ; +LOCATE COMP "RX1_LO2_SYNC" SITE "L16" ; +LOCATE COMP "RX0_SW3_V2" SITE "L12" ; +LOCATE COMP "RX1_LO2_SCK" SITE "K15" ; +LOCATE COMP "RX0_LO2_CSB" SITE "J11" ; +LOCATE COMP "RX1_DSA3_A_n[3]" SITE "K14" ; +LOCATE COMP "RX1_DSA3_A_n[4]" SITE "J13" ; +LOCATE COMP "RX0_LO2_SYNC" SITE "K16" ; +LOCATE COMP "TX1_LO1_CSB" SITE "H11" ; +LOCATE COMP "RX1_LO1_SCK" SITE "J15" ; +LOCATE COMP "TX1_LO2_SYNC" SITE "J14" ; +LOCATE COMP "RX0_LO1_SCK" SITE "J16" ; +LOCATE COMP "RX1_LO1_SYNC" SITE "H16" ; +LOCATE COMP "RX0_LO2_SCK" SITE "J12" ; +LOCATE COMP "CPLD_REFCLK" SITE "H14" ; +LOCATE COMP "RX1_LO2_CSB" SITE "H13" ; +LOCATE COMP "RX0_LO1_SYNC" SITE "H15" ; +LOCATE COMP "RX0_LO1_CSB" SITE "G16" ; +LOCATE COMP "TX0_LO1_SCK" SITE "H12" ; +LOCATE COMP "TX1_LO2_SCK" SITE "G14" ; +LOCATE COMP "TX1_DSA2[4]" SITE "G11" ; +LOCATE COMP "TX0_LO2_SCK" SITE "G15" ; +LOCATE COMP "RX1_LO1_CSB" SITE "G13" ; +LOCATE COMP "TX0_LO2_CSB" SITE "F16" ; +LOCATE COMP "RX1_SW7_SW8_CTRL" SITE "F12" ; +LOCATE COMP "TX0_LO1_SYNC" SITE "F14" ; +LOCATE COMP "TX0_LO2_MUXOUT" SITE "G12" ; +LOCATE COMP "RX_TX_LO_SDI" SITE "F15" ; +LOCATE COMP "TX0_DSA1[3]" SITE "F13" ; +LOCATE COMP "TX1_LO2_CSB" SITE "E16" ; +LOCATE COMP "TX0_DSA1[6]" SITE "D15" ; +LOCATE COMP "TX1_LO1_SYNC" SITE "C16" ; +LOCATE COMP "TX1_LO1_SCK" SITE "E14" ; +LOCATE COMP "TX0_LO1_CSB" SITE "D16" ; +LOCATE COMP "TX1_DSA1[4]" SITE "B16" ; +LOCATE COMP "TX0_LO2_SYNC" SITE "E15" ; +LOCATE COMP "TX1_SW1_SW2_CTRL" SITE "C15" ; +LOCATE COMP "TX1_DSA1[3]" SITE "D14" ; +LOCATE COMP "TX1_DSA1[5]" SITE "A15" ; +LOCATE COMP "TX1_DSA1[6]" SITE "B14" ; +LOCATE COMP "TX1_LO2_MUXOUT" SITE "B12" ; +LOCATE COMP "TX1_DSA1[2]" SITE "C12" ; +LOCATE COMP "TX0_DSA1[4]" SITE "A14" ; +LOCATE COMP "TX0_DSA1[5]" SITE "B13" ; +LOCATE COMP "TX0_SW1_SW2_CTRL" SITE "A12" ; +LOCATE COMP "TX0_SW14_V1" SITE "B11" ; +LOCATE COMP "RX0_SW7_SW8_CTRL" SITE "D11" ; +LOCATE COMP "TX0_DSA1[2]" SITE "C11" ; +LOCATE COMP "TX1_DSA2[3]" SITE "F10" ; +LOCATE COMP "CH1_RX2_LED" SITE "A11" ; +LOCATE COMP "TX0_DSA2[5]" SITE "E10" ; +LOCATE COMP "TX1_LO1_MUXOUT" SITE "D10" ; +LOCATE COMP "TX0_SW13_V1" SITE "E11" ; +LOCATE COMP "TX1_DSA2[6]" SITE "F9" ; +LOCATE COMP "TX1_SW13_V1" SITE "A10" ; +LOCATE COMP "TX1_SW14_V1" SITE "B9" ; +LOCATE COMP "TX0_SW8_V1" SITE "D9" ; +LOCATE COMP "TX1_SW8_V1" SITE "C9" ; +LOCATE COMP "TX1_SW10_A" SITE "F8" ; +LOCATE COMP "TX0_LO1_MUXOUT" SITE "A9" ; +LOCATE COMP "RX1_SW1_B" SITE "E9" ; +LOCATE COMP "TX1_SW8_V2" SITE "D8" ; +LOCATE COMP "TX1_SW8_V3" SITE "A8" ; +LOCATE COMP "TX0_SW8_V2" SITE "C8" ; +LOCATE COMP "RX1_SW1_A" SITE "E8" ; +LOCATE COMP "TX1_SW11_B" SITE "F7" ; +LOCATE COMP "TX1_SW11_A" SITE "D7" ; +LOCATE COMP "TX0_DSA2[3]" SITE "C7" ; +LOCATE COMP "TX0_SW7_B" SITE "E6" ; +LOCATE COMP "TX1_SW9_B" SITE "B7" ; +LOCATE COMP "TX1_SW10_B" SITE "E7" ; +LOCATE COMP "TX0_DSA2[4]" SITE "D6" ; +LOCATE COMP "TX0_DSA2[6]" SITE "B4" ; +LOCATE COMP "TX0_DSA2[2]" SITE "A3" ; +LOCATE COMP "TX0_SW8_V3" SITE "B6" ; +LOCATE COMP "TX0_SW9_A" SITE "A5" ; +LOCATE COMP "TX1_SW7_B" SITE "C5" ; +LOCATE COMP "TX0_SW9_B" SITE "A4" ; +LOCATE COMP "TX1_SW9_A" SITE "B5" ; +LOCATE COMP "TX1_SW7_A" SITE "B3" ; +LOCATE COMP "TX0_SW7_A" SITE "C4" ; + + +###################################################################################### +# Bank Voltage Information +###################################################################################### +BANK 5 VCCIO 1.8 V; +BANK 4 VCCIO 1.8 V; +BANK 3 VCCIO 3.3 V; +BANK 2 VCCIO 3.3 V; +BANK 1 VCCIO 3.3 V; +BANK 0 VCCIO 3.3 V; + + +###################################################################################### +# Pin Drive information +###################################################################################### +#Below is a starting point for Drive strength selection, each designer must decide what drive strength is appropriate for their design +#HYSTERSIS is not specified for all inputs and assume default value, they may be turned on as follows SMALL and LARGE are available options, assuming you want LVCMOS25 +#IOBUF PORT "SigName" IO_TYPE=LVCMOS25 PULLMODE=NONE CLAMP=OFF HYSTERESIS=SMALL ; + +#CLAMP=OFF set to all pins, may be changed as desired. +#Drive set to 8mA SLOW for all pins, may be changed as desired. In future could have tool auto determine best drive, but for now defaults to 8mA slow + + +IOBUF PORT "TX0_SW3_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_FPGA_GPIO[1]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_CTRL_CS" IO_TYPE=LVCMOS18 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "MB_CTRL_MOSI" IO_TYPE=LVCMOS18 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "MB_FPGA_GPIO[12]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_FPGA_GPIO[9]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_FPGA_GPIO[10]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_CTRL_SCK" IO_TYPE=LVCMOS18 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "MB_FPGA_GPIO[13]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_FPGA_GPIO[2]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_FPGA_GPIO[0]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_FPGA_GPIO[5]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_FPGA_GPIO[6]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_FPGA_GPIO[4]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_CTRL_MISO" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_FPGA_GPIO[8]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_FPGA_GPIO[7]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_FPGA_GPIO[11]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_FPGA_GPIO[3]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW3_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW6_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW4_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW3_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW6_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW6_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "MB_SYNTH_SYNC" IO_TYPE=LVCMOS18 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "TX1_SW6_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW4_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW3_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW4_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW4_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW5_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "CTRL_REG_ARST" IO_TYPE=LVCMOS18 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "TX0_SW5_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_SW11_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA1_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_SW11_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA1_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA1_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW5_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "CH1_TX_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_DSA2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA2_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA3_B_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_SW5_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW5_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA1_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA2_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA3_B_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA2_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA2_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA3_B_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA3_B_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA3_B_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA2_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA1_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA3_B_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA3_B_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA3_B_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW10_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA2_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW10_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA1_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_SW4_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_SW1_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_SW2_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_SW5_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA2_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_SW5_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "CH1_RX_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_SW1_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_SW6_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_SW2_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_SW6_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA1_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_DSA2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA2_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_SW11_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_SW6_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_SW11_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_SW3_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_SW6_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA1_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_SW5_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_SW10_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_SW3_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_SW10_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA3_A_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW11_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_LO2_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "CH0_RX2_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "CH0_TX_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_LO1_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "RX1_SW3_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "CH0_RX_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW11_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_LO2_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "RX0_SW3_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_SW11_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_SW3_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_SW11_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA3_A_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_SW9_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "P7V_PG_A" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "P7V_ENABLE_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "P7V_ENABLE_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "P3D3VA_ENABLE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_LO1_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "RX1_SW9_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "P7V_PG_B" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "RX0_SW4_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA3_A_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA3_A_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_DSA3_A_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA3_A_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_LO2_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_SW3_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_LO2_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_LO2_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA3_A_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_DSA3_A_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_LO2_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_LO1_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_LO1_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_LO2_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_LO1_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_LO1_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_LO2_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "CPLD_REFCLK" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "RX1_LO2_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_LO1_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_LO1_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_LO1_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_LO2_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_DSA2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_LO2_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_LO1_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_LO2_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_SW7_SW8_CTRL" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_LO1_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_LO2_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "RX_TX_LO_SDI" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=16 SLEWRATE=FAST CLAMP=OFF ; +IOBUF PORT "TX0_DSA1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_LO2_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_DSA1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_LO1_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_LO1_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_LO1_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_DSA1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_LO2_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW1_SW2_CTRL" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_DSA1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_DSA1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_DSA1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_LO2_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "TX1_DSA1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_DSA1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_DSA1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW1_SW2_CTRL" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW14_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX0_SW7_SW8_CTRL" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_DSA1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_DSA2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "CH1_RX2_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_DSA2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_LO1_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "TX0_SW13_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_DSA2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW13_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW14_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW8_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW8_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW10_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_LO1_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ; +IOBUF PORT "RX1_SW1_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW8_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW8_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW8_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "RX1_SW1_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW11_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW11_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_DSA2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW7_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW9_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW10_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_DSA2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_DSA2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_DSA2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW8_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW9_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW7_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW9_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW9_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX1_SW7_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; +IOBUF PORT "TX0_SW7_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ; diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.sty b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.sty new file mode 100644 index 000000000..b9c890e4e --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.sty @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v index b208c020b..c3a89e887 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v @@ -38,6 +38,12 @@ module basic_regs #( //---------------------------------------------------------- reg [SCRATCH_REG_SIZE-1:0] scratch_reg = {SCRATCH_REG_SIZE {1'b0}}; +`ifdef VARIANT_XO3 + localparam VARIANT_ID = VARIANT_ID_XO3; +`else + localparam VARIANT_ID = VARIANT_ID_MAX10; +`endif + //---------------------------------------------------------- // Handling of CtrlPort //---------------------------------------------------------- @@ -105,7 +111,6 @@ module basic_regs #( s_ctrlport_resp_data[SCRATCH_REG_MSB : SCRATCH_REG] <= scratch_reg; end - BASE_ADDRESS + GIT_HASH_REGISTER: begin `ifdef GIT_HASH s_ctrlport_resp_data <= `GIT_HASH; @@ -114,6 +119,11 @@ module basic_regs #( `endif end + BASE_ADDRESS + SLAVE_VARIANT: begin + s_ctrlport_resp_data[VARIANT_REG_MSB : VARIANT_REG] + <= VARIANT_ID[VARIANT_REG_SIZE-1:0]; + end + // error on undefined address default: begin s_ctrlport_resp_data <= {32{1'b0}}; @@ -150,8 +160,10 @@ endmodule // This enum is used to create the constants held in the basic registers in both verilog and vhdl. // // -// +// // +// +// // // // @@ -214,6 +226,19 @@ endmodule // 7 hex digit hash code of the commit // // +// +// +// +// Contains information pertaining the variant of the programmable. +// +// +// +// Returns the variant of the programmable based on the part vendor. +// MAX10 variants return 0x583033(ASCII for MAX), while the XO3 variant +// returns 0x584F33 (ASCII for XO3) +// +// +// // // //XmlParse xml_off diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v index abc4b62f9..a84625d63 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v @@ -369,10 +369,16 @@ module dsa_control #( wire [31:0] ram_tx0_dia = select_gain_table ? table_tx0_doa : ram_datain; wire [31:0] ram_tx1_dia = select_gain_table ? table_tx1_doa : ram_datain; +`ifdef VARIANT_XO3 + localparam RAM_RW_MODE = "B-READ-ONLY" ; +`else + localparam RAM_RW_MODE = "READ-FIRST" ; +`endif + ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex") @@ -394,7 +400,7 @@ module dsa_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex") @@ -416,7 +422,7 @@ module dsa_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex") @@ -438,7 +444,7 @@ module dsa_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex") @@ -464,7 +470,7 @@ module dsa_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex") @@ -486,7 +492,7 @@ module dsa_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex") @@ -508,7 +514,7 @@ module dsa_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex") @@ -530,7 +536,7 @@ module dsa_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex") diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/led_control.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/led_control.v index 5663d348e..f32b09296 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/led_control.v +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/led_control.v @@ -163,10 +163,17 @@ module led_control #( ch1_rx_led <= ram_ch1_dob[CH1_TRX1_LED_EN + 0]; end +`ifdef VARIANT_XO3 + localparam RAM_RW_MODE = "B-READ-ONLY" ; +`else + localparam RAM_RW_MODE = "READ-FIRST" ; +`endif + + ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("") @@ -188,7 +195,7 @@ module led_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("") diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v index 63ce251b3..5b5290b18 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v @@ -370,10 +370,16 @@ module switch_control #( rx1_switch_11_reg <= ram_rx1_dob[RX_SWITCH_11_MSB: RX_SWITCH_11]; end +`ifdef VARIANT_XO3 + localparam RAM_RW_MODE = "B-READ-ONLY" ; +`else + localparam RAM_RW_MODE = "READ-FIRST" ; +`endif + ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/tx0_path_defaults.hex") @@ -394,7 +400,7 @@ module switch_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/tx1_path_defaults.hex") @@ -415,7 +421,7 @@ module switch_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/rx0_path_defaults.hex") @@ -436,7 +442,7 @@ module switch_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/rx1_path_defaults.hex") diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh index a7ec2f198..3c8181049 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh @@ -16,6 +16,7 @@ // SLAVE_OLDEST_REVISION : 0x8 (basic_regs.v) // SLAVE_SCRATCH : 0xC (basic_regs.v) // GIT_HASH_REGISTER : 0x10 (basic_regs.v) + // SLAVE_VARIANT : 0x14 (basic_regs.v) //=============================================================================== // RegTypes @@ -26,10 +27,12 @@ //=============================================================================== // Enumerated type BASIC_REGISTERS_VALUES - localparam BASIC_REGISTERS_VALUES_SIZE = 3; + localparam BASIC_REGISTERS_VALUES_SIZE = 5; localparam BOARD_ID_VALUE = 'h4002; // BASIC_REGISTERS_VALUES:BOARD_ID_VALUE + localparam VARIANT_ID_MAX10 = 'h4D4158; // BASIC_REGISTERS_VALUES:VARIANT_ID_MAX10 + localparam VARIANT_ID_XO3 = 'h584F33; // BASIC_REGISTERS_VALUES:VARIANT_ID_XO3 localparam OLDEST_CPLD_REVISION = 'h20110611; // BASIC_REGISTERS_VALUES:OLDEST_CPLD_REVISION - localparam CPLD_REVISION = 'h21111614; // BASIC_REGISTERS_VALUES:CPLD_REVISION + localparam CPLD_REVISION = 'h22031611; // BASIC_REGISTERS_VALUES:CPLD_REVISION // SLAVE_SIGNATURE Register (from basic_regs.v) localparam SLAVE_SIGNATURE = 'h0; // Register Offset @@ -73,3 +76,11 @@ localparam GIT_CLEAN_SIZE = 4; //GIT_HASH_REGISTER:GIT_CLEAN localparam GIT_CLEAN_MSB = 31; //GIT_HASH_REGISTER:GIT_CLEAN localparam GIT_CLEAN = 28; //GIT_HASH_REGISTER:GIT_CLEAN + + // SLAVE_VARIANT Register (from basic_regs.v) + localparam SLAVE_VARIANT = 'h14; // Register Offset + localparam SLAVE_VARIANT_SIZE = 32; // register width in bits + localparam SLAVE_VARIANT_MASK = 32'hFFFFFFFF; + localparam VARIANT_REG_SIZE = 32; //SLAVE_VARIANT:VARIANT_REG + localparam VARIANT_REG_MSB = 31; //SLAVE_VARIANT:VARIANT_REG + localparam VARIANT_REG = 0; //SLAVE_VARIANT:VARIANT_REG diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.v index a688db2ff..daf676671 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.v +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.v @@ -19,7 +19,9 @@ module zbx_top_cpld ( input wire MB_SYNTH_SYNC, //Clk and reset for control registers +`ifndef VARIANT_XO3 input wire CTRL_REG_CLK, +`endif input wire CTRL_REG_ARST, //SPI in @@ -66,13 +68,19 @@ module zbx_top_cpld ( input wire TX0_LO1_MUXOUT, output wire TX0_LO1_CSB, output wire TX0_LO1_SCK, - output wire TX0_LO1_SDI, output wire TX0_LO2_SYNC, input wire TX0_LO2_MUXOUT, output wire TX0_LO2_CSB, output wire TX0_LO2_SCK, + + // XO3 variant of this programmable drives all SDI lines from a single pin. +`ifndef VARIANT_XO3 + output wire TX0_LO1_SDI, output wire TX0_LO2_SDI, +`else + output wire RX_TX_LO_SDI, +`endif //Tx0 Switch control output wire TX0_SW1_SW2_CTRL, @@ -111,13 +119,16 @@ module zbx_top_cpld ( input wire TX1_LO1_MUXOUT, output wire TX1_LO1_CSB, output wire TX1_LO1_SCK, - output wire TX1_LO1_SDI, output wire TX1_LO2_SYNC, input wire TX1_LO2_MUXOUT, output wire TX1_LO2_CSB, output wire TX1_LO2_SCK, + +`ifndef VARIANT_XO3 + output wire TX1_LO1_SDI, output wire TX1_LO2_SDI, +`endif //Tx1 Switch control output wire TX1_SW1_SW2_CTRL, @@ -156,13 +167,16 @@ module zbx_top_cpld ( input wire RX0_LO1_MUXOUT, output wire RX0_LO1_CSB, output wire RX0_LO1_SCK, - output wire RX0_LO1_SDI, output wire RX0_LO2_SYNC, input wire RX0_LO2_MUXOUT, output wire RX0_LO2_CSB, output wire RX0_LO2_SCK, + +`ifndef VARIANT_XO3 + output wire RX0_LO1_SDI, output wire RX0_LO2_SDI, +`endif //Rx0 Switch control output wire RX0_SW1_A, @@ -198,13 +212,16 @@ module zbx_top_cpld ( input wire RX1_LO1_MUXOUT, output wire RX1_LO1_CSB, output wire RX1_LO1_SCK, - output wire RX1_LO1_SDI, output wire RX1_LO2_SYNC, input wire RX1_LO2_MUXOUT, output wire RX1_LO2_CSB, output wire RX1_LO2_SCK, + +`ifndef VARIANT_XO3 + output wire RX1_LO1_SDI, output wire RX1_LO2_SDI, +`endif //Rx1 Switch Control output wire RX1_SW1_A, @@ -254,6 +271,66 @@ module zbx_top_cpld ( `include "regmap/spi_regmap_utils.vh" `include "regmap/gpio_regmap_utils.vh" + // Bring pll_ref_clk enable signal to the same clock domain. + wire pll_ref_clk_enable_osc, pll_ref_clk_enable_prc; + wire pll_ref_clk; + + // Clock used to drive reconfiguration register space. + wire config_ref_clk; + + + // Part-dependent clock generation and gating. +`ifdef VARIANT_XO3 + + // Internal oscillator + wire clk_int_osc; + defparam OSCH_inst.NOM_FREQ = "66.5"; + OSCH OSCH_inst ( + .STDBY (1'b0), // 0=Enabled, 1=Disabled + .OSC (clk_int_osc), + .SEDSTDBY () + ); + + wire pll_ref_clk_freerun; + + DCCA pll_clk_buffer ( + .CLKI (CPLD_REFCLK), + .CE (1'b1), + .CLKO (pll_ref_clk_freerun) + ); + + // Bring pll_ref_clk enable signal to the same clock domain. + synchronizer #( + .WIDTH (1), + .STAGES (2), + .INITIAL_VAL (1'b1), + .FALSE_PATH_TO_IN (1) + ) pll_ref_clk_enable_sync_i ( + .clk (pll_ref_clk_freerun), + .rst (1'b0), + .in (pll_ref_clk_enable_osc), + .out (pll_ref_clk_enable_prc) + ); + + // PLL configure to output two clocks, both at the same frequency as the source. + // One clock is phase-aligned with the reference clock, while the second clock + // is shifted by 240 degrees. The shifted clock is used to ease timing on + // output signals with tight setup margins. + wire pll_ref_clk_adjusted; + + pll pll_ref_clk_pll ( + .CLKI(pll_ref_clk_freerun), + .ENCLKOP(pll_ref_clk_enable_prc), + .ENCLKOS(pll_ref_clk_enable_prc), + .CLKOP(pll_ref_clk), + .CLKOS(pll_ref_clk_adjusted), + .LOCK() + ); + + assign config_ref_clk = clk_int_osc; + +`else + // Internal oscillator // In the used MAX10 device this oscillator produces a clock anywhere in the // range of 55 to 116 MHz. It drives all logic required for identification and @@ -274,8 +351,6 @@ module zbx_top_cpld ( ); // Bring pll_ref_clk enable signal to the same clock domain. - wire pll_ref_clk_enable_osc, pll_ref_clk_enable_prc; - synchronizer #( .WIDTH (1), .STAGES (2), @@ -290,13 +365,17 @@ module zbx_top_cpld ( // Add clock buffer with option to enable PLL reference clock during SPLL // reconfiguration - wire pll_ref_clk; clkctrl pll_ref_clk_ctrl_i ( .inclk (CPLD_REFCLK), .ena (pll_ref_clk_enable_prc), .outclk (pll_ref_clk) ); + assign config_ref_clk = CTRL_REG_CLK; + +`endif + + // Generate synchronous resets wire ctrlport_rst_osc; wire ctrlport_rst_prc; @@ -315,7 +394,7 @@ module zbx_top_cpld ( ); reset_sync reset_sync_crc_i ( - .clk (CTRL_REG_CLK), + .clk (config_ref_clk), .reset_in (CTRL_REG_ARST), .reset_out (ctrlport_rst_crc) ); @@ -375,6 +454,11 @@ module zbx_top_cpld ( ctrlport_byte_deserializer ctrlport_byte_deserializer_i ( .ctrlport_clk (pll_ref_clk), + `ifdef VARIANT_XO3 + .ctrlport_clk_adjusted (pll_ref_clk_adjusted), + `else + .ctrlport_clk_adjusted (pll_ref_clk), + `endif .ctrlport_rst (ctrlport_rst_prc), .m_ctrlport_req_wr (gpio_ctrlport_req_wr), .m_ctrlport_req_rd (gpio_ctrlport_req_rd), @@ -420,7 +504,7 @@ module zbx_top_cpld ( // Requests targeting the reconfig engine are filtered because the reconfig // engine clock is disabled when unused. // - // X--------> RECONFIG (CTRL_REG_CLK) + // X--------> RECONFIG (config_ref_clk) // | // F -------> POWER_REGS_REGMAP (clk_int_osc) // |/ @@ -840,7 +924,7 @@ module zbx_top_cpld ( .s_ctrlport_resp_ack (reconfig_ctrlport_resp_ack_filtered_osc), .s_ctrlport_resp_status (reconfig_ctrlport_resp_status_filtered_osc), .s_ctrlport_resp_data (reconfig_ctrlport_resp_data_filtered_osc), - .m_ctrlport_clk (CTRL_REG_CLK), + .m_ctrlport_clk (config_ref_clk), .m_ctrlport_req_wr (reconfig_ctrlport_req_wr_crc), .m_ctrlport_req_rd (reconfig_ctrlport_req_rd_crc), .m_ctrlport_req_addr (reconfig_ctrlport_req_addr_crc), @@ -1158,8 +1242,9 @@ module zbx_top_cpld ( assign ctrlport_rst_crc_n = ~ctrlport_rst_crc; +`ifndef VARIANT_XO3 on_chip_flash flash_i ( - .clock (CTRL_REG_CLK), + .clock (config_ref_clk), .avmm_csr_addr (csr_addr), .avmm_csr_read (csr_read), .avmm_csr_writedata (csr_writedata), @@ -1175,13 +1260,14 @@ module zbx_top_cpld ( .avmm_data_burstcount (4'b0001), .reset_n (ctrlport_rst_crc_n) ); +`endif reconfig_engine #( .BASE_ADDRESS (RECONFIG), .NUM_ADDRESSES (RECONFIG_SIZE), .MEM_INIT (1) ) reconfig_engine_i ( - .ctrlport_clk (CTRL_REG_CLK), + .ctrlport_clk (config_ref_clk), .ctrlport_rst (ctrlport_rst_crc), .s_ctrlport_req_wr (reconfig_ctrlport_req_wr_crc), .s_ctrlport_req_rd (reconfig_ctrlport_req_rd_crc), @@ -1208,46 +1294,53 @@ module zbx_top_cpld ( // LO SPI Break-Out ///////////////////////////////////////////////////////////////////////////// - assign TX0_LO1_SCK = lo_sclk; + // SDI breakout +`ifdef VARIANT_XO3 + assign RX_TX_LO_SDI = lo_mosi; +`else assign TX0_LO1_SDI = lo_mosi; + assign TX0_LO2_SDI = lo_mosi; + assign TX1_LO1_SDI = lo_mosi; + assign TX1_LO2_SDI = lo_mosi; + assign RX0_LO1_SDI = lo_mosi; + assign RX0_LO2_SDI = lo_mosi; + assign RX1_LO1_SDI = lo_mosi; + assign RX1_LO2_SDI = lo_mosi; +`endif + + assign TX0_LO1_SCK = lo_sclk; assign TX0_LO1_CSB = lo_csb[TX0_LO1]; assign lo_miso[TX0_LO1] = TX0_LO1_MUXOUT; assign TX0_LO2_SCK = lo_sclk; - assign TX0_LO2_SDI = lo_mosi; assign TX0_LO2_CSB = lo_csb[TX0_LO2]; assign lo_miso[TX0_LO2] = TX0_LO2_MUXOUT; assign TX1_LO1_SCK = lo_sclk; - assign TX1_LO1_SDI = lo_mosi; assign TX1_LO1_CSB = lo_csb[TX1_LO1]; assign lo_miso[TX1_LO1] = TX1_LO1_MUXOUT; assign TX1_LO2_SCK = lo_sclk; - assign TX1_LO2_SDI = lo_mosi; assign TX1_LO2_CSB = lo_csb[TX1_LO2]; assign lo_miso[TX1_LO2] = TX1_LO2_MUXOUT; assign RX0_LO1_SCK = lo_sclk; - assign RX0_LO1_SDI = lo_mosi; assign RX0_LO1_CSB = lo_csb[RX0_LO1]; assign lo_miso[RX0_LO1] = RX0_LO1_MUXOUT; assign RX0_LO2_SCK = lo_sclk; - assign RX0_LO2_SDI = lo_mosi; assign RX0_LO2_CSB = lo_csb[RX0_LO2]; assign lo_miso[RX0_LO2] = RX0_LO2_MUXOUT; assign RX1_LO1_SCK = lo_sclk; - assign RX1_LO1_SDI = lo_mosi; assign RX1_LO1_CSB = lo_csb[RX1_LO1]; assign lo_miso[RX1_LO1] = RX1_LO1_MUXOUT; assign RX1_LO2_SCK = lo_sclk; - assign RX1_LO2_SDI = lo_mosi; assign RX1_LO2_CSB = lo_csb[RX1_LO2]; assign lo_miso[RX1_LO2] = RX1_LO2_MUXOUT; + endmodule `default_nettype wire -- cgit v1.2.3