From 6d3765605262016a80f71e36357f749ea35cbe5a Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Tue, 8 Jun 2021 19:40:46 -0500 Subject: fpga: x400: Add support for X410 motherboard FPGA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Andrew Moch Co-authored-by: Daniel Jepson Co-authored-by: Javier Valenzuela Co-authored-by: Joerg Hofrichter Co-authored-by: Kumaran Subramoniam Co-authored-by: Max Köhler Co-authored-by: Michael Auchter Co-authored-by: Paul Butler Co-authored-by: Wade Fife Co-authored-by: Hector Rubio --- fpga/usrp3/top/x400/ip/ddr4_64bits/Makefile.inc | 18 + fpga/usrp3/top/x400/ip/ddr4_64bits/ddr4_64bits.xci | 450 +++++++++++++++++++++ 2 files changed, 468 insertions(+) create mode 100644 fpga/usrp3/top/x400/ip/ddr4_64bits/Makefile.inc create mode 100644 fpga/usrp3/top/x400/ip/ddr4_64bits/ddr4_64bits.xci (limited to 'fpga/usrp3/top/x400/ip/ddr4_64bits') diff --git a/fpga/usrp3/top/x400/ip/ddr4_64bits/Makefile.inc b/fpga/usrp3/top/x400/ip/ddr4_64bits/Makefile.inc new file mode 100644 index 000000000..4b3ebada2 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/ddr4_64bits/Makefile.inc @@ -0,0 +1,18 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DDR4_64BITS_SRCS = \ +$(IP_BUILD_DIR)/ddr4_64bits/ddr4_64bits.xci + +IP_DDR4_64BITS_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr4_64bits/, \ +ddr4_64bits.xci.out \ +) + + +$(IP_DDR4_64BITS_SRCS) $(IP_DDR4_64BITS_OUTS) : $(IP_DIR)/ddr4_64bits/ddr4_64bits.xci + $(call BUILD_VIVADO_IP,ddr4_64bits,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x400/ip/ddr4_64bits/ddr4_64bits.xci b/fpga/usrp3/top/x400/ip/ddr4_64bits/ddr4_64bits.xci new file mode 100644 index 000000000..d1b5484e5 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/ddr4_64bits/ddr4_64bits.xci @@ -0,0 +1,450 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ddr4_64bits + + + + + + 0 + + + + 0 + + + + 0 + + + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + + 0 + 0 + 32 + 0 + 0 + 0 + + 512 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 4 + 0 + 256 + 2 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + 29 + 512 + 64 + X0Y11 + X0Y10 + X0Y70 + X0Y11 + 0 + 0 + DDR4_SDRAM + 17 + 0 + 0 + 32 + 512 + 4 + 1 + 2 + 0 + 0 + 0 + 1 + 1 + 0 + 15 + 9996 + 5 + 0 + VCO_2X + 10 + 8Gb + 29 + 1 + 0 + 0 + 8 + 8 + 0 + 938 + 1 + 8 + 8 + 64 + 0 + 1.2V + false + No + 1600 + 0 + 0 + MT40A512M16HA-075E + Components + 16 + 8Gb + 8 + 8192 + 16 + 4294967296 + 750 + DDR4_750_Timing + 0 + 0 + 1 + 0 + 1 + 16 + 0 + 0 + 075E + 1 + 1 + 300000000 + 1 + 1 + 0.84 + 0 + 4 + 1 + 5 + 833 + 0 + 37 + 16 + 2 + 39 + 17 + 9363 + 421 + 145 + 17 + + 8 + 7 + 4 + 10 + 19 + + 10 + 4 + 109 + 128 + 0 + 256 + DDR4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + FALSE + 9996 + 0 + 0 + 0 + 0 + 0 + 0 + NONE + Disable + 1 + 0.0 + 0 + 0.0 + 0 + 0.0 + 0 + 0.0 + 0 + 1 + 0 + None + None + None + None + 0 + 17 + 1 + 1 + 1 + 1 + DDR4_SDRAM + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + false + 32 + RD_PRI_REG + 512 + 4 + false + true + 0 + 0 + 0 + 0 + 8 + Sequential + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 15 + 5 + 0 + 0 + 0 + 0 + 512 + 17 + 12 + true + false + no_file_loaded + 1 + DM_NO_DBI + 64 + false + false + 9996 + 0 + 0 + false + ROW_COLUMN_BANK + MainMemory + MT40A512M16HA-075E + Components + 1.2V + 0 + 0 + 0 + 0 + RZQ/6 + Normal + RZQ/7 + 0 + 4:1 + false + false + false + Single + false + 0 + 0 + 0 + 0 + 833 + false + false + false + 0 + 0 + 0 + 5 + 1 + false + 1 + 1 + Custom + Custom + false + ddr4_64bits + false + false + Disable + false + true + SIMPLE_TG + OFF + false + 1 + false + 1 + false + 1 + Complete_Memory_Controller + false + Custom + Differential + false + BFM + Differential + false + false + false + zynquplusRFSOC + + + xczu28dr + ffvg1517 + VERILOG + + MIXED + -1 + + E + TRUE + TRUE + IP_Flow + 73068 + TRUE + . + + . + 2019.1.1_AR73068 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.2.3