From 6d3765605262016a80f71e36357f749ea35cbe5a Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Tue, 8 Jun 2021 19:40:46 -0500 Subject: fpga: x400: Add support for X410 motherboard FPGA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Andrew Moch Co-authored-by: Daniel Jepson Co-authored-by: Javier Valenzuela Co-authored-by: Joerg Hofrichter Co-authored-by: Kumaran Subramoniam Co-authored-by: Max Köhler Co-authored-by: Michael Auchter Co-authored-by: Paul Butler Co-authored-by: Wade Fife Co-authored-by: Hector Rubio --- fpga/usrp3/top/x400/dts/x410-10gbe-port0.dtsi | 41 +++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 fpga/usrp3/top/x400/dts/x410-10gbe-port0.dtsi (limited to 'fpga/usrp3/top/x400/dts/x410-10gbe-port0.dtsi') diff --git a/fpga/usrp3/top/x400/dts/x410-10gbe-port0.dtsi b/fpga/usrp3/top/x400/dts/x410-10gbe-port0.dtsi new file mode 100644 index 000000000..968c9bb98 --- /dev/null +++ b/fpga/usrp3/top/x400/dts/x410-10gbe-port0.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright 2021 Ettus Research, a National Instruments Brand + * + * SPDX-License-Identifier: LGPL-3.0-or-later + */ + +&fpga_full { + #address-cells = <2>; + #size-cells = <2>; + + nixge0: ethernet@1200000000 { + compatible = "ni,xge-enet-3.00"; + reg = <0x12 0x00000000 0x0 0x4000 + 0x12 0x00008000 0x0 0x2000>; + reg-names = "dma", "ctrl"; + + interrupts = <0 108 4 0 109 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&gic>; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + status = "okay"; + + phy-mode = "xgmii"; + + fixed-link { + speed = <10000>; + full-duplex; + link-gpios = <&gpio 94 0>; + }; + }; + + misc_enet_regs_0: uio@120000A000 { + status = "okay"; + compatible = "usrp-uio"; + reg = <0x12 0x0000A000 0x0 0x2000>; + reg-names = "misc-enet-regs0"; + }; +}; -- cgit v1.2.3