From 87b2cf09301e90dfaf2a6554c424b62e0558e0b1 Mon Sep 17 00:00:00 2001 From: Javier Valenzuela Date: Wed, 23 Jun 2021 11:32:01 -0700 Subject: fpga: x400: Connect Radio Blocks to DIO --- fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm | 3 +- fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm | 188 ++++++++++++++++++++++++++-- 2 files changed, 179 insertions(+), 12 deletions(-) (limited to 'fpga/usrp3/top/x400/doc') diff --git a/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm b/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm index 050be6b86..69ee17738 100644 --- a/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm +++ b/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm @@ -543,7 +543,8 @@

DB_WINDOW

-

RFDC_TIMING_WINDOW

+

RFDC_TIMING_WINDOW

+

DIO_WINDOW

diff --git a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm index 480da73d6..be0e58707 100644 --- a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm +++ b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm @@ -3274,7 +3274,7 @@ Total Offset = - + @@ -3300,6 +3300,38 @@ Total Offset = + + + + + + + + + + + +
DIO_MASTER_REGISTER
+ + + + +
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
+ +		 + + + + + +
+ + +Total Offset =
  0x00C000 + +
+ +

Initial Value = 0x00000000 @@ -3397,7 +3429,7 @@ Sets whether the DIO signal line is driven by this register interface or the use - + @@ -3423,6 +3455,38 @@ Total Offset = + + + + + + + + + + + +
DIO_DIRECTION_REGISTER
+ + + + +
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
+ +		 + + + + + +
+ + +Total Offset =
  0x00C004 + +
+ +

Initial Value = 0x00000000 @@ -3520,7 +3584,7 @@ Set the direction of FPGA buffer connected to DIO ports on the DIO board.
- + @@ -3546,6 +3610,38 @@ Total Offset = + + + + + + + + + + + +
DIO_INPUT_REGISTER
+ + + + +
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
+ +		 + + + + + +
+ + +Total Offset =
  0x00C008 + +
+ +

Initial Value not specified @@ -3642,7 +3738,7 @@ Status of each bit at the FPGA input. - + @@ -3668,6 +3764,38 @@ Total Offset = + + + + + + + + + + + +
DIO_OUTPUT_REGISTER
+ + + + +
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
+ +		 + + + + + +
+ + +Total Offset =
  0x00C00C + +
+ +

Initial Value = 0x00000000 @@ -14357,7 +14485,7 @@ Total Offset =

-

This window is defined in HDL source file rfdc_timing_control.v.

+

This window is defined in HDL source file x4xx_core_common.v.

@@ -14387,7 +14515,7 @@ Daughterboard GPIO interface. Register access within this space - +
RFDC_TIMING_WINDOW
  offset=0x8000
  size=0x8000 (32 Kbytes)
  size=0x4000 (16 Kbytes)
@@ -14396,7 +14524,7 @@ Daughterboard GPIO interface. Register access within this space

-

This window is defined in HDL source file rfdc_timing_control.v.

+

This window is defined in HDL source file x4xx_core_common.v.

@@ -14406,6 +14534,44 @@ RFDC timing control interface. + + +
+ + +

Offset 0xC000: DIO_WINDOW Window (R|W)

+

  Target regmap = DIO_REGMAP

+ (show extended info) +
+ + + + + + + + + +
+ + + + + +
DIO_WINDOW
  offset=0xC000
  size=0x4000 (16 Kbytes)
+ +

+ +

This window is defined in HDL source file x4xx_core_common.v.

+ +
+ +
+ +DIO control interface + +
+
@@ -21627,9 +21793,9 @@ FPGA version.
- 3 + 4 - 0x00000003 + 0x00000004

FPGA_CURRENT_VERSION_MINOR

@@ -21666,9 +21832,9 @@ FPGA version.
- 553915926 + 554176790 - 0x21041616 + 0x21081116

FPGA_VERSION_LAST_MODIFIED_TIME

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