From 38c549d1f7672e38773fc6624539cc166285a1df Mon Sep 17 00:00:00 2001 From: Javier Valenzuela Date: Wed, 29 Sep 2021 10:04:04 -0500 Subject: fpga: x400: Add SPI bus support for GPIO ports --- fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm | 553 +++++++++++++++++++++++++++- 1 file changed, 551 insertions(+), 2 deletions(-) (limited to 'fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm') diff --git a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm index 4e3b3c3a8..2827c1a93 100644 --- a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm +++ b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm @@ -3229,6 +3229,492 @@ Total Offset = + + +
+ +

DIG_IFC_REGMAP

+ +

SPI_OVER_GPIO_REGS

+ +
+ + +

Offset 0x0000: SPI_SLAVE_CONFIG(3:0) Register Array (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + +
+ + + + +
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
+ +		 + + + + +
RADIO_DIO_REGMAP|DIGITAL_IFC_REGS
  0x002000
+ +		 + + + + +
SPI_SLAVE_CONFIG
  offset=0x0000 + i*4
+ +		 + + + + + + +
+ + +Cannot determine accessibility through this path
+Total Offset =
  0x00E000 + i*4 + +
+ +

+ +

Initial Values
+ + +
default=>0x00000000
+

+ +

This register is defined in HDL source file x4xx_gpio_spi.v.
+It uses RegType SPI_SETUP which is defined in HDL source file x4xx_gpio_spi.v.

+ +
+ +
+ +Controls SPI Transaction
+Set of configuration registers for the supported slaves. + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..28 +

Reserved

+

+ +
27 +

MOSI_EDGE   (initialvalue=0)

+

Controls the edge in which the MOSI line is updated.
+ 0 = falling edge of SCLK.
+ 1 = rising edge of SCLK.

+ +
26 +

MISO_EDGE   (initialvalue=0)

+

Controls the edge in which the MISO line is latched.
+ 0 = falling edge of SCLK.
+ 1 = rising edge of SCLK.

+ +
25..20 +

SPI_LENGTH   (initialvalue=0)

+

Indicates the length of SPI transactions to this slave.

+ +
19..15 +

SLAVE_CS   (initialvalue=0)

+

Indicates which GPIO line to use for the CS signal.
+ 0-11 : Port A GPIO
+ 16-27: Port B GPIO

+ +
14..10 +

SLAVE_MISO   (initialvalue=0)

+

Indicates which GPIO line to use for the MISO signal.
+ 0-11 : Port A GPIO
+ 16-27: Port B GPIO

+ +
9..5 +

SLAVE_MOSI   (initialvalue=0)

+

Indicates which GPIO line to use for the MOSI signal.
+ 0-11 : Port A GPIO
+ 16-27: Port B GPIO

+ +
4..0 +

SLAVE_CLK   (initialvalue=0)

+

Indicates which GPIO line to use for the SCLK signal.
+ 0-11 : Port A GPIO
+ 16-27: Port B GPIO

+ +
+ +
+ +
+ + +

Offset 0x0010: SPI_TRANSACTION_CONFIG Register (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + +
+ + + + +
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
+ +		 + + + + +
RADIO_DIO_REGMAP|DIGITAL_IFC_REGS
  0x002000
+ +		 + + + + +
SPI_TRANSACTION_CONFIG
  offset=0x0010
+ +		 + + + + + +
+ + +Total Offset =
  0x00E010 + +
+ +

+ +

Initial Value = 0x00000000 +

+ +

This register is defined in HDL source file x4xx_gpio_spi.v.

+ +
+ +
+ +Controls clock rate and target for subsequent SPI transactions. + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..18 +

Reserved

+

+ +
17..16 +

SPI_SLAVE_SELECT   (initialvalue=0)

+

+ +
15..0 +

SPI_CLK_DIV   (initialvalue=0)

+

Controls the rate for subsequent SPI transactions. SCLK = DataClk/[(SPI_CLK_DIV+1)]

+ +
+ +
+ +
+ + +

Offset 0x0014: SPI_TRANSACTION_GO Register (W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + +
+ + + + +
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
+ +		 + + + + +
RADIO_DIO_REGMAP|DIGITAL_IFC_REGS
  0x002000
+ +		 + + + + +
SPI_TRANSACTION_GO
  offset=0x0014
+ +		 + + + + + +
+ + +Total Offset =
  0x00E014 + +
+ +

+ +

Initial Value = 0x00000000 +

+ +

This register is defined in HDL source file x4xx_gpio_spi.v.

+ +
+ +
+ +Starts a SPI transaction + +
+ + + + + + + + + +
BitsName
31..0w +

SPI_DATA   (initialvalue=0)

+

Payload to be sent for the SPI transaction. If the payload is shorter than 32 bits, + it must be aligned to the MSbs in this field. LSbs are ignored in this scenario.

+ +
+ +
+ +
+ + +

Offset 0x0018: SPI_STATUS Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + +
+ + + + +
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
+ +		 + + + + +
RADIO_DIO_REGMAP|DIGITAL_IFC_REGS
  0x002000
+ +		 + + + + +
SPI_STATUS
  offset=0x0018
+ +		 + + + + + +
+ + +Total Offset =
  0x00E018 + +
+ +

+ +

Initial Value = 0x00000000 +

+ +

This register is defined in HDL source file x4xx_gpio_spi.v.

+ +
+ +
+ +Contains the status of the SPI engine. + +
+ + + + + + + + + + + + + + + + + + + +
BitsName
31..25 +

Reserved

+

+ +
24 +

SPI_READY   (initialvalue=0)

+

Indicates the SPI engine is ready to start a new SPI transaction.

+ +
23..0 +

SPI_RESPONSE   (initialvalue=0)

+

Records the response of the last completed SPI transaction.

+ +
+ +
+ +
+
@@ -8020,7 +8506,7 @@ Total Offset = Controls whether GPIO lines use the TX and RX state of an RF channel (Classic ATR) or the daughterboard state the selector for the - @.GPIO_ATR_STATE. + ATR_STATE.
@@ -8069,7 +8555,7 @@ Controls whether GPIO lines use the TX and RX state of an RF channel

ATR_OPTION   (initialvalue=0)

Sets the scheme in which RF states in the radio will control GPIO lines. 0 = DB state is used. RF states are combined and the - GPIO state is driven based on all 16 @.GPIO_ATR_STATE registers. + GPIO state is driven based on all 16 ATR_STATE registers. 1 = Each RF channel has its separate ATR state(Classic ATR). Use register CLASSIC_ATR_CONFIG to indicate the RF channel to which each GPIO line responds to.

@@ -16322,6 +16808,69 @@ Window to access the DIO register map through the control port from the radio bl + + +
+ + +

Offset 0x2000: DIGITAL_IFC_REGS Window (R|W)

+

  Target regmap = DIG_IFC_REGMAP

+ (show extended info) +
+ + + + + + + + + + + + + +
+ + + + +
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
+ +		 + + + + + +
DIGITAL_IFC_REGS
  offset=0x2000
  size=0x1000 (4 Kbytes)
+ +		 + + + + + +
+ + +Total Offset =
  0x00E000 + +
+ +

+ +

This window is defined in HDL source file x4xx_core_common.v.

+ +
+ +
+ +Register space reserved for configuring a digital interface over the GPIO lines. + Currently, SPI is the only supported protocol. + +
+
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