From 6d3765605262016a80f71e36357f749ea35cbe5a Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Tue, 8 Jun 2021 19:40:46 -0500 Subject: fpga: x400: Add support for X410 motherboard FPGA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Andrew Moch Co-authored-by: Daniel Jepson Co-authored-by: Javier Valenzuela Co-authored-by: Joerg Hofrichter Co-authored-by: Kumaran Subramoniam Co-authored-by: Max Köhler Co-authored-by: Michael Auchter Co-authored-by: Paul Butler Co-authored-by: Wade Fife Co-authored-by: Hector Rubio --- fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm | 684 +++++++++++++++++++++++++++++ 1 file changed, 684 insertions(+) create mode 100644 fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm (limited to 'fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm') diff --git a/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm b/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm new file mode 100644 index 000000000..d643a7346 --- /dev/null +++ b/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm @@ -0,0 +1,684 @@ + + + + + + + +
+

+ + + X4XX_FPGA +

+
+

+ + + P5 Content +

+
+
+

+ + + ports +

+
+

ARM_M_AXI_HPM0

+

ARM_S_AXI_HPC0

+

ARM_S_AXI_HPC1

+

ARM_SPI1_CS3

+
+
+

+ + + AXI_HPM0_REGMAP +

+

+ + + COMMON +

+
+

RPU

+

JTAG_ENGINE

+

WR

+

MPM_ENDPOINT

+

CORE_REGS

+

INT_ETH_DMA

+

INT_ETH_REGS

+

RFDC

+

RFDC_REGS

+
+

+ + + UHD_ONLY +

+
+

QSFP_0_0

+

QSFP_0_1

+

QSFP_0_2

+

QSFP_0_3

+

QSFP_1_0

+

QSFP_1_1

+

QSFP_1_2

+

QSFP_1_3

+
+
+

+ + + MB_CPLD_PS_REGMAP +

+

+ + + MB_CPLD_PS_WINDOWS +

+
+

PS_REGISTERS

+

RECONFIG

+

POWER_REGISTERS

+
+

+ + + PS_SPI_ENDPOINTS +

+
+

enum SPI_ENDPOINT

+
+
+

+ + + CMAC_REGMAP +

+

+ + + XILINX_CMAC_REGISTERS +

+
+
+
+

+ + + CONSTANTS_REGMAP +

+

+ + + CONSTANTS_GROUP +

+
+

enum CONSTANTS_ENUM

+
+
+

+ + + CORE_REGS_REGMAP +

+

+ + + CORE_REGS +

+
+

GLOBAL_REGS

+

VERSIONING_REGS

+

TIMEKEEPER

+

DIO

+
+
+

+ + + CPLD_INTERFACE_REGMAP +

+

+ + + CPLD_INTERFACE_REGS +

+
+

SIGNATURE_REGISTER

+

SCRATCH_REGISTER

+
+

+ + + CPLD_SPI_CONTROL_REGS +

+
+

MOTHERBOARD_CPLD_DIVIDER

+

DAUGHTERBOARD_CPLD_DIVIDER

+
+

+ + + IPASS_REGS +

+
+

IPASS_CONTROL

+
+
+

+ + + DIO_REGMAP +

+

+ + + DIO_REGS +

+
+

DIO_MASTER_REGISTER

+

DIO_DIRECTION_REGISTER

+

DIO_INPUT_REGISTER

+

DIO_OUTPUT_REGISTER

+
+
+

+ + + DMA_REGMAP +

+

+ + + XILINX_DMA_REGISTERS +

+
+
+
+

+ + + ETH_DMA_CTRL_REGMAP +

+

+ + + ETH_DMA_CTRL +

+
+

AXI_DMA_CTRL

+

ETH_IO_CTRL

+
+
+

+ + + GLOBAL_REGS_REGMAP +

+

+ + + GLOBAL_REGS +

+
+

COMPAT_NUM_REG

+

DATESTAMP_REG

+

GIT_HASH_REG

+

SCRATCH_REG

+

DEVICE_ID_REG

+

RFNOC_INFO_REG

+

CLOCK_CTRL_REG

+

PPS_CTRL_REG

+

CHDR_CLK_RATE_REG

+

CHDR_CLK_COUNT_REG

+

GPS_CTRL_REG

+

GPS_STATUS_REG

+

DBOARD_CTRL_REG

+

DBOARD_STATUS_REG

+

NUM_TIMEKEEPERS_REG

+

SERIAL_NUM_LOW_REG

+

SERIAL_NUM_HIGH_REG

+

MFG_TEST_CTRL_REG

+

MFG_TEST_STATUS_REG

+

QSFP_PORT_0_0_INFO_REG

+

QSFP_PORT_0_1_INFO_REG

+

QSFP_PORT_0_2_INFO_REG

+

QSFP_PORT_0_3_INFO_REG

+

QSFP_PORT_1_0_INFO_REG

+

QSFP_PORT_1_1_INFO_REG

+

QSFP_PORT_1_2_INFO_REG

+

QSFP_PORT_1_3_INFO_REG

+
+
+

+ + + JTAG_REGMAP +

+

+ + + JTAG_REGS +

+
+

TX_DATA

+

STB_DATA

+

CONTROL

+

RX_DATA

+
+
+

+ + + MB_CPLD_PL_REGMAP +

+

+ + + MB_CPLD_PL_WINDOWS +

+
+

PL_REGISTERS

+

JTAG_DB0

+

JTAG_DB1

+
+
+

+ + + NIXGE_REGMAP +

+

+ + + XGE_MAC_REGS +

+
+

PORT_INFO

+

MAC_CTRL_STATUS

+

MAC_PHY_STATUS

+

MAC_LED_CTL

+

ETH_MDIO_BASE

+

AURORA_OVERRUNS

+

AURORA_CHECKSUM_ERRORS

+

AURORA_BIST_CHECKER_SAMPS

+

AURORA_BIST_CHECKER_ERRORS

+
+

+ + + XGE_MAC_WINDOW +

+
+

XGE_MAC

+
+
+

+ + + PL_CPLD_BASE_REGMAP +

+

+ + + MB_CPLD_LED_REGS +

+
+

LED_REGISTER

+
+

+ + + PL_CMI_REGS +

+
+

CABLE_PRESENT_REG

+
+

+ + + PL_CPLD_BASE_REGS +

+
+

SIGNATURE_REGISTER

+

REVISION_REGISTER

+

OLDEST_COMPATIBLE_REVISION_REGISTER

+

SCRATCH_REGISTER

+

GIT_HASH_REGISTER

+
+
+

+ + + PL_CPLD_REGMAP +

+

+ + + PL_CPLD_WINDOWS +

+
+

BASE

+

MB_CPLD

+

DB0_CPLD

+

DB1_CPLD

+
+
+

+ + + PL_DMA_MASTER_REGMAP +

+

+ + + HPC0_DMA +

+
+

AXI_HPC0_WINDOW

+
+

+ + + HPC1_DMA +

+
+

AXI_HPC1_WINDOW

+
+
+

+ + + PS_CPLD_BASE_REGMAP +

+

+ + + DIO_REGS +

+
+

DIO_DIRECTION_REGISTER

+
+

+ + + PS_CMI_REGS +

+
+

SERIAL_NUM_LOW_REG

+

SERIAL_NUM_HIGH_REG

+

CMI_CONTROL_STATUS

+
+

+ + + PS_CONTROL_REGS +

+
+

PL_DB_REGISTER

+
+

+ + + PS_CPLD_BASE_REGS +

+
+

SIGNATURE_REGISTER

+

REVISION_REGISTER

+

OLDEST_COMPATIBLE_REVISION_REGISTER

+

SCRATCH_REGISTER

+

GIT_HASH_REGISTER

+
+
+

+ + + PS_POWER_REGMAP +

+

+ + + PS_POWER_REGS +

+
+

IPASS_POWER_REG

+

OSC_POWER_REG

+
+
+

+ + + QSFP_REGMAP +

+

+ + + QSFP_WINDOWS +

+
+

ETH_DMA

+

NIXGE

+

UIO

+

CMAC

+
+
+

+ + + RADIO_CTRLPORT_REGMAP +

+

+ + + RADIO_CTRLPORT_WINDOWS +

+
+

DB_WINDOW

+

RFDC_TIMING_WINDOW

+
+
+

+ + + RECONFIG_REGMAP +

+

+ + + RECONFIG_REGS +

+
+

enum FLASH_PRIMARY_IMAGE_ADDR_ENUM

+

FLASH_STATUS_REG

+

FLASH_CONTROL_REG

+

FLASH_ADDR_REG

+

FLASH_WRITE_DATA_REG

+

FLASH_READ_DATA_REG

+

FLASH_CFM0_START_ADDR_REG

+

FLASH_CFM0_END_ADDR_REG

+
+
+

+ + + RFDC_REGS_REGMAP +

+

+ + + RFDC_REGS +

+
+

enum FABRIC_DSP_BW_ENUM

+

MMCM

+

INVERT_IQ_REG

+

MMCM_RESET_REG

+

RF_RESET_CONTROL_REG

+

RF_RESET_STATUS_REG

+

RF_AXI_STATUS_REG

+

FABRIC_DSP_REG

+

CALIBRATION_DATA

+

CALIBRATION_ENABLE

+

THRESHOLD_STATUS

+

RF_PLL_CONTROL_REG

+

RF_PLL_STATUS_REG

+
+
+

+ + + RFDC_TIMING_REGMAP +

+

+ + + RFDC_TIMING_REGS +

+
+

NCO_RESET_REG

+

GEARBOX_RESET_REG

+
+
+

+ + + SPI_REGMAP +

+

+ + + SPI_REGS +

+
+

RX_DATA_LOW

+

RX_DATA_HIGH

+

TX_DATA_LOW

+

TX_DATA_HIGH

+

CONTROL

+

CLOCK_DIVIDER

+

SLAVE_SELECT

+
+
+

+ + + UIO_REGMAP +

+

+ + + UIO_REGS +

+
+

IP

+

UDP

+

BRIDGE_MAC_LSB

+

BRIDGE_MAC_MSB

+

BRIDGE_IP

+

BRIDGE_UDP

+

BRIDGE_ENABLE

+

CHDR_DROPPED

+

CPU_DROPPED

+

PAUSE

+
+
+

+ + + VERSIONING_REGS_REGMAP +

+

+ + + VERSIONING_CONSTANTS +

+
+

enum CPLD_IFC_VERSION

+

enum DB_GPIO_IFC_VERSION

+

enum FPGA_VERSION

+

enum RF_CORE_100M_VERSION

+

enum RF_CORE_400M_VERSION

+
+

+ + + VERSIONING_REGS +

+
+

enum COMPONENTS_INDEXES

+

CURRENT_VERSION

+

OLDEST_COMPATIBLE_VERSION

+

VERSION_LAST_MODIFIED

+

RESERVED

+
+
+

+ + + XGE_MAC_REGMAP +

+

+ + + OPENCORE_XGE_REGISTERS +

+
+
+
+
+ + \ No newline at end of file -- cgit v1.2.3