From e1ce4565dbc7336ee806adce7c087bda4fcc77ae Mon Sep 17 00:00:00 2001 From: Humberto Jimenez Date: Wed, 27 Oct 2021 14:54:46 -0500 Subject: fpga: x400: Refactor CPLDs build process This commit refactors the X410's CPLDs build process to make it similar to other FPGA targets within the repo. The new process relies on basic Quartus build utilities. Additionally, this commit adds support for an alternative MAX10 CPLD for the motherboard CPLD implementation. Both previous (10M04) and new variant (10M08) are supported concurrently. The images package mapping is updated to reflect these changes. --- fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile | 153 ++-- .../x400/dboards/zbx/cpld/Makefile.zbx_cpld.inc | 68 ++ .../x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm | 68 +- .../top/x400/dboards/zbx/cpld/ip/Makefile.inc | 25 + .../x400/dboards/zbx/cpld/ip/clkctrl/.gitignore | 3 + .../x400/dboards/zbx/cpld/ip/clkctrl/Makefile.inc | 16 + .../x400/dboards/zbx/cpld/ip/clkctrl/clkctrl.qsys | 73 ++ .../top/x400/dboards/zbx/cpld/ip/flash/.gitignore | 3 - .../dboards/zbx/cpld/ip/flash/on_chip_flash.qsys | 90 --- .../dboards/zbx/cpld/ip/on_chip_flash/.gitignore | 3 + .../dboards/zbx/cpld/ip/on_chip_flash/Makefile.inc | 16 + .../zbx/cpld/ip/on_chip_flash/on_chip_flash.qsys | 90 +++ .../top/x400/dboards/zbx/cpld/ip/osc/Makefile.inc | 16 + .../dboards/zbx/cpld/quartus/raw_conversion.cof | 39 + .../x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qpf | 30 + .../x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf | 889 +++++++++++++++++++++ .../top/x400/dboards/zbx/cpld/raw_conversion.cof | 39 - .../zbx/cpld/register_endpoints/basic_regs.v | 2 +- .../zbx/cpld/regmap/basic_regs_regmap_utils.vh | 2 +- .../top/x400/dboards/zbx/cpld/zbx_top_cpld.qpf | 30 - .../top/x400/dboards/zbx/cpld/zbx_top_cpld.qsf | 889 --------------------- 21 files changed, 1408 insertions(+), 1136 deletions(-) create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile.zbx_cpld.inc create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ip/Makefile.inc create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/.gitignore create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/Makefile.inc create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/clkctrl.qsys delete mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/.gitignore delete mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/on_chip_flash.qsys create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/.gitignore create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/Makefile.inc create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/on_chip_flash.qsys create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ip/osc/Makefile.inc create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/raw_conversion.cof create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qpf create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf delete mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/raw_conversion.cof delete mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qpf delete mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qsf (limited to 'fpga/usrp3/top/x400/dboards/zbx/cpld') diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile b/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile index 878054bd6..2ab32fb11 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile @@ -4,87 +4,98 @@ # SPDX-License-Identifier: LGPL-3.0-or-later # -GIT_HASH = $(shell ../../../../../tools/scripts/git-hash.sh) - -build: cpld_defaults ip - @echo -ne "\n---- Make: Synthesis ...\n\n"; - @quartus_map zbx_top_cpld --verilog_macro="GIT_HASH=32'h$(GIT_HASH)"; - @echo -ne "\n\n---- Make: Implementation ...\n\n"; - @quartus_fit zbx_top_cpld; - @echo -ne "\n\n---- Make: Analyzing timing ...\n\n"; - @quartus_sta zbx_top_cpld; - @# grep for unconstrained path warning - @grep "332102" output_files/zbx_top_cpld.sta.rpt; \ - if [ $$? -eq 0 ]; then false; else true; fi - @# grep for timing closure critical warning - @grep "332148" output_files/zbx_top_cpld.sta.rpt; \ - if [ $$? -eq 0 ]; then false; else true; fi - @# expect no warnings - @grep -iw "warning" output_files/zbx_top_cpld.sta.rpt; \ - if [ $$? -eq 0 ]; then false; else true; fi - @# expect no critical warning except "review power analyzer report file" - @grep -i "critical warning" output_files/* | grep -v 16562; \ - if [ $$? -eq 0 ]; then false; else true; fi - @echo -ne "\n\n---- Make: Generating bitfile...\n\n"; - @quartus_asm zbx_top_cpld; - @echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP enabled)...\n\n"; - @quartus_cpf --convert \ - --frequency 12.5MHz \ - --voltage 2.5 \ - --operation p \ - ./output_files/zbx_top_cpld.pof ./output_files/zbx_top_cpld_isp_on.svf -o background_programming=on; - @echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP disabled)...\n\n"; - @quartus_cpf --convert \ - --frequency 12.5MHz \ - --voltage 2.5 \ - --operation p \ - ./output_files/zbx_top_cpld.pof ./output_files/zbx_top_cpld_isp_off.svf; - @echo -ne "\n\n---- Make: Converting bitfile to rdp format...\n\n"; - @quartus_cpf -c raw_conversion.cof - @echo -ne "\n\n---- Make: Copy final files...\n\n"; - @mkdir -p build - @cp output_files/zbx_top_cpld.pof build/usrp_zbx_cpld.pof - @cp output_files/zbx_top_cpld_isp_off.svf build/usrp_zbx_cpld.svf - @cp output_files/zbx_top_cpld_isp_on.svf build/usrp_zbx_cpld_isp_on.svf - @cp output_files/zbx_top_cpld_converted_cfm0_auto.rpd build/usrp_zbx_cpld.rpd - @echo -ne "\n\n---- Make: ZBX CPLD ready!\n"; - @echo -ne " Use build/usrp_zbx_cpld.pof via JTAG programmer or\n" - @echo -ne " build/usrp_zbx_cpld.svf (ISP off) via MB CPLD JTAG engine or\n" - @echo -ne " build/usrp_zbx_cpld.rpd via reconfig engine or\n" - @echo -ne " build/usrp_zbx_cpld_isp_on.rpd via MB CPLD JTAG engine.\n" - -clean: - @echo -ne "\nCleaning ZBX CPLD...\n"; - @git clean -Xdf +# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target +##------------------- +##USRP ZBX CPLD Help +##------------------- +##Usage: +## make +## +##Output: +## build//usrp_zbx_cpld.pof: Bitstream to use with JTAG programmer +## build//usrp_zbx_cpld.svf: Bitstream to use with PS JTAG engine (background programming) +## build//usrp_zbx_cpld.rpd: Bitstream to use via reconfig engine +## build//usrp_zbx_cpld_isp_off.svf: Bitstream to use with JTAG test points (initial programming) -QSYS_PATH=$(subst \,/,$(QUARTUS_ROOTDIR))/sopc_builder/bin +# Definitions +10M04_ID = "10M04SAU324I7G" -ROOT_DIR:=$(shell dirname $(realpath $(firstword $(MAKEFILE_LIST)))) +# Target specific variables +ZBX_CPLD_10M04: DEFS = VARIANT_`echo $(10M04_ID) | cut -c1-5`=1 -REGS_PY_FILE=$(ROOT_DIR)/../../../../../../../host/lib/ic_reg_maps/gen_zbx_cpld_regs.py -REGS_PY_MODULE=register_endpoints/memory_init_files/zbx_cpld_regs_t.py +# Using one of the files as a dependency (all files are generated at the same time) +INIT_FILES := register_endpoints/memory_init_files/rx0_path_defaults.hex -$(REGS_PY_MODULE): $(REGS_PY_FILE) - @python3 $(REGS_PY_FILE) $(REGS_PY_MODULE) +TARGET = bin +TOP ?= zbx_top_cpld -# Using one of the files as a dependency (all files are generated at the same time) -INIT_FILES := $(ROOT_DIR)/register_endpoints/memory_init_files/rx0_path_defaults.hex +# pre_build() +pre_build = @\ + mkdir -p build-$@/register_endpoints/memory_init_files/; \ + cp -rf register_endpoints/memory_init_files/*.hex build-$@/register_endpoints/memory_init_files/ + +# quartus_build($1=Device, $2=Definitions) +quartus_build = make -f Makefile.zbx_cpld.inc $(TARGET) NAME=$@ ARCH="MAX10" PART_ID="$1" $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" POST_STA_TCL="ps_cs_analysis.tcl" + +# quartus_ip($1=Device, $2=Definitions) +quartus_ip = make -f Makefile.zbx_cpld.inc quar_ip NAME=$@ ARCH="MAX10" PART_ID="$1" $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" + +# post_build($1=Artifact Name) +ifeq ($(TARGET),bin) + post_build = @\ + mkdir -p build/; \ + echo "Exporting bitstream files..."; \ + cp build-$@/output_files/$(TOP).pof build/$(1).pof; \ + cp build-$@/output_files/$(TOP)_isp_off.svf build/$(1)_isp_off.svf; \ + cp build-$@/output_files/$(TOP)_isp_on.svf build/$(1).svf; \ + cp build-$@/output_files/$(TOP)_converted_cfm0_auto.rpd build/$(1).rpd; \ + echo -ne "\n\n---- Make: MB CPLD ready!\n"; \ + echo -ne " Use build/$(1).pof via JTAG programmer or\n"; \ + echo -ne " build/$(1).svf (ISP on) via PS JTAG-engine (background programming) or\n"; \ + echo -ne " build/$(1).rpd via reconfig engine or\n"; \ + echo -ne " build/$(1)_isp_off.svf via JTAG test points (initial programming)\n"; +else + post_build = @echo "Skipping bitfile export." +endif -$(INIT_FILES): register_endpoints/memory_init_files/gen_defaults.py $(REGS_PY_MODULE) - @python3 $(ROOT_DIR)/register_endpoints/memory_init_files/gen_defaults.py +## +##Supported Targets +##----------------- -cpld_defaults: $(INIT_FILES) +all: ZBX_CPLD_10M04 ##(Default target) -ip: ip/flash/on_chip_flash/simulation/on_chip_flash.v \ - ip/osc/osc/simulation/osc.v - @make -C ../../../cpld ip +##ZBX_CPLD_10M04: ZBX CPLD targeted to 10M04SAU169I7G. +ZBX_CPLD_10M04: $(INIT_FILES) + $(call pre_build) + $(call quartus_build,$(10M04_ID),$(DEFS)) + $(call post_build,"usrp_zbx_cpld") -ip/flash/on_chip_flash/simulation/on_chip_flash.v: - $(QSYS_PATH)/qsys-generate ip/flash/on_chip_flash.qsys --simulation=VERILOG +ZBX_CPLD_IP: ##Build IPs only, needed for simulation. + @# Building only ZBX_CPLD_10M04 IP + $(call quartus_ip,$(10M04_ID),$(DEFS)) + +$(INIT_FILES): + make -f Makefile.zbx_cpld.inc cpld_defaults + +clean: ##Clean up all target build outputs. + @echo -ne "\nCleaning targets and git repo...\n"; + @rm -rf build-ZBX_CPLD* + @rm -rf build + @git clean -Xdf + +cleanall: ##Clean up all target and ip build outputs. + @echo -ne "\nCleaning targets, IP, and git repo...\n"; + @rm -rf build-ZBX_CPLD* + @rm -rf build + @rm -rf build-ip + @git clean -Xdf -ip/osc/osc/simulation/osc.v: - $(QSYS_PATH)/qsys-generate ip/osc/osc.qsys --simulation=VERILOG +help: ##Show this help message. + @grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' -all: build +## +##Supported Options +##----------------- +## .PHONY: all build clean ip diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile.zbx_cpld.inc b/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile.zbx_cpld.inc new file mode 100644 index 000000000..7b47f61cd --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile.zbx_cpld.inc @@ -0,0 +1,68 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +################################################## +# Project Setup +################################################## +# TOP_MODULE = +# NAME = +# PART_ID = +# ARCH = + +################################################## +# Include other makefiles +################################################## + +PROJECT_DIR = $(abspath .) +BASE_DIR = $(abspath ../../../../) +IP_DIR = $(abspath ./ip) +include $(BASE_DIR)/../tools/make/quartus_design_builder.mak + +# Include IP directory +include $(IP_DIR)/Makefile.inc + +# Define VERILOG_DEFS for macros definition +VERILOG_DEFS=$(EXTRA_DEFS) $(GIT_HASH_VERILOG_DEF) + +# Memory initialization files (CPLD default values) +REGS_PY_FILE=$(PROJECT_DIR)/../../../../../../../host/lib/ic_reg_maps/gen_zbx_cpld_regs.py +INIT_FILES_DIR=$(PROJECT_DIR)/register_endpoints/memory_init_files/ +REGS_PY_MODULE=$(INIT_FILES_DIR)/zbx_cpld_regs_t.py + +$(REGS_PY_MODULE): $(REGS_PY_FILE) + @python3 $(REGS_PY_FILE) $(REGS_PY_MODULE) + +# Using one of the files as a dependency (all files are generated at the same time) +INIT_FILES := $(INIT_FILES_DIR)/rx0_path_defaults.hex + +$(INIT_FILES): $(REGS_PY_MODULE) $(INIT_FILES_DIR)/gen_defaults.py + @python3 $(INIT_FILES_DIR)/gen_defaults.py + +cpld_defaults: .prereqs $(INIT_FILES) + @echo "Initialization files DONE ..." + +bin: .prereqs + $(call BUILD_QUARTUS_DESIGN,$(TOP_MODULE),$(ARCH),$(PART_ID),$(PROJECT_DIR),$(BUILD_DIR),$(POST_TCL_SCRIPT),0) + @\ + pushd $(BUILD_DIR); \ + echo "Converting bitfile to svf format (ISP enabled)..."; \ + quartus_cpf --convert \ + --frequency 12.5MHz \ + --voltage 2.5 \ + --operation p \ + output_files/$(TOP_MODULE).pof output_files/$(TOP_MODULE)_isp_on.svf -o background_programming=on; \ + echo "Converting bitfile to svf format (ISP disabled)..."; \ + quartus_cpf --convert \ + --frequency 12.5MHz \ + --voltage 2.5 \ + --operation p \ + output_files/$(TOP_MODULE).pof output_files/$(TOP_MODULE)_isp_off.svf; \ + echo "Converting bitfile to rpd format..."; \ + quartus_cpf -c raw_conversion.cof; \ + popd; + +quar_ip: .prereqs ip + @echo "IP Build DONE ..." diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm b/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm index 97bd80ee4..3d8f4475c 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm @@ -1486,9 +1486,9 @@ This enum is used to create the constants held in the basic registers in both ve - 553848841 + 554767892 - 0x21031009 + 0x21111614

CPLD_REVISION

@@ -6914,10 +6914,12 @@ Offers ability to enable or disable the PLL reference clock.

FLASH_PRIMARY_IMAGE_ADDR_ENUM Enumeration

-Those values are the start and end address of the CFM image flash - sector from Intel's On-Chip Flash IP Generator. Note that the values - given in the IP generator are byte based where the values of this enum - are U32 based (divided by 4). +These values are the start and end address of the CFM image flash + sector from Intel's On-Chip Flash IP Generator. + Be aware that three different values exist per each of the two + supported MAX10 variants: 10M04 and 10M08 + Note that the values given in the IP generator are byte based where + the values of this enum are U32 based (divided by 4). @@ -6941,7 +6943,20 @@ Those values are the start and end address of the CFM image flash + + + + + + + + + + @@ -6954,7 +6969,20 @@ Those values are the start and end address of the CFM image flash + + + + + + + + + + @@ -6967,7 +6995,20 @@ Those values are the start and end address of the CFM image flash + + + + + + + + + + @@ -7357,9 +7398,12 @@ Total Offset =

Defines the sector to be erased. Has to be set latest with the write access which starts the erase operation by strobing FLASH_ERASE_STB.
- If the flash is configured to support memory initialization (see - FLASH_MEM_INIT_ENABLED flag) the sectors 2 to 4 have to be erased. - If the flag is not asserted only sector 4 has to be erased.

+ With 10M04 variants, if the flash is configured to support memory + initialization (see FLASH_MEM_INIT_ENABLED flag) the sectors 2 + to 4 have to be erased. If the flag is not asserted only sector 4 + has to be erased. + With 10M08 variants, the sectors to be erased are 3 to 5 when + using memory initialization or only sector 5 otherwise.

diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/Makefile.inc b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/Makefile.inc new file mode 100644 index 000000000..77d9fce18 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/Makefile.inc @@ -0,0 +1,25 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(IP_DIR)/on_chip_flash/Makefile.inc +include $(IP_DIR)/osc/Makefile.inc +include $(IP_DIR)/clkctrl/Makefile.inc + +IP_SRCS = \ +$(IP_ON_CHIP_FLASH_SRCS) \ +$(IP_OSC_SRCS) \ +$(IP_CLKCTRL_SRCS) + + +IP_OUTPUTS = \ +$(IP_ON_CHIP_FLASH_OUTS) \ +$(IP_OSC_OUTS) \ +$(IP_CLKCTRL_OUTS) + + +ip: $(IP_OUTPUTS) + +.PHONY: ip diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/.gitignore b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/.gitignore new file mode 100644 index 000000000..87dce88a7 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/.gitignore @@ -0,0 +1,3 @@ +# generate files +clkctrl/ +clkctrl.sopcinfo diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/Makefile.inc b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/Makefile.inc new file mode 100644 index 000000000..2015c6976 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/Makefile.inc @@ -0,0 +1,16 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/quartus_ip_builder.mak + +IP_CLKCTRL_SRCS = \ +$(IP_BUILD_DIR)/clkctrl/clkctrl.qsys + +IP_CLKCTRL_OUTS = \ +$(IP_BUILD_DIR)/clkctrl/clkctrl.sopcinfo + +$(IP_CLKCTRL_SRCS) $(IP_CLKCTRL_OUTS) : $(IP_DIR)/clkctrl/clkctrl.qsys + $(call BUILD_QUARTUS_IP,clkctrl,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/clkctrl.qsys b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/clkctrl.qsys new file mode 100644 index 000000000..7a77cfc14 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/clkctrl.qsys @@ -0,0 +1,73 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/.gitignore b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/.gitignore deleted file mode 100644 index 585bc126d..000000000 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -# generate files -on_chip_flash/ -on_chip_flash.sopcinfo diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/on_chip_flash.qsys b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/on_chip_flash.qsys deleted file mode 100644 index 6598d63cb..000000000 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/on_chip_flash.qsys +++ /dev/null @@ -1,90 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Single Compressed Image with Memory Initialization - Internal Configuration - - - - - - Read and write,Read and write,Read and write,Read and write,Read and write - $${FILENAME}_onchip_flash_0 - - altera_onchip_flash.hex - altera_onchip_flash.dat - - - - - - - diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/.gitignore b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/.gitignore new file mode 100644 index 000000000..585bc126d --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/.gitignore @@ -0,0 +1,3 @@ +# generate files +on_chip_flash/ +on_chip_flash.sopcinfo diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/Makefile.inc b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/Makefile.inc new file mode 100644 index 000000000..fcd8528e6 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/Makefile.inc @@ -0,0 +1,16 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/quartus_ip_builder.mak + +IP_ON_CHIP_FLASH_SRCS = \ +$(IP_BUILD_DIR)/on_chip_flash/on_chip_flash.qsys + +IP_ON_CHIP_FLASH_OUTS = \ +$(IP_BUILD_DIR)/on_chip_flash/on_chip_flash.sopcinfo + +$(IP_ON_CHIP_FLASH_SRCS) $(IP_ON_CHIP_FLASH_OUTS) : $(IP_DIR)/on_chip_flash/on_chip_flash.qsys + $(call BUILD_QUARTUS_IP,on_chip_flash,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/on_chip_flash.qsys b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/on_chip_flash.qsys new file mode 100644 index 000000000..6598d63cb --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/on_chip_flash.qsys @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Single Compressed Image with Memory Initialization + Internal Configuration + + + + + + Read and write,Read and write,Read and write,Read and write,Read and write + $${FILENAME}_onchip_flash_0 + + altera_onchip_flash.hex + altera_onchip_flash.dat + + + + + + + diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/osc/Makefile.inc b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/osc/Makefile.inc new file mode 100644 index 000000000..0793a43b8 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/osc/Makefile.inc @@ -0,0 +1,16 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/quartus_ip_builder.mak + +IP_OSC_SRCS = \ +$(IP_BUILD_DIR)/osc/osc.qsys + +IP_OSC_OUTS = \ +$(IP_BUILD_DIR)/osc/osc.sopcinfo + +$(IP_OSC_SRCS) $(IP_OSC_OUTS) : $(IP_DIR)/osc/osc.qsys + $(call BUILD_QUARTUS_IP,osc,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/raw_conversion.cof b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/raw_conversion.cof new file mode 100644 index 000000000..dc74498aa --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/raw_conversion.cof @@ -0,0 +1,39 @@ + + + output_files/zbx_top_cpld_converted.pof + 1 + 1 + 14 + + Page_0 + 1 + + output_files/zbx_top_cpld.sof1 + + + 10 + 0 + 0 + 1 + 1 + + 1 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + + + 1 + 2 + 0 + -1 + -1 + 1 + + \ No newline at end of file diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qpf b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qpf new file mode 100644 index 000000000..972f9788d --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition +# Date created = 17:19:38 August 16, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.1" +DATE = "17:19:38 August 16, 2019" + +# Revisions + +PROJECT_REVISION = "zbx_top_cpld" diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf new file mode 100644 index 000000000..c164b34e5 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf @@ -0,0 +1,889 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 15:10:13 February 02, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# TopCpld_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" + +# Device that is being used in production run +set_global_assignment -name DEVICE 10M04SAU324I7G + +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:10:13 FEBRUARY 02, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name GENERATE_SVF_FILE OFF +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +set_global_assignment -name NUM_PARALLEL_PROCESSORS 2 + +set_location_assignment PIN_P2 -to CTRL_REG_ARST +set_instance_assignment -name IO_STANDARD "1.8 V" -to CTRL_REG_ARST + +set_location_assignment PIN_M4 -to CTRL_REG_CLK +set_instance_assignment -name IO_STANDARD "1.8 V" -to CTRL_REG_CLK + +set_location_assignment PIN_N1 -to MB_CTRL_CS +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_CS + +set_location_assignment PIN_U2 -to MB_CTRL_MISO +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_MISO + +set_location_assignment PIN_N3 -to MB_CTRL_MOSI +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_MOSI + +set_location_assignment PIN_L3 -to MB_CTRL_SCK +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_SCK + +# The digital daughterboard connector has 120 pins [A-F][1-20]. +# The assignment below orders the CPLD IOs MSB first and connects it to the DB +# connection with increasing letter and increasing number. +# This results in: +# FPGA Bit 13 = A14 (trace: MB_FPGA_GPIO_A14) +# FPGA Bit 12 = A16 (trace: MB_FPGA_GPIO_A16) +# ... +# FPGA Bit 0 = C19 (trace: MB_FPGA_GPIO_C19) +set_location_assignment PIN_R2 -to MB_FPGA_GPIO[13] +# Workaround for missing pull down resistor: +# Use pull up and schmitt trigger to detect FPGA reload by line going high unexpectedly +set_instance_assignment -name IO_STANDARD "1.8 V SCHMITT TRIGGER" -to MB_FPGA_GPIO[13] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MB_FPGA_GPIO[13] + +set_location_assignment PIN_N4 -to MB_FPGA_GPIO[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[12] + +set_location_assignment PIN_K8 -to MB_FPGA_GPIO[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[11] + +set_location_assignment PIN_M2 -to MB_FPGA_GPIO[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[10] + +set_location_assignment PIN_M1 -to MB_FPGA_GPIO[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[9] + +set_location_assignment PIN_T1 -to MB_FPGA_GPIO[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[8] + +set_location_assignment PIN_U1 -to MB_FPGA_GPIO[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[7] + +set_location_assignment PIN_P1 -to MB_FPGA_GPIO[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[6] + +set_location_assignment PIN_R3 -to MB_FPGA_GPIO[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[5] + +set_location_assignment PIN_M7 -to MB_FPGA_GPIO[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[4] + +set_location_assignment PIN_T3 -to MB_FPGA_GPIO[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[3] + +set_location_assignment PIN_P4 -to MB_FPGA_GPIO[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[2] + +set_location_assignment PIN_L7 -to MB_FPGA_GPIO[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[1] + +set_location_assignment PIN_L8 -to MB_FPGA_GPIO[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[0] + +set_location_assignment PIN_M3 -to MB_SYNTH_SYNC +set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_SYNTH_SYNC + +set_location_assignment PIN_G18 -to RX0_LO1_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_CSB + +set_location_assignment PIN_J18 -to RX0_LO1_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_SCK + +set_location_assignment PIN_F16 -to RX0_LO1_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_SDI + +set_location_assignment PIN_H17 -to RX0_LO1_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_SYNC + +set_location_assignment PIN_J12 -to RX0_LO2_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_CSB + +set_location_assignment PIN_J15 -to RX0_LO2_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_SCK + +set_location_assignment PIN_J16 -to RX0_LO2_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_SDI + +set_location_assignment PIN_K18 -to RX0_LO2_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_SYNC + +set_location_assignment PIN_F15 -to RX1_LO1_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_CSB + +set_location_assignment PIN_K17 -to RX1_LO1_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_SCK + +set_location_assignment PIN_G15 -to RX1_LO1_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_SDI + +set_location_assignment PIN_H18 -to RX1_LO1_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_SYNC + +set_location_assignment PIN_H15 -to RX1_LO2_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_CSB + +set_location_assignment PIN_L17 -to RX1_LO2_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_SCK + +set_location_assignment PIN_M17 -to RX1_LO2_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_SDI + +set_location_assignment PIN_L18 -to RX1_LO2_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_SYNC + +set_location_assignment PIN_C18 -to TX0_LO1_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_CSB + +set_location_assignment PIN_H12 -to TX0_LO1_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_SCK + +set_location_assignment PIN_D15 -to TX0_LO1_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_SDI + +set_location_assignment PIN_E15 -to TX0_LO1_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_SYNC + +set_location_assignment PIN_E18 -to TX0_LO2_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_CSB + +set_location_assignment PIN_G17 -to TX0_LO2_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_SCK + +set_location_assignment PIN_C17 -to TX0_LO2_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_SDI + +set_location_assignment PIN_D17 -to TX0_LO2_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_SYNC + +set_location_assignment PIN_G11 -to TX1_LO1_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_CSB + +set_location_assignment PIN_D16 -to TX1_LO1_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_SCK + +set_location_assignment PIN_E16 -to TX1_LO1_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_SDI + +set_location_assignment PIN_B18 -to TX1_LO1_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_SYNC + +set_location_assignment PIN_E17 -to TX1_LO2_CSB +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_CSB + +set_location_assignment PIN_G16 -to TX1_LO2_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_SCK + +set_location_assignment PIN_D18 -to TX1_LO2_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_SDI + +set_location_assignment PIN_H16 -to TX1_LO2_SYNC +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_SYNC + +set_location_assignment PIN_M12 -to RX0_DSA3_A_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[1] + +set_location_assignment PIN_T16 -to RX0_DSA3_A_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[2] + +set_location_assignment PIN_N15 -to RX0_DSA3_A_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[3] + +set_location_assignment PIN_M15 -to RX0_DSA3_A_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[4] + +set_location_assignment PIN_L12 -to RX1_DSA3_A_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[1] + +set_location_assignment PIN_L15 -to RX1_DSA3_A_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[2] + +set_location_assignment PIN_L16 -to RX1_DSA3_A_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[3] + +set_location_assignment PIN_K15 -to RX1_DSA3_A_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[4] + +set_location_assignment PIN_R18 -to P7V_PG_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_PG_A + +set_location_assignment PIN_N18 -to P7V_PG_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_PG_B + +set_location_assignment PIN_K12 -to CPLD_REFCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CPLD_REFCLK + +set_location_assignment PIN_R16 -to P3D3VA_ENABLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P3D3VA_ENABLE +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to P3D3VA_ENABLE + +set_location_assignment PIN_P16 -to P7V_ENABLE_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_ENABLE_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to P7V_ENABLE_A + +set_location_assignment PIN_R17 -to P7V_ENABLE_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_ENABLE_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to P7V_ENABLE_B + +set_location_assignment PIN_H6 -to RX0_DSA1_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[1] + +set_location_assignment PIN_J3 -to RX0_DSA1_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[2] + +set_location_assignment PIN_J4 -to RX0_DSA1_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[3] + +set_location_assignment PIN_K4 -to RX0_DSA1_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[4] + +set_location_assignment PIN_T4 -to RX0_DSA2_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[1] + +set_location_assignment PIN_N8 -to RX0_DSA2_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[2] + +set_location_assignment PIN_T5 -to RX0_DSA2_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[3] + +set_location_assignment PIN_T6 -to RX0_DSA2_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[4] + +set_location_assignment PIN_V2 -to RX0_DSA3_B_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[1] + +set_location_assignment PIN_U5 -to RX0_DSA3_B_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[2] + +set_location_assignment PIN_V5 -to RX0_DSA3_B_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[3] + +set_location_assignment PIN_V6 -to RX0_DSA3_B_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[4] + +set_location_assignment PIN_T15 -to RX0_LO1_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_LO1_MUXOUT + +set_location_assignment PIN_T14 -to RX0_LO2_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_LO2_MUXOUT + +set_location_assignment PIN_U8 -to RX0_SW1_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW1_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW1_A + +set_location_assignment PIN_V8 -to RX0_SW1_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW1_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW1_B + +set_location_assignment PIN_T12 -to RX0_SW10_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW10_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW10_V1 + +set_location_assignment PIN_P10 -to RX0_SW11_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW11_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW11_V1 + +set_location_assignment PIN_U17 -to RX0_SW11_V2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW11_V2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW11_V2 + +set_location_assignment PIN_F5 -to RX0_SW11_V3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW11_V3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW11_V3 + +set_location_assignment PIN_R8 -to RX0_SW2_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW2_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW2_A + +set_location_assignment PIN_U15 -to RX0_SW3_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW3_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW3_V1 + +set_location_assignment PIN_P14 -to RX0_SW3_V2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW3_V2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW3_V2 + +set_location_assignment PIN_T11 -to RX0_SW3_V3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW3_V3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW3_V3 + +set_location_assignment PIN_L11 -to RX0_SW4_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW4_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW4_A + +set_location_assignment PIN_P5 -to RX0_SW5_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW5_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW5_A + +set_location_assignment PIN_N7 -to RX0_SW5_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW5_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW5_B + +set_location_assignment PIN_U13 -to RX0_SW6_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW6_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW6_A + +set_location_assignment PIN_V10 -to RX0_SW6_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW6_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW6_B + +set_location_assignment PIN_D13 -to RX0_SW7_SW8_CTRL +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW7_SW8_CTRL +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW7_SW8_CTRL + +set_location_assignment PIN_R15 -to RX0_SW9_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW9_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW9_V1 + +set_location_assignment PIN_R9 -to RX1_DSA1_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[1] + +set_location_assignment PIN_P6 -to RX1_DSA1_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[2] + +set_location_assignment PIN_R6 -to RX1_DSA1_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[3] + +set_location_assignment PIN_M10 -to RX1_DSA1_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[4] + +set_location_assignment PIN_T7 -to RX1_DSA2_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[1] + +set_location_assignment PIN_M9 -to RX1_DSA2_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[2] + +set_location_assignment PIN_R5 -to RX1_DSA2_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[3] + +set_location_assignment PIN_R4 -to RX1_DSA2_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[4] + +set_location_assignment PIN_U6 -to RX1_DSA3_B_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[1] + +set_location_assignment PIN_V4 -to RX1_DSA3_B_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[2] + +set_location_assignment PIN_V3 -to RX1_DSA3_B_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[3] + +set_location_assignment PIN_U3 -to RX1_DSA3_B_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[4] + +set_location_assignment PIN_P15 -to RX1_LO1_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_LO1_MUXOUT + +set_location_assignment PIN_R14 -to RX1_LO2_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_LO2_MUXOUT + +set_location_assignment PIN_D7 -to RX1_SW1_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW1_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW1_A + +set_location_assignment PIN_D8 -to RX1_SW1_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW1_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW1_B + +set_location_assignment PIN_R12 -to RX1_SW10_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW10_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW10_V1 + +set_location_assignment PIN_V17 -to RX1_SW11_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW11_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW11_V1 + +set_location_assignment PIN_R10 -to RX1_SW11_V2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW11_V2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW11_V2 + +set_location_assignment PIN_F2 -to RX1_SW11_V3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW11_V3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW11_V3 + +set_location_assignment PIN_T8 -to RX1_SW2_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW2_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW2_A + +set_location_assignment PIN_T10 -to RX1_SW3_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW3_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW3_V1 + +set_location_assignment PIN_V16 -to RX1_SW3_V2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW3_V2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW3_V2 + +set_location_assignment PIN_U16 -to RX1_SW3_V3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW3_V3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW3_V3 + +set_location_assignment PIN_K7 -to RX1_SW4_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW4_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW4_A + +set_location_assignment PIN_M11 -to RX1_SW5_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW5_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW5_A + +set_location_assignment PIN_M8 -to RX1_SW5_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW5_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW5_B + +set_location_assignment PIN_U9 -to RX1_SW6_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW6_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW6_A + +set_location_assignment PIN_V9 -to RX1_SW6_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW6_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW6_B + +set_location_assignment PIN_E14 -to RX1_SW7_SW8_CTRL +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW7_SW8_CTRL +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW7_SW8_CTRL + +set_location_assignment PIN_N14 -to RX1_SW9_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW9_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW9_V1 + +set_location_assignment PIN_C13 -to TX0_DSA1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[2] + +set_location_assignment PIN_D14 -to TX0_DSA1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[3] + +set_location_assignment PIN_A15 -to TX0_DSA1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[4] + +set_location_assignment PIN_B14 -to TX0_DSA1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[5] + +set_location_assignment PIN_C16 -to TX0_DSA1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[6] + +set_location_assignment PIN_A2 -to TX0_DSA2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[2] + +set_location_assignment PIN_C5 -to TX0_DSA2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[3] + +set_location_assignment PIN_C4 -to TX0_DSA2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[4] + +set_location_assignment PIN_D10 -to TX0_DSA2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[5] + +set_location_assignment PIN_B2 -to TX0_DSA2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[6] + +set_location_assignment PIN_A8 -to TX0_LO1_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_LO1_MUXOUT + +set_location_assignment PIN_F12 -to TX0_LO2_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_LO2_MUXOUT + +set_location_assignment PIN_A14 -to TX0_SW1_SW2_CTRL +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW1_SW2_CTRL +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW1_SW2_CTRL + +set_location_assignment PIN_U7 -to TX0_SW10_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW10_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW10_A + +set_location_assignment PIN_V7 -to TX0_SW10_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW10_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW10_B + +set_location_assignment PIN_V15 -to TX0_SW11_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW11_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW11_A + +set_location_assignment PIN_V14 -to TX0_SW11_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW11_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW11_B + +set_location_assignment PIN_F11 -to TX0_SW13_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW13_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW13_V1 + +set_location_assignment PIN_B9 -to TX0_SW14_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW14_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW14_V1 + +set_location_assignment PIN_E4 -to TX0_SW3_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW3_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW3_A + +set_location_assignment PIN_D1 -to TX0_SW3_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW3_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW3_B + +set_location_assignment PIN_J1 -to TX0_SW4_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW4_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW4_A + +set_location_assignment PIN_H2 -to TX0_SW4_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW4_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW4_B + +set_location_assignment PIN_K3 -to TX0_SW5_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW5_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW5_A + +set_location_assignment PIN_L2 -to TX0_SW5_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW5_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW5_B + +set_location_assignment PIN_G1 -to TX0_SW6_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW6_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW6_A + +set_location_assignment PIN_G3 -to TX0_SW6_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW6_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW6_B + +set_location_assignment PIN_C1 -to TX0_SW7_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW7_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW7_A + +set_location_assignment PIN_D4 -to TX0_SW7_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW7_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW7_B + +set_location_assignment PIN_C8 -to TX0_SW8_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW8_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW8_V1 + +set_location_assignment PIN_C6 -to TX0_SW8_V2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW8_V2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW8_V2 + +set_location_assignment PIN_B4 -to TX0_SW8_V3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW8_V3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW8_V3 + +set_location_assignment PIN_A4 -to TX0_SW9_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW9_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW9_A + +set_location_assignment PIN_A3 -to TX0_SW9_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW9_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW9_B + +set_location_assignment PIN_C14 -to TX1_DSA1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[2] + +set_location_assignment PIN_C15 -to TX1_DSA1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[3] + +set_location_assignment PIN_B17 -to TX1_DSA1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[4] + +set_location_assignment PIN_A17 -to TX1_DSA1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[5] + +set_location_assignment PIN_A16 -to TX1_DSA1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[6] + +set_location_assignment PIN_J6 -to TX1_DSA2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[2] + +set_location_assignment PIN_F10 -to TX1_DSA2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[3] + +set_location_assignment PIN_G10 -to TX1_DSA2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[4] + +set_location_assignment PIN_L10 -to TX1_DSA2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[5] + +set_location_assignment PIN_D9 -to TX1_DSA2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[6] + +set_location_assignment PIN_C9 -to TX1_LO1_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_LO1_MUXOUT + +set_location_assignment PIN_B13 -to TX1_LO2_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_MUXOUT +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_LO2_MUXOUT + +set_location_assignment PIN_B16 -to TX1_SW1_SW2_CTRL +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW1_SW2_CTRL +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW1_SW2_CTRL + +set_location_assignment PIN_G7 -to TX1_SW10_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW10_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW10_A + +set_location_assignment PIN_D5 -to TX1_SW10_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW10_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW10_B + +set_location_assignment PIN_D6 -to TX1_SW11_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW11_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW11_A + +set_location_assignment PIN_E5 -to TX1_SW11_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW11_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW11_B + +set_location_assignment PIN_A9 -to TX1_SW13_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW13_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW13_V1 + +set_location_assignment PIN_B8 -to TX1_SW14_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW14_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW14_V1 + +set_location_assignment PIN_E1 -to TX1_SW3_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW3_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW3_A + +set_location_assignment PIN_D2 -to TX1_SW3_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW3_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW3_B + +set_location_assignment PIN_J2 -to TX1_SW4_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW4_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW4_A + +set_location_assignment PIN_K1 -to TX1_SW4_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW4_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW4_B + +set_location_assignment PIN_L1 -to TX1_SW5_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW5_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW5_A + +set_location_assignment PIN_K2 -to TX1_SW5_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW5_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW5_B + +set_location_assignment PIN_H1 -to TX1_SW6_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW6_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW6_A + +set_location_assignment PIN_F1 -to TX1_SW6_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW6_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW6_B + +set_location_assignment PIN_B1 -to TX1_SW7_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW7_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW7_A + +set_location_assignment PIN_C2 -to TX1_SW7_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW7_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW7_B + +set_location_assignment PIN_B7 -to TX1_SW8_V1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW8_V1 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW8_V1 + +set_location_assignment PIN_C7 -to TX1_SW8_V2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW8_V2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW8_V2 + +set_location_assignment PIN_A6 -to TX1_SW8_V3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW8_V3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW8_V3 + +set_location_assignment PIN_B3 -to TX1_SW9_A +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW9_A +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW9_A + +set_location_assignment PIN_B5 -to TX1_SW9_B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW9_B +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW9_B + +set_location_assignment PIN_N11 -to CH0_RX2_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH0_RX2_LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH0_RX2_LED + +set_location_assignment PIN_T13 -to CH0_RX_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH0_RX_LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH0_RX_LED + +set_location_assignment PIN_R13 -to CH0_TX_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH0_TX_LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH0_TX_LED + +set_location_assignment PIN_A10 -to CH1_RX2_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_RX2_LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_RX2_LED + +set_location_assignment PIN_H7 -to CH1_RX_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_RX_LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_RX_LED + +set_location_assignment PIN_G6 -to CH1_TX_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_TX_LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_TX_LED + +# The zbx_top_cpld.v has to stand first as it contains a define statement. +set_global_assignment -name VERILOG_FILE ../zbx_top_cpld.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_decoder.v +set_global_assignment -name SDC_FILE ../../../../constraints/timing/shared_constants.sdc +set_global_assignment -name SDC_FILE ../../../../cpld/db_spi_shared_constants.sdc +set_global_assignment -name SDC_FILE ../zbx_top_cpld.sdc +set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer_impl.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/reset_sync.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_splitter.v +set_global_assignment -name VERILOG_FILE ../../../../cpld/spi_slave.v +set_global_assignment -name VERILOG_FILE ../../../../cpld/spi_slave_to_ctrlport_master.v +set_global_assignment -name VERILOG_FILE ../register_endpoints/basic_regs.v +set_global_assignment -name VERILOG_FILE ../register_endpoints/power_regs.v +set_global_assignment -name VERILOG_FILE ../register_endpoints/switch_control.v +set_global_assignment -name VERILOG_FILE ../register_endpoints/dsa_control.v +set_global_assignment -name VERILOG_FILE ../register_endpoints/led_control.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/wb_spi/rtl/verilog/spi_top.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/wb_spi/rtl/verilog/spi_clgen.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/wb_spi/rtl/verilog/spi_shift.v +set_global_assignment -name VERILOG_FILE ../register_endpoints/lo_control.v +set_global_assignment -name VERILOG_FILE ../zbx_cpld_core.v +set_global_assignment -name VERILOG_FILE ../../../ctrlport_byte_deserializer.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v +set_global_assignment -name VERILOG_FILE ../../../../cpld/reconfig_engine.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_combiner.v +set_global_assignment -name VERILOG_FILE ../register_endpoints/atr_controller.v +set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../../lib/control/ram_2port_impl.vh +set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/ram_2port.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/handshake.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/pulse_synchronizer.v +set_global_assignment -name VERILOG_FILE ../ctrlport_window.v + +set_global_assignment -name QSYS_FILE ../ip/on_chip_flash/on_chip_flash.qsys +set_global_assignment -name QSYS_FILE ../ip/osc/osc.qsys +set_global_assignment -name QSYS_FILE ../../../../cpld/ip/clkctrl/clkctrl.qsys +set_global_assignment -name SOURCE_FILE ../db/zbx_top_cpld.cmp.rdb + +set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/tx1_path_defaults.hex +set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/tx0_path_defaults.hex +set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/tx_dsa_defaults.hex +set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/rx1_path_defaults.hex +set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/rx0_path_defaults.hex +set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/rx_dsa_defaults.hex + +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE WITH ERAM" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" + +set_global_assignment -name TOP_LEVEL_ENTITY zbx_top_cpld + + + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/raw_conversion.cof b/fpga/usrp3/top/x400/dboards/zbx/cpld/raw_conversion.cof deleted file mode 100644 index dc74498aa..000000000 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/raw_conversion.cof +++ /dev/null @@ -1,39 +0,0 @@ - - - output_files/zbx_top_cpld_converted.pof - 1 - 1 - 14 - - Page_0 - 1 - - output_files/zbx_top_cpld.sof1 - - - 10 - 0 - 0 - 1 - 1 - - 1 - - - 0 - 1 - 0 - 0 - 0 - 0 - 0 - - - 1 - 2 - 0 - -1 - -1 - 1 - - \ No newline at end of file diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v index 3c218de17..b208c020b 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v @@ -150,7 +150,7 @@ endmodule // This enum is used to create the constants held in the basic registers in both verilog and vhdl. // // -// +// // // // diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh index 0bbbd704e..dd6e13b8c 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh @@ -29,7 +29,7 @@ localparam BASIC_REGISTERS_VALUES_SIZE = 3; localparam BOARD_ID_VALUE = 'h4002; // BASIC_REGISTERS_VALUES:BOARD_ID_VALUE localparam OLDEST_CPLD_REVISION = 'h20110611; // BASIC_REGISTERS_VALUES:OLDEST_CPLD_REVISION - localparam CPLD_REVISION = 'h21031009; // BASIC_REGISTERS_VALUES:CPLD_REVISION + localparam CPLD_REVISION = 'h21111614; // BASIC_REGISTERS_VALUES:CPLD_REVISION // SLAVE_SIGNATURE Register (from basic_regs.v) localparam SLAVE_SIGNATURE = 'h0; // Register Offset diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qpf b/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qpf deleted file mode 100644 index 972f9788d..000000000 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2017 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition -# Date created = 17:19:38 August 16, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "17.1" -DATE = "17:19:38 August 16, 2019" - -# Revisions - -PROJECT_REVISION = "zbx_top_cpld" diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qsf b/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qsf deleted file mode 100644 index 141cfa9a4..000000000 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qsf +++ /dev/null @@ -1,889 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2017 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition -# Date created = 15:10:13 February 02, 2018 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# TopCpld_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus Prime software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "MAX 10" - -# Device that is being used in production run -set_global_assignment -name DEVICE 10M04SAU324I7G - -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:10:13 FEBRUARY 02, 2018" -set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 -set_global_assignment -name GENERATE_SVF_FILE OFF -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - -set_global_assignment -name NUM_PARALLEL_PROCESSORS 2 - -set_location_assignment PIN_P2 -to CTRL_REG_ARST -set_instance_assignment -name IO_STANDARD "1.8 V" -to CTRL_REG_ARST - -set_location_assignment PIN_M4 -to CTRL_REG_CLK -set_instance_assignment -name IO_STANDARD "1.8 V" -to CTRL_REG_CLK - -set_location_assignment PIN_N1 -to MB_CTRL_CS -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_CS - -set_location_assignment PIN_U2 -to MB_CTRL_MISO -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_MISO - -set_location_assignment PIN_N3 -to MB_CTRL_MOSI -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_MOSI - -set_location_assignment PIN_L3 -to MB_CTRL_SCK -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_SCK - -# The digital daughterboard connector has 120 pins [A-F][1-20]. -# The assignment below orders the CPLD IOs MSB first and connects it to the DB -# connection with increasing letter and increasing number. -# This results in: -# FPGA Bit 13 = A14 (trace: MB_FPGA_GPIO_A14) -# FPGA Bit 12 = A16 (trace: MB_FPGA_GPIO_A16) -# ... -# FPGA Bit 0 = C19 (trace: MB_FPGA_GPIO_C19) -set_location_assignment PIN_R2 -to MB_FPGA_GPIO[13] -# Workaround for missing pull down resistor: -# Use pull up and schmitt trigger to detect FPGA reload by line going high unexpectedly -set_instance_assignment -name IO_STANDARD "1.8 V SCHMITT TRIGGER" -to MB_FPGA_GPIO[13] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MB_FPGA_GPIO[13] - -set_location_assignment PIN_N4 -to MB_FPGA_GPIO[12] -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[12] - -set_location_assignment PIN_K8 -to MB_FPGA_GPIO[11] -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[11] - -set_location_assignment PIN_M2 -to MB_FPGA_GPIO[10] -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[10] - -set_location_assignment PIN_M1 -to MB_FPGA_GPIO[9] -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[9] - -set_location_assignment PIN_T1 -to MB_FPGA_GPIO[8] -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[8] - -set_location_assignment PIN_U1 -to MB_FPGA_GPIO[7] -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[7] - -set_location_assignment PIN_P1 -to MB_FPGA_GPIO[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[6] - -set_location_assignment PIN_R3 -to MB_FPGA_GPIO[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[5] - -set_location_assignment PIN_M7 -to MB_FPGA_GPIO[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[4] - -set_location_assignment PIN_T3 -to MB_FPGA_GPIO[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[3] - -set_location_assignment PIN_P4 -to MB_FPGA_GPIO[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[2] - -set_location_assignment PIN_L7 -to MB_FPGA_GPIO[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[1] - -set_location_assignment PIN_L8 -to MB_FPGA_GPIO[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[0] - -set_location_assignment PIN_M3 -to MB_SYNTH_SYNC -set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_SYNTH_SYNC - -set_location_assignment PIN_G18 -to RX0_LO1_CSB -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_CSB - -set_location_assignment PIN_J18 -to RX0_LO1_SCK -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_SCK - -set_location_assignment PIN_F16 -to RX0_LO1_SDI -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_SDI - -set_location_assignment PIN_H17 -to RX0_LO1_SYNC -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_SYNC - -set_location_assignment PIN_J12 -to RX0_LO2_CSB -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_CSB - -set_location_assignment PIN_J15 -to RX0_LO2_SCK -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_SCK - -set_location_assignment PIN_J16 -to RX0_LO2_SDI -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_SDI - -set_location_assignment PIN_K18 -to RX0_LO2_SYNC -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_SYNC - -set_location_assignment PIN_F15 -to RX1_LO1_CSB -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_CSB - -set_location_assignment PIN_K17 -to RX1_LO1_SCK -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_SCK - -set_location_assignment PIN_G15 -to RX1_LO1_SDI -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_SDI - -set_location_assignment PIN_H18 -to RX1_LO1_SYNC -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_SYNC - -set_location_assignment PIN_H15 -to RX1_LO2_CSB -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_CSB - -set_location_assignment PIN_L17 -to RX1_LO2_SCK -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_SCK - -set_location_assignment PIN_M17 -to RX1_LO2_SDI -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_SDI - -set_location_assignment PIN_L18 -to RX1_LO2_SYNC -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_SYNC - -set_location_assignment PIN_C18 -to TX0_LO1_CSB -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_CSB - -set_location_assignment PIN_H12 -to TX0_LO1_SCK -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_SCK - -set_location_assignment PIN_D15 -to TX0_LO1_SDI -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_SDI - -set_location_assignment PIN_E15 -to TX0_LO1_SYNC -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_SYNC - -set_location_assignment PIN_E18 -to TX0_LO2_CSB -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_CSB - -set_location_assignment PIN_G17 -to TX0_LO2_SCK -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_SCK - -set_location_assignment PIN_C17 -to TX0_LO2_SDI -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_SDI - -set_location_assignment PIN_D17 -to TX0_LO2_SYNC -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_SYNC - -set_location_assignment PIN_G11 -to TX1_LO1_CSB -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_CSB - -set_location_assignment PIN_D16 -to TX1_LO1_SCK -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_SCK - -set_location_assignment PIN_E16 -to TX1_LO1_SDI -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_SDI - -set_location_assignment PIN_B18 -to TX1_LO1_SYNC -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_SYNC - -set_location_assignment PIN_E17 -to TX1_LO2_CSB -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_CSB - -set_location_assignment PIN_G16 -to TX1_LO2_SCK -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_SCK - -set_location_assignment PIN_D18 -to TX1_LO2_SDI -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_SDI - -set_location_assignment PIN_H16 -to TX1_LO2_SYNC -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_SYNC - -set_location_assignment PIN_M12 -to RX0_DSA3_A_n[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[1] - -set_location_assignment PIN_T16 -to RX0_DSA3_A_n[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[2] - -set_location_assignment PIN_N15 -to RX0_DSA3_A_n[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[3] - -set_location_assignment PIN_M15 -to RX0_DSA3_A_n[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[4] - -set_location_assignment PIN_L12 -to RX1_DSA3_A_n[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[1] - -set_location_assignment PIN_L15 -to RX1_DSA3_A_n[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[2] - -set_location_assignment PIN_L16 -to RX1_DSA3_A_n[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[3] - -set_location_assignment PIN_K15 -to RX1_DSA3_A_n[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[4] - -set_location_assignment PIN_R18 -to P7V_PG_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_PG_A - -set_location_assignment PIN_N18 -to P7V_PG_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_PG_B - -set_location_assignment PIN_K12 -to CPLD_REFCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CPLD_REFCLK - -set_location_assignment PIN_R16 -to P3D3VA_ENABLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P3D3VA_ENABLE -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to P3D3VA_ENABLE - -set_location_assignment PIN_P16 -to P7V_ENABLE_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_ENABLE_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to P7V_ENABLE_A - -set_location_assignment PIN_R17 -to P7V_ENABLE_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_ENABLE_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to P7V_ENABLE_B - -set_location_assignment PIN_H6 -to RX0_DSA1_n[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[1] - -set_location_assignment PIN_J3 -to RX0_DSA1_n[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[2] - -set_location_assignment PIN_J4 -to RX0_DSA1_n[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[3] - -set_location_assignment PIN_K4 -to RX0_DSA1_n[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[4] - -set_location_assignment PIN_T4 -to RX0_DSA2_n[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[1] - -set_location_assignment PIN_N8 -to RX0_DSA2_n[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[2] - -set_location_assignment PIN_T5 -to RX0_DSA2_n[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[3] - -set_location_assignment PIN_T6 -to RX0_DSA2_n[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[4] - -set_location_assignment PIN_V2 -to RX0_DSA3_B_n[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[1] - -set_location_assignment PIN_U5 -to RX0_DSA3_B_n[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[2] - -set_location_assignment PIN_V5 -to RX0_DSA3_B_n[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[3] - -set_location_assignment PIN_V6 -to RX0_DSA3_B_n[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[4] - -set_location_assignment PIN_T15 -to RX0_LO1_MUXOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_MUXOUT -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_LO1_MUXOUT - -set_location_assignment PIN_T14 -to RX0_LO2_MUXOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_MUXOUT -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_LO2_MUXOUT - -set_location_assignment PIN_U8 -to RX0_SW1_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW1_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW1_A - -set_location_assignment PIN_V8 -to RX0_SW1_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW1_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW1_B - -set_location_assignment PIN_T12 -to RX0_SW10_V1 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW10_V1 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW10_V1 - -set_location_assignment PIN_P10 -to RX0_SW11_V1 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW11_V1 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW11_V1 - -set_location_assignment PIN_U17 -to RX0_SW11_V2 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW11_V2 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW11_V2 - -set_location_assignment PIN_F5 -to RX0_SW11_V3 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW11_V3 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW11_V3 - -set_location_assignment PIN_R8 -to RX0_SW2_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW2_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW2_A - -set_location_assignment PIN_U15 -to RX0_SW3_V1 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW3_V1 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW3_V1 - -set_location_assignment PIN_P14 -to RX0_SW3_V2 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW3_V2 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW3_V2 - -set_location_assignment PIN_T11 -to RX0_SW3_V3 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW3_V3 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW3_V3 - -set_location_assignment PIN_L11 -to RX0_SW4_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW4_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW4_A - -set_location_assignment PIN_P5 -to RX0_SW5_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW5_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW5_A - -set_location_assignment PIN_N7 -to RX0_SW5_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW5_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW5_B - -set_location_assignment PIN_U13 -to RX0_SW6_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW6_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW6_A - -set_location_assignment PIN_V10 -to RX0_SW6_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW6_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW6_B - -set_location_assignment PIN_D13 -to RX0_SW7_SW8_CTRL -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW7_SW8_CTRL -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW7_SW8_CTRL - -set_location_assignment PIN_R15 -to RX0_SW9_V1 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW9_V1 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW9_V1 - -set_location_assignment PIN_R9 -to RX1_DSA1_n[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[1] - -set_location_assignment PIN_P6 -to RX1_DSA1_n[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[2] - -set_location_assignment PIN_R6 -to RX1_DSA1_n[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[3] - -set_location_assignment PIN_M10 -to RX1_DSA1_n[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[4] - -set_location_assignment PIN_T7 -to RX1_DSA2_n[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[1] - -set_location_assignment PIN_M9 -to RX1_DSA2_n[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[2] - -set_location_assignment PIN_R5 -to RX1_DSA2_n[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[3] - -set_location_assignment PIN_R4 -to RX1_DSA2_n[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[4] - -set_location_assignment PIN_U6 -to RX1_DSA3_B_n[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[1] - -set_location_assignment PIN_V4 -to RX1_DSA3_B_n[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[2] - -set_location_assignment PIN_V3 -to RX1_DSA3_B_n[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[3] - -set_location_assignment PIN_U3 -to RX1_DSA3_B_n[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[4] - -set_location_assignment PIN_P15 -to RX1_LO1_MUXOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_MUXOUT -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_LO1_MUXOUT - -set_location_assignment PIN_R14 -to RX1_LO2_MUXOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_MUXOUT -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_LO2_MUXOUT - -set_location_assignment PIN_D7 -to RX1_SW1_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW1_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW1_A - -set_location_assignment PIN_D8 -to RX1_SW1_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW1_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW1_B - -set_location_assignment PIN_R12 -to RX1_SW10_V1 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW10_V1 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW10_V1 - -set_location_assignment PIN_V17 -to RX1_SW11_V1 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW11_V1 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW11_V1 - -set_location_assignment PIN_R10 -to RX1_SW11_V2 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW11_V2 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW11_V2 - -set_location_assignment PIN_F2 -to RX1_SW11_V3 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW11_V3 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW11_V3 - -set_location_assignment PIN_T8 -to RX1_SW2_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW2_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW2_A - -set_location_assignment PIN_T10 -to RX1_SW3_V1 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW3_V1 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW3_V1 - -set_location_assignment PIN_V16 -to RX1_SW3_V2 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW3_V2 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW3_V2 - -set_location_assignment PIN_U16 -to RX1_SW3_V3 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW3_V3 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW3_V3 - -set_location_assignment PIN_K7 -to RX1_SW4_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW4_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW4_A - -set_location_assignment PIN_M11 -to RX1_SW5_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW5_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW5_A - -set_location_assignment PIN_M8 -to RX1_SW5_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW5_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW5_B - -set_location_assignment PIN_U9 -to RX1_SW6_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW6_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW6_A - -set_location_assignment PIN_V9 -to RX1_SW6_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW6_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW6_B - -set_location_assignment PIN_E14 -to RX1_SW7_SW8_CTRL -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW7_SW8_CTRL -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW7_SW8_CTRL - -set_location_assignment PIN_N14 -to RX1_SW9_V1 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW9_V1 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW9_V1 - -set_location_assignment PIN_C13 -to TX0_DSA1[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[2] - -set_location_assignment PIN_D14 -to TX0_DSA1[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[3] - -set_location_assignment PIN_A15 -to TX0_DSA1[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[4] - -set_location_assignment PIN_B14 -to TX0_DSA1[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[5] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[5] - -set_location_assignment PIN_C16 -to TX0_DSA1[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[6] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[6] - -set_location_assignment PIN_A2 -to TX0_DSA2[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[2] - -set_location_assignment PIN_C5 -to TX0_DSA2[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[3] - -set_location_assignment PIN_C4 -to TX0_DSA2[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[4] - -set_location_assignment PIN_D10 -to TX0_DSA2[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[5] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[5] - -set_location_assignment PIN_B2 -to TX0_DSA2[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[6] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[6] - -set_location_assignment PIN_A8 -to TX0_LO1_MUXOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_MUXOUT -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_LO1_MUXOUT - -set_location_assignment PIN_F12 -to TX0_LO2_MUXOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_MUXOUT -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_LO2_MUXOUT - -set_location_assignment PIN_A14 -to TX0_SW1_SW2_CTRL -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW1_SW2_CTRL -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW1_SW2_CTRL - -set_location_assignment PIN_U7 -to TX0_SW10_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW10_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW10_A - -set_location_assignment PIN_V7 -to TX0_SW10_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW10_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW10_B - -set_location_assignment PIN_V15 -to TX0_SW11_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW11_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW11_A - -set_location_assignment PIN_V14 -to TX0_SW11_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW11_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW11_B - -set_location_assignment PIN_F11 -to TX0_SW13_V1 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW13_V1 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW13_V1 - -set_location_assignment PIN_B9 -to TX0_SW14_V1 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW14_V1 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW14_V1 - -set_location_assignment PIN_E4 -to TX0_SW3_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW3_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW3_A - -set_location_assignment PIN_D1 -to TX0_SW3_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW3_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW3_B - -set_location_assignment PIN_J1 -to TX0_SW4_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW4_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW4_A - -set_location_assignment PIN_H2 -to TX0_SW4_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW4_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW4_B - -set_location_assignment PIN_K3 -to TX0_SW5_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW5_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW5_A - -set_location_assignment PIN_L2 -to TX0_SW5_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW5_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW5_B - -set_location_assignment PIN_G1 -to TX0_SW6_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW6_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW6_A - -set_location_assignment PIN_G3 -to TX0_SW6_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW6_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW6_B - -set_location_assignment PIN_C1 -to TX0_SW7_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW7_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW7_A - -set_location_assignment PIN_D4 -to TX0_SW7_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW7_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW7_B - -set_location_assignment PIN_C8 -to TX0_SW8_V1 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW8_V1 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW8_V1 - -set_location_assignment PIN_C6 -to TX0_SW8_V2 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW8_V2 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW8_V2 - -set_location_assignment PIN_B4 -to TX0_SW8_V3 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW8_V3 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW8_V3 - -set_location_assignment PIN_A4 -to TX0_SW9_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW9_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW9_A - -set_location_assignment PIN_A3 -to TX0_SW9_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW9_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW9_B - -set_location_assignment PIN_C14 -to TX1_DSA1[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[2] - -set_location_assignment PIN_C15 -to TX1_DSA1[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[3] - -set_location_assignment PIN_B17 -to TX1_DSA1[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[4] - -set_location_assignment PIN_A17 -to TX1_DSA1[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[5] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[5] - -set_location_assignment PIN_A16 -to TX1_DSA1[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[6] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[6] - -set_location_assignment PIN_J6 -to TX1_DSA2[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[2] - -set_location_assignment PIN_F10 -to TX1_DSA2[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[3] - -set_location_assignment PIN_G10 -to TX1_DSA2[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[4] - -set_location_assignment PIN_L10 -to TX1_DSA2[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[5] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[5] - -set_location_assignment PIN_D9 -to TX1_DSA2[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[6] -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[6] - -set_location_assignment PIN_C9 -to TX1_LO1_MUXOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_MUXOUT -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_LO1_MUXOUT - -set_location_assignment PIN_B13 -to TX1_LO2_MUXOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_MUXOUT -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_LO2_MUXOUT - -set_location_assignment PIN_B16 -to TX1_SW1_SW2_CTRL -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW1_SW2_CTRL -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW1_SW2_CTRL - -set_location_assignment PIN_G7 -to TX1_SW10_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW10_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW10_A - -set_location_assignment PIN_D5 -to TX1_SW10_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW10_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW10_B - -set_location_assignment PIN_D6 -to TX1_SW11_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW11_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW11_A - -set_location_assignment PIN_E5 -to TX1_SW11_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW11_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW11_B - -set_location_assignment PIN_A9 -to TX1_SW13_V1 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW13_V1 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW13_V1 - -set_location_assignment PIN_B8 -to TX1_SW14_V1 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW14_V1 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW14_V1 - -set_location_assignment PIN_E1 -to TX1_SW3_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW3_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW3_A - -set_location_assignment PIN_D2 -to TX1_SW3_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW3_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW3_B - -set_location_assignment PIN_J2 -to TX1_SW4_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW4_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW4_A - -set_location_assignment PIN_K1 -to TX1_SW4_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW4_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW4_B - -set_location_assignment PIN_L1 -to TX1_SW5_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW5_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW5_A - -set_location_assignment PIN_K2 -to TX1_SW5_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW5_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW5_B - -set_location_assignment PIN_H1 -to TX1_SW6_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW6_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW6_A - -set_location_assignment PIN_F1 -to TX1_SW6_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW6_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW6_B - -set_location_assignment PIN_B1 -to TX1_SW7_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW7_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW7_A - -set_location_assignment PIN_C2 -to TX1_SW7_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW7_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW7_B - -set_location_assignment PIN_B7 -to TX1_SW8_V1 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW8_V1 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW8_V1 - -set_location_assignment PIN_C7 -to TX1_SW8_V2 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW8_V2 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW8_V2 - -set_location_assignment PIN_A6 -to TX1_SW8_V3 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW8_V3 -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW8_V3 - -set_location_assignment PIN_B3 -to TX1_SW9_A -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW9_A -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW9_A - -set_location_assignment PIN_B5 -to TX1_SW9_B -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW9_B -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW9_B - -set_location_assignment PIN_N11 -to CH0_RX2_LED -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH0_RX2_LED -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH0_RX2_LED - -set_location_assignment PIN_T13 -to CH0_RX_LED -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH0_RX_LED -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH0_RX_LED - -set_location_assignment PIN_R13 -to CH0_TX_LED -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH0_TX_LED -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH0_TX_LED - -set_location_assignment PIN_A10 -to CH1_RX2_LED -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_RX2_LED -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_RX2_LED - -set_location_assignment PIN_H7 -to CH1_RX_LED -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_RX_LED -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_RX_LED - -set_location_assignment PIN_G6 -to CH1_TX_LED -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_TX_LED -set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_TX_LED - -# The zbx_top_cpld.v has to stand first as it contains a define statement. -set_global_assignment -name VERILOG_FILE ./zbx_top_cpld.v -set_global_assignment -name VERILOG_FILE ../../../../../lib/rfnoc/utils/ctrlport_decoder.v -set_global_assignment -name SDC_FILE ../../../constraints/timing/shared_constants.sdc -set_global_assignment -name SDC_FILE ../../../cpld/db_spi_shared_constants.sdc -set_global_assignment -name SDC_FILE zbx_top_cpld.sdc -set_global_assignment -name VERILOG_FILE ./../../../../../lib/control/synchronizer_impl.v -set_global_assignment -name VERILOG_FILE ./../../../../../lib/control/synchronizer.v -set_global_assignment -name VERILOG_FILE ./../../../../../lib/control/reset_sync.v -set_global_assignment -name VERILOG_FILE ./../../../../../lib/rfnoc/utils/ctrlport_splitter.v -set_global_assignment -name VERILOG_FILE ./../../../cpld/spi_slave.v -set_global_assignment -name VERILOG_FILE ./../../../cpld/spi_slave_to_ctrlport_master.v -set_global_assignment -name VERILOG_FILE ./register_endpoints/basic_regs.v -set_global_assignment -name VERILOG_FILE ./register_endpoints/power_regs.v -set_global_assignment -name VERILOG_FILE ./register_endpoints/switch_control.v -set_global_assignment -name VERILOG_FILE ./register_endpoints/dsa_control.v -set_global_assignment -name VERILOG_FILE ./register_endpoints/led_control.v -set_global_assignment -name VERILOG_FILE ./../../../../../lib/wb_spi/rtl/verilog/spi_top.v -set_global_assignment -name VERILOG_FILE ./../../../../../lib/wb_spi/rtl/verilog/spi_clgen.v -set_global_assignment -name VERILOG_FILE ./../../../../../lib/wb_spi/rtl/verilog/spi_shift.v -set_global_assignment -name VERILOG_FILE ./register_endpoints/lo_control.v -set_global_assignment -name VERILOG_FILE ./zbx_cpld_core.v -set_global_assignment -name VERILOG_FILE ../../ctrlport_byte_deserializer.v -set_global_assignment -name VERILOG_FILE ../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v -set_global_assignment -name VERILOG_FILE ../../../cpld/reconfig_engine.v -set_global_assignment -name VERILOG_FILE ../../../../../lib/rfnoc/utils/ctrlport_combiner.v -set_global_assignment -name VERILOG_FILE register_endpoints/atr_controller.v -set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../lib/control/ram_2port_impl.vh -set_global_assignment -name VERILOG_FILE ../../../../../lib/control/ram_2port.v -set_global_assignment -name VERILOG_FILE ../../../../../lib/control/handshake.v -set_global_assignment -name VERILOG_FILE ../../../../../lib/control/pulse_synchronizer.v -set_global_assignment -name VERILOG_FILE ./ctrlport_window.v - -set_global_assignment -name QSYS_FILE ip/flash/on_chip_flash.qsys -set_global_assignment -name QSYS_FILE ip/osc/osc.qsys -set_global_assignment -name QSYS_FILE ../../../cpld/ip/clkctrl/clkctrl.qsys -set_global_assignment -name SOURCE_FILE db/zbx_top_cpld.cmp.rdb - -set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/tx1_path_defaults.hex -set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/tx0_path_defaults.hex -set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/tx_dsa_defaults.hex -set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/rx1_path_defaults.hex -set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/rx0_path_defaults.hex -set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/rx_dsa_defaults.hex - -set_global_assignment -name ENABLE_OCT_DONE OFF -set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE WITH ERAM" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON -set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" - -set_global_assignment -name TOP_LEVEL_ENTITY zbx_top_cpld - - - -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file -- cgit v1.2.3
0x01000 -

FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT

+

FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04

+ +
81920x02000 +

FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08

0x09C00 -

FLASH_PRIMARY_IMAGE_START_ADDR

+

FLASH_PRIMARY_IMAGE_START_ADDR_10M04

+ +
440320x0AC00 +

FLASH_PRIMARY_IMAGE_START_ADDR_10M08

0x127FF -

FLASH_PRIMARY_IMAGE_END_ADDR

+

FLASH_PRIMARY_IMAGE_END_ADDR_10M04

+ +
798710x137FF +

FLASH_PRIMARY_IMAGE_END_ADDR_10M08