From e1ce4565dbc7336ee806adce7c087bda4fcc77ae Mon Sep 17 00:00:00 2001 From: Humberto Jimenez Date: Wed, 27 Oct 2021 14:54:46 -0500 Subject: fpga: x400: Refactor CPLDs build process This commit refactors the X410's CPLDs build process to make it similar to other FPGA targets within the repo. The new process relies on basic Quartus build utilities. Additionally, this commit adds support for an alternative MAX10 CPLD for the motherboard CPLD implementation. Both previous (10M04) and new variant (10M08) are supported concurrently. The images package mapping is updated to reflect these changes. --- .../top/x400/dboards/zbx/cpld/ip/Makefile.inc | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 fpga/usrp3/top/x400/dboards/zbx/cpld/ip/Makefile.inc (limited to 'fpga/usrp3/top/x400/dboards/zbx/cpld/ip/Makefile.inc') diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/Makefile.inc b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/Makefile.inc new file mode 100644 index 000000000..77d9fce18 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/Makefile.inc @@ -0,0 +1,25 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(IP_DIR)/on_chip_flash/Makefile.inc +include $(IP_DIR)/osc/Makefile.inc +include $(IP_DIR)/clkctrl/Makefile.inc + +IP_SRCS = \ +$(IP_ON_CHIP_FLASH_SRCS) \ +$(IP_OSC_SRCS) \ +$(IP_CLKCTRL_SRCS) + + +IP_OUTPUTS = \ +$(IP_ON_CHIP_FLASH_OUTS) \ +$(IP_OSC_OUTS) \ +$(IP_CLKCTRL_OUTS) + + +ip: $(IP_OUTPUTS) + +.PHONY: ip -- cgit v1.2.3