From e1ce4565dbc7336ee806adce7c087bda4fcc77ae Mon Sep 17 00:00:00 2001
From: Humberto Jimenez <humberto.jimenez@ni.com>
Date: Wed, 27 Oct 2021 14:54:46 -0500
Subject: fpga: x400: Refactor CPLDs build process

This commit refactors the X410's CPLDs build process to make it similar to other
FPGA targets within the repo. The new process relies on basic Quartus build
utilities.
Additionally, this commit adds support for an alternative MAX10 CPLD for the
motherboard CPLD implementation. Both previous (10M04) and new variant
(10M08) are supported concurrently. The images package mapping is updated to
reflect these changes.
---
 .../top/x400/cpld/ip/on_chip_flash/.gitignore      |  3 +
 .../top/x400/cpld/ip/on_chip_flash/Makefile.inc    | 16 ++++
 .../x400/cpld/ip/on_chip_flash/on_chip_flash.qsys  | 90 ++++++++++++++++++++++
 3 files changed, 109 insertions(+)
 create mode 100644 fpga/usrp3/top/x400/cpld/ip/on_chip_flash/.gitignore
 create mode 100644 fpga/usrp3/top/x400/cpld/ip/on_chip_flash/Makefile.inc
 create mode 100644 fpga/usrp3/top/x400/cpld/ip/on_chip_flash/on_chip_flash.qsys

(limited to 'fpga/usrp3/top/x400/cpld/ip/on_chip_flash')

diff --git a/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/.gitignore b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/.gitignore
new file mode 100644
index 000000000..585bc126d
--- /dev/null
+++ b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/.gitignore
@@ -0,0 +1,3 @@
+# generate files
+on_chip_flash/
+on_chip_flash.sopcinfo
diff --git a/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/Makefile.inc b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/Makefile.inc
new file mode 100644
index 000000000..fcd8528e6
--- /dev/null
+++ b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/Makefile.inc
@@ -0,0 +1,16 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/quartus_ip_builder.mak
+
+IP_ON_CHIP_FLASH_SRCS = \
+$(IP_BUILD_DIR)/on_chip_flash/on_chip_flash.qsys
+
+IP_ON_CHIP_FLASH_OUTS = \
+$(IP_BUILD_DIR)/on_chip_flash/on_chip_flash.sopcinfo
+
+$(IP_ON_CHIP_FLASH_SRCS) $(IP_ON_CHIP_FLASH_OUTS) : $(IP_DIR)/on_chip_flash/on_chip_flash.qsys
+	$(call BUILD_QUARTUS_IP,on_chip_flash,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR))
diff --git a/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/on_chip_flash.qsys b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/on_chip_flash.qsys
new file mode 100644
index 000000000..4cbe8726a
--- /dev/null
+++ b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/on_chip_flash.qsys
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags="INTERNAL_COMPONENT=true"
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element onchip_flash_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10M04SAU169I7G" />
+ <parameter name="deviceFamily" value="MAX 10" />
+ <parameter name="deviceSpeedGrade" value="7" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="clk" internal="onchip_flash_0.clk" type="clock" dir="end">
+  <port name="clock" internal="clock" />
+ </interface>
+ <interface name="csr" internal="onchip_flash_0.csr" type="avalon" dir="end">
+  <port name="avmm_csr_addr" internal="avmm_csr_addr" />
+  <port name="avmm_csr_read" internal="avmm_csr_read" />
+  <port name="avmm_csr_writedata" internal="avmm_csr_writedata" />
+  <port name="avmm_csr_write" internal="avmm_csr_write" />
+  <port name="avmm_csr_readdata" internal="avmm_csr_readdata" />
+ </interface>
+ <interface name="data" internal="onchip_flash_0.data" type="avalon" dir="end">
+  <port name="avmm_data_addr" internal="avmm_data_addr" />
+  <port name="avmm_data_read" internal="avmm_data_read" />
+  <port name="avmm_data_writedata" internal="avmm_data_writedata" />
+  <port name="avmm_data_write" internal="avmm_data_write" />
+  <port name="avmm_data_readdata" internal="avmm_data_readdata" />
+  <port name="avmm_data_waitrequest" internal="avmm_data_waitrequest" />
+  <port name="avmm_data_readdatavalid" internal="avmm_data_readdatavalid" />
+  <port name="avmm_data_burstcount" internal="avmm_data_burstcount" />
+ </interface>
+ <interface name="nreset" internal="onchip_flash_0.nreset" type="reset" dir="end">
+  <port name="reset_n" internal="reset_n" />
+ </interface>
+ <module
+   name="onchip_flash_0"
+   kind="altera_onchip_flash"
+   version="18.1"
+   enabled="1"
+   autoexport="1">
+  <parameter name="AUTO_CLOCK_RATE" value="0" />
+  <parameter name="CLOCK_FREQUENCY" value="50.0" />
+  <parameter name="CONFIGURATION_MODE">Single Compressed Image</parameter>
+  <parameter name="CONFIGURATION_SCHEME">Internal Configuration</parameter>
+  <parameter name="DATA_INTERFACE" value="Parallel" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="PART_NAME" value="10M04SAU169I7G" />
+  <parameter name="READ_BURST_COUNT" value="8" />
+  <parameter name="READ_BURST_MODE" value="Incrementing" />
+  <parameter name="SECTOR_ACCESS_MODE">Read and write,Read and write,Read and write,Read and write,Read and write</parameter>
+  <parameter name="autoInitializationFileName">$${FILENAME}_onchip_flash_0</parameter>
+  <parameter name="initFlashContent" value="false" />
+  <parameter name="initializationFileName">altera_onchip_flash.hex</parameter>
+  <parameter name="initializationFileNameForSim">altera_onchip_flash.dat</parameter>
+  <parameter name="useNonDefaultInitFile" value="false" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
-- 
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