From 6d3765605262016a80f71e36357f749ea35cbe5a Mon Sep 17 00:00:00 2001
From: Wade Fife <wade.fife@ettus.com>
Date: Tue, 8 Jun 2021 19:40:46 -0500
Subject: fpga: x400: Add support for X410 motherboard FPGA
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Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>
---
 fpga/usrp3/top/x400/constraints/pins/qsfp0_2.xdc | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 fpga/usrp3/top/x400/constraints/pins/qsfp0_2.xdc

(limited to 'fpga/usrp3/top/x400/constraints/pins/qsfp0_2.xdc')

diff --git a/fpga/usrp3/top/x400/constraints/pins/qsfp0_2.xdc b/fpga/usrp3/top/x400/constraints/pins/qsfp0_2.xdc
new file mode 100644
index 000000000..8344b4cb6
--- /dev/null
+++ b/fpga/usrp3/top/x400/constraints/pins/qsfp0_2.xdc
@@ -0,0 +1,21 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#   QSFP28 Port 0 (Lane 2) pin constraints for X410.
+#
+
+###############################################################################
+# Pin constraints for the MGTs (QSFP28 ports)
+###############################################################################
+
+# Bank 131 (Quad X0Y4, Lanes X0Y16-X0Y19)
+# Lane 2 (X0Y18)
+
+set_property PACKAGE_PIN C38  [get_ports {QSFP0_2_RX_P}]
+set_property PACKAGE_PIN C39  [get_ports {QSFP0_2_RX_N}]
+
+set_property PACKAGE_PIN B31  [get_ports {QSFP0_2_TX_P}]
+set_property PACKAGE_PIN B32  [get_ports {QSFP0_2_TX_N}]
-- 
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