From bafa9d95453387814ef25e6b6256ba8db2df612f Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Thu, 23 Jan 2020 16:10:22 -0800 Subject: Merge FPGA repository back into UHD repository MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams Co-authored-by: Andrej Rode Co-authored-by: Ashish Chaudhari Co-authored-by: Ben Hilburn Co-authored-by: Ciro Nishiguchi Co-authored-by: Daniel Jepson Co-authored-by: Derek Kozel Co-authored-by: EJ Kreinar Co-authored-by: Humberto Jimenez Co-authored-by: Ian Buckley Co-authored-by: Jörg Hofrichter Co-authored-by: Jon Kiser Co-authored-by: Josh Blum Co-authored-by: Jonathon Pendlum Co-authored-by: Martin Braun Co-authored-by: Matt Ettus Co-authored-by: Michael West Co-authored-by: Moritz Fischer Co-authored-by: Nick Foster Co-authored-by: Nicolas Cuervo Co-authored-by: Paul Butler Co-authored-by: Paul David Co-authored-by: Ryan Marlow Co-authored-by: Sugandha Gupta Co-authored-by: Sylvain Munaut Co-authored-by: Trung Tran Co-authored-by: Vidush Vishwanath Co-authored-by: Wade Fife --- fpga/usrp3/top/x300/ip/Makefile.inc | 81 + .../top/x300/ip/aurora_64b66b_pcs_pma/Makefile.inc | 34 + .../aurora_64b66b_pcs_pma.xci | 1780 +++++ .../ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v | 329 + .../ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v | 51 + .../x300/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v | 370 + .../top/x300/ip/axi4_dualport_sram/Makefile.inc | 15 + .../ip/axi4_dualport_sram/axi4_dualport_sram.xci | 314 + .../top/x300/ip/axi64_4k_2clk_fifo/Makefile.inc | 15 + .../ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci | 584 ++ .../top/x300/ip/axi64_8k_2clk_fifo/Makefile.inc | 15 + .../ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci | 582 ++ .../x300/ip/axi_intercon_2x64_128_bd/Makefile.inc | 19 + .../axi_intercon_2x64_128_bd.bd | 1326 ++++ .../axi_intercon_2x64_128_bd.bxml | 132 + .../axi_intercon_2x64_128_bd_wrapper.v | 508 ++ fpga/usrp3/top/x300/ip/bootram/Makefile.inc | 15 + fpga/usrp3/top/x300/ip/bootram/bootram.coe | 8194 ++++++++++++++++++++ fpga/usrp3/top/x300/ip/bootram/bootram.xci | 318 + fpga/usrp3/top/x300/ip/bus_clk_gen/Makefile.inc | 15 + fpga/usrp3/top/x300/ip/bus_clk_gen/bus_clk_gen.xci | 786 ++ fpga/usrp3/top/x300/ip/ddr3_32bit/Makefile.inc | 26 + fpga/usrp3/top/x300/ip/ddr3_32bit/ddr3_32bit.xci | 2645 +++++++ .../x300/ip/ddr3_32bit/mig_xc7k325tffg900-2.prj | 163 + .../x300/ip/ddr3_32bit/mig_xc7k410tffg900-2.prj | 163 + fpga/usrp3/top/x300/ip/fifo_4k_2clk/Makefile.inc | 15 + .../top/x300/ip/fifo_4k_2clk/fifo_4k_2clk.xci | 576 ++ .../usrp3/top/x300/ip/fifo_short_2clk/Makefile.inc | 15 + .../x300/ip/fifo_short_2clk/fifo_short_2clk.xci | 578 ++ .../top/x300/ip/input_sample_fifo/Makefile.inc | 15 + .../ip/input_sample_fifo/input_sample_fifo.xci | 575 ++ .../top/x300/ip/one_gig_eth_pcs_pma/Makefile.inc | 50 + .../ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci | 353 + .../one_gig_eth_pcs_pma_clocking.v.patch | 25 + .../one_gig_eth_pcs_pma_support.v.patch | 17 + .../top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.v | 100 + .../x300/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc | 164 + .../ip/one_gig_eth_pcs_pma/one_gige_phy_clk_gen.v | 29 + fpga/usrp3/top/x300/ip/pcie_clk_gen/Makefile.inc | 15 + .../top/x300/ip/pcie_clk_gen/pcie_clk_gen.xci | 752 ++ fpga/usrp3/top/x300/ip/radio_clk_gen/Makefile.inc | 19 + .../top/x300/ip/radio_clk_gen/radio_clk_gen.xci | 755 ++ .../x300/ip/radio_clk_gen/radio_clk_gen.xdc.patch | 4 + .../top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc | 42 + .../ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci | 192 + .../top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v | 249 + .../x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc | 91 + .../ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v | 51 + 48 files changed, 23162 insertions(+) create mode 100644 fpga/usrp3/top/x300/ip/Makefile.inc create mode 100644 fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/Makefile.inc create mode 100644 fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci create mode 100644 fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v create mode 100644 fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v create mode 100644 fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v create mode 100644 fpga/usrp3/top/x300/ip/axi4_dualport_sram/Makefile.inc create mode 100644 fpga/usrp3/top/x300/ip/axi4_dualport_sram/axi4_dualport_sram.xci create mode 100644 fpga/usrp3/top/x300/ip/axi64_4k_2clk_fifo/Makefile.inc create mode 100644 fpga/usrp3/top/x300/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci create mode 100644 fpga/usrp3/top/x300/ip/axi64_8k_2clk_fifo/Makefile.inc create mode 100644 fpga/usrp3/top/x300/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci create mode 100644 fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/Makefile.inc create mode 100755 fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd create mode 100755 fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bxml create mode 100644 fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd_wrapper.v create mode 100644 fpga/usrp3/top/x300/ip/bootram/Makefile.inc create mode 100644 fpga/usrp3/top/x300/ip/bootram/bootram.coe create mode 100644 fpga/usrp3/top/x300/ip/bootram/bootram.xci create mode 100644 fpga/usrp3/top/x300/ip/bus_clk_gen/Makefile.inc create mode 100644 fpga/usrp3/top/x300/ip/bus_clk_gen/bus_clk_gen.xci create mode 100644 fpga/usrp3/top/x300/ip/ddr3_32bit/Makefile.inc create mode 100644 fpga/usrp3/top/x300/ip/ddr3_32bit/ddr3_32bit.xci create mode 100644 fpga/usrp3/top/x300/ip/ddr3_32bit/mig_xc7k325tffg900-2.prj create mode 100644 fpga/usrp3/top/x300/ip/ddr3_32bit/mig_xc7k410tffg900-2.prj create mode 100644 fpga/usrp3/top/x300/ip/fifo_4k_2clk/Makefile.inc create mode 100644 fpga/usrp3/top/x300/ip/fifo_4k_2clk/fifo_4k_2clk.xci create mode 100644 fpga/usrp3/top/x300/ip/fifo_short_2clk/Makefile.inc create mode 100644 fpga/usrp3/top/x300/ip/fifo_short_2clk/fifo_short_2clk.xci create mode 100644 fpga/usrp3/top/x300/ip/input_sample_fifo/Makefile.inc create mode 100644 fpga/usrp3/top/x300/ip/input_sample_fifo/input_sample_fifo.xci create mode 100644 fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/Makefile.inc create mode 100644 fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci create mode 100644 fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch create mode 100644 fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch create mode 100644 fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.v create mode 100644 fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc create mode 100644 fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy_clk_gen.v create mode 100644 fpga/usrp3/top/x300/ip/pcie_clk_gen/Makefile.inc create mode 100644 fpga/usrp3/top/x300/ip/pcie_clk_gen/pcie_clk_gen.xci create mode 100644 fpga/usrp3/top/x300/ip/radio_clk_gen/Makefile.inc create mode 100644 fpga/usrp3/top/x300/ip/radio_clk_gen/radio_clk_gen.xci create mode 100644 fpga/usrp3/top/x300/ip/radio_clk_gen/radio_clk_gen.xdc.patch create mode 100644 fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc create mode 100644 fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci create mode 100644 fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v create mode 100644 fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc create mode 100644 fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v (limited to 'fpga/usrp3/top/x300/ip') diff --git a/fpga/usrp3/top/x300/ip/Makefile.inc b/fpga/usrp3/top/x300/ip/Makefile.inc new file mode 100644 index 000000000..2b53823e4 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/Makefile.inc @@ -0,0 +1,81 @@ +# +# Copyright 2014 Ettus Research +# + +include $(IP_DIR)/axi4_dualport_sram/Makefile.inc +include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi_intercon_2x64_128_bd/Makefile.inc +include $(IP_DIR)/bootram/Makefile.inc +include $(IP_DIR)/bus_clk_gen/Makefile.inc +include $(IP_DIR)/ddr3_32bit/Makefile.inc +include $(IP_DIR)/fifo_4k_2clk/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +include $(IP_DIR)/input_sample_fifo/Makefile.inc +include $(IP_DIR)/one_gig_eth_pcs_pma/Makefile.inc +include $(IP_DIR)/pcie_clk_gen/Makefile.inc +include $(IP_DIR)/radio_clk_gen/Makefile.inc +include $(IP_DIR)/ten_gig_eth_pcs_pma/Makefile.inc +include $(IP_DIR)/aurora_64b66b_pcs_pma/Makefile.inc + +IP_XCI_SRCS = \ +$(IP_AXI64_4K_2CLK_FIFO_SRCS) \ +$(IP_AXI64_8K_2CLK_FIFO_SRCS) \ +$(IP_BOOTRAM_SRCS) \ +$(IP_BUS_CLK_GEN_SRCS) \ +$(IP_FIFO_4K_2CLK_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +$(IP_PCIE_CLK_GEN_SRCS) \ +$(IP_RADIO_CLK_GEN_SRCS) +# $(IP_AXI4_BRAM_SRCS) \ + +BD_SRCS = \ +$(IP_AXI_INTERCON_2X64_128_BD_SRCS) + +IP_ONE_GIGE_PHY_XCI_SRCS = \ +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) \ + +IP_TEN_GIGE_PHY_XCI_SRCS = \ +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) + +IP_AURORA_XCI_SRCS = \ +$(IP_AURORA_64B66B_PCS_PMA_SRCS) + +IP_DRAM_XCI_SRCS = \ +$(IP_DDR3_32BIT_SRCS) + +# Currently unused +# $(IP_INPUT_SAMPLE_FIFO_SRCS) \ +# $(IP_AXI_INTERCON_4X64_128_SRCS) \ +# $(IP_AXI_INTERCON_2X64_128_SRCS) \ + +IP_CODEGEN_SRCS = \ +$(ONE_GIGE_PHY_SRCS) \ +$(TEN_GIGE_PHY_SRCS) + +IP_SYNTH_OUTPUTS = \ +$(IP_AXI64_4K_2CLK_FIFO_OUTS) \ +$(IP_AXI64_8K_2CLK_FIFO_OUTS) \ +$(IP_BOOTRAM_OUTS) \ +$(IP_BUS_CLK_GEN_OUTS) \ +$(IP_FIFO_4K_2CLK_OUTS) \ +$(IP_FIFO_SHORT_2CLK_OUTS) \ +$(IP_ONE_GIG_ETH_PCS_PMA_OUTS) \ +$(IP_PCIE_CLK_GEN_OUTS) \ +$(IP_RADIO_CLK_GEN_OUTS) \ +$(IP_TEN_GIG_ETH_PCS_PMA_OUTS) \ +$(IP_AURORA_64B66B_PCS_PMA_OUTS) +# $(IP_AXI4_BRAM_OUTS) \ + +BD_OUTPUTS = \ +$(IP_AXI_INTERCON_2X64_128_BD_OUTS) + +# Currently unused +# $(IP_INPUT_SAMPLE_FIFO_OUTS) \ +# $(IP_AXI_INTERCON_4X64_128_OUTS) \ +# $(IP_AXI_INTERCON_2X64_128_OUTS) \ + +ip: $(IP_SYNTH_OUTPUTS) $(IP_CODEGEN_SRCS) $(BD_OUTPUTS) + +.PHONY: ip + diff --git a/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/Makefile.inc b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/Makefile.inc new file mode 100644 index 000000000..49e58dbc0 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/Makefile.inc @@ -0,0 +1,34 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma_ex/, \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_clock_module.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_gt_common_wrapper.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_support_reset_logic.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_support.v \ +imports/aurora_64b66b_pcs_pma_cdc_sync_exdes.v \ +imports/aurora_64b66b_pcs_pma_example_axi_to_ll.v \ +imports/aurora_64b66b_pcs_pma_example_ll_to_axi.v \ +imports/aurora_64b66b_pcs_pma_exdes.v \ +imports/aurora_64b66b_pcs_pma_exdes.xdc \ +imports/aurora_64b66b_pcs_pma_frame_check.v \ +imports/aurora_64b66b_pcs_pma_frame_gen.v \ +) + +AURORA_PHY_SRCS = \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_x1.v \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_axis_mac.v \ +$(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS) + +IP_AURORA_64B66B_PCS_PMA_SRCS = $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci + +IP_AURORA_64B66B_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/, \ +aurora_64b66b_pcs_pma.xci.out \ +) + +$(IP_AURORA_64B66B_PCS_PMA_SRCS) $(IP_AURORA_64B66B_PCS_PMA_OUTS) $(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS): $(IP_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci + $(call BUILD_VIVADO_IP,aurora_64b66b_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) diff --git a/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci new file mode 100644 index 000000000..0bfdcb8b0 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci @@ -0,0 +1,1780 @@ + + + xilinx.com + xci + unknown + 1.0 + + + aurora_64b66b_pcs_pma + + + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 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aurora_64b66b_pcs_pma + 78.125 + 20 + AC + AUTO + 0 + PROGRAMMABLE + 800 + false + false + 0 + false + false + Duplex + AXI4_LITE + None + Streaming + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v new file mode 100644 index 000000000..1ee89c030 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v @@ -0,0 +1,329 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_axis_mac #( + parameter PHY_ENDIANNESS = "LITTLE", //{"LITTLE, "BIG"} + parameter PACKET_MODE = 0, + parameter MAX_PACKET_SIZE = 512, + parameter BIST_ENABLED = 1 +) ( + // Clocks and resets + input phy_clk, + input phy_rst, + input sys_clk, + input sys_rst, + input clear, + // PHY TX Interface (Synchronous to phy_clk) + output [63:0] phy_m_axis_tdata, + output phy_m_axis_tvalid, + input phy_m_axis_tready, + // PHY RX Interface (Synchronous to phy_clk) + input [63:0] phy_s_axis_tdata, + input phy_s_axis_tvalid, + // User TX Interface (Synchronous to sys_clk) + input [63:0] s_axis_tdata, + input s_axis_tlast, + input s_axis_tvalid, + output s_axis_tready, + // User RX Interface (Synchronous to sys_clk) + output [63:0] m_axis_tdata, + output m_axis_tlast, + output m_axis_tvalid, + input m_axis_tready, + // PHY Status Inputs (Synchronous to phy_clk) + input channel_up, + input hard_err, + input soft_err, + // Status and Error Outputs (Synchronous to sys_clk) + output [31:0] overruns, + output [31:0] soft_errors, + output reg [31:0] checksum_errors, + output critical_err, + // BIST Interface (Synchronous to sys_clk) + input bist_gen_en, + input [5:0] bist_gen_rate, + input bist_checker_en, + input bist_loopback_en, + output reg bist_checker_locked, + output reg [47:0] bist_checker_samps, + output reg [47:0] bist_checker_errors +); + + // ---------------------------------------------- + // Resets, Clears, Clock crossings + // ---------------------------------------------- + + wire phy_s_axis_tready; // Internal only. The PHY has no backpressure signal. + + // Stay idle if the PHY is not up or if it experiences a fatal error + wire clear_sysclk, clear_phyclk; + synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_phyclk_i ( + .clk(phy_clk), .rst(1'b0 /* no reset */), .in((~channel_up) | hard_err | clear), .out(clear_phyclk)); + synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_sysclk_i ( + .clk(sys_clk), .rst(1'b0 /* no reset */), .in(clear_phyclk), .out(clear_sysclk)); + + // ---------------------------------------------- + // Counters + // ---------------------------------------------- + + reg [31:0] overruns_reg; + reg [31:0] soft_errors_reg; + + // Counter for recoverable errors. For reporting only. + always @(posedge phy_clk) + if (phy_rst | clear_phyclk) + soft_errors_reg <= 32'd0; + else if (soft_err) + soft_errors_reg <= soft_errors_reg + 32'd1; + + // Tag an overrun if the FIFO is full. Samples will get dropped + always @(posedge phy_clk) + if (phy_rst | clear_phyclk) + overruns_reg <= 32'd0; + else if (phy_s_axis_tvalid & ~phy_s_axis_tready) + overruns_reg <= overruns_reg + 32'd1; + + wire [7:0] dummy0; + fifo_short_2clk status_counters_2clk_i ( + .rst(phy_rst), + .wr_clk(phy_clk), .din({8'h00, soft_errors_reg, overruns_reg}), .wr_en(1'b1), .full(), .wr_data_count(), + .rd_clk(sys_clk), .dout({dummy0, soft_errors, overruns}), .rd_en(1'b1), .empty(), .rd_data_count() + ); + + // ---------------------------------------------- + // BIST Wires + // ---------------------------------------------- + + wire [63:0] bist_o_tdata; + wire bist_o_tvalid, bist_o_tready; + wire [63:0] bist_i_tdata; + wire bist_i_tvalid, bist_i_tready; + wire [63:0] loopback_tdata; + wire loopback_tvalid, loopback_tready; + reg bist_gen_en_reg = 1'b0, bist_checker_en_reg = 1'b0, bist_loopback_en_reg = 1'b0; + reg [5:0] bist_gen_rate_reg = 'd0; + + generate if (BIST_ENABLED == 1) begin + // Pipeline control signals + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk) begin + bist_gen_en_reg <= 1'b0; + bist_checker_en_reg <= 1'b0; + bist_loopback_en_reg <= 1'b0; + bist_gen_rate_reg <= 'd0; + end else begin + bist_gen_en_reg <= bist_gen_en; + bist_checker_en_reg <= bist_checker_en; + bist_loopback_en_reg <= bist_loopback_en; + bist_gen_rate_reg <= bist_gen_rate; + end + end + end endgenerate + // ---------------------------------------------- + // RX Data Path + // ---------------------------------------------- + + wire [63:0] i_raw_tdata; + wire i_raw_tvalid, i_raw_tready; + + wire [63:0] i_pip_tdata; + wire i_pip_tvalid, i_pip_tready; + + wire [63:0] i_pkt_tdata; + wire i_pkt_tlast, i_pkt_tvalid, i_pkt_tready; + + wire [63:0] i_gt_tdata; + wire i_gt_tlast, i_gt_tvalid, i_gt_tready; + + wire checksum_err; + + wire [63:0] phy_s_axis_tdata_endian, phy_m_axis_tdata_endian; + + generate if (PHY_ENDIANNESS == "BIG") begin + assign phy_s_axis_tdata_endian = { + phy_s_axis_tdata[7:0], phy_s_axis_tdata[15:8], phy_s_axis_tdata[23:16], phy_s_axis_tdata[31:24], + phy_s_axis_tdata[39:32], phy_s_axis_tdata[47:40], phy_s_axis_tdata[55:48], phy_s_axis_tdata[63:56] + }; + assign phy_m_axis_tdata = { + phy_m_axis_tdata_endian[7:0], phy_m_axis_tdata_endian[15:8], phy_m_axis_tdata_endian[23:16], phy_m_axis_tdata_endian[31:24], + phy_m_axis_tdata_endian[39:32], phy_m_axis_tdata_endian[47:40], phy_m_axis_tdata_endian[55:48], phy_m_axis_tdata_endian[63:56] + }; + end else begin + assign phy_s_axis_tdata_endian = phy_s_axis_tdata; + assign phy_m_axis_tdata = phy_m_axis_tdata_endian; + end endgenerate + + // Large FIFO must be able to run input side at 64b@156MHz to sustain 10Gb Rx. + axi64_4k_2clk_fifo ingress_fifo_i ( + .s_aresetn(~phy_rst), .s_aclk(phy_clk), + .s_axis_tdata(phy_s_axis_tdata_endian), .s_axis_tlast(phy_s_axis_tvalid), .s_axis_tuser(4'h0), + .s_axis_tvalid(phy_s_axis_tvalid), .s_axis_tready(phy_s_axis_tready), .axis_wr_data_count(), + .m_aclk(sys_clk), + .m_axis_tdata(i_raw_tdata), .m_axis_tlast(), .m_axis_tuser(), + .m_axis_tvalid(i_raw_tvalid), .m_axis_tready(i_raw_tready), .axis_rd_data_count() + ); + + // AXI-Flop to ease timing + axi_fifo_flop2 #(.WIDTH(64)) input_pipe_i0 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(i_raw_tdata), .i_tvalid(i_raw_tvalid), .i_tready(i_raw_tready), + .o_tdata(i_pip_tdata), .o_tvalid(i_pip_tvalid), + .o_tready(bist_checker_en_reg ? bist_i_tready : (bist_loopback_en_reg ? loopback_tready : i_pip_tready)), + .space(), .occupied() + ); + + assign bist_i_tdata = i_pip_tdata; + assign bist_i_tvalid = i_pip_tvalid & bist_checker_en_reg; + + assign loopback_tdata = i_pip_tdata; + assign loopback_tvalid = i_pip_tvalid & bist_loopback_en_reg; + + axi_strip_preamble #(.WIDTH(64), .MAX_PKT_SIZE(MAX_PACKET_SIZE)) axi_strip_preamble_i ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(i_pip_tdata), .i_tvalid(i_pip_tvalid & ~bist_checker_en_reg & ~bist_loopback_en_reg), .i_tready(i_pip_tready), + .o_tdata(i_gt_tdata), .o_tlast(i_gt_tlast), .o_tvalid(i_gt_tvalid), .o_tready(i_gt_tready), + .crc_err(checksum_err), .pkt_dropped(), .crit_error(critical_err) + ); + + axi_fifo_flop2 #(.WIDTH(65)) input_pipe_i1 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata({i_gt_tlast, i_gt_tdata}), .i_tvalid(i_gt_tvalid), .i_tready(i_gt_tready), + .o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready), + .space(), .occupied() + ); + + always @(posedge sys_clk) + if (sys_rst | clear_sysclk) + checksum_errors <= 32'd0; + else if (checksum_err) + checksum_errors <= checksum_errors + 32'd1; + + // ---------------------------------------------- + // TX Data Path + // ---------------------------------------------- + + wire [63:0] o_pkt_tdata; + wire o_pkt_tlast, o_pkt_tvalid, o_pkt_tready; + + wire [63:0] o_pip_tdata; + wire o_pip_tvalid, o_pip_tready; + + wire [63:0] o_raw_tdata; + wire o_raw_tvalid, o_raw_tready; + + // AXI-Flop to ease timing + axi_fifo_flop2 #(.WIDTH(65)) output_pipe_i0 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata({s_axis_tlast, s_axis_tdata}), .i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready), + .o_tdata({o_pkt_tlast, o_pkt_tdata}), .o_tvalid(o_pkt_tvalid), .o_tready(o_pkt_tready), + .space(), .occupied() + ); + + // Insert preamble and EOP + axi_add_preamble #(.WIDTH(64)) axi_add_preamble_i ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(o_pkt_tdata), .i_tlast(o_pkt_tlast), .i_tvalid(o_pkt_tvalid), .i_tready(o_pkt_tready), + .o_tdata(o_pip_tdata), .o_tvalid(o_pip_tvalid), .o_tready(o_pip_tready & ~bist_gen_en_reg & ~bist_loopback_en_reg) + ); + + // AXI-Flop to ease timing + axi_fifo_flop2 #(.WIDTH(64)) output_pipe_i1 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(bist_gen_en_reg ? bist_o_tdata : (bist_loopback_en_reg ? loopback_tdata : o_pip_tdata)), + .i_tvalid(bist_gen_en_reg ? bist_o_tvalid : (bist_loopback_en_reg ? loopback_tvalid : o_pip_tvalid)), + .i_tready(o_pip_tready), + .o_tdata(o_raw_tdata), .o_tvalid(o_raw_tvalid), .o_tready(o_raw_tready), + .space(), .occupied() + ); + + assign bist_o_tready = o_pip_tready; + assign loopback_tready = o_pip_tready; + + // Egress FIFO + axi64_4k_2clk_fifo egress_fifo_i ( + .s_aresetn(~phy_rst), .s_aclk(sys_clk), + .s_axis_tdata(o_raw_tdata), .s_axis_tlast(o_raw_tvalid), .s_axis_tuser(4'h0), + .s_axis_tvalid(o_raw_tvalid), .s_axis_tready(o_raw_tready), .axis_wr_data_count(), + .m_aclk(phy_clk), + .m_axis_tdata(phy_m_axis_tdata_endian), .m_axis_tlast(), .m_axis_tuser(), + .m_axis_tvalid(phy_m_axis_tvalid), .m_axis_tready(phy_m_axis_tready), .axis_rd_data_count() + ); + + // ------------------------------------------------- + // BIST: Generator and checker for a LFSR polynomial + // ------------------------------------------------- + localparam LFSR_LEN = 32; + localparam LFSR_SEED = {LFSR_LEN{1'b1}}; + + function [LFSR_LEN-1:0] compute_lfsr_next; + input [LFSR_LEN-1:0] current; + // Maximal length polynomial: x^32 + x^22 + x^2 + x^1 + 1 + compute_lfsr_next = {current[30:0], current[31]^current[21]^current[1]^current[0]}; + endfunction + + function [63:0] lfsr_to_axis; + input [LFSR_LEN-1:0] lfsr; + lfsr_to_axis = {~lfsr, lfsr}; + endfunction + + function [LFSR_LEN-1:0] axis_to_lfsr; + input [63:0] axis; + axis_to_lfsr = axis[LFSR_LEN-1:0]; + endfunction + + generate if (BIST_ENABLED == 1) begin + // Throttle outgoing LFSR to based on the specified rate + // BIST Throughput = sys_clk BW * (bist_gen_rate+1)/64 + reg [5:0] throttle_cnt; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk) + throttle_cnt <= 6'd0; + else if (bist_gen_en_reg) + throttle_cnt <= throttle_cnt + 6'd1; + end + // NOTE: This techinically violates AXIS spec (valid revocation) + assign bist_o_tvalid = bist_gen_en_reg && (throttle_cnt <= bist_gen_rate_reg); + + // Unsynchronized LFSR generator (for BIST output) + reg [LFSR_LEN-1:0] lfsr_gen = LFSR_SEED, lfsr_check = LFSR_SEED; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk | ~bist_gen_en_reg) + lfsr_gen <= LFSR_SEED; + else if (bist_o_tready & bist_o_tvalid) + lfsr_gen <= compute_lfsr_next(lfsr_gen); + end + assign bist_o_tdata = lfsr_to_axis(lfsr_gen); + + // Synchronized LFSR checker (for BIST input) + wire [LFSR_LEN-1:0] lfsr_next = compute_lfsr_next(lfsr_check);; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk | ~bist_checker_en_reg) begin + bist_checker_locked <= 1'b0; + lfsr_check <= LFSR_SEED; + end else if (bist_i_tvalid && bist_i_tready) begin + lfsr_check <= axis_to_lfsr(bist_i_tdata); + if (bist_i_tdata == lfsr_to_axis(LFSR_SEED)) + bist_checker_locked <= 1'b1; + end + end + + // LFSR checker + always @(posedge sys_clk) begin + if (bist_checker_locked) begin + if (bist_i_tvalid & bist_i_tready) begin + bist_checker_samps <= bist_checker_samps + 48'd1; + if (bist_i_tdata != lfsr_to_axis(lfsr_next)) begin + bist_checker_errors <= bist_checker_errors + 48'd1; + end + end + end else begin + bist_checker_samps <= 48'd0; + bist_checker_errors <= 48'd0; + end + end + assign bist_i_tready = 1'b1; + end endgenerate + +endmodule + diff --git a/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v new file mode 100644 index 000000000..9e994aefe --- /dev/null +++ b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v @@ -0,0 +1,51 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_phy_clk_gen +( + input areset, + input refclk_p, + input refclk_n, + + output refclk, + output clk156, + output init_clk +); + + wire clk156_buf; + wire init_clk_buf; + wire clkfbout; + + IBUFDS_GTE2 ibufds_inst ( + .O (refclk), + .ODIV2 (), + .CEB (1'b0), + .I (refclk_p), + .IB (refclk_n) + ); + + BUFG clk156_bufg_inst ( + .I (refclk), + .O (clk156) + ); + + // Divding independent clock by 2 as source for DRP clock + BUFR # ( + .BUFR_DIVIDE ("2") + ) dclk_divide_by_2_buf ( + .I (clk156), + .O (init_clk_buf), + .CE (1'b1), + .CLR (1'b0) + ); + + BUFG dclk_bufg_i ( + .I (init_clk_buf), + .O (init_clk) + ); + +endmodule + + + diff --git a/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v new file mode 100644 index 000000000..c3fc89749 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v @@ -0,0 +1,370 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_phy_x1 #( + parameter SIMULATION = 0 +)( + // Clocks and Resets + input areset, + input refclk, + input init_clk, + output user_clk, + output user_rst, + // GTX Serial I/O + input rx_p, + input rx_n, + output tx_p, + output tx_n, + // AXI4-Stream TX Interface + input [63:0] s_axis_tdata, + input s_axis_tvalid, + output s_axis_tready, + // AXI4-Stream RX Interface + output [63:0] m_axis_tdata, + output m_axis_tvalid, + // AXI4-Lite Config Interface + input [31:0] s_axi_awaddr, + input [31:0] s_axi_araddr, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + input s_axi_awvalid, + input s_axi_rready, + output [31:0] s_axi_rdata, + output s_axi_awready, + output s_axi_wready, + output s_axi_bvalid, + output [1:0] s_axi_bresp, + output [1:0] s_axi_rresp, + input s_axi_bready, + output s_axi_arready, + output s_axi_rvalid, + input s_axi_arvalid, + input s_axi_wvalid, + // Status and Error Reporting Interface + output reg channel_up, + output reg hard_err, + output reg soft_err +); + + //-------------------------------------------------------------- + // Status and Error Signals + //-------------------------------------------------------------- + wire hard_err_i, soft_err_i, channel_up_i, lane_up_i; + always @(posedge user_clk) begin + hard_err <= hard_err_i; + soft_err <= soft_err_i; + channel_up <= channel_up_i && lane_up_i; + end + + //-------------------------------------------------------------- + // Reset and PMA Init Sequence + //-------------------------------------------------------------- + // Requirements from PG074: + // - It is expected that user_clock is stable when the reset_pb signal is applied. + // - During the board power-on sequence, both the pma_init and reset_pb signals are + // expected to be High. INIT_CLK and GT_REFCLK are expected to be stable during + // power-on for the proper functioning of the Aurora 64B/66B core. When both clocks are + // stable, pma_init is deasserted followed by the deassertion of reset_pb. + // - Normal Operation Reset Sequence: + // 1. Assert reset. Wait for a minimum time equal to 128*user_clk's time-period. + // 2. Assert pma_init. Keep pma_init and reset asserted for at least one second to prevent + // the transmission of CC characters and ensure that the remote agent detects a hot plug event. + // 3. Deassert pma_init. + // 4. Deassert reset_pb. + + localparam PWRON_PMA_INIT_CYC = 32'd1024; + localparam SYSRST_ASSERT_CYC = 32'd128; + localparam PMA_INIT_ASSERT_CYC_LOG2 = (SIMULATION == 1) ? 4 : 26; + localparam SYSRST_DEASSERT_CYC = 32'd20; + + wire reset_iclk, pma_init, reset_pb; + wire gt_pll_lock, gt_pll_lock_iclk, mmcm_locked, mmcm_locked_iclk; + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b1) ) input_rst_sync_i ( + .clk(init_clk), .rst(1'b0), .in(areset), .out(reset_iclk) + ); + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) gt_pll_lock_sync_i ( + .clk(init_clk), .rst(1'b0), .in(gt_pll_lock), .out(gt_pll_lock_iclk) + ); + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) mmcm_locked_sync_i ( + .clk(init_clk), .rst(1'b0), .in(mmcm_locked), .out(mmcm_locked_iclk) + ); + + localparam [2:0] RST_ST_PWRON_PMA_INIT = 3'd0; + localparam [2:0] RST_ST_PWRON_PMA_SYSRST = 3'd1; + localparam [2:0] RST_ST_IDLE = 3'd2; + localparam [2:0] RST_ST_SYSRST_PRE = 3'd3; + localparam [2:0] RST_ST_PMA_INIT = 3'd4; + localparam [2:0] RST_ST_SYSRST_POST = 3'd5; + + reg [2:0] rst_state = RST_ST_PWRON_PMA_INIT; + reg [31:0] rst_counter = PWRON_PMA_INIT_CYC; + + always @(posedge init_clk) begin + case (rst_state) + RST_ST_PWRON_PMA_INIT: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_PWRON_PMA_SYSRST; + rst_counter <= SYSRST_DEASSERT_CYC; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_PWRON_PMA_SYSRST: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_IDLE; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_IDLE: begin + if (reset_iclk) begin + rst_state <= RST_ST_SYSRST_PRE; + rst_counter <= SYSRST_ASSERT_CYC; + end + end + RST_ST_SYSRST_PRE: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_PMA_INIT; + rst_counter <= {{(32-PMA_INIT_ASSERT_CYC_LOG2){1'b0}}, {PMA_INIT_ASSERT_CYC_LOG2{1'b1}}}; + end else if (mmcm_locked_iclk) begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_PMA_INIT: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_SYSRST_POST; + rst_counter <= SYSRST_DEASSERT_CYC; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_SYSRST_POST: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_IDLE; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + endcase + end + + assign reset_pb = (rst_state != RST_ST_IDLE); + assign pma_init = (rst_state == RST_ST_PMA_INIT || rst_state == RST_ST_PWRON_PMA_INIT); + + //-------------------------------------------------------------- + // Clocking + //-------------------------------------------------------------- + + wire tx_out_clk, tx_out_clk_bufg; + wire sync_clk_i; + wire user_clk_i; + wire mmcm_fb_clk; + wire sync_clk; + + localparam MULT = 10; + localparam DIVIDE = 5; + localparam CLK_PERIOD = 3.103; + localparam OUT0_DIVIDE = 4; + localparam OUT1_DIVIDE = 2; + localparam OUT2_DIVIDE = 6; + localparam OUT3_DIVIDE = 8; + + MMCME2_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (DIVIDE), + .CLKFBOUT_MULT_F (MULT), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (OUT0_DIVIDE), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (CLK_PERIOD), + .CLKOUT1_DIVIDE (OUT1_DIVIDE), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (OUT2_DIVIDE), + .CLKOUT2_PHASE (0.000), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKOUT3_DIVIDE (OUT3_DIVIDE), + .CLKOUT3_PHASE (0.000), + .CLKOUT3_DUTY_CYCLE (0.500), + .CLKOUT3_USE_FINE_PS ("FALSE"), + .REF_JITTER1 (0.010) + ) mmcm_adv_inst ( + .CLKFBOUT (mmcm_fb_clk), + .CLKFBOUTB (), + .CLKOUT0 (user_clk_i), + .CLKOUT0B (), + .CLKOUT1 (sync_clk_i), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (mmcm_fb_clk), + .CLKIN1 (tx_out_clk_bufg), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (mmcm_locked), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (!gt_pll_lock) + ); + + // BUFG for the feedback clock. The feedback signal is phase aligned to the input + // and must come from the CLK0 or CLK2X output of the PLL. In this case, we use + // the CLK0 output. + BUFG txout_clock_net_i ( + .I(tx_out_clk), + .O(tx_out_clk_bufg) + ); + BUFG user_clk_net_i ( + .I(user_clk_i), + .O(user_clk) + ); + BUFG sync_clock_net_i ( + .I(sync_clk_i), + .O(sync_clk) + ); + + //-------------------------------------------------------------- + // GT Common + //-------------------------------------------------------------- + + wire gt_qpllclk_quad1_i; + wire gt_qpllrefclk_quad1_i; + wire gt_to_common_qpllreset_i; + wire gt_qpllrefclklost_i; + wire gt_qplllock_i; + + wire [7:0] qpll_drpaddr_in_i = 8'h0; + wire [15:0] qpll_drpdi_in_i = 16'h0; + wire qpll_drpen_in_i = 1'b0; + wire qpll_drpwe_in_i = 1'b0; + wire [15:0] qpll_drpdo_out_i; + wire qpll_drprdy_out_i; + + aurora_64b66b_pcs_pma_gt_common_wrapper gt_common_support ( + .gt_qpllclk_quad1_out (gt_qpllclk_quad1_i), + .gt_qpllrefclk_quad1_out (gt_qpllrefclk_quad1_i), + .GT0_GTREFCLK0_COMMON_IN (refclk), + //----------------------- Common Block - QPLL Ports ------------------------ + .GT0_QPLLLOCK_OUT (gt_qplllock_i), + .GT0_QPLLRESET_IN (gt_to_common_qpllreset_i), + .GT0_QPLLLOCKDETCLK_IN (init_clk), + .GT0_QPLLREFCLKLOST_OUT (gt_qpllrefclklost_i), + //---------------------- Common DRP Ports ---------------------- + .qpll_drpaddr_in (qpll_drpaddr_in_i), + .qpll_drpdi_in (qpll_drpdi_in_i), + .qpll_drpclk_in (init_clk), + .qpll_drpdo_out (qpll_drpdo_out_i), + .qpll_drprdy_out (qpll_drprdy_out_i), + .qpll_drpen_in (qpll_drpen_in_i), + .qpll_drpwe_in (qpll_drpwe_in_i) + ); + + //-------------------------------------------------------------- + // IP Instantiation + //-------------------------------------------------------------- + + wire gt_rxcdrovrden_i = 1'b0; + wire [2:0] loopback_i = 3'b000; + wire power_down_i = 1'b0; + + aurora_64b66b_pcs_pma aurora_64b66b_pcs_pma_i ( + .refclk1_in (refclk), + // TX AXI4-S Interface + .s_axi_tx_tdata (s_axis_tdata), + .s_axi_tx_tvalid (s_axis_tvalid), + .s_axi_tx_tready (s_axis_tready), + // RX AXI4-S Interface + .m_axi_rx_tdata (m_axis_tdata), + .m_axi_rx_tvalid (m_axis_tvalid), + // GTX Serial I/O + .rxp (rx_p), + .rxn (rx_n), + .txp (tx_p), + .txn (tx_n), + // Status and Error + .hard_err (hard_err_i), + .soft_err (soft_err_i), + .channel_up (channel_up_i), + .lane_up (lane_up_i), + // System Interface + .mmcm_not_locked (!mmcm_locked), + .user_clk (user_clk), + .sync_clk (sync_clk), + .reset_pb (reset_pb), + .gt_rxcdrovrden_in (gt_rxcdrovrden_i), + .power_down (power_down_i), + .loopback (loopback_i), + .pma_init (pma_init), + .gt_pll_lock (gt_pll_lock), + .drp_clk_in (init_clk), + .gt_qpllclk_quad1_in (gt_qpllclk_quad1_i), + .gt_qpllrefclk_quad1_in (gt_qpllrefclk_quad1_i), + .gt_to_common_qpllreset_out(gt_to_common_qpllreset_i), + .gt_qplllock_in (gt_qplllock_i), + .gt_qpllrefclklost_in (gt_qpllrefclklost_i), + // AXI4-Lite config + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bresp (s_axi_bresp), + .s_axi_bready (s_axi_bready), + .s_axi_araddr (s_axi_araddr), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + .s_axi_rdata (s_axi_rdata), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rresp (s_axi_rresp), + .s_axi_rready (s_axi_rready), + // GTXE2 COMMON DRP Ports + .qpll_drpaddr_in (qpll_drpaddr_in_i), + .qpll_drpdi_in (qpll_drpdi_in_i), + .qpll_drpdo_out (), + .qpll_drprdy_out (), + .qpll_drpen_in (qpll_drpen_in_i), + .qpll_drpwe_in (qpll_drpwe_in_i), + .init_clk (init_clk), + .link_reset_out (), + .sys_reset_out (user_rst), + .tx_out_clk (tx_out_clk) + ); + + endmodule diff --git a/fpga/usrp3/top/x300/ip/axi4_dualport_sram/Makefile.inc b/fpga/usrp3/top/x300/ip/axi4_dualport_sram/Makefile.inc new file mode 100644 index 000000000..8fe97ec5a --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi4_dualport_sram/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI4_BRAM_SRCS = $(IP_BUILD_DIR)/axi4_dualport_sram/axi4_dualport_sram.xci + +IP_AXI4_BRAM_OUTS = $(addprefix $(IP_BUILD_DIR)/axi4_dualport_sram/, \ +axi4_dualport_sram.xci.out \ +synth/axi4_dualport_sram.vhd \ +) + +$(IP_AXI4_BRAM_SRCS) $(IP_AXI4_BRAM_OUTS) : $(IP_DIR)/axi4_dualport_sram/axi4_dualport_sram.xci + $(call BUILD_VIVADO_IP,axi4_dualport_sram,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/axi4_dualport_sram/axi4_dualport_sram.xci b/fpga/usrp3/top/x300/ip/axi4_dualport_sram/axi4_dualport_sram.xci new file mode 100644 index 000000000..f06d744aa --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi4_dualport_sram/axi4_dualport_sram.xci @@ -0,0 +1,314 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi4_dualport_sram + + + 4096 + 32 + 0 + 0 + 0 + + 64 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 256 + 2 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + + 64 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 256 + 2 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0.000 + 0 + 18 + 18 + 1 + 1 + 0 + 1 + 8 + 1 + 0 + 512 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 42.036212 mW + kintex7 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + axi4_dualport_sram.mem + no_coe_file_loaded + 1 + 0 + 1 + 0 + 1 + 262144 + 262144 + 1 + 1 + 64 + 64 + 0 + 0 + CE + CE + ALL + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 8 + 8 + 262144 + 262144 + READ_FIRST + READ_FIRST + 64 + 64 + kintex7 + 1 + Memory_Slave + AXI4_Full + false + Minimum_Area + true + 8 + NONE + no_coe_file_loaded + ALL + axi4_dualport_sram + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Use_ENB_Pin + Single_Bit_Error_Injection + false + AXI4 + false + no_Mem_file_loaded + Simple_Dual_Port_RAM + READ_FIRST + READ_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 0 + 8kx2 + false + false + 1 + 1 + 64 + 64 + false + false + false + false + 0 + false + false + CE + CE + ASYNC + true + true + false + false + false + false + true + 262144 + 64 + 64 + No_ECC + false + false + false + Stand_Alone + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/axi64_4k_2clk_fifo/Makefile.inc b/fpga/usrp3/top/x300/ip/axi64_4k_2clk_fifo/Makefile.inc new file mode 100644 index 000000000..75bdf99c3 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi64_4k_2clk_fifo/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI64_4K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + +IP_AXI64_4K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \ +axi64_4k_2clk_fifo.xci.out \ +synth/axi64_4k_2clk_fifo.vhd \ +) + +$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + $(call BUILD_VIVADO_IP,axi64_4k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci b/fpga/usrp3/top/x300/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci new file mode 100644 index 000000000..3747f059f --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci @@ -0,0 +1,584 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi64_4k_2clk_fifo + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 64 + 1 + 1 + 8 + 8 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 10 + BlankString + 18 + 69 + 32 + 64 + 32 + 64 + 2 + 0 + 18 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintex7 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 12 + 11 + 12 + 11 + 12 + 0 + 1 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 4kx4 + 512x72 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 509 + 13 + 1021 + 13 + 1021 + 13 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1022 + 511 + 15 + 1023 + 15 + 1023 + 15 + 1021 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 512 + 16 + 1024 + 16 + 1024 + 16 + 1 + 10 + 9 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Independent_Clock + axi64_4k_2clk_fifo + 64 + false + 10 + false + false + 0 + 2 + 509 + 13 + 1021 + 13 + 1021 + 13 + 3 + false + false + true + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + true + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Common_Clock_Block_RAM + 1 + 1022 + 511 + 15 + 1023 + 15 + 1023 + 15 + 1021 + false + false + false + 0 + AXI_STREAM + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 18 + 1024 + 512 + 16 + 1024 + 16 + 1024 + 16 + false + 18 + 1024 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 8 + 0 + 0 + 8 + 8 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/axi64_8k_2clk_fifo/Makefile.inc b/fpga/usrp3/top/x300/ip/axi64_8k_2clk_fifo/Makefile.inc new file mode 100644 index 000000000..647ca003b --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi64_8k_2clk_fifo/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI64_8K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci + +IP_AXI64_8K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/, \ +axi64_8k_2clk_fifo.xci.out \ +synth/axi64_8k_2clk_fifo.vhd \ +) + +$(IP_AXI64_8K_2CLK_FIFO_SRCS) $(IP_AXI64_8K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci + $(call BUILD_VIVADO_IP,axi64_8k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci b/fpga/usrp3/top/x300/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci new file mode 100644 index 000000000..8c3264cb7 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci @@ -0,0 +1,582 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi64_8k_2clk_fifo + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 64 + 1 + 1 + 8 + 8 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 10 + BlankString + 18 + 69 + 32 + 64 + 32 + 64 + 2 + 0 + 18 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintex7 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 12 + 11 + 12 + 11 + 12 + 0 + 1 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 4kx4 + 1kx36 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 1021 + 13 + 1021 + 13 + 1021 + 13 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1022 + 1023 + 15 + 1023 + 15 + 1023 + 15 + 1021 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 10 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Independent_Clock + axi64_8k_2clk_fifo + 64 + false + 10 + false + false + 0 + 2 + 1021 + 13 + 1021 + 13 + 1021 + 13 + 3 + false + false + true + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + true + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Common_Clock_Block_RAM + 1 + 1022 + 1023 + 15 + 1023 + 15 + 1023 + 15 + 1021 + false + false + false + 0 + AXI_STREAM + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 18 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 18 + 1024 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 8 + 0 + 0 + 8 + 8 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/Makefile.inc b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/Makefile.inc new file mode 100644 index 000000000..51dd6135e --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/Makefile.inc @@ -0,0 +1,19 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCON_2X64_128_BD_SRCS = $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd \ +$(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bxml \ +$(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd_wrapper.v + +BD_AXI_INTERCON_2X64_128_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/, \ +axi_intercon_2x64_128_bd.bd.out \ +axi_intercon_2x64_128_bd_ooc.xdc \ +) + +# The cp below is a workaround for a Vivado issue where it is pulling in wrong sources +$(IP_AXI_INTERCON_2X64_128_BD_SRCS) $(IP_AXI_INTERCON_2X64_128_BD_OUTS) : $(IP_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd + $(call BUILD_VIVADO_BD,axi_intercon_2x64_128_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) + cp -f $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/synth/axi_intercon_2x64_128_bd.v $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/hdl/axi_intercon_2x64_128_bd.v diff --git a/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd new file mode 100755 index 000000000..962d94246 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd @@ -0,0 +1,1326 @@ + + + + + xilinx.com + BlockDiagram + axi_intercon_2x64_128_bd + 1.00.a + + + isTop + true + + + + + S01_AXI + + + + + + DATA_WIDTH + 64 + + + + + + + + PROTOCOL + AXI4 + + + + + + + + FREQ_HZ + 100000000 + + + + + + + + ID_WIDTH + 1 + + + + + + + + ADDR_WIDTH + 32 + + + + + + + + AWUSER_WIDTH + 0 + + + + + + + + ARUSER_WIDTH + 0 + + + + + + + + WUSER_WIDTH + 0 + + + + + + + + RUSER_WIDTH + 0 + + + + + + + + BUSER_WIDTH + 0 + + + + + + + + READ_WRITE_MODE + READ_WRITE + + + + + + + + HAS_BURST + 1 + + + + + + + + HAS_LOCK + 1 + + + + + + + + HAS_PROT + 1 + + + + + + + + HAS_CACHE + 1 + + + + + + + + HAS_QOS + 1 + + + + + + + + HAS_REGION + 1 + + + + + + + + HAS_WSTRB + 1 + + + + + + + + HAS_BRESP + 1 + + + + + + + + HAS_RRESP + 1 + + + + + + + + SUPPORTS_NARROW_BURST + 1 + + + + + + + + NUM_READ_OUTSTANDING + 2 + + + + + + + + NUM_WRITE_OUTSTANDING + 2 + + + + + + + + MAX_BURST_LENGTH + 256 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_S01_ACLK + + + + + + + + + + S00_AXI + + + + + + DATA_WIDTH + 64 + + + + + + + + PROTOCOL + AXI4 + + + + + + + + FREQ_HZ + 1000000000 + + + + + + + + ID_WIDTH + 1 + + + + + + + + ADDR_WIDTH + 32 + + + + + + + + AWUSER_WIDTH + 0 + + + + + + + + ARUSER_WIDTH + 0 + + + + + + + + WUSER_WIDTH + 0 + + + + + + + + RUSER_WIDTH + 0 + + + + + + + + BUSER_WIDTH + 0 + + + + + + + + READ_WRITE_MODE + READ_WRITE + + + + + + + + HAS_BURST + 1 + + + + + + + + HAS_LOCK + 1 + + + + + + + + HAS_PROT + 1 + + + + + + + + HAS_CACHE + 1 + + + + + + + + HAS_QOS + 1 + + + + + + + + HAS_REGION + 1 + + + + + + + + HAS_WSTRB + 1 + + + + + + + + HAS_BRESP + 1 + + + + + + + + HAS_RRESP + 1 + + + + + + + + SUPPORTS_NARROW_BURST + 1 + + + + + + + + NUM_READ_OUTSTANDING + 2 + + + + + + + + NUM_WRITE_OUTSTANDING + 2 + + + + + + + + MAX_BURST_LENGTH + 256 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_S00_ACLK + + + + + + + + + + M00_AXI + + + + + + DATA_WIDTH + 256 + + + + + + + + PROTOCOL + AXI4 + + + + + + + + FREQ_HZ + 100000000 + + + + + + + + ID_WIDTH + 1 + + + + + + + + ADDR_WIDTH + 32 + + + + + + + + AWUSER_WIDTH + 0 + + + + + + + + ARUSER_WIDTH + 0 + + + + + + + + WUSER_WIDTH + 0 + + + + + + + + RUSER_WIDTH + 0 + + + + + + + + BUSER_WIDTH + 0 + + + + + + + + READ_WRITE_MODE + READ_WRITE + + + + + + + + HAS_BURST + 1 + + + + + + + + HAS_LOCK + 1 + + + + + + + + HAS_PROT + 1 + + + + + + + + HAS_CACHE + 1 + + + + + + + + HAS_QOS + 1 + + + + + + + + HAS_REGION + 1 + + + + + + + + HAS_WSTRB + 1 + + + + + + + + HAS_BRESP + 1 + + + + + + + + HAS_RRESP + 1 + + + + + + + + SUPPORTS_NARROW_BURST + 1 + + + + + + + + NUM_READ_OUTSTANDING + 2 + + + + + + + + NUM_WRITE_OUTSTANDING + 2 + + + + + + + + MAX_BURST_LENGTH + 256 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_M00_ACLK + + + + + + + + + + CLK.S00_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S00_AXI_ACLK + + + + + + FREQ_HZ + 1000000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_S00_ACLK + + + + + + + + ASSOCIATED_BUSIF + S00_AXI + + + + + + + + ASSOCIATED_RESET + S00_AXI_ARESETN + + + + + + + + + + RST.S00_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S00_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + CLK.S01_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S01_AXI_ACLK + + + + + + FREQ_HZ + 100000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_S01_ACLK + + + + + + + + ASSOCIATED_BUSIF + S01_AXI + + + + + + + + ASSOCIATED_RESET + S01_AXI_ARESETN + + + + + + + + + + RST.S01_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S01_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + CLK.M00_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + M00_AXI_ACLK + + + + + + FREQ_HZ + 100000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_M00_ACLK + + + + + + + + ASSOCIATED_BUSIF + M00_AXI + + + + + + + + ASSOCIATED_RESET + M00_AXI_ARESETN + + + + + + + + + + RST.M00_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + M00_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + S00_AXI_ACLK + + in + + + + S00_AXI_ARESETN + + in + + + + S01_AXI_ACLK + + in + + + + S01_AXI_ARESETN + + in + + + + M00_AXI_ACLK + + in + + + + M00_AXI_ARESETN + + in + + + + + + + S01_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x02000000 + 32M + + + + + S00_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 32M + + + + + + + M00_AXI + + Reg + 0 + 64K + 32 + register + + + + + + + xilinx.com + BlockDiagram + axi_intercon_2x64_128_bd_imp + 1.00.a + + + s00_width_conv + + + axi_intercon_2x64_128_bd_s00_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + s01_width_conv + + + axi_intercon_2x64_128_bd_s01_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + xbar + + + axi_intercon_2x64_128_bd_xbar_0 + 2 + 1 + 2 + 256 + 1 + 0x00000001 + 0x00000002 + 0x00000003 + 0x00000004 + 0x00000005 + 0x00000006 + 0x00000007 + 0x00000008 + 0x00000009 + 0x0000000a + 0x0000000b + 0x0000000c + 0x0000000d + 0x0000000e + 0x0000000f + + + + m00_rs + + + axi_intercon_2x64_128_bd_m00_rs_0 + 1 + 1 + 1 + + + + s01_rs_0 + + + axi_intercon_2x64_128_bd_s01_rs_0_0 + 1 + 1 + 1 + 1 + 1 + + + + s00_rs_0 + + + axi_intercon_2x64_128_bd_s00_rs_0_0 + 1 + 1 + 1 + 1 + 1 + + + + s00_rs_1 + + + axi_intercon_2x64_128_bd_s00_rs_1_0 + 1 + 1 + 1 + 1 + 1 + + + + s01_rs_1 + + + axi_intercon_2x64_128_bd_s01_rs_1_0 + 1 + 1 + 1 + 1 + 1 + + + + + + xbar_M00_AXI + + + + + s01_rs_M_AXI + + + + + s00_rs_M_AXI + + + + + s00_width_conv_M_AXI + + + + + s01_width_conv_M_AXI + + + + + s00_rs_1_M_AXI + + + + + s01_rs_1_M_AXI + + + + + + + M00_AXI_ACLK_1 + + + + + + + + + + M00_AXI_ARESETN_1 + + + + + + + + + + S01_AXI_ACLK_1 + + + + + + S01_AXI_ARESETN_1 + + + + + + S00_AXI_ACLK_1 + + + + + + S00_AXI_ARESETN_1 + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bxml b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bxml new file mode 100755 index 000000000..e26003603 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bxml @@ -0,0 +1,132 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd_wrapper.v b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd_wrapper.v new file mode 100644 index 000000000..0a6fbf6cf --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd_wrapper.v @@ -0,0 +1,508 @@ +//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015 +//Date : Mon Oct 24 19:58:35 2016 +//Host : ubuntu-VM running 64-bit Ubuntu 14.04.5 LTS +//Command : generate_target axi_intercon_2x64_128_bd_wrapper.bd +//Design : axi_intercon_2x64_128_bd_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module axi_intercon_2x64_128_bd_wrapper + (M00_AXI_ACLK, + M00_AXI_ARESETN, + M00_AXI_ARADDR, + M00_AXI_ARBURST, + M00_AXI_ARCACHE, + M00_AXI_ARID, + M00_AXI_ARLEN, + M00_AXI_ARLOCK, + M00_AXI_ARPROT, + M00_AXI_ARQOS, + M00_AXI_ARREADY, + M00_AXI_ARREGION, + M00_AXI_ARSIZE, + M00_AXI_ARVALID, + M00_AXI_AWADDR, + M00_AXI_AWBURST, + M00_AXI_AWCACHE, + M00_AXI_AWID, + M00_AXI_AWLEN, + M00_AXI_AWLOCK, + M00_AXI_AWPROT, + M00_AXI_AWQOS, + M00_AXI_AWREADY, + M00_AXI_AWREGION, + M00_AXI_AWSIZE, + M00_AXI_AWVALID, + M00_AXI_BID, + M00_AXI_BREADY, + M00_AXI_BRESP, + M00_AXI_BVALID, + M00_AXI_RDATA, + M00_AXI_RID, + M00_AXI_RLAST, + M00_AXI_RREADY, + M00_AXI_RRESP, + M00_AXI_RVALID, + M00_AXI_WDATA, + M00_AXI_WLAST, + M00_AXI_WREADY, + M00_AXI_WSTRB, + M00_AXI_WVALID, + S00_AXI_ACLK, + S00_AXI_ARESETN, + S00_AXI_ARADDR, + S00_AXI_ARBURST, + S00_AXI_ARCACHE, + S00_AXI_ARID, + S00_AXI_ARLEN, + S00_AXI_ARLOCK, + S00_AXI_ARPROT, + S00_AXI_ARQOS, + S00_AXI_ARREADY, + S00_AXI_ARREGION, + S00_AXI_ARSIZE, + S00_AXI_ARVALID, + S00_AXI_AWADDR, + S00_AXI_AWBURST, + S00_AXI_AWCACHE, + S00_AXI_AWID, + S00_AXI_AWLEN, + S00_AXI_AWLOCK, + S00_AXI_AWPROT, + S00_AXI_AWQOS, + S00_AXI_AWREADY, + S00_AXI_AWREGION, + S00_AXI_AWSIZE, + S00_AXI_AWVALID, + S00_AXI_BID, + S00_AXI_BREADY, + S00_AXI_BRESP, + S00_AXI_BVALID, + S00_AXI_RDATA, + S00_AXI_RID, + S00_AXI_RLAST, + S00_AXI_RREADY, + S00_AXI_RRESP, + S00_AXI_RVALID, + S00_AXI_WDATA, + S00_AXI_WLAST, + S00_AXI_WREADY, + S00_AXI_WSTRB, + S00_AXI_WVALID, + S01_AXI_ACLK, + S01_AXI_ARESETN, + S01_AXI_ARADDR, + S01_AXI_ARBURST, + S01_AXI_ARCACHE, + S01_AXI_ARID, + S01_AXI_ARLEN, + S01_AXI_ARLOCK, + S01_AXI_ARPROT, + S01_AXI_ARQOS, + S01_AXI_ARREADY, + S01_AXI_ARREGION, + S01_AXI_ARSIZE, + S01_AXI_ARVALID, + S01_AXI_AWADDR, + S01_AXI_AWBURST, + S01_AXI_AWCACHE, + S01_AXI_AWID, + S01_AXI_AWLEN, + S01_AXI_AWLOCK, + S01_AXI_AWPROT, + S01_AXI_AWQOS, + S01_AXI_AWREADY, + S01_AXI_AWREGION, + S01_AXI_AWSIZE, + S01_AXI_AWVALID, + S01_AXI_BID, + S01_AXI_BREADY, + S01_AXI_BRESP, + S01_AXI_BVALID, + S01_AXI_RDATA, + S01_AXI_RID, + S01_AXI_RLAST, + S01_AXI_RREADY, + S01_AXI_RRESP, + S01_AXI_RVALID, + S01_AXI_WDATA, + S01_AXI_WLAST, + S01_AXI_WREADY, + S01_AXI_WSTRB, + S01_AXI_WVALID); + input M00_AXI_ACLK; + input M00_AXI_ARESETN; + output [31:0]M00_AXI_ARADDR; + output [1:0]M00_AXI_ARBURST; + output [3:0]M00_AXI_ARCACHE; + output [0:0]M00_AXI_ARID; + output [7:0]M00_AXI_ARLEN; + output [0:0]M00_AXI_ARLOCK; + output [2:0]M00_AXI_ARPROT; + output [3:0]M00_AXI_ARQOS; + input M00_AXI_ARREADY; + output [3:0]M00_AXI_ARREGION; + output [2:0]M00_AXI_ARSIZE; + output M00_AXI_ARVALID; + output [31:0]M00_AXI_AWADDR; + output [1:0]M00_AXI_AWBURST; + output [3:0]M00_AXI_AWCACHE; + output [0:0]M00_AXI_AWID; + output [7:0]M00_AXI_AWLEN; + output [0:0]M00_AXI_AWLOCK; + output [2:0]M00_AXI_AWPROT; + output [3:0]M00_AXI_AWQOS; + input M00_AXI_AWREADY; + output [3:0]M00_AXI_AWREGION; + output [2:0]M00_AXI_AWSIZE; + output M00_AXI_AWVALID; + input [0:0]M00_AXI_BID; + output M00_AXI_BREADY; + input [1:0]M00_AXI_BRESP; + input M00_AXI_BVALID; + input [255:0]M00_AXI_RDATA; + input [0:0]M00_AXI_RID; + input M00_AXI_RLAST; + output M00_AXI_RREADY; + input [1:0]M00_AXI_RRESP; + input M00_AXI_RVALID; + output [255:0]M00_AXI_WDATA; + output M00_AXI_WLAST; + input M00_AXI_WREADY; + output [31:0]M00_AXI_WSTRB; + output M00_AXI_WVALID; + input S00_AXI_ACLK; + input S00_AXI_ARESETN; + input [31:0]S00_AXI_ARADDR; + input [1:0]S00_AXI_ARBURST; + input [3:0]S00_AXI_ARCACHE; + input [0:0]S00_AXI_ARID; + input [7:0]S00_AXI_ARLEN; + input [0:0]S00_AXI_ARLOCK; + input [2:0]S00_AXI_ARPROT; + input [3:0]S00_AXI_ARQOS; + output S00_AXI_ARREADY; + input [3:0]S00_AXI_ARREGION; + input [2:0]S00_AXI_ARSIZE; + input S00_AXI_ARVALID; + input [31:0]S00_AXI_AWADDR; + input [1:0]S00_AXI_AWBURST; + input [3:0]S00_AXI_AWCACHE; + input [0:0]S00_AXI_AWID; + input [7:0]S00_AXI_AWLEN; + input [0:0]S00_AXI_AWLOCK; + input [2:0]S00_AXI_AWPROT; + input [3:0]S00_AXI_AWQOS; + output S00_AXI_AWREADY; + input [3:0]S00_AXI_AWREGION; + input [2:0]S00_AXI_AWSIZE; + input S00_AXI_AWVALID; + output [0:0]S00_AXI_BID; + input S00_AXI_BREADY; + output [1:0]S00_AXI_BRESP; + output S00_AXI_BVALID; + output [63:0]S00_AXI_RDATA; + output [0:0]S00_AXI_RID; + output S00_AXI_RLAST; + input S00_AXI_RREADY; + output [1:0]S00_AXI_RRESP; + output S00_AXI_RVALID; + input [63:0]S00_AXI_WDATA; + input S00_AXI_WLAST; + output S00_AXI_WREADY; + input [7:0]S00_AXI_WSTRB; + input S00_AXI_WVALID; + input S01_AXI_ACLK; + input S01_AXI_ARESETN; + input [31:0]S01_AXI_ARADDR; + input [1:0]S01_AXI_ARBURST; + input [3:0]S01_AXI_ARCACHE; + input [0:0]S01_AXI_ARID; + input [7:0]S01_AXI_ARLEN; + input [0:0]S01_AXI_ARLOCK; + input [2:0]S01_AXI_ARPROT; + input [3:0]S01_AXI_ARQOS; + output S01_AXI_ARREADY; + input [3:0]S01_AXI_ARREGION; + input [2:0]S01_AXI_ARSIZE; + input S01_AXI_ARVALID; + input [31:0]S01_AXI_AWADDR; + input [1:0]S01_AXI_AWBURST; + input [3:0]S01_AXI_AWCACHE; + input [0:0]S01_AXI_AWID; + input [7:0]S01_AXI_AWLEN; + input [0:0]S01_AXI_AWLOCK; + input [2:0]S01_AXI_AWPROT; + input [3:0]S01_AXI_AWQOS; + output S01_AXI_AWREADY; + input [3:0]S01_AXI_AWREGION; + input [2:0]S01_AXI_AWSIZE; + input S01_AXI_AWVALID; + output [0:0]S01_AXI_BID; + input S01_AXI_BREADY; + output [1:0]S01_AXI_BRESP; + output S01_AXI_BVALID; + output [63:0]S01_AXI_RDATA; + output [0:0]S01_AXI_RID; + output S01_AXI_RLAST; + input S01_AXI_RREADY; + output [1:0]S01_AXI_RRESP; + output S01_AXI_RVALID; + input [63:0]S01_AXI_WDATA; + input S01_AXI_WLAST; + output S01_AXI_WREADY; + input [7:0]S01_AXI_WSTRB; + input S01_AXI_WVALID; + + wire M00_AXI_ACLK; + wire M00_AXI_ARESETN; + wire [31:0]M00_AXI_ARADDR; + wire [1:0]M00_AXI_ARBURST; + wire [3:0]M00_AXI_ARCACHE; + wire [0:0]M00_AXI_ARID; + wire [7:0]M00_AXI_ARLEN; + wire [0:0]M00_AXI_ARLOCK; + wire [2:0]M00_AXI_ARPROT; + wire [3:0]M00_AXI_ARQOS; + wire M00_AXI_ARREADY; + wire [3:0]M00_AXI_ARREGION; + wire [2:0]M00_AXI_ARSIZE; + wire M00_AXI_ARVALID; + wire [31:0]M00_AXI_AWADDR; + wire [1:0]M00_AXI_AWBURST; + wire [3:0]M00_AXI_AWCACHE; + wire [0:0]M00_AXI_AWID; + wire [7:0]M00_AXI_AWLEN; + wire [0:0]M00_AXI_AWLOCK; + wire [2:0]M00_AXI_AWPROT; + wire [3:0]M00_AXI_AWQOS; + wire M00_AXI_AWREADY; + wire [3:0]M00_AXI_AWREGION; + wire [2:0]M00_AXI_AWSIZE; + wire M00_AXI_AWVALID; + wire [0:0]M00_AXI_BID; + wire M00_AXI_BREADY; + wire [1:0]M00_AXI_BRESP; + wire M00_AXI_BVALID; + wire [255:0]M00_AXI_RDATA; + wire [0:0]M00_AXI_RID; + wire M00_AXI_RLAST; + wire M00_AXI_RREADY; + wire [1:0]M00_AXI_RRESP; + wire M00_AXI_RVALID; + wire [255:0]M00_AXI_WDATA; + wire M00_AXI_WLAST; + wire M00_AXI_WREADY; + wire [31:0]M00_AXI_WSTRB; + wire M00_AXI_WVALID; + wire S00_AXI_ACLK; + wire S00_AXI_ARESETN; + wire [31:0]S00_AXI_ARADDR; + wire [1:0]S00_AXI_ARBURST; + wire [3:0]S00_AXI_ARCACHE; + wire [0:0]S00_AXI_ARID; + wire [7:0]S00_AXI_ARLEN; + wire [0:0]S00_AXI_ARLOCK; + wire [2:0]S00_AXI_ARPROT; + wire [3:0]S00_AXI_ARQOS; + wire S00_AXI_ARREADY; + wire [3:0]S00_AXI_ARREGION; + wire [2:0]S00_AXI_ARSIZE; + wire S00_AXI_ARVALID; + wire [31:0]S00_AXI_AWADDR; + wire [1:0]S00_AXI_AWBURST; + wire [3:0]S00_AXI_AWCACHE; + wire [0:0]S00_AXI_AWID; + wire [7:0]S00_AXI_AWLEN; + wire [0:0]S00_AXI_AWLOCK; + wire [2:0]S00_AXI_AWPROT; + wire [3:0]S00_AXI_AWQOS; + wire S00_AXI_AWREADY; + wire [3:0]S00_AXI_AWREGION; + wire [2:0]S00_AXI_AWSIZE; + wire S00_AXI_AWVALID; + wire [0:0]S00_AXI_BID; + wire S00_AXI_BREADY; + wire [1:0]S00_AXI_BRESP; + wire S00_AXI_BVALID; + wire [63:0]S00_AXI_RDATA; + wire [0:0]S00_AXI_RID; + wire S00_AXI_RLAST; + wire S00_AXI_RREADY; + wire [1:0]S00_AXI_RRESP; + wire S00_AXI_RVALID; + wire [63:0]S00_AXI_WDATA; + wire S00_AXI_WLAST; + wire S00_AXI_WREADY; + wire [7:0]S00_AXI_WSTRB; + wire S00_AXI_WVALID; + wire S01_AXI_ACLK; + wire S01_AXI_ARESETN; + wire [31:0]S01_AXI_ARADDR; + wire [1:0]S01_AXI_ARBURST; + wire [3:0]S01_AXI_ARCACHE; + wire [0:0]S01_AXI_ARID; + wire [7:0]S01_AXI_ARLEN; + wire [0:0]S01_AXI_ARLOCK; + wire [2:0]S01_AXI_ARPROT; + wire [3:0]S01_AXI_ARQOS; + wire S01_AXI_ARREADY; + wire [3:0]S01_AXI_ARREGION; + wire [2:0]S01_AXI_ARSIZE; + wire S01_AXI_ARVALID; + wire [31:0]S01_AXI_AWADDR; + wire [1:0]S01_AXI_AWBURST; + wire [3:0]S01_AXI_AWCACHE; + wire [0:0]S01_AXI_AWID; + wire [7:0]S01_AXI_AWLEN; + wire [0:0]S01_AXI_AWLOCK; + wire [2:0]S01_AXI_AWPROT; + wire [3:0]S01_AXI_AWQOS; + wire S01_AXI_AWREADY; + wire [3:0]S01_AXI_AWREGION; + wire [2:0]S01_AXI_AWSIZE; + wire S01_AXI_AWVALID; + wire [0:0]S01_AXI_BID; + wire S01_AXI_BREADY; + wire [1:0]S01_AXI_BRESP; + wire S01_AXI_BVALID; + wire [63:0]S01_AXI_RDATA; + wire [0:0]S01_AXI_RID; + wire S01_AXI_RLAST; + wire S01_AXI_RREADY; + wire [1:0]S01_AXI_RRESP; + wire S01_AXI_RVALID; + wire [63:0]S01_AXI_WDATA; + wire S01_AXI_WLAST; + wire S01_AXI_WREADY; + wire [7:0]S01_AXI_WSTRB; + wire S01_AXI_WVALID; + + axi_intercon_2x64_128_bd axi_intercon_2x64_128_bd_i + (.M00_AXI_ACLK(M00_AXI_ACLK), + .M00_AXI_ARESETN(M00_AXI_ARESETN), + .M00_AXI_araddr(M00_AXI_ARADDR), + .M00_AXI_arburst(M00_AXI_ARBURST), + .M00_AXI_arcache(M00_AXI_ARCACHE), + .M00_AXI_arid(M00_AXI_ARID), + .M00_AXI_arlen(M00_AXI_ARLEN), + .M00_AXI_arlock(M00_AXI_ARLOCK), + .M00_AXI_arprot(M00_AXI_ARPROT), + .M00_AXI_arqos(M00_AXI_ARQOS), + .M00_AXI_arready(M00_AXI_ARREADY), + .M00_AXI_arregion(M00_AXI_ARREGION), + .M00_AXI_arsize(M00_AXI_ARSIZE), + .M00_AXI_arvalid(M00_AXI_ARVALID), + .M00_AXI_awaddr(M00_AXI_AWADDR), + .M00_AXI_awburst(M00_AXI_AWBURST), + .M00_AXI_awcache(M00_AXI_AWCACHE), + .M00_AXI_awid(M00_AXI_AWID), + .M00_AXI_awlen(M00_AXI_AWLEN), + .M00_AXI_awlock(M00_AXI_AWLOCK), + .M00_AXI_awprot(M00_AXI_AWPROT), + .M00_AXI_awqos(M00_AXI_AWQOS), + .M00_AXI_awready(M00_AXI_AWREADY), + .M00_AXI_awregion(M00_AXI_AWREGION), + .M00_AXI_awsize(M00_AXI_AWSIZE), + .M00_AXI_awvalid(M00_AXI_AWVALID), + .M00_AXI_bid(M00_AXI_BID), + .M00_AXI_bready(M00_AXI_BREADY), + .M00_AXI_bresp(M00_AXI_BRESP), + .M00_AXI_bvalid(M00_AXI_BVALID), + .M00_AXI_rdata(M00_AXI_RDATA), + .M00_AXI_rid(M00_AXI_RID), + .M00_AXI_rlast(M00_AXI_RLAST), + .M00_AXI_rready(M00_AXI_RREADY), + .M00_AXI_rresp(M00_AXI_RRESP), + .M00_AXI_rvalid(M00_AXI_RVALID), + .M00_AXI_wdata(M00_AXI_WDATA), + .M00_AXI_wlast(M00_AXI_WLAST), + .M00_AXI_wready(M00_AXI_WREADY), + .M00_AXI_wstrb(M00_AXI_WSTRB), + .M00_AXI_wvalid(M00_AXI_WVALID), + .S00_AXI_ACLK(S00_AXI_ACLK), + .S00_AXI_ARESETN(S00_AXI_ARESETN), + .S00_AXI_araddr(S00_AXI_ARADDR), + .S00_AXI_arburst(S00_AXI_ARBURST), + .S00_AXI_arcache(S00_AXI_ARCACHE), + .S00_AXI_arid(S00_AXI_ARID), + .S00_AXI_arlen(S00_AXI_ARLEN), + .S00_AXI_arlock(S00_AXI_ARLOCK), + .S00_AXI_arprot(S00_AXI_ARPROT), + .S00_AXI_arqos(S00_AXI_ARQOS), + .S00_AXI_arready(S00_AXI_ARREADY), + .S00_AXI_arregion(S00_AXI_ARREGION), + .S00_AXI_arsize(S00_AXI_ARSIZE), + .S00_AXI_arvalid(S00_AXI_ARVALID), + .S00_AXI_awaddr(S00_AXI_AWADDR), + .S00_AXI_awburst(S00_AXI_AWBURST), + .S00_AXI_awcache(S00_AXI_AWCACHE), + .S00_AXI_awid(S00_AXI_AWID), + .S00_AXI_awlen(S00_AXI_AWLEN), + .S00_AXI_awlock(S00_AXI_AWLOCK), + .S00_AXI_awprot(S00_AXI_AWPROT), + .S00_AXI_awqos(S00_AXI_AWQOS), + .S00_AXI_awready(S00_AXI_AWREADY), + .S00_AXI_awregion(S00_AXI_AWREGION), + .S00_AXI_awsize(S00_AXI_AWSIZE), + .S00_AXI_awvalid(S00_AXI_AWVALID), + .S00_AXI_bid(S00_AXI_BID), + .S00_AXI_bready(S00_AXI_BREADY), + .S00_AXI_bresp(S00_AXI_BRESP), + .S00_AXI_bvalid(S00_AXI_BVALID), + .S00_AXI_rdata(S00_AXI_RDATA), + .S00_AXI_rid(S00_AXI_RID), + .S00_AXI_rlast(S00_AXI_RLAST), + .S00_AXI_rready(S00_AXI_RREADY), + .S00_AXI_rresp(S00_AXI_RRESP), + .S00_AXI_rvalid(S00_AXI_RVALID), + .S00_AXI_wdata(S00_AXI_WDATA), + .S00_AXI_wlast(S00_AXI_WLAST), + .S00_AXI_wready(S00_AXI_WREADY), + .S00_AXI_wstrb(S00_AXI_WSTRB), + .S00_AXI_wvalid(S00_AXI_WVALID), + .S01_AXI_ACLK(S01_AXI_ACLK), + .S01_AXI_ARESETN(S01_AXI_ARESETN), + .S01_AXI_araddr(S01_AXI_ARADDR), + .S01_AXI_arburst(S01_AXI_ARBURST), + .S01_AXI_arcache(S01_AXI_ARCACHE), + .S01_AXI_arid(S01_AXI_ARID), + .S01_AXI_arlen(S01_AXI_ARLEN), + .S01_AXI_arlock(S01_AXI_ARLOCK), + .S01_AXI_arprot(S01_AXI_ARPROT), + .S01_AXI_arqos(S01_AXI_ARQOS), + .S01_AXI_arready(S01_AXI_ARREADY), + .S01_AXI_arregion(S01_AXI_ARREGION), + .S01_AXI_arsize(S01_AXI_ARSIZE), + .S01_AXI_arvalid(S01_AXI_ARVALID), + .S01_AXI_awaddr(S01_AXI_AWADDR), + .S01_AXI_awburst(S01_AXI_AWBURST), + .S01_AXI_awcache(S01_AXI_AWCACHE), + .S01_AXI_awid(S01_AXI_AWID), + .S01_AXI_awlen(S01_AXI_AWLEN), + .S01_AXI_awlock(S01_AXI_AWLOCK), + .S01_AXI_awprot(S01_AXI_AWPROT), + .S01_AXI_awqos(S01_AXI_AWQOS), + .S01_AXI_awready(S01_AXI_AWREADY), + .S01_AXI_awregion(S01_AXI_AWREGION), + .S01_AXI_awsize(S01_AXI_AWSIZE), + .S01_AXI_awvalid(S01_AXI_AWVALID), + .S01_AXI_bid(S01_AXI_BID), + .S01_AXI_bready(S01_AXI_BREADY), + .S01_AXI_bresp(S01_AXI_BRESP), + .S01_AXI_bvalid(S01_AXI_BVALID), + .S01_AXI_rdata(S01_AXI_RDATA), + .S01_AXI_rid(S01_AXI_RID), + .S01_AXI_rlast(S01_AXI_RLAST), + .S01_AXI_rready(S01_AXI_RREADY), + .S01_AXI_rresp(S01_AXI_RRESP), + .S01_AXI_rvalid(S01_AXI_RVALID), + .S01_AXI_wdata(S01_AXI_WDATA), + .S01_AXI_wlast(S01_AXI_WLAST), + .S01_AXI_wready(S01_AXI_WREADY), + .S01_AXI_wstrb(S01_AXI_WSTRB), + .S01_AXI_wvalid(S01_AXI_WVALID)); +endmodule diff --git a/fpga/usrp3/top/x300/ip/bootram/Makefile.inc b/fpga/usrp3/top/x300/ip/bootram/Makefile.inc new file mode 100644 index 000000000..a42639f25 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/bootram/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_BOOTRAM_SRCS = $(IP_BUILD_DIR)/bootram/bootram.xci + +IP_BOOTRAM_OUTS = $(addprefix $(IP_BUILD_DIR)/bootram/, \ +bootram.xci.out \ +synth/bootram.vhd \ +) + +$(IP_BOOTRAM_SRCS) $(IP_BOOTRAM_OUTS) : $(IP_DIR)/bootram/bootram.xci $(IP_DIR)/bootram/bootram.coe + $(call BUILD_VIVADO_IP,bootram,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/bootram/bootram.coe b/fpga/usrp3/top/x300/ip/bootram/bootram.coe new file mode 100644 index 000000000..253a292b1 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/bootram/bootram.coe @@ -0,0 +1,8194 @@ +memory_initialization_radix=16; +memory_initialization_vector= +0b0b80e4, +c9040000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +0b0b0b89, +92040000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +71fd0608, +72830609, +81058205, +832b2a83, +ffff0652, +04000000, +00000000, +00000000, +71fd0608, +83ffff73, +83060981, +05820583, +2b2b0906, +7383ffff, +0b0b0b0b, +83a70400, +72098105, +72057373, +09060906, +73097306, +070a8106, +53510400, +00000000, +00000000, +72722473, +732e0753, +51040000, +00000000, +00000000, +00000000, +00000000, +00000000, +71737109, +71068106, +30720a10, +0a720a10, +0a31050a, +81065151, +53510400, +00000000, +72722673, +732e0753, +51040000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +0b0b0b88, +c4040000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +720a722b, +0a535104, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +72729f06, +0981050b, +0b0b88a7, +05040000, +00000000, +00000000, +00000000, +00000000, +72722aff, +739f062a, +0974090a, +8106ff05, +06075351, +04000000, +00000000, +00000000, +71715351, +020d0406, +73830609, +81058205, +832b0b2b, +0772fc06, +0c515104, +00000000, +72098105, +72050970, +81050906, +0a810653, +51040000, +00000000, +00000000, +00000000, +72098105, +72050970, +81050906, +0a098106, +53510400, +00000000, +00000000, +00000000, +71098105, +52040000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +72720981, +05055351, +04000000, +00000000, +00000000, +00000000, +00000000, +00000000, +72097206, +73730906, +07535104, +00000000, +00000000, +00000000, +00000000, +00000000, +71fc0608, +72830609, +81058305, +1010102a, +81ff0652, +04000000, +00000000, +00000000, +71fc0608, +0b0b80e6, +e8738306, +10100508, +060b0b0b, +88aa0400, +00000000, +00000000, +0b0b0b88, +f9040000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +0b0b0b88, +e0040000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +72097081, +0509060a, +8106ff05, +70547106, +73097274, +05ff0506, +07515151, +04000000, +72097081, +0509060a, +098106ff, +05705471, +06730972, +7405ff05, +06075151, +51040000, +05ff0504, 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+00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000; \ No newline at end of file diff --git a/fpga/usrp3/top/x300/ip/bootram/bootram.xci b/fpga/usrp3/top/x300/ip/bootram/bootram.xci new file mode 100644 index 000000000..ec46d7a5f --- /dev/null +++ b/fpga/usrp3/top/x300/ip/bootram/bootram.xci @@ -0,0 +1,318 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bootram + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0.000 + 0 + 13 + 13 + 1 + 4 + 0 + 1 + 8 + 0 + 0 + 8 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 20.388 mW + kintex7 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + bootram.mem + bootram.mif + 0 + 1 + 0 + 0 + 1 + 8192 + 8192 + 1 + 1 + 32 + 32 + 0 + 0 + CE + CE + ALL + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 4 + 4 + 8192 + 8192 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + kintex7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 8 + NONE + bootram.coe + ALL + bootram + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + true + Native + true + no_Mem_file_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 50 + 8kx2 + false + false + 1 + 1 + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + true + false + false + false + false + false + 8192 + 32 + 32 + No_ECC + false + false + false + Stand_Alone + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/bus_clk_gen/Makefile.inc b/fpga/usrp3/top/x300/ip/bus_clk_gen/Makefile.inc new file mode 100644 index 000000000..e05a173c3 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/bus_clk_gen/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_BUS_CLK_GEN_SRCS = $(IP_BUILD_DIR)/bus_clk_gen/bus_clk_gen.xci + +IP_BUS_CLK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/bus_clk_gen/, \ +bus_clk_gen.xci.out \ +bus_clk_gen.v \ +) + +$(IP_BUS_CLK_GEN_SRCS) $(IP_BUS_CLK_GEN_OUTS) : $(IP_DIR)/bus_clk_gen/bus_clk_gen.xci + $(call BUILD_VIVADO_IP,bus_clk_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/bus_clk_gen/bus_clk_gen.xci b/fpga/usrp3/top/x300/ip/bus_clk_gen/bus_clk_gen.xci new file mode 100644 index 000000000..dd1f688fb --- /dev/null +++ b/fpga/usrp3/top/x300/ip/bus_clk_gen/bus_clk_gen.xci @@ -0,0 +1,786 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bus_clk_gen + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + CLKFB_IN_N + CLKFB_IN + CLKFB_IN_P + SINGLE + CLKFB_OUT_N + CLKFB_OUT + CLKFB_OUT_P + CLKFB_STOPPED + 80.0 + 100.0 + 0000 + 0000 + 187.500 + 0000 + 0000 + 125.000 + BUFG + 50.0 + false + 187.500 + 0.000 + 50.000 + 187.5 + 0.00 + 1 + 0000 + 0000 + 93.750 + No_buffer + 50.0 + false + 125.000 + 0.000 + 50.000 + 125.000 + 0.000 + 1 + 1 + 0000 + 0000 + 214.286 + BUFG + 50.0 + false + 93.750 + 0.000 + 50.000 + 93.75 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 214.286 + 0.000 + 50.000 + 215 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + CLK_IN_SEL + CLK_OUT1 + CLK_OUT2_UNBUF + CLK_OUT3 + CLK_OUT4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + DADDR + DCLK + DEN + DIN + 0000 + 1 + 1.5 + 2.0 + 0.872093023255814 + 1.875 + 1.875 + 1.875 + DOUT + DRDY + DWE + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_ONCHIP + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________125.000____________0.010 + no_secondary_input_clock + INPUT_CLK_STOPPED + 0 + Units_MHz + No_Jitter + LOCKED + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 12.000 + 0.000 + FALSE + 8.000 + 10.000 + 8.000 + 0.500 + 0.000 + FALSE + 12 + 0.500 + 0.000 + FALSE + 16 + 0.500 + 0.000 + FALSE + 7 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.010 + 0.010 + FALSE + 4 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + CLK_OUT1___187.500______0.000______50.0_______85.263_____73.940 + CLK_OUT2_UNBUF___125.000______0.000______50.0_______91.831_____73.940 + CLK_OUT3____93.750______0.000______50.0_______96.813_____73.940 + CLK_OUT4___214.286______0.000______50.0_______83.210_____73.940 + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + POWER_DOWN + 0000 + 1 + CLK_IN1 + PLL + AUTO + 125.000 + 0.010 + 10.000 + No_buffer + PSCLK + PSDONE + PSEN + PSINCDEC + 100.0 + 0 + RESET + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + bus_clk_gen + MMCM + false + DONE + cddcdone + cddcreq + CLKFB_IN_N + CLKFB_IN + CLKFB_IN_P + SINGLE + CLKFB_OUT_N + CLKFB_OUT + CLKFB_OUT_P + CLKFB_STOPPED + 80.0 + 0.010 + 100.0 + 0.010 + BUFG + 85.263 + false + 73.940 + 50.000 + 187.5 + 0.00 + 1 + true + No_buffer + 91.831 + false + 73.940 + 50.000 + 125.000 + 0.000 + 1 + true + BUFG + 96.813 + false + 73.940 + 50.000 + 93.75 + 0.000 + 1 + true + BUFG + 83.210 + false + 73.940 + 50.000 + 215 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + CLK_IN_SEL + CLK_OUT1 + false + CLK_OUT2_UNBUF + false + CLK_OUT3 + false + CLK_OUT4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + MANUAL + bus_clk_gen + DADDR + DCLK + DEN + Custom + Custom + DIN + DOUT + DRDY + DWE + false + false + false + false + false + false + false + false + false + FDBK_ONCHIP + INPUT_CLK_STOPPED + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + LOCKED + OPTIMIZED + 12 + 0.000 + false + 8.000 + 10.000 + 8 + 0.500 + 0.000 + false + 12 + 0.500 + 0.000 + false + 16 + 0.500 + 0.000 + false + 7 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 4 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + POWER_DOWN + 1 + CLK_IN1 + PLL + MMCM_ADV + 125.000 + 0.010 + 10.000 + No_buffer + PSCLK + PSDONE + PSEN + PSINCDEC + 100.0 + REL_PRIMARY + Custom + RESET + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + false + false + false + false + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/ddr3_32bit/Makefile.inc b/fpga/usrp3/top/x300/ip/ddr3_32bit/Makefile.inc new file mode 100644 index 000000000..90b0be153 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ddr3_32bit/Makefile.inc @@ -0,0 +1,26 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DDR3_32BIT_SRCS = \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit.xci \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v + +IP_DDR3_32BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \ +ddr3_32bit.xci.out \ +ddr3_32bit/user_design/rtl/ddr3_32bit.v \ +ddr3_32bit/user_design/rtl/ddr3_32bit_mig.v \ +) + +IP_DDR3_32BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \ +ddr3_32bit/example_design/sim/ddr3_model.sv \ +ddr3_32bit/example_design/sim/ddr3_model_parameters.vh \ +) + + +$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS) : $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_*.prj + cp -f $(IP_DIR)/ddr3_32bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_32bit/mig_a.prj # Note: This won't allow parallel IP builds + $(call BUILD_VIVADO_IP,ddr3_32bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + rm -f $(IP_DIR)/ddr3_32bit/mig_a.prj diff --git a/fpga/usrp3/top/x300/ip/ddr3_32bit/ddr3_32bit.xci b/fpga/usrp3/top/x300/ip/ddr3_32bit/ddr3_32bit.xci new file mode 100644 index 000000000..58fad4f82 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ddr3_32bit/ddr3_32bit.xci @@ -0,0 +1,2645 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ddr3_32bit + + + 0 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/ddr3_32bit/mig_xc7k325tffg900-2.prj b/fpga/usrp3/top/x300/ip/ddr3_32bit/mig_xc7k325tffg900-2.prj new file mode 100644 index 000000000..ed5c3dcaa --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ddr3_32bit/mig_xc7k325tffg900-2.prj @@ -0,0 +1,163 @@ + + + + ddr3_32bit + 1 + 1 + OFF + 1024 + ON + Disabled + xc7k325t-ffg900/-2 + 4.0 + Single-Ended + No Buffer + ACTIVE HIGH + FALSE + 0 + 50 Ohms + 0 + + 7k/xc7k325t-ffg900 + + + DDR3_SDRAM/Components/MT41J256m16XX-125 + 1666 + 1.8V + 4:1 + 100.04 + 1 + 1200 + 4.000 + 6 + 1 + 1 + 1 + 32 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + ROW_BANK_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 9 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 7 + Enabled + Normal + Dynamic ODT off + AXI + + ROUND_ROBIN + 30 + 256 + 1 + 1 + + + + diff --git a/fpga/usrp3/top/x300/ip/ddr3_32bit/mig_xc7k410tffg900-2.prj b/fpga/usrp3/top/x300/ip/ddr3_32bit/mig_xc7k410tffg900-2.prj new file mode 100644 index 000000000..00c7fa345 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ddr3_32bit/mig_xc7k410tffg900-2.prj @@ -0,0 +1,163 @@ + + + + ddr3_32bit + 1 + 1 + OFF + 1024 + ON + Disabled + xc7k410t-ffg900/-2 + 4.0 + Single-Ended + No Buffer + ACTIVE HIGH + FALSE + 0 + 50 Ohms + 0 + + 7k/xc7k325t-ffg900 + + + DDR3_SDRAM/Components/MT41J256m16XX-125 + 1666 + 1.8V + 4:1 + 100.04 + 1 + 1200 + 4.000 + 6 + 1 + 1 + 1 + 32 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + ROW_BANK_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 9 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 7 + Enabled + Normal + Dynamic ODT off + AXI + + ROUND_ROBIN + 30 + 256 + 1 + 1 + + + + diff --git a/fpga/usrp3/top/x300/ip/fifo_4k_2clk/Makefile.inc b/fpga/usrp3/top/x300/ip/fifo_4k_2clk/Makefile.inc new file mode 100644 index 000000000..e022d9a1c --- /dev/null +++ b/fpga/usrp3/top/x300/ip/fifo_4k_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + +IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \ +fifo_4k_2clk.xci.out \ +synth/fifo_4k_2clk.vhd \ +) + +$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + $(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/fifo_4k_2clk/fifo_4k_2clk.xci b/fpga/usrp3/top/x300/ip/fifo_4k_2clk/fifo_4k_2clk.xci new file mode 100644 index 000000000..dddfacc1e --- /dev/null +++ b/fpga/usrp3/top/x300/ip/fifo_4k_2clk/fifo_4k_2clk.xci @@ -0,0 +1,576 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_4k_2clk + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 9 + BlankString + 72 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 72 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintex7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 0 + 0 + 0 + 0 + 0 + 1 + 512x72 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 511 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 510 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 512 + 1 + 9 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 9 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_4k_2clk + 64 + false + 9 + true + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 1 + 511 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 510 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 72 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 72 + 512 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + true + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 0 + 0 + 0 + 0 + 0 + 4 + false + false + Active_High + Active_High + true + false + false + true + false + Active_High + 0 + false + Active_High + 1 + true + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/fifo_short_2clk/Makefile.inc b/fpga/usrp3/top/x300/ip/fifo_short_2clk/Makefile.inc new file mode 100644 index 000000000..8c5c54213 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/fifo_short_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci + +IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \ +fifo_short_2clk.xci.out \ +synth/fifo_short_2clk.vhd \ +) + +$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci + $(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/fifo_short_2clk/fifo_short_2clk.xci b/fpga/usrp3/top/x300/ip/fifo_short_2clk/fifo_short_2clk.xci new file mode 100644 index 000000000..49761459c --- /dev/null +++ b/fpga/usrp3/top/x300/ip/fifo_short_2clk/fifo_short_2clk.xci @@ -0,0 +1,578 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_short_2clk + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 5 + BlankString + 72 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 72 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintex7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 2 + BlankString + 1 + 0 + 0 + 0 + 0 + 1 + 512x72 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 31 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 30 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 32 + 1 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 32 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 5 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_short_2clk + 64 + false + 5 + false + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Distributed_RAM + 1 + 31 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 30 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 72 + 32 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 72 + 32 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + true + 6 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 0 + 0 + 0 + 0 + 0 + 4 + false + false + Active_High + Active_High + true + false + false + true + false + Active_High + 0 + false + Active_High + 1 + true + 6 + false + FIFO + false + false + false + false + FIFO + FIFO + 3 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/input_sample_fifo/Makefile.inc b/fpga/usrp3/top/x300/ip/input_sample_fifo/Makefile.inc new file mode 100644 index 000000000..d79a40e91 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/input_sample_fifo/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_INPUT_SAMPLE_FIFO_SRCS = $(IP_BUILD_DIR)/input_sample_fifo/input_sample_fifo.xci + +IP_INPUT_SAMPLE_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/input_sample_fifo/, \ +nput_sample_fifo.xci.out \ +synth/input_sample_fifo.vhd \ +) + +$(IP_INPUT_SAMPLE_FIFO_SRCS) $(IP_INPUT_SAMPLE_FIFO_OUTS) : $(IP_DIR)/input_sample_fifo/input_sample_fifo.xci + $(call BUILD_VIVADO_IP,input_sample_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/input_sample_fifo/input_sample_fifo.xci b/fpga/usrp3/top/x300/ip/input_sample_fifo/input_sample_fifo.xci new file mode 100644 index 000000000..1f3e58e2d --- /dev/null +++ b/fpga/usrp3/top/x300/ip/input_sample_fifo/input_sample_fifo.xci @@ -0,0 +1,575 @@ + + + xilinx.com + xci + unknown + 1.0 + + + input_sample_fifo + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 4 + BlankString + 28 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 28 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintex7 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 2 + BlankString + 1 + 0 + 0 + 0 + 0 + 1 + 512x36 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 15 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 14 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + 16 + 1 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + 16 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 4 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + true + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + input_sample_fifo + 64 + false + 4 + false + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Distributed_RAM + 1 + 15 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 14 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 28 + 16 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 28 + 16 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 4 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 0 + 0 + 0 + 0 + 0 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 4 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/Makefile.inc b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/Makefile.inc new file mode 100644 index 000000000..9c14cc13a --- /dev/null +++ b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/Makefile.inc @@ -0,0 +1,50 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +ONE_GIGE_PHY_SRCS = \ +$(IP_DIR)/one_gig_eth_pcs_pma/one_gige_phy_clk_gen.v \ +$(IP_DIR)/one_gig_eth_pcs_pma/one_gige_phy.v \ +$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) + +IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/, \ +one_gig_eth_pcs_pma_example_design.v \ +one_gig_eth_pcs_pma_reset_sync_ex.v \ +one_gig_eth_pcs_pma_sync_block_ex.v \ +one_gig_eth_pcs_pma_tx_elastic_buffer.v \ +one_gig_eth_pcs_pma_clocking.v \ +one_gig_eth_pcs_pma_gt_common.v \ +one_gig_eth_pcs_pma_resets.v \ +one_gig_eth_pcs_pma_support.v \ +) + +IP_ONE_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci + +IP_ONE_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/, \ +one_gig_eth_pcs_pma.xci.out \ +synth/one_gig_eth_pcs_pma_block.v \ +synth/one_gig_eth_pcs_pma_reset_sync.v \ +synth/one_gig_eth_pcs_pma.v \ +synth/one_gig_eth_pcs_pma_ooc.xdc \ +synth/one_gig_eth_pcs_pma_sync_block.v \ +synth/one_gig_eth_pcs_pma.xdc \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_gt.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard.v \ +synth/transceiver/one_gig_eth_pcs_pma_transceiver.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_init.v \ +synth/transceiver/one_gig_eth_pcs_pma_reset_wtd_timer.v \ +synth/transceiver/one_gig_eth_pcs_pma_tx_startup_fsm.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_multi_gt.v \ +synth/transceiver/one_gig_eth_pcs_pma_rx_startup_fsm.v \ +) + +$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) + +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,one_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + cp $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v.orig + patch $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch + cp $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_support.v $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_support.v.orig + patch $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_support.v $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch diff --git a/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci new file mode 100644 index 000000000..245a6dd8b --- /dev/null +++ b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci @@ -0,0 +1,353 @@ + + + xilinx.com + xci + unknown + 1.0 + + + one_gig_eth_pcs_pma + + + 1 + 1 + 1 + 1 + + + + 0 + + + + 0 + + + 0 + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + false + false + false + false + 0 + + + + 0 + + + + 0 + false + 100000000 + + + + 0 + + + + 0 + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + false + false + false + false + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + false + false + false + + + + 100000000 + 0 + 0.000 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + ACTIVE_LOW + ACTIVE_LOW + ACTIVE_LOW + ACTIVE_LOW + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + true + 0 + 0 + false + false + DIFF_PAIR_0 + DIFF_PAIR_1 + false + DIFF_PAIR_0 + DIFF_PAIR_1 + kintex7 + 0 + one_gig_eth_pcs_pma + 50 + false + . + false + false + false + false + kintex7 + 8 + 9 + X0Y0 + 7 + 4 + GTH + false + false + false + false + true + false + false + 1 + clk0 + 125 + TXOUTCLK + true + false + one_gig_eth_pcs_pma_gt + false + GTXE2 + false + 1 + false + false + true + xc7k410t + false + 1 + false + false + Sync + one_gig_eth_pcs_pma + Custom + 50 + TEMAC + Custom + 0 + false + false + false + false + X0Y0 + GTH + false + false + 125 + Custom + true + 1G + 1 + Transceiver + 125 + clk0 + TXOUTCLK + DIFF_PAIR_0 + DIFF_PAIR_1 + false + 10_100_1000 + false + 1000BASEX + Include_Shared_Logic_in_Example_Design + Time_of_day + false + DIFF_PAIR_0 + DIFF_PAIR_1 + 1 + false + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 6 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch new file mode 100644 index 000000000..41f963797 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch @@ -0,0 +1,25 @@ +65,66d64 +< input gtrefclk_p, // Differential +ve of reference clock for MGT: 125MHz, very high quality. +< input gtrefclk_n, // Differential -ve of reference clock for MGT: 125MHz, very high quality. +70,71d67 +< output gtrefclk, // gtrefclk routed through an IBUFG. +< output gtrefclk_bufg, // gtrefclk routed through a BUFG for driving logic. +88d83 +< wire gtrefclk_i; +93,108d87 +< // Clock circuitry for the Transceiver uses a differential input clock. +< // gtrefclk is routed to the tranceiver. +< IBUFDS_GTE2 ibufds_gtrefclk ( +< .I (gtrefclk_p), +< .IB (gtrefclk_n), +< .CEB (1'b0), +< .O (gtrefclk_i), +< .ODIV2 () +< ); +< +< assign gtrefclk = gtrefclk_i; +< +< BUFG bufg_gtrefclk ( +< .I (gtrefclk_i), +< .O (gtrefclk_bufg) +< ); diff --git a/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch new file mode 100644 index 000000000..277c890f1 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch @@ -0,0 +1,17 @@ +70,73c70,71 +< input gtrefclk_p, // differential clock +< input gtrefclk_n, // differential clock +< output gtrefclk_out, // Very high quality clock for GT transceiver. +< output gtrefclk_bufg_out, +--- +> input gtrefclk, // gtrefclk routed through an IBUFG. +> input gtrefclk_bufg, // gtrefclk routed through a BUFG for driving logic. +125,126d122 +< wire gtrefclk; // High quality clock +< wire gtrefclk_bufg; +205,206d200 +< .gtrefclk_p (gtrefclk_p), +< .gtrefclk_n (gtrefclk_n), +210,211d203 +< .gtrefclk (gtrefclk), +< .gtrefclk_bufg (gtrefclk_bufg), diff --git a/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.v b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.v new file mode 100644 index 000000000..0b02b1942 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.v @@ -0,0 +1,100 @@ +// +// Copyright 2014 Ettus Research LLC +// + +module one_gige_phy +( + input independent_clock, + + // Tranceiver Interface + //--------------------- + input gtrefclk, // Reference clock for MGT: 125MHz, very high quality. + input gtrefclk_bufg, // Reference clock routed through a BUFG + output txp, // Differential +ve of serial transmission from PMA to PMD. + output txn, // Differential -ve of serial transmission from PMA to PMD. + input rxp, // Differential +ve for serial reception from PMD to PMA. + input rxn, // Differential -ve for serial reception from PMD to PMA. + + // GMII Interface (client MAC <=> PCS) + //------------------------------------ + output gmii_clk, // Receive clock to client MAC. + input [7:0] gmii_txd, // Transmit data from client MAC. + input gmii_tx_en, // Transmit control signal from client MAC. + input gmii_tx_er, // Transmit control signal from client MAC. + output reg [7:0] gmii_rxd, // Received Data to client MAC. + output reg gmii_rx_dv, // Received control signal to client MAC. + output reg gmii_rx_er, // Received control signal to client MAC. + + // Management: MDIO Interface + //--------------------------- + input mdc, // Management Data Clock + input mdio_i, // Management Data In + output mdio_o, // Management Data Out + output mdio_t, // Management Data Tristate + input [4:0] configuration_vector, // Alternative to MDIO interface. + input configuration_valid, // Validation signal for Config vector + + // General IO's + //------------- + output [15:0] status_vector, // Core status. + input reset, // Asynchronous reset for entire core. + input signal_detect // Input from PMD to indicate presence of optical input. +); + + wire resetdone; // To indicate that the GT transceiver has completed its reset cycle + wire userclk; // 62.5MHz clock for GT transceiver Tx/Rx user clocks + wire userclk2; // 125MHz clock for core reference clock. + wire rxuserclk2; + wire gmii_isolate; // internal gmii_isolate signal. + + wire [7:0] gmii_rxd_int; + wire gmii_rx_dv_int; + wire gmii_rx_er_int; + + always @(posedge gmii_clk) begin + gmii_rxd <= gmii_rxd_int; + gmii_rx_dv <= gmii_rx_dv_int; + gmii_rx_er <= gmii_rx_er_int; + end + + //---------------------------------------------------------------------------- + // Instantiate core wrapper + //---------------------------------------------------------------------------- + one_gig_eth_pcs_pma_support core_support_i ( + .gtrefclk (gtrefclk), + .gtrefclk_bufg (gtrefclk_bufg), + .txp (txp), + .txn (txn), + .rxp (rxp), + .rxn (rxn), + .mmcm_locked_out (), + .userclk_out (userclk), + .userclk2_out (userclk2), + .rxuserclk_out (), + .rxuserclk2_out (rxuserclk2), + .independent_clock_bufg(independent_clock), + .pma_reset_out (), + .resetdone (resetdone), + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd_int), + .gmii_rx_dv (gmii_rx_dv_int), + .gmii_rx_er (gmii_rx_er_int), + .gmii_isolate (gmii_isolate), + .mdc (mdc), + .mdio_i (mdio_i), + .mdio_o (mdio_o), + .mdio_t (mdio_t), + .configuration_vector (configuration_vector), + .configuration_valid (configuration_valid), + .status_vector (status_vector), + .reset (reset), + .signal_detect (signal_detect), + .gt0_qplloutclk_out (), + .gt0_qplloutrefclk_out () + ); + + assign gmii_clk = userclk2; + +endmodule // one_gige_phy diff --git a/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc new file mode 100644 index 000000000..4dadace3b --- /dev/null +++ b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc @@ -0,0 +1,164 @@ + + +#*********************************************************** +# The following constraints target the Transceiver Physical* +# Interface which is instantiated in the Example Design. * +#*********************************************************** +#----------------------------------------------------------- +# Transceiver I/O placement: - +#----------------------------------------------------------- + + +# Place the transceiver components, chosen for this example design +# *** These values should be modified according to your specific design *** + +#set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells */*/*/transceiver_inst/gtwizard_inst/*/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i] + + +#----------------------------------------------------------- +# Clock source used for the IDELAY Controller (if present) - +# and for the transceiver reset circuitry - +#----------------------------------------------------------- + + +create_clock -name independent_clock -period 5.000 [get_ports independent_clock] + +#----------------------------------------------------------- +# PCS/PMA Clock period Constraints: please do not relax - +#----------------------------------------------------------- + +create_clock -add -name gtrefclk -period 8.000 [get_ports gtrefclk_p] + + +#----------------------------------------------------------- +# Transceiver I/O placement: - +#----------------------------------------------------------- + +# Place the transceiver components, chosen for this example design +# *** These values should be modified according to your specific design *** + +#set_property LOC H6 [get_ports gtrefclk_p] +#set_property LOC H5 [get_ports gtrefclk_n] + + +#*********************************************************** +# The following constraints target the GMII implemented in * +# the Example Design. * +#*********************************************************** +# If the GMII is intended to be an internal interface, * +# the GMII signals can be connected directly to user * +# logic and all of the following constraints in this file * +# should be removed. * +# * +# If the GMII is intended to be an external interface, * +# all of the following constraints in this file should be * +# maintained. * +#*********************************************************** + +#----------------------------------------------------------- +# GMII IOSTANDARD Constraints: please select an I/O - +# Standard (LVTTL is suggested). - +#----------------------------------------------------------- + +# Please update the IOSTANDARD according to that available in the device + +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[4]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[5]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er] + +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[4]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[5]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er] + +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_clk] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_clk] + +#----------------------------------------------------------- +# Lock down the GMII Tx signals to the same bank for low - +# skew. This is an example placement only. - +#----------------------------------------------------------- + + +#----------------------------------------------------------- +# To Adjust GMII Tx Input Setup/Hold Timing - +#----------------------------------------------------------- +# These constraints will be set at a later date when device speed files have matured + +#set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_en] +#set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_er] + +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[7].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[6].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[5].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[4].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[3].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[2].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[1].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[0].delay_gmii_txd}] + + + +#----------------------------------------------------------- +# To check (analyze) GMII Tx Input Setup/Hold Timing - +#----------------------------------------------------------- + +create_clock -name gmii_tx_clk -period 8.000 [get_ports gmii_tx_clk] + + + +#----------------------------------------------------------- +# Fast Skew maximises output setup and hold timing - +#----------------------------------------------------------- +set_property SLEW FAST [get_ports {gmii_rxd[*]}] +set_property SLEW FAST [get_ports gmii_rx_dv] +set_property SLEW FAST [get_ports gmii_rx_er] +set_property SLEW FAST [get_ports gmii_rx_clk] + + +#----------------------------------------------------------- +# GMII Transmitter Constraints: place flip-flops in IOB - +#----------------------------------------------------------- +#set_property IOB TRUE [get_cells gmii_txd_IBUF*] +#set_property IOB TRUE [get_cells gmii_tx_en_IBUF*] +#set_property IOB TRUE [get_cells gmii_tx_er_IBUF*] + +#----------------------------------------------------------- +# GMII Receiver Constraints: place flip-flops in IOB - +#----------------------------------------------------------- +#set_property IOB TRUE [get_cells gmii_rxd_obuf_reg*] +#set_property IOB TRUE [get_cells gmii_rx_dv_obuf_reg] +#set_property IOB TRUE [get_cells gmii_rx_er_obuf_reg] + + + +#----------------------------------------------------------- +# GMII Tx Elastic Buffer Constraints - +#----------------------------------------------------------- + +# Control Gray Code delay and skew across clock boundary +set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_rd_addrgray*/data_sync*/D}] +set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_wr_addrgray*/data_sync*/D}] + +# Constrain between Distributed Memory (output data) and the 1st set of flip-flops +set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/tx_en_fifo_reg1*/D}] +set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/tx_er_fifo_reg1*/D}] +set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/txd_fifo_reg1*/D}] + +set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }] + +set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe_reg*/PRE}] +set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe*[0]/D}] diff --git a/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy_clk_gen.v b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy_clk_gen.v new file mode 100644 index 000000000..347a0e550 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy_clk_gen.v @@ -0,0 +1,29 @@ +// +// Copyright 2014 Ettus Research LLC +// + +module one_gige_phy_clk_gen +( + input refclk_p, + input refclk_n, + output refclk, + output refclk_bufg +); + + IBUFDS_GTE2 ibufds_inst ( + .O (refclk), + .ODIV2 (), + .CEB (1'b0), + .I (refclk_p), + .IB (refclk_n) + ); + + BUFG bufg_gtrefclk_inst ( + .I(refclk), + .O(refclk_bufg) + ); + +endmodule + + + diff --git a/fpga/usrp3/top/x300/ip/pcie_clk_gen/Makefile.inc b/fpga/usrp3/top/x300/ip/pcie_clk_gen/Makefile.inc new file mode 100644 index 000000000..72ddc140d --- /dev/null +++ b/fpga/usrp3/top/x300/ip/pcie_clk_gen/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_PCIE_CLK_GEN_SRCS = $(IP_BUILD_DIR)/pcie_clk_gen/pcie_clk_gen.xci + +IP_PCIE_CLK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/pcie_clk_gen/, \ +pcie_clk_gen.xci.out \ +pcie_clk_gen.v \ +) + +$(IP_PCIE_CLK_GEN_SRCS) $(IP_PCIE_CLK_GEN_OUTS) : $(IP_DIR)/pcie_clk_gen/pcie_clk_gen.xci + $(call BUILD_VIVADO_IP,pcie_clk_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/pcie_clk_gen/pcie_clk_gen.xci b/fpga/usrp3/top/x300/ip/pcie_clk_gen/pcie_clk_gen.xci new file mode 100644 index 000000000..a36035616 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/pcie_clk_gen/pcie_clk_gen.xci @@ -0,0 +1,752 @@ + + + xilinx.com + xci + unknown + 1.0 + + + pcie_clk_gen + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + CLKFB_IN_N + CLKFB_IN + CLKFB_IN_P + SINGLE + CLKFB_OUT_N + CLKFB_OUT + CLKFB_OUT_P + CLKFB_STOPPED + 800.0 + 100.0 + 0000 + 0000 + 40.000 + 0000 + 0000 + 200.000 + BUFH + 50.0 + false + 40.000 + 0.000 + 50.000 + 40 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFH + 50.0 + false + 200.000 + 0.000 + 50.000 + 200 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + CLK_IN_SEL + CLK_OUT1 + CLK_OUT2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + DADDR + DCLK + DEN + DIN + 0000 + 1 + 0.2 + 0.4 + 0.4 + 0.4 + 0.4 + 0.4 + DOUT + DRDY + DWE + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________125.000____________0.100 + no_secondary_input_clock + INPUT_CLK_STOPPED + 0 + Units_MHz + No_Jitter + LOCKED + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 8.000 + 0.000 + FALSE + 8.000 + 10.0 + 25.000 + 0.500 + 0.000 + FALSE + 5 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.100 + 0.010 + FALSE + 2 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + CLK_OUT1____40.000______0.000______50.0______353.417_____96.948 + CLK_OUT2___200.000______0.000______50.0______192.299_____96.948 + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + POWER_DOWN + 0000 + 1 + CLK_IN1 + PLL + AUTO + 125.000 + 0.100 + 10.000 + No_buffer + PSCLK + PSDONE + PSEN + PSINCDEC + 100.0 + 0 + RESET + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + pcie_clk_gen + MMCM + false + DONE + cddcdone + cddcreq + CLKFB_IN_N + CLKFB_IN + CLKFB_IN_P + SINGLE + CLKFB_OUT_N + CLKFB_OUT + CLKFB_OUT_P + CLKFB_STOPPED + 800.0 + 0.100 + 100.0 + 0.010 + BUFH + 1181.857 + false + 265.359 + 50.000 + 40 + 0.000 + 1 + true + BUFH + 440.890 + false + 265.359 + 50.000 + 200 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + CLK_IN_SEL + CLK_OUT1 + false + CLK_OUT2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + MANUAL + pcie_clk_gen + DADDR + DCLK + DEN + Custom + Custom + DIN + DOUT + DRDY + DWE + false + false + false + false + false + false + false + false + false + FDBK_AUTO + INPUT_CLK_STOPPED + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + LOCKED + OPTIMIZED + 8 + 0.000 + false + 8.000 + 10.0 + 25 + 0.500 + 0.000 + false + 5 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.100 + 0.010 + false + 2 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + POWER_DOWN + 1 + CLK_IN1 + PLL + MMCM_ADV + 125.000 + 0.100 + 10.000 + No_buffer + PSCLK + PSDONE + PSEN + PSINCDEC + 100.0 + REL_PRIMARY + Custom + RESET + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/radio_clk_gen/Makefile.inc b/fpga/usrp3/top/x300/ip/radio_clk_gen/Makefile.inc new file mode 100644 index 000000000..f96bc9d7d --- /dev/null +++ b/fpga/usrp3/top/x300/ip/radio_clk_gen/Makefile.inc @@ -0,0 +1,19 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_RADIO_CLK_GEN_SRCS = $(IP_BUILD_DIR)/radio_clk_gen/radio_clk_gen.xci + +IP_RADIO_CLK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/radio_clk_gen/, \ +radio_clk_gen.xci.out \ +radio_clk_gen.v \ +) + +# We have to patch the XDC file to remove constraints on the source clock for the module +# All timing constraints are handled in one place (timing.xdc) +$(IP_RADIO_CLK_GEN_SRCS) $(IP_RADIO_CLK_GEN_OUTS) : $(IP_DIR)/radio_clk_gen/radio_clk_gen.xci + $(call BUILD_VIVADO_IP,radio_clk_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + patch $(IP_BUILD_DIR)/radio_clk_gen/radio_clk_gen.xdc $(IP_DIR)/radio_clk_gen/radio_clk_gen.xdc.patch + diff --git a/fpga/usrp3/top/x300/ip/radio_clk_gen/radio_clk_gen.xci b/fpga/usrp3/top/x300/ip/radio_clk_gen/radio_clk_gen.xci new file mode 100644 index 000000000..9c68fcee3 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/radio_clk_gen/radio_clk_gen.xci @@ -0,0 +1,755 @@ + + + xilinx.com + xci + unknown + 1.0 + + + radio_clk_gen + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + CLKFB_IN_N + CLKFB_IN + CLKFB_IN_P + SINGLE + CLKFB_OUT_N + CLKFB_OUT + CLKFB_OUT_P + CLKFB_STOPPED + 50.0 + 100.0 + 0000 + 0000 + 200.000 + 0000 + 0000 + 400.000 + BUFG + 50.0 + false + 200.000 + 0.000 + 50.000 + 200.000 + 0.000 + 1 + 0000 + 0000 + 400.000 + BUFG + 50.0 + false + 400.000 + -45.000 + 50.000 + 400.000 + -45.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 400.000 + 60.000 + 50.000 + 400.000 + 60.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + CLK_IN_SEL + CLK_OUT1 + CLK_OUT2 + CLK_OUT3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + DADDR + DCLK + DEN + DIN + 0000 + 1 + 0.5 + 0.5 + 2.0 + 2.0 + 2.0 + 2.0 + DOUT + DRDY + DWE + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________200.000____________0.010 + no_secondary_input_clock + INPUT_CLK_STOPPED + 0 + Units_MHz + No_Jitter + LOCKED + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 6.000 + 0.000 + FALSE + 5.000 + 10.0 + 6.000 + 0.500 + 0.000 + FALSE + 3 + 0.500 + -45.000 + FALSE + 3 + 0.500 + 60.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.010 + 0.010 + FALSE + 3 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + CLK_OUT1___200.000______0.000______50.0_______92.799_____82.655 + CLK_OUT2___400.000____-45.000______50.0_______81.254_____82.655 + CLK_OUT3___400.000_____60.000______50.0_______81.254_____82.655 + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + POWER_DOWN + 0000 + 1 + clk_in1 + MMCM + AUTO + 200.000 + 0.010 + 10.000 + Differential_clock_capable_pin + PSCLK + PSDONE + PSEN + PSINCDEC + 100.0 + 0 + RESET + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + radio_clk_gen + MMCM + false + DONE + cddcdone + cddcreq + CLKFB_IN_N + CLKFB_IN + CLKFB_IN_P + SINGLE + CLKFB_OUT_N + CLKFB_OUT + CLKFB_OUT_P + CLKFB_STOPPED + 50.0 + 0.010 + 100.0 + 0.010 + BUFG + 92.799 + false + 82.655 + 50.000 + 200.000 + 0.000 + 1 + true + BUFG + 81.254 + false + 82.655 + 50.000 + 400.000 + -45.000 + 1 + true + BUFG + 81.254 + false + 82.655 + 50.000 + 400.000 + 60.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + CLK_IN_SEL + CLK_OUT1 + false + CLK_OUT2 + false + CLK_OUT3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + MANUAL + radio_clk_gen + DADDR + DCLK + DEN + Custom + Custom + DIN + DOUT + DRDY + DWE + false + false + false + false + false + false + false + false + false + FDBK_AUTO + INPUT_CLK_STOPPED + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + LOCKED + OPTIMIZED + 6.000 + 0.000 + false + 5.000 + 10.0 + 6.000 + 0.500 + 0.000 + false + 3 + 0.500 + -45.000 + false + 3 + 0.500 + 60.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 3 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + POWER_DOWN + 1 + clk_in1 + MMCM + MMCM_ADV + 200.000 + 0.010 + 10.000 + Differential_clock_capable_pin + PSCLK + PSDONE + PSEN + PSINCDEC + 100.0 + REL_PRIMARY + Custom + RESET + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/radio_clk_gen/radio_clk_gen.xdc.patch b/fpga/usrp3/top/x300/ip/radio_clk_gen/radio_clk_gen.xdc.patch new file mode 100644 index 000000000..d4a0c072f --- /dev/null +++ b/fpga/usrp3/top/x300/ip/radio_clk_gen/radio_clk_gen.xdc.patch @@ -0,0 +1,4 @@ +56,58d55 +< create_clock -period 5.000 [get_ports clk_in1_p] +< set_input_jitter [get_clocks -of_objects [get_ports clk_in1_p]] 0.05 +< diff --git a/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc new file mode 100644 index 000000000..3c3d99107 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc @@ -0,0 +1,42 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +TEN_GIGE_PHY_SRCS = \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy.v \ +$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) + +IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma_ex/imports/, \ +ten_gig_eth_pcs_pma_example_design.v \ +ten_gig_eth_pcs_pma_ff_synchronizer_rst2.v \ +ten_gig_eth_pcs_pma_gt_common.v \ +ten_gig_eth_pcs_pma_shared_clock_and_reset.v \ +ten_gig_eth_pcs_pma_support.v \ +) + +IP_TEN_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + +IP_TEN_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/, \ +ten_gig_eth_pcs_pma.xci.out \ +synth/ten_gig_eth_pcs_pma_block.v \ +synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_multi_gt.v \ +synth/ten_gig_eth_pcs_pma_cable_pull_logic.v \ +synth/ten_gig_eth_pcs_pma_local_clock_and_reset.v \ +synth/ten_gig_eth_pcs_pma_clocks.xdc \ +synth/ten_gig_eth_pcs_pma_ooc.xdc \ +synth/ten_gig_eth_pcs_pma_ff_synchronizer_rst.v \ +synth/ten_gig_eth_pcs_pma_sim_speedup_controller.v \ +synth/ten_gig_eth_pcs_pma_ff_synchronizer.v \ +synth/ten_gig_eth_pcs_pma.v \ +synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \ +synth/ten_gig_eth_pcs_pma.xdc \ +) + +$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) + +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + diff --git a/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci new file mode 100644 index 000000000..453f49cd9 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci @@ -0,0 +1,192 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ten_gig_eth_pcs_pma + + + 0 + 0 + 0 + 0 + 0 + + + 0 + 0.000 + + + + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 0 + false + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + false + 0 + 0 + + + 0 + 0.000 + 0 + + + + 0 + 0.000 + + + + 0 + 0.000 + 0 + + + + 0 + 0.000 + + + + 0 + 0.000 + + 0 + 0.000 + + + + 0 + 0.000 + 0 + ten_gig_eth_pcs_pma + 100.00 + kintex7 + X0Y0 + 32 + 0 + false + false + true + false + false + false + clk0 + 156 + 10 + ten_gig_eth_pcs_pma_gt + ten_gig_eth_pcs_pma + 100.00 + None + X0Y0 + true + clk0 + 156.25 + 0 + Time_of_day + false + false + false + BASE-R + 64bit + false + false + 10Gig + GTH + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 15 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + diff --git a/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v new file mode 100644 index 000000000..de98ea53a --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v @@ -0,0 +1,249 @@ +// +// Copyright 2008-2013 Ettus Research LLC +// + +module ten_gige_phy +( + input refclk, + input clk156, + input dclk, + input areset, + input sim_speedup_control, + input [63:0] xgmii_txd, + input [7:0] xgmii_txc, + output reg [63:0] xgmii_rxd, + output reg [7:0] xgmii_rxc, + output txp, + output txn, + input rxp, + input rxn, + input mdc, + input mdio_in, + output reg mdio_out, + output reg mdio_tri, + input [4:0] prtad, + output [7:0] core_status, + output resetdone, + input signal_detect, + input tx_fault, + output tx_disable +); + + reg [63:0] xgmii_txd_reg; + reg [7:0] xgmii_txc_reg; + wire [63:0] xgmii_rxd_int; + wire [7:0] xgmii_rxc_int; + + // Add a pipeline to the xmgii_tx inputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_txd_reg <= xgmii_txd; + xgmii_txc_reg <= xgmii_txc; + end + + // Add a pipeline to the xmgii_rx outputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_rxd <= xgmii_rxd_int; + xgmii_rxc <= xgmii_rxc_int; + end + + wire mdio_out_int; + wire mdio_tri_int; + reg mdc_reg; + reg mdio_in_reg; + + // Add a pipeline to the mdio in/outputs, to aid timing closure + // This is safe because the mdio clock is running so slowly + always @(posedge clk156) + begin + mdio_out <= mdio_out_int; + mdio_tri <= mdio_tri_int; + mdc_reg <= mdc; + mdio_in_reg <= mdio_in; + end + + // Signal declarations + wire txclk322; + wire qplloutclk; + wire qplloutrefclk; + wire qplllock; + + wire drp_gnt; + wire drp_req; + wire drp_den_o; + wire drp_dwe_o; + wire [15:0] drp_daddr_o; + wire [15:0] drp_di_o; + wire drp_drdy_o; + wire [15:0] drp_drpdo_o; + wire drp_den_i; + wire drp_dwe_i; + wire [15:0] drp_daddr_i; + wire [15:0] drp_di_i; + wire drp_drdy_i; + wire [15:0] drp_drpdo_i; + + wire tx_resetdone_int; + wire rx_resetdone_int; + + wire areset_clk156; + wire gttxreset; + wire gtrxreset; + wire qpllreset; + wire qplllock_txusrclk2; + wire gttxreset_txusrclk2; + wire reset_counter_done; + wire txusrclk; + wire txusrclk2; + reg txuserrdy; + + assign resetdone = tx_resetdone_int && rx_resetdone_int; + + // If no arbitration is required on the GT DRP ports then connect REQ to GNT + // and connect other signals i <= o; + assign drp_gnt = drp_req; + assign drp_den_i = drp_den_o; + assign drp_dwe_i = drp_dwe_o; + assign drp_daddr_i = drp_daddr_o; + assign drp_di_i = drp_di_o; + assign drp_drdy_i = drp_drdy_o; + assign drp_drpdo_i = drp_drpdo_o; + + // Instantiate the 10GBASER/KR GT Common block + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) ten_gig_eth_pcs_pma_gt_common_block ( + .refclk(refclk), + .qpllreset(qpllreset), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk) + ); + + // Asynch reset synchronizers... + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b1) + ) areset_clk156_sync_i ( + .clk(clk156), + .rst(areset), + .data_in(1'b0), + .data_out(areset_clk156) + ); + + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b0) + ) qplllock_txusrclk2_sync_i ( + .clk(txusrclk2), + .rst(!qplllock), + .data_in(1'b1), + .data_out(qplllock_txusrclk2) + ); + + reg [7:0] reset_counter = 8'h00; + reg [3:0] reset_pulse = 4'b1110; + assign reset_counter_done = reset_counter[7]; + + // Hold off the GT resets until 500ns after configuration. + // 128 ticks at 6.4ns period will be >> 500 ns. + always @(posedge clk156) + begin + if (!reset_counter[7]) + reset_counter <= reset_counter + 1'b1; + else + reset_counter <= reset_counter; + end + + always @(posedge clk156) + begin + if (areset_clk156 == 1'b1) + reset_pulse <= 4'b1110; + else if(reset_counter[7]) + reset_pulse <= {1'b0, reset_pulse[3:1]}; + end + + assign qpllreset = reset_pulse[0]; + assign gttxreset = reset_pulse[0]; + assign gtrxreset = reset_pulse[0]; + + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b1) + ) gttxreset_txusrclk2_sync_i ( + .clk(txusrclk2), + .rst(gttxreset), + .data_in(1'b0), + .data_out(gttxreset_txusrclk2) + ); + + always @(posedge txusrclk2 or posedge gttxreset_txusrclk2) + begin + if(gttxreset_txusrclk2) + txuserrdy <= 1'b0; + else + txuserrdy <= qplllock_txusrclk2; + end + + BUFG tx322clk_bufg_i ( + .I (txclk322), + .O (txusrclk) + ); + + assign txusrclk2 = txusrclk; + + // Instantiate the 10GBASER/KR Block Level + ten_gig_eth_pcs_pma ten_gig_eth_pcs_pma_i ( + .coreclk(clk156), + .dclk(dclk), + .txusrclk(txusrclk), + .txusrclk2(txusrclk2), + .txoutclk(txclk322), + .areset_coreclk(areset_clk156), + .txuserrdy(txuserrdy), + .areset(areset), + .gttxreset(gttxreset), + .gtrxreset(gtrxreset), + .sim_speedup_control(sim_speedup_control), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .reset_counter_done(reset_counter_done), + .xgmii_txd(xgmii_txd_reg), + .xgmii_txc(xgmii_txc_reg), + .xgmii_rxd(xgmii_rxd_int), + .xgmii_rxc(xgmii_rxc_int), + .txp(txp), + .txn(txn), + .rxp(rxp), + .rxn(rxn), + .mdc(mdc_reg), + .mdio_in(mdio_in_reg), + .mdio_out(mdio_out_int), + .mdio_tri(mdio_tri_int), + .prtad(prtad), + .core_status(core_status), + .tx_resetdone(tx_resetdone_int), + .rx_resetdone(rx_resetdone_int), + .signal_detect(signal_detect), + .tx_fault(tx_fault), + .drp_req(drp_req), + .drp_gnt(drp_gnt), + .drp_den_o(drp_den_o), + .drp_dwe_o(drp_dwe_o), + .drp_daddr_o(drp_daddr_o), + .drp_di_o(drp_di_o), + .drp_drdy_o(drp_drdy_o), + .drp_drpdo_o(drp_drpdo_o), + .drp_den_i(drp_den_i), + .drp_dwe_i(drp_dwe_i), + .drp_daddr_i(drp_daddr_i), + .drp_di_i(drp_di_i), + .drp_drdy_i(drp_drdy_i), + .drp_drpdo_i(drp_drpdo_i), + .pma_pmd_type(3'b101), + .tx_disable(tx_disable) + ); + +endmodule diff --git a/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc new file mode 100644 index 000000000..c8656e43a --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc @@ -0,0 +1,91 @@ +## (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. + +create_clock -period 6.400 [get_ports {dclk}] + +create_clock -period 6.400 [get_ports refclk_p] + +create_generated_clock -name ddrclock -divide_by 1 -invert -source [get_pins *rx_clk_ddr/C] [get_ports xgmii_rx_clk] +set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}] +set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}] +set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}] +set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}] + +# False paths for async reset removal synchronizers +set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *PRE}] +set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *CLR}] + + +## Sample constraint for GT location +#set_property LOC GTXE2_CHANNEL_X0Y18 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_i/*/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i] +#set_property LOC GTXE2_COMMON_X0Y4 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_gt_common_block/gtxe2_common_0_i] + +set_property IOSTANDARD HSTL_I [get_ports {xgmii_txc[*]}] +set_property IOSTANDARD HSTL_I [get_ports {xgmii_txd[*]}] + +set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxc[*]}] +set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxd[*]}] + +set_property IOB TRUE [get_cells {xgmii_rxc_reg[*]}] +set_property IOB TRUE [get_cells {xgmii_rxd_reg[*]}] + +set_property IOSTANDARD HSTL_I [get_ports xgmii_rx_clk] + + +################################################################## +# MDIO-related constraints # +################################################################## +set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_out*reg*}] +set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_tri*reg*}] +################################################################### + +################################################################## +# MDIO-related constraints # +################################################################## +set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdc_reg_reg}] +set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdio_in_reg_reg}] +################################################################### + diff --git a/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v new file mode 100644 index 000000000..27655571a --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v @@ -0,0 +1,51 @@ +// +// Copyright 2008-2013 Ettus Research LLC +// + +module ten_gige_phy_clk_gen +( + input areset, + input refclk_p, + input refclk_n, + + output refclk, + output clk156, + output dclk +); + + wire clk156_buf; + wire dclk_buf; + wire clkfbout; + + IBUFDS_GTE2 ibufds_inst ( + .O (refclk), + .ODIV2 (), + .CEB (1'b0), + .I (refclk_p), + .IB (refclk_n) + ); + + BUFG clk156_bufg_inst ( + .I (refclk), + .O (clk156) + ); + + // Divding independent clock by 2 as source for DRP clock + BUFR # ( + .BUFR_DIVIDE ("2") + ) dclk_divide_by_2_buf ( + .I (clk156), + .O (dclk_buf), + .CE (1'b1), + .CLR (1'b0) + ); + + BUFG dclk_bufg_i ( + .I (dclk_buf), + .O (dclk) + ); + +endmodule + + + -- cgit v1.2.3