From 4b4365a517938b365af57674a3ab1462432c2c3a Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Tue, 3 Dec 2013 10:35:35 -0800 Subject: b2xx: Updating FPGA source with recent bugfixes. --- fpga/usrp3/top/python/check_inout.py | 15 +++++++++++++-- fpga/usrp3/top/python/check_timing.py | 12 ++++++++++++ fpga/usrp3/top/python/make_lvbitx.py | 13 +++++++++++++ 3 files changed, 38 insertions(+), 2 deletions(-) (limited to 'fpga/usrp3/top/python') diff --git a/fpga/usrp3/top/python/check_inout.py b/fpga/usrp3/top/python/check_inout.py index d3b63dc34..ff371d378 100755 --- a/fpga/usrp3/top/python/check_inout.py +++ b/fpga/usrp3/top/python/check_inout.py @@ -2,8 +2,19 @@ # # Copyright 2010 Ettus Research LLC # - - +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# # Description: # generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf. # outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes diff --git a/fpga/usrp3/top/python/check_timing.py b/fpga/usrp3/top/python/check_timing.py index 4fec3e7d4..5e32141f4 100644 --- a/fpga/usrp3/top/python/check_timing.py +++ b/fpga/usrp3/top/python/check_timing.py @@ -2,6 +2,18 @@ # # Copyright 2011-2012 Ettus Research LLC # +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . import sys import re diff --git a/fpga/usrp3/top/python/make_lvbitx.py b/fpga/usrp3/top/python/make_lvbitx.py index b8ed99866..1b78e35e4 100644 --- a/fpga/usrp3/top/python/make_lvbitx.py +++ b/fpga/usrp3/top/python/make_lvbitx.py @@ -2,6 +2,19 @@ # # Copyright 2012 Ettus Research LLC # +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# import xml.etree.ElementTree as et -- cgit v1.2.3